201247092 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於—種增進 電磁遮蔽層接地連接之半導體封裝構造。 a 【先前技術】 按，半導體晶片是-種微小型電子零件，即使經過封 =之後，仍有可能受到電磁干擾（EMI)而導致晶片運算異 常或是n力能失效’特別是晶片的運算頻率越高時越 容易欠到干擾。故依已知的傳統作法之其中之一，於其 内密封有晶片的封膠體之外表面覆蓋上一電磁遮蔽層 (或可稱為射頻遮蔽層）。然而，電磁遮蔽層必須有效接 地連接才能發揮良好的遮蔽效果。又，封膠體本身為電 !生絕緣材料，僅能利用基板之特殊接地結構與特殊封裝 製程方可達成電磁遮蔽層之接地連接，導致封裝成本的 提局。 美國專利US 7,342,303 B1揭示一種使電磁遮蔽層接 地連接之半導體封裝技術，在封裝製程中需要多道半切 割操作’基板於切割道尚需要預先製作可被半切之鍍通 孔。第1圖所示者為依該習知方法製得之半導體封裝構 造1 00 ’包含一具有特殊結構之基板丨！ 〇，在側邊設有鍍 通孔114，晶片丨20設置於基板11 〇上，利用銲線1 60 電性連接該晶片120至該基板110，再以一封膠體140 密封該晶片120。封膠體140之表面（如第1圖所示之頂 面1 4 1與切割側面丨42)形成有一導電塗層，作為電磁遮 201247092 蔽層150。該基板110之下方則設有複數個銲球170。在 形成該電磁遮蔽層1 5 0之前，必須先執行一預切割步 驟，切穿該封膠體1 40以及切到該基板11 〇之一部分， 以形成該封膠體1 40之切割側面1 42與該基板丨丨〇之上 切緣11 3 A，且第一次切割寬度大於第二次切割寬度使該 鍍通孔114露出’方能連接該電磁遮蔽層150。在形成 該電磁遮蔽層1 5 0之後，再以第二次切割步驟單體化分 離該半導體封裝構造1 0 〇。因此，第一次切割基板的深 度如果不夠便會影響該電磁遮蔽層150之接地連接效 果，然而只切到基板預定深度的切割操作需要相當高的 精準度與基板平坦度。此外’如單純以基板側面外露的 線路切斷端連接該電磁遮蔽層1 5 0 ’則因線路切斷端過 小容易會有接地連接失敗的問題發生。 【發明内容】 有鑒於此’本發明之主要目的係在於提供一種增進電 磁遮蔽層接地連接之半導體封裝構造，不需要半切基板 之多次切割操作，以達到製程簡化之功效。 本發明之次一目的係在於提供一種增進電磁遮蔽層 接地連接之半導體封裝構造，使基板結構簡化或是不需 要設置與電磁遮蔽層接地連接之特殊基板結構。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種增進電磁遮蔽層接地連接 之半導體封裝構造包含一基板、一晶片、一銲線殘留部 份、一封膠體以及一電磁遮蔽層。該基板係具有一上表 201247092 面以及複數個切緣，於該上表面之周邊係設有一接地 塾°該晶片係設置於該基板上。該銲線殘留部份係包含 一打線結球銲點’該打線結球銲點係設置於該接地墊 上。該封膠體係形成於該基板之該上表面上，以密封該 晶片與該銲線殘留部份，該封膠體係具有一頂面以及複 數個切割側面，該銲線殘留部份係具有一顯露於該切割 侧面之金屬切面。該電磁遮蔽層係形成於該封膠體之該 頂面與該些切割側面，並覆蓋連接至該銲線殘留部份之 該金屬切面。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在則述的半導體封裝構造中’該打線結球銲點係可為 非完整’而使該金屬切面位於該打線結球銲點之外側。 在前述的半導體封裝構造中，該接地墊係可延伸至該 基板之鄰近切緣並被該電磁遮蔽層所覆蓋連接。 在前述的半導體封裝構造中，該銲線殘留部份係可更 包含一殘留線段，係由該打線結球銲點拉出並截斷於與 該封膝體相鄰之切割側面。 在前述的半導體封裝構造中，該電磁遮蔽層係可更延 伸覆蓋至該基板之該些切緣。 在前述的半導體封裝構造中’該封膠體之該些切割側 面係可與該些切緣垂直向切齊。 在前述的半導體封裝構造中，該封膠體之該些切割側 面係可與該些切緣傾斜地切齊。 5 201247092 在前述的半導體封裝構造中，該基板之該上表面係可 更設有複數個接指，該基板内係具有一線路，係連接至 少一之該些接指至該接地墊，該半導體封裝構造另包含 複數個完整銲線，其兩端係分別連接該晶片之複數個銲 墊與該些接指，並且該封膠體係更密封該些完整銲線。 在前述的半導體封裝構造中，可另包含複數個銲球， 係設於該基板之一下表面。 在前述的半導體封裝構造中，該些銲球係可包含一殘 留銲料，係緊鄰該些切緣之其中之一並被該電磁遮蔽層 連接。 由以上技術方案可以看出，本發明之增進電磁遮蔽層 接地連接之半導體封裝構造，具有以下優點與功效： 一、可藉由在基板上形成之一銲線殘留部份與一形成於 封膠體表面之電磁遮蔽層的連接關係作為其中之一 技術手段，電磁遮蔽層覆蓋連接至該鲜線殘留部份 之金屬切面’不需要半切基板之多次切割操作，以 達到製程簡化之功效。 一、可藉由在基板上形成之一銲線殘留部份與一形成於 封膠體表面之電磁遮蔽層的連接關係作為其中之一 技術手段’電磁遮蔽層覆蓋連接至該銲線殘留部份 之金屬切面’使基板結構簡化或是不需要設置與電 磁遮蔽層接地連接之特殊基板結構。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 201247092 注意的是’該些圖示均為簡化之示意圖’僅以示意方法 來說明本發明之基本架構或實施方法’故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計’詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種增進電磁遮蔽層 接地連接之半導體封裝構造舉例說明於第2圖之截面示 意圖以及第3A至3G圖於製造過程中各步驟形成元件之 截面示意圖。該半導體封裝構造200係主要包含一基板 210、一晶片220、一銲線殘留部份230、一封膠體240 以及一電磁遮蔽層250。 如第2圖所示’該基板210係具有一上表面211、一 下表面212以及複數個切緣213，於該上表面211之周 邊係δ又有一接地塾2 1 4。該些切緣2 1 3係位於該上表面 2 11與該下表面2 1 2之間的側緣並以切割形成。通常該 基板210係為適用於半導體封裝之印刷電路板或軟性電 路板’用以承載與電性連接半導體晶片，可具有單層或 是多層的線路結構。其中，該上表面2 11係為晶片設置 表面。在本實施例中，該晶片220與該基板2 1 0之電性 連接方式係為打線連接（wire_b〇n(ling connection)。除了 該接地墊214，該上表面211係更設置有複數個接指 215’其中至少一接指215係經由該基板210内之一線路 201247092 216連接至該接地墊214。 該晶片220係設置於該基板2 1 0上。可利用一黏晶材 料，例如熱固性樹脂，黏著該晶片220之背面至該基板 21〇之該上表面211。該晶片220係為由一半導體晶圓切 割出之晶粒，内有各式積體電路或光主動元件，例如特 殊應用積體電路（ASIC)、記憶體、或邏輯元件。此外， 該基板2 1 0上不限於設置一個晶片，亦可設置更多相同 或不同功能、尺寸的晶片，以達到多晶片封裝。在本實 施例中，該晶片220之主動面係設有複數個銲墊22 i， 可為平塾狀或是凸出狀。而該半導體封裝構造2〇〇另包 含複數個完整銲線2 6 0，其兩端係分別連接該晶片2 2 〇 之該些銲墊221與該些接指215，並且該些完整銲線26〇 係被該封膠體240密封。 如第2與3C圖所示，該銲線殘留部份23〇係包含一 打線結球銲點232，該打線結球銲點232係設置於該接 地墊214上。該打線結球銲點232係為一銲線在打線開 始的接合點，通常稱其為球結合點（baU b〇nd)，但實際 上非球狀，而是依銲嘴的形狀並壓合形成，並且在該接 地墊214上接合面積大於銲線的線截面圓形面積。該打 線結球銲，點232係可為完整銲點或是非完整録點，在本 實施例中，該打線結球銲點232係為非完整銲點。而「銲 線殘留。P伤」表不為非完整的銲線，即一完整銲線中至 少包含在打線結束尾端之部位係不形成於該半導體封裝 構造200内。 201247092 再如第2圖所示，該封膠體24〇係形成於該基板2i〇 之該上表面211上，以密封該晶片22〇與該銲線殘留部 份230。1¾封膠豸24〇係、τ由轉移模注或是壓縮模封等 方法形成。該封膠體240之材質係可為包含無機填充材 與色料之電絕緣性熱固性樹脂。該封膠體24〇係具有一 頂面241以及複數個切割側面242。在本實施例中，該 封膠體240之該些切割側面242係可與該些切緣213垂 直向切齊。特別的是，該銲線殘留部份23〇係具有一顯 露於該切割側面2 42之金屬切面2 3 1。 該電磁遮蔽層250係形成於該封膠體24〇之該頂面 241與該些切割側面242 ’即沿著該封膠體24〇之外形輪 廓而形成，並覆蓋連接至該銲線殘留部份23〇之該金屬 切面23 1。因此，該電磁遮蔽層25〇不是直接與該基板 2 1 〇接地連接，該基板2 1 〇不需要特別製造位在切割道 供接地連接之鍍通孔或線路。該電磁遮蔽層25〇係提供 該晶片220之電磁遮蔽，其材質可為金屬，其形成方法 可利用濺鍍、蒸鍍、化學鍍、物理氣相沉積、印刷或喷 塗等方式。較佳地’該打線結球銲點232係可為非完整， 如第3 C圖所示，該打線結球銲點2 3 2於製程中是完整 的’但經切割後為非完整（如第3F圖所示），而使該金屬 切面23 1位於該打線結球銲點232之外側，能提供被該 打線結球銲點2 3 2覆蓋連接之較大面積。尤佳地，如第 2圖所示，該接地墊214係可延伸至該基板21〇之鄰近 切緣213並被該電磁遮蔽層250所覆蓋連接，以確保該 201247092 電磁遮蔽層250之接地連接。在本實施例中，該電磁遮 蔽層250係可更延伸覆蓋至該基板210之該些切緣 2 1 3 ’以避免該基板2 1 0之核心層外露並增進侧向的電磁 遮蔽效果。此外，該半導體封裝構造200可另包含複數 個銲球270’係設於該基板210之該下表面212，作為該 半導體封裝構造200之外接端子。 第3A至3G圖繪示該半導體封裝構造2〇〇之製造過 程’用以說明該半導體封裝構造200不需要半切基板之 多次切割操作，以達到製程簡化之功效。 首先’如第3A與4圖所示，提供該基板21〇,其係 複數個型態形成於一基板條。基板2〖〇與基板2丨〇之間 係定義有一切割線20 1。該基板2 10的接指2 1 5中接地 作用之接指係藉由一線路216連接至該接地墊214，而 該接地墊214係可超過該切割線2〇1或不超過。在本實 施例中，如第4圖所示，該接地墊2丨4係可超過該切割 線2〇 1。第3B圖係為在黏晶步驟中，至少一之該晶片 220设置於該基板21〇上但不超過該切割線2〇1。第％ 圖係為在打線步驟中，利用打線形成之該些銲線26〇連 接該晶片220之辉墊221與該基板21〇之接指215;同 時’在本實施例中’亦利用打線方式在該接地墊214上 形成打線結球銲點2 3 2，該打線結球銲點2 3 2的尺寸可 大於或等於該些銲線26〇之結球銲點，在較佳的結構 中’該打線結球銲點232的尺寸是大於該些銲線26〇之 結球銲點’可利用多銲點堆疊接合或是選用較粗的銲線 10 201247092 構成’以確保該打線結球銲點2 3 2超過該切割線2 〇 i。 第30圖係為在模封步驟中之元件截面圖，在該基板 210上形成該封膠體240。在本實施例中’該模封步驟係 模封陣列製程（MAP)，該封膠體24〇係連續覆蓋多個基 板及其之間的切割線20 1 ’以密封該晶片220、該打線結 球銲點232以及該些銲線260。第3E圖係為在植球步驟 中之元件截面圖，利用球放置加上回焊的方式或是銲料 印刷與回焊的方式設置該些銲球27〇於該基板21〇之下 表面212°第3F圖係為在單體化切割步驟中之元件戴面 圖’利用刀具沿著上述切割線2〇 1切穿該封膠體24〇與 該基板2 1 〇，使該基板2丨〇分離。在單體化切割步驟中 除了形成該封膠體240之該些切割側面242與該基板之 該些切緣2 1 3，同時切過該打線結球銲點232，以構成具 有該金屬切面231之銲線殘留部份230。最後’如第3G 圖所示’形成該電磁遮蔽層250於該封膠體240之該頂 面241與該些切割側面242，並覆蓋連接至該銲線殘留 部份230之該金屬切面23丨。因此，本發明達成該電磁 遮蔽層250之接地連接並不需要包含半切基板之多次切 割操作。 在本發明之第二具體實施例中，揭示另一種增進電磁 遮蔽層接地連接之半導體封裝構造，說明於第5圖之截 面示意圖以及第6圖在單體化切割之前之截面示意圖。 該半導體封裝構造300主要包含一基板210、一晶片 220、一銲線殘留部份23〇、一封膠體24〇以及一電磁遮 11 201247092 蔽層250。主要元件大體與第一具體實施例相同，相同 圖號的元件不再詳細贅述。 該銲線殘留部份23 0係具有一顯露於該封膠體24〇 切割側面242之金屬切面23 1。該電磁遮蔽層250係形 成於該封膠體240之該頂面241與該些切割側面242， 並覆蓋連接至該銲線殘留部份230之該金屬切面231。 在本實施例中，該銲線殘留部份2 3 0係可更包含一殘留 線段333，係由一打線結球銲點332拉出並截斷於與該 封膠體240相鄰之切割側面242。較佳地，該封膠體24〇 之該些切割側面242係可與該些切緣2 1 3傾斜地切齊， 藉以擴大該金屬切面231之面積，以利該電磁遮蔽層25〇 之覆蓋連接。此外，該些銲球270係可包含一殘留銲料 371，係緊鄰該些切緣213之其中之一並被該電磁遮蔽層 250連接，藉以增進該電磁遮蔽層25〇之接地連接。 如第ό圖所示，在單體化切割之前’上述銲線殘留部 份230係為一銲線33〇α之一部份，該銲線33〇α之中間 線段係穿過該切割線20 1。而該殘留銲料3 7 1在切割前 係為位於該切割線201之銲球，可與該些銲球27〇同時 形成。 以上所述’僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 揭路如上，然而並非用以限定本發明，任何熟悉本項技 術者，在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修飾，均仍屬於本發明的技術範圍 12 201247092 内。 【圖式簡單說明】 第1圖：習知電磁遮蔽層接地連接至基板半切割邊緣之 半導體封裝構造之截面示意圖。 第2圖.依據本發明之第一具體實施例的一種增進電磁 遮蔽層接地連接之半導體封裝構造之戴面示意 圖。 第3A至3G圖：依據本發明之第一具體實施例的該半導 體封裝構造於製造過程中各步驟形成元件之截 面示意圖。 第4圖.依據本發明之第一具體實施例的該半導體封裝 構造之基板上表面示意圖。 第5圖：依據本發明之第二具體實施例的另一種增進電 磁遮蔽層接地連接之半導體封裝構造之截面示 意圖。 第6圖：依據本發明之第二具體實施例的該半導體封裝 構造在單體化切割之前之截面示意圖。 【主要元件符號說明】 I 0 0習知半導體封裝構造 110基板 II 3 A上切緣 11 3 B下切緣 11 4鍍通孔 120晶片 140封膠體 141頂面 142切割側面 13 201247092 150 電 磁 遮 蔽層 160 銲 線 170 銲 球 200 半 導 體 封裝 構 造 201 切 割 線 210 基 板 211 上 表 面 212 下 表 面 213 切 緣 214 接 地 墊 215 接 指 216 線 路 220 晶 片 221 銲 塾 230 銲 線 殘 留部 份 231 金 屬 切 面 232 打 線 結 球銲點 240 封 膠 體 241 頂 面 242 切 割 側 面 250 電 磁 遮 蔽層 260 完 整 銲 線 270 銲 球 300 半 導 體 封裝 構 造 330A銲線 332 打 線 結 球鲜 點 333 殘 留 線 371 殘 留 銲 料 14201247092 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a semiconductor package structure for improving the ground connection of an electromagnetic shielding layer. a [Prior Art] According to the semiconductor wafer, it is a kind of micro-small electronic parts. Even after sealing =, it may be subject to electromagnetic interference (EMI), which may cause abnormal operation of the wafer or failure of the n-force, especially the operating frequency of the wafer. The higher the higher the easier it is to owe interference. Therefore, according to one of the known conventional methods, the surface of the sealant in which the wafer is sealed is covered with an electromagnetic shielding layer (or may be referred to as a radio frequency shielding layer). However, the electromagnetic shielding layer must be effectively grounded to provide a good shielding effect. Moreover, the encapsulant itself is an electric insulating material, and the grounding connection of the electromagnetic shielding layer can be achieved only by using the special grounding structure of the substrate and the special packaging process, resulting in a package cost improvement. U.S. Patent No. 7,342, 303 B1 discloses a semiconductor packaging technique for the ground connection of an electromagnetic shielding layer, which requires multiple half-cut operations in the packaging process. The substrate needs to be pre-formed with a half-cut plated through hole in the dicing street. The one shown in Fig. 1 is a semiconductor package structure manufactured by the conventional method. The package includes a substrate having a special structure!镀, a plated through hole 114 is formed on the side, the wafer cassette 20 is disposed on the substrate 11 ,, the wafer 120 is electrically connected to the substrate 110 by the bonding wire 160, and the wafer 120 is sealed with a gel 140. The surface of the encapsulant 140 (such as the top surface 141 and the cut side surface 42 shown in Fig. 1) is formed with a conductive coating as an electromagnetic shielding 201247092 mask 150. A plurality of solder balls 170 are disposed under the substrate 110. Before forming the electromagnetic shielding layer 150, a pre-cutting step must be performed, cutting through the encapsulant 110 and cutting into a portion of the substrate 11 to form the cut side 1 42 of the encapsulant 140. The substrate has a cutting edge 11 3 A, and the first cutting width is greater than the second cutting width to expose the plated through hole 114 to connect the electromagnetic shielding layer 150. After the electromagnetic shielding layer 150 is formed, the semiconductor package structure 10 〇 is separately singulated by a second dicing step. Therefore, if the depth of the first cutting of the substrate is insufficient, the grounding effect of the electromagnetic shielding layer 150 is affected. However, the cutting operation only to the predetermined depth of the substrate requires a relatively high degree of precision and substrate flatness. Further, if the electromagnetic shielding layer 150' is simply connected to the line cut-off end exposed on the side of the substrate, the problem that the ground connection fails due to the line cut-off end is too small. SUMMARY OF THE INVENTION In view of the above, the main object of the present invention is to provide a semiconductor package structure for improving the grounding connection of an electromagnetic shielding layer, which does not require multiple cutting operations of a half-cut substrate to achieve the simplification of the process. A second object of the present invention is to provide a semiconductor package structure for improving the ground connection of an electromagnetic shielding layer, which simplifies the substrate structure or does not require a special substrate structure to be grounded to the electromagnetic shielding layer. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semiconductor package structure for improving the grounding connection of an electromagnetic shielding layer, comprising a substrate, a wafer, a residual portion of the bonding wire, a gel and an electromagnetic shielding layer. The substrate has a surface of the upper surface 201247092 and a plurality of cutting edges, and a grounding layer is disposed on the periphery of the upper surface. The wafer is disposed on the substrate. The remaining portion of the bonding wire includes a wire bonding ball joint point. The wire bonding ball bonding point is disposed on the grounding pad. The encapsulation system is formed on the upper surface of the substrate to seal the wafer and the residual portion of the bonding wire. The encapsulation system has a top surface and a plurality of cutting sides, and the remaining portion of the bonding wire has a revealing portion The metal cut surface on the cut side. The electromagnetic shielding layer is formed on the top surface of the encapsulant and the cut side surfaces, and covers the metal cut surface connected to the residual portion of the bonding wire. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the semiconductor package construction described herein, the wire bonding ball joint may be incomplete and the metal cutting surface is located outside the wire bonding ball joint. In the foregoing semiconductor package construction, the ground pad may extend to and be covered by the adjacent edge of the substrate. In the foregoing semiconductor package structure, the wire remaining portion may further comprise a residual line segment which is pulled out by the wire bonding ball joint and cut off from the cutting side adjacent to the sealing body. In the foregoing semiconductor package construction, the electromagnetic shielding layer can be extended to cover the cutting edges of the substrate. In the foregoing semiconductor package construction, the cutting sides of the encapsulant may be perpendicular to the cutting edges. In the foregoing semiconductor package construction, the cut sides of the sealant may be obliquely aligned with the cut edges. 5 201247092 In the foregoing semiconductor package structure, the upper surface of the substrate may further comprise a plurality of fingers, the substrate having a line connecting at least one of the contacts to the ground pad, the semiconductor The package structure further comprises a plurality of complete bonding wires, the two ends of which are respectively connected to the plurality of pads of the wafer and the connecting fingers, and the sealing system further seals the complete bonding wires. In the foregoing semiconductor package structure, a plurality of solder balls may be further included and disposed on a lower surface of the substrate. In the foregoing semiconductor package construction, the solder balls may include a residual solder adjacent to and connected by the one of the cutting edges. It can be seen from the above technical solution that the semiconductor package structure for improving the grounding connection of the electromagnetic shielding layer of the present invention has the following advantages and effects: 1. A residual portion of the bonding wire can be formed on the substrate and formed in the sealing body. As one of the technical means, the electromagnetic shielding layer covers the metal cut surface connected to the residual portion of the fresh wire, and does not require multiple cutting operations of the half-cut substrate to achieve the simplification of the process. 1. The connection relationship between the residual portion of the bonding wire and the electromagnetic shielding layer formed on the surface of the sealing body is formed on the substrate as one of the technical means that the electromagnetic shielding layer covers the remaining portion of the bonding wire. The metal cut surface 'simplifies the substrate structure or does not require a special substrate structure to be grounded to the electromagnetic shielding layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which: FIG. 'Therefore, only the components and combinations related to this case are displayed. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of scales and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design. Detailed component layout may be more complicated. According to a first embodiment of the present invention, a semiconductor package structure for improving the grounding connection of an electromagnetic shielding layer is illustrated in a cross-sectional view of Fig. 2 and a schematic cross-sectional view of the elements formed in each step of the manufacturing process in Figs. 3A to 3G. The semiconductor package structure 200 mainly includes a substrate 210, a wafer 220, a wire remaining portion 230, a gel body 240, and an electromagnetic shielding layer 250. As shown in Fig. 2, the substrate 210 has an upper surface 211, a lower surface 212, and a plurality of cutting edges 213. The peripheral surface 211 has a grounding 塾 2 14 . The cutting edges 2 1 3 are located on the side edges between the upper surface 2 11 and the lower surface 2 1 2 and are formed by cutting. Generally, the substrate 210 is a printed circuit board or a flexible circuit board for a semiconductor package for carrying and electrically connecting the semiconductor wafer, and may have a single layer or a plurality of layers. Wherein, the upper surface 2 11 is a wafer setting surface. In this embodiment, the electrical connection between the wafer 220 and the substrate 210 is a wire connection (wire_b〇n (ling connection). In addition to the ground pad 214, the upper surface 211 is further provided with a plurality of connections. At least one of the fingers 215' is connected to the ground pad 214 via a line 201247092 216 in the substrate 210. The wafer 220 is disposed on the substrate 210. A die-bonding material such as a thermosetting resin may be utilized. Adhering the back surface of the wafer 220 to the upper surface 211 of the substrate 21. The wafer 220 is a die cut from a semiconductor wafer, and has various integrated circuits or optical active components, such as a special application product. An integrated circuit (ASIC), a memory, or a logic element. In addition, the substrate 210 is not limited to one wafer, and more wafers of the same or different functions and sizes may be disposed to achieve multi-chip packaging. In an example, the active surface of the wafer 220 is provided with a plurality of pads 22 i, which may be flat or convex, and the semiconductor package structure 2 〇〇 further includes a plurality of complete bonding wires 260. The two ends are connected separately The pads 221 and the fingers 215 of the film 2 2, and the complete bonding wires 26 are sealed by the sealing body 240. As shown in Figures 2 and 3C, the wire remaining portion 23〇 The ball bonding ball joint 232 is disposed on the grounding pad 214. The wire bonding ball joint 232 is a joint of a bonding wire at the beginning of the wire bonding, and is generally referred to as a ball bonding point ( baU b〇nd), but actually non-spherical, but formed according to the shape of the tip and press-fit, and the joint area on the ground pad 214 is larger than the circular cross-sectional area of the wire. The 232 series can be a complete solder joint or a non-complete recording point. In this embodiment, the wire bonding ball joint 232 is a non-complete solder joint, and the "welding wire residue. P injury" table is not a non-complete welding wire. That is, a portion of a complete bonding wire including at least the end of the wire bonding is not formed in the semiconductor package structure 200. 201247092 As shown in FIG. 2, the sealing body 24 is formed on the substrate 2i. a surface 211 for sealing the wafer 22 and the remaining portion of the bonding wire 230. 13⁄4 sealing tape 2 The structure of the sealant 240 can be an electrically insulating thermosetting resin comprising an inorganic filler and a colorant. The sealant 24 has a top. The surface 241 and the plurality of cutting side surfaces 242. In the embodiment, the cutting side surfaces 242 of the sealing body 240 are perpendicular to the cutting edges 213. In particular, the wire remaining portion 23〇 The metal shielding surface 213 is exposed on the cutting side surface 2 42. The electromagnetic shielding layer 250 is formed on the top surface 241 of the sealing body 24 and the cutting side surface 242 ′ along the sealing body 24 . The outer contour is formed and covers the metal cut surface 23 1 connected to the residual portion 23 of the bonding wire. Therefore, the electromagnetic shielding layer 25 is not directly connected to the substrate 2 1 , and the substrate 2 1 〇 does not need to specifically manufacture plated through holes or lines at the scribe lines for ground connection. The electromagnetic shielding layer 25 is provided with electromagnetic shielding of the wafer 220, and the material thereof may be metal. The forming method may be by sputtering, evaporation, electroless plating, physical vapor deposition, printing or spraying. Preferably, the wire bonding ball joint 232 can be incomplete. As shown in FIG. 3C, the wire ball joint 2 2 2 is complete during the process but is not complete after cutting (eg, 3F) As shown, the metal cut surface 23 1 is located outside the wire ball joint 232, providing a larger area covered by the wire ball joint 232. More preferably, as shown in FIG. 2, the ground pad 214 can extend to and be covered by the adjacent shielding edge 213 of the substrate 21 to ensure the ground connection of the 201247092 electromagnetic shielding layer 250. . In this embodiment, the electromagnetic shielding layer 250 can extend to cover the cutting edges 2 1 3 ' of the substrate 210 to prevent the core layer of the substrate 210 from being exposed and enhance the lateral electromagnetic shielding effect. In addition, the semiconductor package structure 200 may further include a plurality of solder balls 270' disposed on the lower surface 212 of the substrate 210 as external terminals of the semiconductor package structure 200. 3A to 3G illustrate the manufacturing process of the semiconductor package structure 2' to illustrate that the semiconductor package structure 200 does not require a plurality of half-cutting operations of the half-cut substrate to achieve process simplification. First, as shown in Figs. 3A and 4, the substrate 21 is provided in a plurality of patterns formed on a substrate strip. A cutting line 20 1 is defined between the substrate 2 and the substrate 2 . The grounding contact of the finger 2 1 5 of the substrate 2 10 is connected to the ground pad 214 by a line 216, and the ground pad 214 may exceed the cutting line 2〇1 or not. In the present embodiment, as shown in Fig. 4, the ground pad 2丨4 can extend beyond the cutting line 2〇1. In Fig. 3B, at least one of the wafers 220 is disposed on the substrate 21〇 but does not exceed the cutting line 2〇1 in the die bonding step. In the step of the wire bonding, the wire bonding wires 26 formed by the wire bonding are connected to the bonding pad 221 of the wafer 220 and the finger 215 of the substrate 21; and in the present embodiment, the wire bonding method is also used. A wire bonding ball joint 2 2 2 is formed on the grounding pad 214, and the wire bonding ball bonding point 2 3 2 may be larger than or equal to the ball bonding point of the bonding wire 26〇. In the preferred structure, the wire bonding ball is formed. The size of the solder joint 232 is larger than the solder joints of the soldering wires 26' can be stacked by using multiple solder joints or by using a thicker bonding wire 10 201247092 to ensure that the bonding ball solder joints 2 3 2 exceed the cutting Line 2 〇i. Figure 30 is a cross-sectional view of the element in the molding step on which the encapsulant 240 is formed. In the present embodiment, the molding step is a die-stacking process (MAP), and the encapsulant 24 continuously covers a plurality of substrates and a cutting line 20 1 ' therebetween to seal the wafer 220 and the wire bonding ball bonding Point 232 and the bond wires 260. Figure 3E is a cross-sectional view of the component in the step of implanting the ball, and the solder balls 27 are disposed on the lower surface of the substrate 21 by means of ball placement plus reflow or solder printing and reflow soldering. The third FF is a component wearing surface in the singulation cutting step. The cutter 20 is cut through the sealing body 24 沿着 along the cutting line 2〇1 to separate the substrate 2丨〇. In the singulation cutting step, in addition to forming the cut side 242 of the sealant 240 and the cutting edges 2 1 3 of the substrate, the wire ball joint 232 is cut at the same time to form a weld having the metal cut surface 231. Line residual portion 230. Finally, the electromagnetic shielding layer 250 is formed on the top surface 241 of the encapsulant 240 and the cut side surfaces 242 as shown in FIG. 3G, and covers the metal cut surface 23丨 connected to the wire remaining portion 230. Thus, the present invention achieves a ground connection of the electromagnetic shielding layer 250 and does not require multiple cutting operations including a half-cut substrate. In a second embodiment of the present invention, another semiconductor package structure for enhancing the ground connection of the electromagnetic shielding layer is disclosed. A cross-sectional view of Fig. 5 and a schematic cross-sectional view of Fig. 6 before singulation are illustrated. The semiconductor package structure 300 mainly includes a substrate 210, a wafer 220, a wire remaining portion 23A, a glue body 24A, and an electromagnetic shielding layer 201247092. The main components are generally the same as those of the first embodiment, and the components of the same reference numerals will not be described in detail. The wire remaining portion 230 has a metal cut surface 23 1 exposed on the cut side 242 of the sealant 24'. The electromagnetic shielding layer 250 is formed on the top surface 241 of the encapsulant 240 and the cutting side surfaces 242, and covers the metal cut surface 231 connected to the wire remaining portion 230. In this embodiment, the wire remaining portion 203 further includes a residual line segment 333 which is pulled by a wire bonding ball joint 332 and cut into a cutting side 242 adjacent to the sealing body 240. Preferably, the cutting sides 242 of the sealing body 24 are obliquely aligned with the cutting edges 2 1 3 to enlarge the area of the metal cutting surface 231 to facilitate the covering connection of the electromagnetic shielding layer 25 . In addition, the solder balls 270 may include a residual solder 371 adjacent to and connected by one of the cutting edges 213 to enhance the ground connection of the electromagnetic shielding layer 25 . As shown in the figure, before the singulation cutting, the above-mentioned wire remaining portion 230 is a part of a bonding wire 33〇α, and the middle line segment of the bonding wire 33〇α passes through the cutting line 20 1. The residual solder 317 is a solder ball located on the dicing line 201 before cutting, and can be formed simultaneously with the solder balls 27 。. The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention has been described above by the preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made by the skilled person within the technical scope of the present invention are still within the technical scope 12 201247092 of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a semiconductor package structure in which a conventional electromagnetic shielding layer is grounded to a half-cut edge of a substrate. Fig. 2 is a perspective view of a semiconductor package structure for enhancing the grounding connection of an electromagnetic shielding layer in accordance with a first embodiment of the present invention. 3A to 3G are views showing a cross-sectional view of the components formed in each step of the manufacturing process in accordance with the first embodiment of the present invention. Fig. 4 is a view showing the upper surface of the substrate of the semiconductor package structure according to the first embodiment of the present invention. Fig. 5 is a cross-sectional view showing another semiconductor package structure for improving the grounding connection of an electromagnetic shielding layer in accordance with a second embodiment of the present invention. Figure 6 is a schematic cross-sectional view of the semiconductor package construction in accordance with a second embodiment of the present invention prior to singulation. [Main component symbol description] I 0 0 conventional semiconductor package structure 110 substrate II 3 A upper cutting edge 11 3 B lower cutting edge 11 4 plated through hole 120 wafer 140 encapsulant 141 top surface 142 cut side 13 201247092 150 electromagnetic shielding layer 160 Welding wire 170 solder ball 200 semiconductor package structure 201 cutting line 210 substrate 211 upper surface 212 lower surface 213 cutting edge 214 grounding pad 215 finger 216 line 220 wafer 221 soldering wire 230 wire residual portion 231 metal cutting surface 232 wire ball solder joint 240 Sealant 241 Top surface 242 Cutting side 250 Electromagnetic shielding layer 260 Complete bonding wire 270 Solder ball 300 Semiconductor package construction 330A Bond wire 332 Wire ball ball fresh spot 333 Residual wire 371 Residual solder 14