TW201246803A - Rate matching device - Google Patents

Abstract

In rate matching and interleaving in a Long Term Evolution (LTE) system, use of a circular buffer following interleaving may be avoided by reading out interleaved data directly from the interleaver in a manner which matches an expected output from a circular buffer. The read out data may be rate matched according to instructions from upper layers. The order in which the data is read out is configured to match the expected rate matched output from a circular buffer. In this manner use of a circular buffer may be avoided, resulting in saved memory costs.

Description

201246803, the invention is hereby incorporated by reference. The entire disclosure of the provisional application is expressly incorporated herein by reference. BACKGROUND OF THE INVENTION The present invention relates generally to communication systems and, more particularly, to rate matching of long term evolution (LTE) code blocks without the need for a circular buffer. [Prior Art] Wireless communication networks are widely deployed to provide various communication services such as voice, video, packet data, message transmission, broadcast, and the like. Such wireless networks may be multiplexed access networks capable of supporting multiple users by sharing available system resources. Examples of such multiplexed access networks include code division multiplex access (CDMA) networks, time division multiplex access (TDMA) networks, frequency division multiplex access (FDMA) networks, and orthogonal FDMA. (OFDMA) network and single carrier FDMA (SC-FDMA) network. The wireless communication network can include a plurality of base stations that can support communication for multiple user equipments (UEs). The UE can communicate with the base station via the downlink and uplink. The downlink (or forward link) represents the communication link from the base station to the UE, and the uplink (or reverse link) represents the communication link from the UE to the base station. 201246803 The base station can provide u, 霄廷, and control information on the downlink and/or can access sighs and control information from the UE on the uplink. On the downlink road, 'the transmission from the base station can be 4,®, and it will encounter interference caused by transmissions from neighboring base stations or from other non-(10) transmitters. The transmission from the UE on the up-key may encounter uplink (four) transmissions from other UEs communicating with neighboring base stations or interference from other wireless RF transmitters. This box _ such interference may reduce the performance of the downlink and uplink keys. As the demand for mobile broadband access continues to grow, the potential for interference and network queuing is increasing as more and more UEs access the remote wireless communication network and more and more short-range wireless systems are deployed. The community continues to grow. Not only to meet the needs of mobile broadband access for the benefit of growth, but also to promote and enhance the user experience of using mobile communications, research and development continue to advance the advancement of UMTS technology. SUMMARY OF THE INVENTION The present invention provides a method for rate matching in a long term evolution (LTE) wireless communication system. The method includes receiving a plurality of data streams from an encoder. The method also includes writing the plurality of data streams to the human memory. The method further includes performing interleaving and rate matching of the plurality of data streams. The method further includes reading the interleaved and rate matched data in an order that is formatted as an analog output from the circular buffer. The present invention provides an apparatus for rate matching in a Long Term Evolution (LTE) wireless communication system. The apparatus includes means for receiving a plurality of 201246803 data streams from an encoder. The apparatus also includes means for writing the plurality of streams of data into the memory. The apparatus further includes means for performing interleaving and rate matching of the plurality of data streams. The apparatus further includes means for reading the interleaved and rate matched data in an order that is formatted to be analogous to the output from the circular buffer. The present invention provides a computer program product for rate matching in a long term evolution (LTE) wireless communication system. The computer program product includes non-transitory computer readable media having a non-transitory code recorded thereon. The code contains code for receiving multiple streams of data from the encoder. The code also contains code for writing the plurality of data streams to the memory. The code further includes code for performing interleaving and rate matching of the plurality of data streams. The code further includes code for reading the data of the interleaved and rate matched data in an order that is formatted to be analogous to the output from the circular buffer. The present invention provides an apparatus for rate matching in a Long Term Evolution (LTE) wireless communication system. The device includes a memory and a processor coupled to the memory. The processor is configured to receive a plurality of data streams from the encoder. The processor is also configured to write the plurality of data streams to the memory. The processor is further configured to perform interleaving and rate matching of the plurality of data streams. The processor is further configured to read the interleaved and rate matched data in an order that is formatted to be analogous to the output from the circular buffer. For a better understanding of the detailed description that follows, the features and technical advantages of the present invention are summarized broadly. Additional features and advantages of this case are described below. It will be understood by those skilled in the art that the present disclosure can be used as a basis for modifying or designing other structures for achieving the same purpose as the present application. It should also be appreciated by those skilled in the art that (4) the equivalent construction does not depart from the scope of the teachings of the present invention provided in the appended claims. In conjunction with the drawings, the following description will better understand the novel features of the case in terms of its organizational relationship, method of operation, and the purpose and advantages of the case (the novel features are considered to be unique to the case) However, it is to be understood that the drawings are only for the purpose of illustration and description The description is intended to be illustrative of the various configurations, and is not intended to represent a particular configuration of the concepts described herein. In order to provide a thorough understanding of various concepts, the detailed description herein includes specific details. However, those skilled in the art will It is appreciated that such concepts may be practiced without these specific details. In some instances, 'in order to avoid obscuring the concepts, the well-known structures and elements are illustrated in the form of block diagrams. Can be used for such as code division multiplex access (CDMA) networks, 'time division multiplexed access (TDMA) networks, frequency division multiplexing access (FDMA)

Various wireless communication networks such as networks, orthogonal FDMA (OFDMA) networks, and single carrier FDMA (SC-FDMA) networks. The terms "network" and "system" are often used interchangeably. A CDMA network can implement radio technologies such as Universal Terrestrial Radio Access (UTRA), CDMA2000, and the like. UTRA includes wideband-CDMA (W-CDMA) and low chip rate 201246803 (LCR). CDMA2000 covers the IS-2000 'IS-9 5 and IS-856 standards. A TDMA network can implement a radio technology such as the Global System for Mobile Communications (GSM). The OFDMA network can implement radio technologies such as evolved UTRA (E-UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, Flash-OFDM®, and the like. UTRA 'E-UTRA and GSM are part of the Universal Mobile Telecommunications System (UMTS). Long Term Evolution (LTE) is a release of UMTS that will be released using E-UTRA. UTRA, E-UTRA, GSM, UMTS, and LTE are described in documents from an organization named "3rd Generation Partnership Project" (3GPP). CDMA2000 is described in documents from an organization named "3rd Generation Partnership Project 2" (3GPP2). These different radio technologies and standards are known in the art. For the sake of clarity, certain aspects of the techniques are described below for LTE, and most of the following description uses LTE terminology. The techniques described herein can be used in a variety of wireless communication networks such as CDMA, TDMA, FDMA, OFDMA 'SC-FDMA, and other networks. The terms "network" and "system" are often used interchangeably. A CDMA network can implement a radio technology such as Universal Terrestrial Radio Access (UTRA), the Telecommunications Industry Association (TIA) CDMA20008. UTRA technology includes wideband CDMA (WCDMA) and other variants of CDMA. The eDMA2()()〇® technology includes the IS_2000, Is_95, and IS 856 standards from the Electronic Industries Alliance (EIA) and TIA. The tDma network can implement radio technologies such as the Global System for Mobile Communications (GSM). The OFDMA network can implement radios such as Evolved UTRA (E-UTRA), Super Mobile Broadband 201246803 (UMB) 'IEEE 8 02.11 (Wi-Fi) 'IEEE 8 02.16 (WiMAX) 'IEEE 802.20, Flash-OFDMA, etc. technology. UTRA and E-UTRA technologies are part of the Universal Mobile Telecommunications System (UMTS). 3GPP Long Term Evolution (LTE) and LTE-Advanced (LTE-A) are new versions of UMTS that use E-UTRA. UTRA, E-UTRA, UMTS, LTE, LTE-A, and GSM are described in documents from an organization known as the Third Generation Partnership Project (3GPP). CDMA2000® and UMB are described in documents from an organization known as the 3rd Generation Partnership Project 2 (3GPP2). The techniques described herein can be used with the wireless networks and radio access technologies mentioned above, as well as other wireless networks and radio access technologies. For the sake of clarity, certain aspects of the techniques are described below for LTE or LTE-A (or collectively referred to as "LTE/-A"), and are used in most of the sections described below. LTE/-A terminology. Figure 1 illustrates a wireless communication network 100, which may be an LTE-A network. Wireless network 100 includes a plurality of evolved Node Bs (eNodeBs) 110 and other network entities. The eNodeB may be a station that communicates with the UE, and the eNodeB may also be referred to as a base station, a Node B, an access point, and the like. Each eNodeB 110 can provide communication coverage for a particular geographic area. In 3GPP, depending on the context in which the term "cell service area" is used, the term may refer to the above-described specific geographic coverage area of the eNodeB and/or the eNodeB subsystem serving the coverage area. The eNodeB can provide communication coverage for macrocell service areas, pico cell service areas, femtocell service areas, and/or other types of cell service areas. 201246803 In general, a macro cell service area covers a relatively large geographic area (e.g., a few kilometers in radius) and can allow unrestricted access by UEs with contracted services to a network service provider. The picocell service area typically covers a relatively small geographic area and can allow unrestricted access by UEs with contracted services to the network service provider. The femtocell service area will typically also cover a relatively small geographic area (e.g., home)' and in addition to unrestricted access, the femtocell service area may also provide UEs associated with it (e.g., closed users) Restricted access by UEs in a group (CSG), UEs for users in the home, etc.). The eNodeB of the macro cell service area may be referred to as a macro eNodeB. The eNodeB of the picocell service area may be referred to as a pico eNodeB. And the eN〇deB of the 'nano cell service area' may be referred to as a femto eNodeB or a home eNodeB. In the example illustrated in FIG. 1, eNodeBs 110a, 110b, and 110c are macro eNodeBs of macro cell service areas i 〇 2a, 102b, and 〇 2c, respectively. The eNodeB 11 is the pico eNodeB of the pico cell service area 102χ. Also, the eNodeBs 110y and 110ζ are femto eN〇deB of the femtocell service areas 102y and 102z, respectively. An eNodeB can support one or more (e.g., 2, 3, 4, etc.) cell service areas. The wireless network 100 can also include a relay station. A relay station is a station that receives transmissions of data and/or other information from upstream stations (e.g., 'eNodeBs and UEs, etc.) and transmits the transmission of data and/or other information to downstream stations (e.g., UEs or eNodeBs). The relay station may also be a UE that relays transmissions for other UEs. In the example illustrated in FIG. 1, in order to facilitate communication between the eNodeB 110a and the 201246803 UE 12〇Γ, the relay station u〇r can communicate with the (4) fork and the UE 12〇Γ. Relay stations can also be referred to as relay eN secrets and relays. eNodeB (e.g., macro network 100 may be an eNodeB containing different types of femto eNodeBs, relay stations, etc.), pico eN〇deB,

Heterogeneous network. These different types of codes (9) may have different levels of transmit power, different coverage areas, and have different effects on interference in the wireless network 100. For example, macro eNGdeB may have a high transmit power level (e.g., '20 watts)' while pico eNodeBs, femto eNodeBs, and relay stations may have lower transmit power levels (e.g., 1 watt). The wireless network 1GG can support synchronous or asynchronous operations. For synchronous operation, the eNodeB can have similar frame timing, and transmissions from different cafes (4) can be approximately aligned in time. For multiple asynchronous operations, multiple eNodeBs may have different frame timings, and transmissions from different eNodeBs may not be aligned in time. The techniques described herein can be used for either synchronous or asynchronous operation. . In one aspect, the 4-wire network 100 can support a frequency division duplex (fdd) mode of operation or a time division double guard (TDD) mode of operation. The techniques described herein can be used in FDD mode of operation or TDD mode of operation. The network controller 130 can be coupled to the group eN〇deB 11〇 and provide coordination and control to the eNodeBs 11〇, and the network controller 13 can communicate with the eNodeB 110 via the load. The eN〇deB 11〇 can also communicate with each other' directly or indirectly via, for example, wireless backhaul or wired backhaul. 10 201246803 ^ 120 is scattered throughout the wireless network 100, and each of them can be static: E or action one can also be called a terminal, a mobile station user, a station, etc. The UE may be a cellular personal digital assistant (pda), a wireless data modem, a wireless communication device, a handheld device, a laptop computer, a wireless telephone, a wireless area loop (WLL) A, a tablet computer, and the like. The UE can communicate with the macro eN〇deB, the pico eN〇_, the femto heart (four), the relay station, and the like. In the figure ", the solid line of the double arrow does not expect the transmission between the UE and the serving eNQdeB, and the serving eNodeB is the eNodeB designated to serve on the downlink and/or uplink. Interference transmission between the dashed line table of the double arrow and the heart (4) LTE utilizes orthogonal frequency division multiplexing () on the downlink and single carrier frequency division multiplexing (SC-FDM) on the uplink. OFDM and SC-FDM divide the system bandwidth into a plurality of (K) orthogonal subcarriers, which are also referred to as tones, frequency bands, and the like. Data can be used to modulate each subcarrier. In general, 〇fdm is used in the frequency domain to transmit modulation symbols, while SC_FDM is used in the time domain to transmit modulation symbols. The spacing between adjacent subcarriers may be fixed, and the total number of subcarriers (K) may depend on the system bandwidth. For example, the subcarrier spacing may be 15 kHz' and the smallest resource allocation (referred to as "resource block") may be 12 subcarriers (or 18 kHz). Thus, for a corresponding system bandwidth of 丨25, 2 5, 5, 10 or 20 dead Hertz (MHz), the nominal FFT size can be equal to 128, 256, 512, 1024 or 2048, respectively. The system bandwidth can also be divided into sub-bands. For example, a sub-band can cover 11 201246803 2.5, 5, 4, 8 or cover i·08· (ie 6 resource blocks), and the corresponding system bandwidth for 125 1 0 or 20 MHz can have 1 respectively. 16 sub-bands. 2 Figure 2 Table * LTE towel routing downlink lion wheel transmission isochronous line can be divided into radio frame: two-light wire box can have a predetermined parent-free pre-regulation duration (for example, (7) (5)) and can be divided into 1 sub-frames (so) for two frames can contain 2 time slots °^, each radio frame can be 匕3 2 时 time slots (so W 〇—19). Each time slot can contain L characters: period, for example, 'contains a solid symbol period for a standard cyclic prefix (as shown in Figure 2) or 6 for an extended cyclic prefix) Symbol period. The index can be 2 to 2 L symbol periods assigned to each sub-frame command. The available time-frequency resources can be divided into resource blocks. Each resource block can cover a time slot. _subcarrier (for example, 12 subcarriers). In LTE, the eNodeB can transmit a primary synchronization signal (2) and a secondary synchronization signal (batch = sSS) for each cell service area in the eN〇deB. For the yang 0 mode of operation, as shown in Figure 2, you can have 払The primary synchronization signal and the secondary synchronization L number are respectively transmitted in the symbol periods 6 and 5 of each of the subframes 〇 and 5 of each radio frame of the quasi-cyclic prefix. The UE can use the synchronization signal to perform the cell service area. Detecting and Acquiring For the FDD mode of operation, the eNodeB can send a physical broadcast channel (PBCh) within the symbol period 0-3 in the slot 1 of the subframe. The PBCH can carry certain system information. 12 201246803 The eNodeB may send a Physical Control Format Indicator Channel (PCFICH) in the first symbol period of each subframe. The PCFICH may transmit the number of symbol periods (M) used to control the channel, where Μ may be equal to 1. 2 or 3 and the value of Μ between different sub-frames can be changed. For smaller system bandwidths (for example, with less than 10 resource blocks), Μ can also be equal to 4. In Figure 2 In the example illustrated in the figure, Μ = 3. The eNodeB may send an entity HARQ indicator channel (PHICH) and a physical downlink control channel (PDCCH) within the first symbol period of each subframe. In the illustrated example The PDCCH and PHICH are also included in the first 3 symbol periods. The PHICH can carry information to support hybrid automatic repeat request (HARQ). The PDCCH can carry resource allocation information on the uplink and downlink for the UE and for the uplink. Power control information of the channel. The eNodeB may send a Physical Downlink Shared Channel (PDSCH) in the remaining symbol period of each subframe. The PDSCH may carry data for the UE, where for the data transmission on the downlink, The UE performs scheduling. The eNodeB can transmit PSC, SSC, and PBCH in the middle l_08 MHz of the system bandwidth it uses. The eNodeB can transmit the PCFICH and PHICH over the entire system bandwidth for each symbol period in which the PCFICH and PHICH are transmitted. The eNodeB may send PDCCHs to some groups of UEs in certain portions of the system bandwidth. The eNodeB may send the PDSCH to some UE groups in a specific part of the system bandwidth. The eNodeB may send the PSC, SSC, PBCH, PCFICH*PHICH to all UEs via broadcast, and may send the PDCCH to the specific UE via unicast mode. It is also possible to transmit the PDSCH to a specific UE via the unicast mode on 13 201246803. There can be multiple resource elements available in each symbol period. Each resource element may cover one subcarrier in one symbol period and may be used to transmit a modulation symbol, which may be a real value or a complex value. For symbols used to control channels, resource elements that are not used for reference symbols in each symbol period can be arranged into resource element groups (REGs). Each REG can include 4 resource elements within one symbol period. The PCFICH can occupy 4 REGs in symbol period 0, which can be approximately equally spaced in frequency. The PHICH can occupy 3 REGs in one or more configurable symbol periods, which can be spread over frequency. For example, the three REGs for the PHICH may all belong to the symbol period 〇 or be scattered in symbol periods 0, 1, and 2. The PDCCH may occupy 9, 18, 36, or 72 REGs in the first symbol period, and the REGs are selected from available REGs. Only certain REG combinations can be allowed for the PDCCH. The UE can know the specific REG for PHICH and PCFICH. The UE may search for different REG combinations for the PDCCH. Typically, for all UEs in the PDCCH, the number of combinations that need to be searched is less than the number of allowed combinations. The eNodeB may send the PDCCH to the UE in any one of the combinations in which the UE is to perform a search. The UE may be within the coverage of multiple eNodeBs. One of the eNodeBs may be selected to provide services to the UE. The eNodeB providing the service can be selected based on various criteria such as received power, path loss, signal to interference ratio (SNR), and the like. 14 201246803 Figure 3 is a block diagram showing the structure of the sub-frames of the non-existent and TDD (only non-special sub-frames) in the uplink long-term evolution (LTE) communication. The available resource blocks (RBs) 1 of the uplink are divided into a data portion and a control portion. The control portion can be formed at both edges of the system bandwidth and the control portion can have a configurable size. The resource blocks in the control section can be allocated and used by the UE to control the transmission of information. The data section can contain all resource blocks that are not included in the control section. The design in Figure 3 results in a data portion containing consecutive subcarriers that allows all consecutive subcarriers in the data portion to be assigned to a single ue. A resource block in the control portion can be allocated to the UE for transmitting control information to the eNodeB. The resource blocks in the data portion can also be allocated to the UE for transmitting data to the eNodeB. The UE may send control information in the physical uplink control channel (pUCCH) on the resource block in the allocated control portion. The UE may only send data or send both data and control information on the resource blocks in the allocated data portion in the Physical Uplink Shared Channel (PUSCH). As shown in Figure 3, the uplink transmission can span the two time slots of the sub-frame and can jump in frequency. According to one aspect, in a less stringent single carrier operation, parallel channels can be transmitted on the UL k source. For example, the UE can send a control channel and a data channel, parallel control channels, and parallel data channels. PSC, SSC, CRS, PBCH, PUCCH, PUSCH, and other such signals used in lte/_a in the 3GPP TS 3 6.211 file entitled "Evolved Universal Terrestrial Radio Access (E-UTRA); Physical Channels and Modulation" And the channel is described, the 15 201246803 document is publicly available. 4 illustrates a block diagram of a design of base station/eNodeB 110 and UE 120, where base station/eNodeB 110 and UE 120 may be one of the base station/eNodeBs of FIG. 1 and one of the UEs, respectively. The base station 11A may be the macro eNodeB 110c in Fig. 1, and the UE 120 may be the UE 120y. The base station 11 can also be some other type of base station. The base station 110 can be equipped with antennas 434a through 434t' and the UE 120 can be equipped with antennas 452a through 452r. At base station 110, transmit processor 420 can receive data from data source 412 and receive control information from controller/processor 440. The control information may be for PBCH, PCFICH, PHICH, PDCCH, and the like. The data can be for PDSCH and the like. The processor 42 can process the data and control information (e.g., encoding and symbol mapping) to obtain the data symbols and control symbols, respectively. The processor 42A can also generate reference symbols (e.g., for PSS and SSS) and cell-specific service area-specific reference signals. If feasible, a 'transmission (TX) multiple-input multiple-output processor 430 may perform spatial processing (eg, pre-coding) on data symbols, control symbols, and/or reference symbols, and may provide an output symbol stream to the modulator. (MODs) 432a to 432t. Each modulator 432 can process a respective output symbol stringer (e.g., for 〇FDM, etc.) to obtain an output sample stream. Each modulator 432 can further process (e.g., convert to analog, amplify, sweep, and upconvert) the output sample stream to obtain a downlink signal. The downlink of the modulators 432a to 432t can be transmitted via the antennas 434a to 434t. 16 201246803 At UE 120, antennas 452a through 452r may receive downlink signals from base 纟ιι and may provide received signals to demodulators (DEMODs) 454a through 454r, respectively. Each demodulator 454 can condition (e. g., filter, amplify, downconvert, and digitize) the respective received signals to obtain input samples. Each demodulator 々Η can process the input samples (eg, 'for _M, etc.') to obtain the received symbols 456. The 416 can be obtained from all the demodulators. Feasible, the detector (4) can perform MIM detection on the received symbols and provide the symbol of the debt measurement. Receive processor 458 can process (e.g., demodulate, deinterleave, and decode) the detected symbols to provide decoded data for UE 12A to data slot 46G and provide decoded control information to control / processor 480. On the uplink, at the UE 12, the transmit processor 4M can receive and process the data from the data source 462 (eg, for (d) (8) and control information from the controller/processor (eg, for PUCCH). 464 φ may generate a reference symbol for the reference signal. If feasible, the symbols from the transmit processor 464 may be precoded by the TX MIM0 processor 466 for further processing by the demultiplexers 454a through 454r (eg, for SC-FDM calculations, And pulling and transmitting to the base station 110. At the base station 11 ,, the uplink link signal from the UE 12 〇 ± Α U can be received by the antenna 434, by the demodulator 432, the mountain Α/ΓΤΧ, ~ reason ΜΙΜΟ Detector 436 detects (if applicable) and is further processed by receive processor 438 to obtain decoded data jitter control information transmitted by UE 120. Processor 438 may The data of the decoded 17 201246803 is provided to the data slot 439, and the decoded control information is provided to the processor/processor 44. The base station 1 can transmit to other base stations, for example, on the X2 interface 44 i . The controllers/processors 440 and 480 can direct operations at the base station 110 and the UE 120. The processor 440 and/or other processors and modules at the base station can perform or direct the techniques described herein. Implementation of various processes. The processor 48 and/or other processors and modules at the UE 120 may also perform or direct the use of the force month b block illustrated in the method flow diagram (Fig. 8) and/or Implementation of other processes of the described techniques. Memory 442 and 482 can store data and code for base station 11 and UE 12, respectively. Scheduler 444 can be used for data transmission on the downlink and/or uplink. Scheduling the UE. Parallel deinterlacing of LTE interlaced data Figure 5 illustrates an exemplary wireless device 500 that is configured to implement channel processing consistent with various aspects. The beta wireless device 5 can be a user equipment (UE) Or a portion of the UE, and/or a base station (eg, 6Ν〇&Β and access point, etc.) or a base station. The wireless device 5(10) may be in various wireless communication networks (eg, but not limited to 3Gpp long term evolution) Network, 3GPP LTE -A, network, WCDMA network, HspA network, cdma network, WiMAX network, etc. The wireless device 500 can contain a coded stomach 〇2, the latter from a higher layer (eg, media access _ layer) The receive data transfer area & transport block can be divided into code blocks. The encoder 502 can encode the code block to generate a set of code blocks. In one example, the encoder 5 〇 2 can implement Twh 18 201246803 encoding; however, it should be understood that other encoding techniques may also be employed. The set of coded blocks may be provided to the rate matching module 5 〇4, and the rate matching module 504 may extract the set of bits actually extracted by the rate matching module 504 from the set of coded blocks. The element is provided to modulator 506 for modulation and, after modulation, to transmitter 5〇8 for transmission over the wireless link. Figure 6 illustrates an exemplary data flow illustrating the above described procedure. As shown in FIG. 6, the transport block 6〇2 can be divided into code blocks 6〇4. The code blocks are sent to an encoder 502 where they are encoded into code blocks 6〇6. The coding block (illustrated as coding block 〇 to coding block M-1) is sent to the rate matching device 5, and the rate matching device can perform rate matching and interleaving. As described below, interleaving is a process by which bits are reorganized in a data block to reduce the effects of interference. In wireless communication systems, various techniques can be employed to increase the likelihood that a wireless signal will be correctly transmitted and received and communication will not be interrupted. One such technique involves the data group before being transmitted by a transmitting entity (e.g., a [base station]). The group is re-ordered, and then finally re-engaged by the receiving entity (e.g., UE). The process of reordering information prior to transmission is called interleaving. The process of returning information to order after reception is called deinterlacing. The benefit of interleaving is to reduce the impact of potential interference on the transmitted signal. In the absence of interleaving, if the part of the data transmission encounters interference (or other transmission error) and is not received by the receiving entity, then all the lost data will be located in the data part of the data signal. When the same part of 201246803 loses too much information, it may be difficult for ue to correct the feed, which may result in the interruption of wireless communication. If the - part of the interlaced signal is lost before receiving, all missing data does not necessarily come from the same data group. If the lost part of the data is discontinuous, the receiving entity (UE) can more easily correct the lost data without interfering with the wireless communication. For example, if the data bit 〇 _149 is sent in order, and the transmission 4 is lost, then it may be difficult to solve the 5 missing consecutive data bits (3, 31, 32, 33, and 34). And communication interruption may occur. But 'if the data bits M49 are interleaved before transmission, the data bits can be ordered such that consecutive data bits can be transmitted at different times from each other (eg, the transmission may be a data bit) 3, 22, 43, 59, 67, 75, 88, %, 4, and 27). Therefore, the right transmission of 3 0 - 3 4 is awkward, and the target transmission may correspond to a non-contiguous position 7G (for example, 〇1 1 _, a 3 20 57 , 81 and 98) If the missing data is not continuous, the UE can better correct the lost data' to avoid communication interruption. In order to correctly interleave and deinterlace, the method of reordering the data group by the transmitter is known to the receiver so that the data can be correctly reordered at the receiving end for further information. deal with. Different wireless transmission networks may use different interleaving schemes. For purposes of illustration, this document describes interleaving performed by Long Term Evolution (LTE) communications, but other interleaving schemes may be used. As shown in FIG. 6, in LTE, the coded bit sequence is divided into three data 20 201246803 Streaming System (S) 608, Co-located 1 (P1) 610, and Co-located 2 (p2) 6i2 Typically, the system bit is first inserted. The element is then inserted alternately into the first and 苐_ parity bits. The streams are interleaved as indicated by blocks 614, 616 and 618.纟 LTE, the same position! And the parity 2 sequence are combined in the interleaving period. Since & 'after interleaving, there is a coded interleaving block 620 and co-located of system bits! And the two coded interleaved blocks 622 and 62 of the parity 2 bits are stored in the body position in the rate matching module. ° μ In lte, the interleaved stream is then sent to the circular buffer for storage and rate 8&. Rate matching is a process by which the number of bits to be transmitted matches the available bandwidth of the number of bits allowed to be transmitted. In some instances, the amount of data that needs to be sent is less than the available bandwidth 'in this case' all data that needs to be sent (and one or more copies of the material) will be sent (this technique is called duplication) ). In other instances, the amount of data that needs to be sent exceeds the available bandwidth, in which case some portion of the material that needs to be sent will be ignored without transmission (this technique becomes punctured). Typically, LTE material matching is accomplished using a circular buffer 626 as shown in FIG. The interleaved bits are stored in a circular buffer in a sequence of interleaved system bits followed by alternating interleaved P1 and interleaved P2. After the interleaved bits are stored in the circular buffer, then the interleaved bits are read (four) modulator 5Q6. The number of bits transmitted depends on the result of the rate match. The upper layer can indicate which parts of the material that the lower layer needs to send will be punctured and which parts will be sent by 21 201246803. The above instructions may include the starting bit position in the circular buffer and the number of bits to be transmitted. For example, the starting point 628 in the circular buffer can be indicated along with an indication of the number of bits that need to be read. This number can correspond to the available transmission bandwidth. Subsequently, the bits in the circular buffer 626 are read out in the following order: starting from the first bit position 628, and then surrounding the circular buffer 626 (as shown, the reading is in a clockwise direction, but This direction is not necessary) until the end bit position 63〇 is reached. Any bit that is not required to be transmitted in the loop buffer is considered to be the punctured bit 632, and the punctured bits are not read out from the rate matching module 5〇4 to the modulator 506. If the available bandwidth exceeds the number of bits to be transmitted, the bit can be read again from the circular buffer to fill the allocated transmission bandwidth. During this iteration, certain bits of the circular buffer may be read more than once. As shown in Figure 6, in LTE, the rate matching module can perform cyclic buffer based rate matching on a per code block basis. The location of the data in the LTE circular buffer may depend on the row-column rectangular organization of the delta, pi, and P2 bits. The use of circular buffers (although common in LTE) consumes additional resources (including additional memory). This case provides a method and implementation that avoids the use of circular buffers in LTE communications and equipment. Instead of reading data from the circular buffer to the modulator, the data can be read directly from the output of the interleaving process (e.g., directly from blocks 614-618 or blocks 620-624 shown in Figure 6). In this way, additional steps and additional hardware can be removed from the interleaving and rate matching process, thus improving system performance 22 201246803 and reducing resource usage for such tasks. Equipped with:: It is expected that the output format obtained from using the circular buffer will be matched, and (or the appropriate component) can be obtained for the rate t ^ of the % buffer to be 曰 π (for example, They are deducted from the upper layer 7)' and the instructions are translated into instructions to read the material from the interleaved block in a manner that mimics the expected output from the circular buffer. For example, the improved rate matching module can indicate the starting bit in the interleaved block for reading and the location of subsequent bits that need to be read. The data that may be contiguous in the circular buffer is not necessarily contiguous in the interleaved data block, thus causing the data to be read out in a different order than the interleaved data block. Translating the memory locations expected from the circular buffer into interleaved memory locations allows the data to be sent directly to the modulator after interleaving without the need for a circular buffer. In one aspect, rate matching module 504 can include rate matching engine 700 as shown in FIG. The rate matching engine 700 can be used to implement the method described above for performing interleaving and rate matching' while circumventing the circular buffer and still maintaining the traffic specification associated with LTE. According to the illustrated example, rate matching engine 700 includes the inputs and outputs described in Table 1 below. Name Type Description CLK Input The clock signal that drives the synchronization logic. Reset Input Sets the trigger to a synchronous reset of the known state. 23 201246803 Name Type Description ENC_NEW_CO DEBLOCK Input The high level pulse of one clock is continued during the first data transfer of the code block. ENC_DATA_V ALID Input Drives high to indicate that the encoder data and control signals are valid on this clock. Xk Input The data stream corresponding to the system bit in the four data streams output by the encoder (except during the tail bit). Xk, Inputs a stream of data that is only made during the tail bit of the four data streams output by the encoder. Zk Input A stream of data corresponding to the same 1-bit in the four data streams output by the encoder (except during the tail bit). Zk, Input A data stream corresponding to the same 2 bits in the 4 data streams output by the encoder (except during the tail bit). 24 201246803 Name Type Description K_QPP Input The size of the block in bits. It can vary between 40-6144. ENC_DATA_VALID is valid for high timing. RV Enter the redundancy version of the code block. Change between 0 - 3 . ENC_DATA—VALID is high and on time. NUM_XMIT_B ITS Input The number of bits from the encoded data that need to be forwarded to the modulator after rate matching. ENC_DATA_VALID is high and is valid on time. NCB Input The size of the circular buffer in bits. NUM_FILLER _BITS Enter the number of padding bits at the beginning of each of the Xk and zk data streams. Possible values are {0, 8, 16, 24, 32, 40, 48, 56}. ENC_DATA_VALID is high and is valid on time. 25 201246803 Name Type Description NUM_DUMMY Input The number of dummy bits added to the data stream when interleaving is performed so that the total number of bits in the interleaver is a multiple of 32. COL_SEL Internal Select the column to be read at a specific point in time. Inside the BUF_SEL At a specific point in time, a selection is made between the system bit, the parity 1 bit, and the parity 2 bit for reading. RD_ADDR Internal Read address based on the line number being read at a specific point in time ° 26 201246803

Name Type ~_ Description RM_HALT Rounding If the rate matching engine cannot accept a new code block, it is set to a high level by the rate matching engine on the last clock edge of the code block. The encoding engine waits for the signal to go low before the encoding engine can begin transmitting code blocks. As soon as the encoding engine begins to transmit the code block, it ignores the signal until the next code block. ------- RM_DATA_VA Rounding is set to a high level to indicate the presence of valid data on the LID RM-DATA bus. RM_CB_STAR Round---~-_ Continuously one clock is set to the level D RM_CB_END when the first valid resource of the code block is transmitted ~------------- ------- A clock is set to a high bit during the last valid data transfer of the code block. --~--J 27 201246803 Name ------ Type Description RM_NUM_BIT Rounded Out Effective when rm_cb__end and S_VALID rm_data_valid are asserted' and indicates the number of valid bits on the last data transfer of the code block. It is equal to (NUM_XMIT_BITS mod 16) ° RM_DATA Output The rate data sent to the modulator J---- the output data. The input of the i-rate matching engine 700 and the input of the rate matching engine are shown on the left hand side of Figure 7 as a data bit stream 702 from the encoder. Each stream can contain i 6 bits, (for large code blocks (eg, greater than 248 bits), data can be received on all &amp; 16 bits for small code regions The data is received on the block and the bits. The hardware 700 can receive the data of the code block at the low bit coder 504 each time, as shown in the figure, at a rate of 16 bits per clock cycle. Receiving. Input 16 bits per clock cycle to make the final round of the hardware full of throughput requirements. This results in the storage structure 71〇 illustrated in ® 7. Alternatively, a single pipeline structure can be used Or an alternate number of bit rate matching engines for each clock cycle (4) control resources associated with the (four) block: for example, code block length and redundancy version) and bits that need to be forwarded to modulator 506 after rate matching The number of yuan. 28 201246803 Data stream is divided into system, same and parity 2, in which system bit YS) is not the input of the upper part of Figure 7 'Peer 1 bit (P1) is displayed as the middle of the figure ... the same position 2 bits ( P2) is displayed as the input at the bottom of the figure. As an example, the system stream is discussed in detail, and the same and the same 2 hardware power month package also works in a similar manner. The encoded input elements are sent to the deferred storage element _ 704 to ensure that the interleaving in the eLTE that is sufficient for the data stream to be interleaved depends on the row and column format. Therefore, in order to ensure correct interleaving, it is necessary to save a sufficient number of bits. Once the sufficient amount of data has been received, the data is stored and reordered as shown in hardware blocks 7〇6 and 7〇8 to convert the data into an interleaved format. The interleaved data is then passed to the memory buffer bank 7 for storage. Select g7i6 to select interleaved data from the INTLV RAM memory block, and selector 716 locates the data and reads the data in a manner that is translated to match the data that should have been read from the circular buffer. The interleaver memory for each stream contains two buffers to support simultaneous reading and writing of the interleaver memory without collision. As shown, the flag (large_cb) 714 indicates whether the code block is large (e.g., more than 248 bits) or small. If the code block is smaller for system streaming, then after reordering, the first 16 lines of data are also filled into dedicated memory block 712 (8 lines for co-located 1 stream or co-located 2 stream) ). The dedicated memory block copies the first few lines of interleaved data to prevent access to the same memory block twice in the same clock cycle. ^ If the size of the Kawasaki block is large, the upper layer data stream can also be used. For smaller code blocks 29 201246803, it is also possible to not use the intermediate storage block 7〇4. In one example, the system interleaver memory corresponding to the system data stream can contain 16 libraries, each with 13 locations. A location can be ^bit width. The co-located interleaver memory corresponding to the first and second co-located streams may contain 8 banks, each having 26 positions. In a pattern, the "larger code blocks" data are written to the interleaver memory in the order in which they are received. For example, [the write indicator at the beginning of the code block points to the location of the bank in the interleaver memory. After each write (for example, after 32 bits are written to the location indicated by the write indicator), the write indicator moves forward. Before moving to position 1 of the library, write the indicator "position 0 across all libraries. The Writer indicator continues the loop until all bits of the code block are received from encoder 502. Each bit position in the position of the interleaver memory corresponds to a column. For example, the bit position 〇 corresponds to column 0. For smaller code blocks, the data can be rearranged and stored in an external register based on specific row and column interchanges. After receiving the complete code block, the contents of the external register are transferred to the interleaver memory. After the complete code block is stored in the interleaver memory, the rate matching engine 700 can read the data to the modulator 5% in the interleaved order. In one example, the data can be read in the order of the bit flip column. In one aspect, the rate matching engine can include an architecture that causes the data to be shunted out to the modulators 3〇6 in a bit flip column order. ^ The order of the columns represents the bit flip of the column number. For example, column 1 can be represented as a binary digit 0000 of 5 digits, and the bit sequence is reversed to obtain 30 201246803 10000, which represents 16 of the binary. Therefore, the columns of the interleaver memory can be sold in the order of 卞: {0,16,8,24,4,20,12,2 8,2,18,10,26,6,22,14, 3 0,1,17,9,25,5,21 ,13,29,3,19,11,27,7,23,15,31}. The starting point of the reading can be determined based on the redundancy version (RV) value, the buffer size (Kw), and the circular buffer size (Ncb). Table 2 provides possible starting point values for various parameter values. Ceil(12Ncb/Kw) RV Number of columns to skip = 2*ceil(12Ncb/Kw)*RV+2 Start column number Start column position from the beginning of the buffer Start buffer Any 0 2 8 2 System 5 1 12 6 12 System 31 201246803 5 2 22 13 22 System 5 3 32 0 0 Co-located 6 1 14 14 14 System 6 2 26 11 26 System 6 3 38 24 3 Co-located 7 1 16 1 16 System 7 2 30 15 30 System 7 3 44 12 6 Co-located 8 1 18 9 18 System 8 2 34 16 1 Co-located 8 3 50 18 9 Co-located 9 1 20 5 20 System 9 2 38 24 3 Co-located 9 3 56 6 12 Co-located 10 1 22 13 22 System 10 2 42 20 5 Identical 10 3 62 30 15 Identical 11 1 24 3 24 System 11 2 46 28 7 Isomorphic 11 3 68 9 18 Iso 12 1 26 11 26 System 12 2 50 18 9 Iso 12 3 74 21 21 Iso s 32 201246803 Table 2 - The starting point column indicator read is initialized to the starting column of the starting buffer. The read location (e. g., line number) can be initialized to point to the first entry in the starting column. In one example, rate matching engine 700 can read 16 bits per clock cycle starting at that point. The 丨6 bits contain one bit from each bank of each interleaver memory. When the number of available bits in the column is less than 16, the remaining bits can be read from the next bit flip column number in the bit flip order. FIG. 8 is a diagram illustrating rate matching according to an aspect of the present disclosure. As indicated by block 802, a stream of data is received from the encoder. As shown in block 8.4, the data stream is written to the memory. As shown in block 8〇6, parent error and rate matching are performed on the data stream. As indicated by block 808, the interleaved and rate matched data is read in an order that is formatted as an analog output from the circular buffer. In one configuration, the apparatus configured for wireless communication includes means for receiving a stream of data from an encoder, means for writing a stream of data to a memory, and for performing interleaving of the stream of data streams A rate matching component, and means for reading interleaved and rate matched data in an order that is formatted to be analogous to the output from the circular buffer. In one aspect, the components of the description may be the transmit processor 420, the transmit processor 464, the controller/processor 440, the controller/processor 48, the rate matching module 5〇4, and the rate matching engine 700. In another aspect, the above-described components can be configured to execute a module or any device that performs the functions described herein. It will be further understood by those skilled in the art that the brain software or a combination of both can be implemented in conjunction with the various exemplary logical blocks, modules, spurs, and nasal steps described in the present disclosure. The relationship between the body and the software can be used to describe the hard block, the die, and the above-mentioned various illustrative components, and the steps of the material are all integrated with this function. Tian Shu·Yueyue 匕疋 is realized as a hardware or a software application and a whole 糸 silk, 疋 疋 疋 可以 可以 可以 。 。 。 。 。 。 。 。 。. Those skilled in the art will be able to implement the described work in a modified manner for each particular application, but such implementation decisions should not be construed as a departure from the scope of the invention. The various illustrative logic blocks, modules, and circuits described in connection with the present disclosure can be implemented or implemented by the following elements: general purpose, digital signal processor (DSP), special application integrated circuit (Asic), field programmable array (FPGA) or other programmable logic device, individual closed or transistor logic, individual hardware components, or any combination thereof designed to perform the functions described herein. The general purpose processor may be a microprocessor, but alternatively, the process The device can be any conventional processor 'controller, microcontroller or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a Dsp and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core or any other similar configuration. The steps of the method or algorithm described in connection with the present invention can be directly embodied as a hardware, a software module executed by a processor, or a combination of both. The software module can be located in RAM memory, flash memory, rom memory, epr〇m memory, EEPROM memory, scratchpad, hard disk, removable disk, CD-ROM, or any of those well known in the art. Other forms of storage media. An exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and can write information to the storage medium. Alternatively, the storage medium can also be integrated into the processor. The processor and storage media X can be located in the ASIC. The ASIC can be located in the user terminal. Alternatively, the processor and the storage medium may also be present in the user class as individual components. 'In one or more exemplary designs, the functions described herein may be implemented in hardware, software, work, or any combination thereof. If implemented in software, the functions can be stored or transferred to computer readable media as one or more instructions or codes on a computer readable medium. Computer-readable media consists of both computer-storage media and communication media, which contain any media that facilitates the transfer of computer programs from one place to another. The storage medium can be any available media that can be accessed by a general purpose or special purpose computer. By way of example and not limitation, such computer-readable media may contain fun, face, EEPR〇m, cd_r〇m or other optical disk storage or other magnetic storage device, or can be used for carrying or storing The desired code component in the form of an instruction or data structure and any other medium that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. In addition, any farther than ι, human white can be called computer readable media. For example, if the software is using coaxial cable, fiber optic TEM, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, strobos, or other wireless technology from a website, server, or other remote station. Then, coaxial power, fiber optic power, twisted pair, cymbal or wireless technologies such as infrared: radio and microwave are included in the definition of the media. The disks and optical discs used in this case include dust-reducing discs (cd), cone-shaped light 35 201246803 discs, optical discs, digital versatile discs (DVDs), floppy discs and Blu-ray discs, in which the discs are usually magnetically reproduced, while the discs are used. The laser optically reproduces the data. The above combinations should also be included in the scope of computer readable media. The description of the present application is provided to enable any person skilled in the art to make or use the present invention. Various modifications to the present invention will be obvious to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope or spirit of the invention. Accordingly, the present invention is not limited to the examples and designs described herein, but rather the broadest scope consistent with the principles and novel features disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS The features, nature and advantages of the present invention will become more apparent from the detailed description set forth in the <RTIgt; The symbols denote the same components, and FIG. 1 is a block diagram conceptually illustrating the actions of the singularity. Fig. 2 is a block diagram conceptually illustrating an example of a downlink frame structure in a mobile printing system. Figure 3 is a block diagram conceptually illustrating an exemplary frame structure in an uplink, a μ + 仃 link communication. The configuration of the configuration is implemented to implement the channel. FIG. 4 is a conceptual diagram not according to the present invention - a block diagram of the design of the platform/eNodeB and the UE. FIG. 5 illustrates an aspect according to the present aspect. A block diagram of an exemplary wireless device. 36 201246803 Figure 6 illustrates a block diagram of an exemplary data stream in accordance with the present invention. Figure 7 illustrates a block diagram in accordance with the present invention. An exemplary loop buffer rate matching 示例 示例 示例 m m 返 返 返 返 匹配 匹配 匹配 匹配 图 图 图 图 图 图 图 图 图 图 图 图 图 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 [Main component symbol description]

100 wireless communication network 102a macro cell service area 102b macro cell service area 102c macro cell service area 102x pico cell service area 102y femto cell service area 102z femtocell service area 110 eNodeB 110a eNodeB 110b eNodeB 110c eNodeB llOr relay station llOx eNodeB llOy eNodeB llOz eNodeB 120 UE 37 201246803 120r 120y 130 412 420 430 432a 432t 434a 434t 436 438 439 440 441 442 444 452a 452r 454a 454r 456 458 460

UE

UE Network Controller Data Source Processor Transmit (TX) Multiple Input Multiple Output (ΜΙΜΟ) Processor Modulator Modulator Antenna Antenna Detector Receive Processor Data Slot Controller/Processor Χ 2 Interface Memory Scheduler Antenna Antenna demodulator demodulator ΜΙΜΟ detector receiver processor data slot 38 201246803 462 464 466 480 482 500 502 504 506 508 602 604 606 608 612 614 616 618 620 622 624 626 628 Data source processor ΜΙΜΟ ΜΙΜΟ processor Controller/processor memory exemplary wireless device encoder rate matching module modulator transmitter transmission block code block coding block system (S) parity 1 ( Ρ 1 ) parity 2 ( Ρ 2 ) block block Interleaved block interleave block interleave block loop buffer start point/first bit position 39 201246803 630 End bit position 632 Delimited bit 700 Rate matching engine 702 Data bit stream 704 Delay Storage element 706 hardware block 708 hardware block 710 memory buffer bank 712 dedicated memory block 714 flag, (large_cb) 716 802 block 804 block 806 block 808 block s 40

Claims (1)

201246803 VII. Patent application scope: 1. A method for rate matching in a long-term evolution (LTE) wireless communication system, the method comprising the steps of: receiving a plurality of data streams from an encoder; The stream is written to the memory; the interleaving and rate matching of the plurality of data streams is performed; and the interleaved and rate matched data is read in an order formatted from the _output of the circular buffer. 2' The method of claim 1 further comprising the step of: determining the read step by translating a start bit of a = ring buffer into a start bit of the interleaved and rate matched material A starting bit. 3 -&gt;. The method of claim 1, wherein the order of the readout steps corresponds to - the bit flip column order. The method of clause 1, wherein the interleaved and rate matched data is read for transmission. The method of claim 4, wherein the interleaved and rate matched data is directly read out to the modulator. 6 - using &gt;_ in the long-term evolution (LTE) wireless communication system for speed 201246803 rate matching device, the device comprising: means for receiving a plurality of data streams from an encoder; The plurality of data streams are written to the memory component; .V is used to perform the interleaving and rate matching of the plurality of data streams; and is used for a round out of a circular buffer according to the format. The components of the interleaved and rate matched data are read out in sequence. 7. The apparatus of claim 6, further comprising: determining a start of the read by translating a start bit of a circular buffer into a start bit of the interleaved and rate matched data The component of the bit. 8. The apparatus of claim 6, wherein the order of the reads corresponds to the - bit flip column order. 9. The apparatus of claim 6, wherein the interleaved and rate matched data is read for transmission. 10. The apparatus of claim 9, wherein the interleaved and rate matched data is read directly to a modulator. • 11 _ - a computer program product for speed and rate matching in a long-term evolution (LTE) wireless communication system, the computer program product includes: ~~ non-transitory computer readable media, which has recorded in it The non-transitory code on the program code includes: 42 201246803 a code for receiving a plurality of data streams from an encoder; and a code for writing the plurality of data streams into the memory; a program code for performing interleaving and rate matching of the plurality of data streams; and a program for reading the interleaved and rate matched data in accordance with a rounded item sequence formatted from a circular buffer code. 12. The computer program product of claim 9, wherein the code step further comprises determining to convert a start bit of a circular buffer into a start bit of the interleaved and rate matched data. The read-out code of the start bit. 13. The computer program product of claim u, wherein the sequence of readings corresponds to a one-dimensional flip column order. 14. The computer program product of claim u, wherein the interlaced and captured rate data is read for transmission. 15. The computer program product of claim 14, wherein the interleaved and rate matched data is read directly to a modulator. ► - 16. An apparatus for rate matching in a long term evolution (LTE) wireless communication system, the apparatus comprising: a memory; and 43 201246803 at least one processor coupled to the memory, the at least one The processor is configured to: receive a plurality of data streams from an encoder; write the plurality of data streams into the memory; perform interleaving and rate matching of the plurality of data streams; and use an analogy from the format An order of an output of the circular buffer is used to read the interleaved and rate matched data. 17. The apparatus of claim 16, wherein the at least one processor is further configured to determine the read by translating a start bit of a circular buffer into a start bit of the interleaved and rate matched data. A starting bit. 18. The apparatus of claim 16, wherein the order of the reads corresponds to a one-bit flip column order. 19. A device for requesting jg wherein the parental and rate matched material is read for use in a pass. 2 0 _ As for the device requesting jg 1 Λ 4, wherein the interleaved and rate matched data is directly read out to 调制 4 to a modulator. 44