201244570 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路板及其製作方法，且特別是 有關於一種可降低成本的線路板及其製作方法。 【先前技術】 近年來，隨著電子技術的日新月異，高科技電子產業 的相繼問世，使得更人性化、功能更佳的電子產品不斷地 推陳出新，並朝向輕、薄、短、小的趨勢設計。在這些電 子產品内通常會配置用來安裝電子元件於其上的線路板。 在一般的線路板製程中，通常是先於其上具有第一線 路層的基板上形齡電層。然後，於介電射形成暴露出 部分第-線路層的盲孔。接著，於介f層以及盲孔所暴露 2第-祕層上形油層。錢，於鋪上形成圖案化 層之後以圖案化軍幕層為I虫刻罩幕，對銅層進行 蝕刻製程，以形成第二線路層。 製財，由於形成第二⑽層時需進 製程’因此必須花費較高的成本，且所 2的_齡對魏造成㈣。 電層的附著力較差，因Μ且“ 不佳的_。 自介電層剝離而造成可靠度 【發明内容】 本發明提供一種線路板的製作方法，其可以有效地降 201244570 低生產成本。 本發明另提供一種線路板，其具有較高的可靠度。 本發明提出-種線路板的製作方法，其是先提供其上 具f線路層的基板。雜，於基板上形成介電層。介電層 ，蓋線路層’且具有暴露&部分線路層的盲孔。接著，於 介電層上共形地形成硫化層。而後，於硫化層上形成圖案 化罩幕層。圖案化罩幕層暴露出盲孔與部分硫化層。繼之， 於圖案化罩幕層所暴露的硫化層與線路層上形成第一觸媒 層。隨後，移除圖案化罩幕層以及圖案化罩幕層下方的硫 化層。接著，進行第一化學沈積，以於觸媒層上共形地形 成第一導電層。之後，進行第二化學沈積，以於第一導電 層上形成第二導電層，第二導電覆蓋第一導電層。此外， 第一導電層填滿盲孔。 依照本發明實施例所述之線路板的製作方法，上述之 電層的形成方法例如是先進行壓合步驟，以於基板上形 成介電層與金屬層，其中介電層位於基板與金屬層之間。 然後，移除金屬層。之後，進行雷射鑽孔步驟，以於介電 層中形成盲孔。 依照本發明實施例所述之線路板的製作方法，上述在 形成盲孔之後以及在形成硫化層之前，還可以對介電層以 及盲孔所暴露的線路層進行表面處理。 依照本發明實施例所述之線路板的製作方法，上述之 表面處理例如是進行去膠漬(desmear)製程和/或粗糖化製 201244570 依照本發明實施例所述之線路板的製作方法，上述之 觸媒層的材料例如為鈀。 依照本發明實施例所述之線路板的製作方法，上述< 觸媒層的形成方法例如是進行第三化學沈積。 依照本發明實施例所述之線路板的製作方法，上述< 硫化層的形成方法例如是對介電層進行硫化處理。 本發明另提出一種線路板，其包括其上具有第—線$ 層的基板、介電層、硫化層以及第二線路層。介電層配置 於基板上並覆蓋第一線路層，且介電層具有盲孔。盲孔暴 露出部分第一線路層。硫化層共形地配置於部分介電^a 上。第二線路層配置於硫化層以及盲孔所暴露的第—線: 層上。第二線路層包括觸媒層、第一導電層以及第二導電 層。觸媒層共形地配置於硫化層以及盲孔所暴露的第—線 路層上。第一導電層共形地配置於觸媒上。第二導電層配 置於第一導電層上且覆蓋第一導電層。此外，第二導^層 填滿盲孔。第二導電層的位於盲孔中的部分具有凹陷，I 此凹陷的深度小於或等於5 μιη。第二導電層的邊緣超出其 下方的第一導電層的邊緣的距離為X，位於介電層上的第 二導體層的厚度為Υ，且Υ與X的比值介於6至1〇之間。 依照本發明實施例所述之線路板，上述之觸媒層的材 料例如為la。 依照本發明實施例所述之線路板，上述之第一導電層 的材料例如為錄β 依照本發明貫施例所述之線路板，上述之第二導電声 201244570 的材料例如為銅。 依照本發明實施例所述之線路板’上述之第二導電層 的邊緣超出其下方的第一導電層的邊緣的距離例如介於2 μιη至3 μιη之間。 基於上述，本發明於介電層上形成線路層時，先於介 電層上形成硫化層’再以具有線路圖案的圖案化罩幕層為 罩幕來進行化學沈積，以於硫化層上形成觸媒層。然後， 移除圖案化罩幕層及其下方的硫化層。接著，進行化學沈 積而於觸媒層上形成與觸媒層產生化學鍵結的第一導電 層。之後，進行化學沈積而於第一導電層上形成第二導電 層。因此，所形成的線路層（由觸媒層、第一導電層與第二 導電層構成）即可具有所需的線路圖案，而不需額外地利用 蝕刻製程來進行圖案化，因而降低了生產成本，且避免對 環境造成污染。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例’並配合所_式作詳細說明如下。 【實施方式】 夕至圖1D為依照本發明實施例所繪示的線路板 7〇=剖面圖。首先’請參照®1 lA，提供具有線路層 a Γ _。基板100例如為介電核心、（dieiectric _)。 彼此相對的第—表面1術與第二表面 路層腿配詈3-咖配置於第一表面驗上，而線 ;第二表面i〇〇b上。線路層i〇2a、102b 7 201244570 的材料例如為金屬。 在本實施例中，基板100為具有二層線路層的基板， 但本發明並不以此為限。在其他實施例中，基板1〇〇中亦 可具有多層線路層。 請繼續參照圖1A，進行壓合步驟，將金屬層1〇如與 介電層104a壓合於基板1〇〇的第一表面1〇〇&上，以及將 金屬層106b與介電層l〇4b壓合於基板1〇〇的第二表面 100b上。介電層i〇4a覆蓋線路層丨〇2a，而介電層i〇4b 覆蓋線路層102b。金屬層l〇6a與金屬層106b的材料例如 為銅。 然後’請參照圖1B，移除金屬層1〇^與金屬層1〇6b。 移除金屬層106a與金屬層l〇6b的方法例如是進行化學蝕 刻和/或機械研磨製程。之後，進行雷射鑽孔步驟，以於介 電層104a中形成盲孔i〇8a，以及於介電層1〇扑中形成盲 孔l〇8b。雷射鑽孔步驟例如是使用二氧化碳(c〇2)雷射來 進行。盲孔108a暴露出部分線路層1〇2a，而盲孔1〇訃暴 露出部分線路層l〇2b。此外，在形成盲孔1〇8a與盲孔1〇8b 之後，還可以對介電層104a、1〇4b以及盲孔1〇8a所暴露 的部分線路層l〇2a與盲孔i〇8b所暴露的部分線路層1〇2b 進行表面處理110。表面處理11〇例如是進行去膠渣製程， 以去除雷射鑽孔後所殘留的樹脂。表面處理110也可以是 進行粗縫化製程，對盲孔腿與_所曝露出的線路層 102a與l〇2b進行微蝕刻，以增加線路層1〇2a與1〇2b的 表面粗糙度，有利於後續金屬鍍層的附著力。此外，上述 201244570 的粗糙化製程也可接續在去膠渣製程之後進行。 接著，請參照圖1C ’於介電層l〇4a上共形地形成硫 化層112a，以及於介電層104b上形成硫化層112b。硫化 層112a、112b的形成方法例如是對介電層1〇如、104b進 行硫化處理。然後’於硫化層112a上形成圖案化罩幕層 114a，以及於硫化層112b上形成圖案化罩幕層n4b。圖 案化罩幕層114a具有線路圖案，其暴露出盲孔1〇8a與部 分硫化層112a。圖案化罩幕層114b具有線路圖案，其暴 露出盲孔108b與部分硫化層112b。圖案化罩幕層U4a與 圖案化罩幕層114b的材料例如是光阻材料。 請繼續參照圖ic，在形成圖案化罩幕層114a、U4b 之後，於圖案化罩幕層114a所暴露的硫化層U2a與線路 層102a上形成觸媒層115a’以及於圖案化罩幕層丨丨仆所 暴露的硫化層112b與線路層i〇2b上形成觸媒層115b。觸 媒層115a、115b的材料例如為鈀。觸媒層U5a、U5b的 形成方法例如為進行化學沈積。 之後，請參照圖1D，移除圖案化罩幕層114a、U4b 及其下方的硫化層112a、112b。移除圖案化罩幕層U4a、 ⑽及其下方的硫化層112a、⑽的方法例如是使用驗 性去膜液，例如氫氧灿。錢，崎化學沈積，以於觸 媒層115a上共形地形成導電層U6a，以及於觸媒層 上共形地形成導電層U6b。導電層116a、U6b的材料例 如為錄。特別一提岐，導電層U6a、可分別與觸媒 層115a、115b產生化學鍵結，因此可以提高導電層116& 201244570 與觸媒層115a之間的附著力以及導電層116b與觸媒層 115b之間的附著力。之後，進行化學鍍處理，以選擇性地 於導電層116a上形成導電層118a，以及選擇性地於導電 層116b上形成導電層118b。導電層118a、118b的材料例 如為銅。在此步驟中’導電層118a、118b僅會形成於導電 層116a、116b上，並且導電層118a、118b分別會完全覆 蓋導電層116a、116b。此外，導電層118a、118b分別填 滿盲孔108a、108b。在本實施例中’導電層U8a及其下 方的導電層116a、觸媒層115a構成線路層12〇a，而導電 層118b及其下方的導電層U6b、觸媒層115b構成線路層 120b。 在本實施例中，由於導電層116a與導電層ii8a的材 料皆為金屬，因此在形成導電層118a之後，導電層U8a 可以有效地附著於導電層116a上。同樣地，導電層iigb 可以有效地附著於導電層116b上。此外，由於導電層116a 與觸媒層115a之間以及導電層116b與觸媒層U5b之間具 有較佳的附著力，因此使得線路層120a可以牢固地配置於 介電層104a上，且使得線路層12〇b可以牢固地配置於介 電層104b上，因而能夠解決線路層自介電層剝離的問題， 進而提高元件的可靠度。 、此外，在本實施例中，在形成觸媒層U5a、115b時， 、、有線路圖案的圖案化罩幕層n4a、1 i^b作為罩幕，因 ^續形成於觸媒層115a、115b上的導電層116a、116b 即具有所需的線路㈣。如此-來，後續選擇性地於導電 201244570 層116a、116b上以化學沈積分別形成導電層U8a、118b 之後’所形成的線路層120a、120b亦具有所需的線路圖 案’而不需再進行蝕刻製程來將線路層120a、12〇b圖案 化，因此可以有效地降低生產成本，且避免蝕刻劑斜環境 造成污染。 乃外一提的是，由於導電層118a、118b是利用化學 沈積來形成，因此可以藉由調整進行化學沈積時的製程= 數來控制所形成的導電層118a、118b寬度與厚度。以下& 以線路層120a為例來作詳細地說明。 圖2為依照本發明實施例所繪示的位於介電層上的線 路層之剖面示意圖。請參照圖2，在利用化學沈積的方式 選擇性地於導電層116a上形成導電層118a時，可藉由绸 整化學沈積的製程參數來控制所形成的導電層118:且: 適當的寬度與厚度。舉例來說，在本實施财，娜 化學沈積的製程參數，使得導電層U8a的邊緣超出龙^ 的導電層116a的邊緣的距離為χ，而位於介電層^ 的導體層118a的厚度為γ，與χ的比值介於 之間。在-實施例中，可將χ控制為介於2帅至 間，並將Υ控制為約20μιη。 μ之 不思圖。請參照圖3’導電層1版的位於盲孔= 、科具有凹陷122。經由調整化學沈積的製程 需:J凹陷m的深度z小於或等於5 μιη，以符合平垣化的 11 201244570 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤御，故本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖1D為依照本發明實施例所繪示的線路板 之製作流程剖面圖。 圖2為依照本發明實施例所繪示的位於介電層上的線 路層之剖面示意圖。 圖3為依照本發明實施例所繪示的位於盲孔中的線路 層之剖面示意圖。 【主要元件符號說明】 100 :基板 100a :第一表面 100b :第二表面 102a、102b、120a、120b :線路層 104a、104b :介電層 106a、106b :金屬層 108a、108b :盲孔 110 :表面處理 112a、112b :硫化層 114a、114b :圖案化罩幕層201244570 VI. Description of the Invention: [Technical Field] The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board capable of reducing cost and a method of fabricating the same. [Prior Art] In recent years, with the rapid development of electronic technology, the high-tech electronics industry has emerged, making more humanized and functional electronic products continue to evolve, and are designed toward light, thin, short, and small trends. A circuit board on which electronic components are mounted is usually disposed in these electronic products. In a typical circuit board process, it is usually preceded by an age-old electrical layer on a substrate having a first wiring layer thereon. Then, a dielectric hole is formed to expose a blind hole of a portion of the first-line layer. Next, the oil layer is formed on the layer of the first layer and the second layer exposed by the blind hole. After the formation of the patterned layer on the paving, the patterned silicon layer is patterned as a mask, and the copper layer is etched to form a second wiring layer. The production of money, because of the formation of the second (10) layer, requires a higher cost, and the age of 2 is caused by Wei (4). The adhesion of the electric layer is poor, because "poor". The reliability of the self-dielectric layer is peeled off. [Invention] The present invention provides a method for manufacturing a circuit board, which can effectively reduce the low production cost of 201244570. The invention further provides a circuit board which has high reliability. The invention provides a method for fabricating a circuit board, which first provides a substrate having an f-line layer thereon, and forms a dielectric layer on the substrate. The electrical layer covers the circuit layer 'and has a blind via exposed & part of the wiring layer. Next, a vulcanization layer is conformally formed on the dielectric layer. Then, a patterned mask layer is formed on the vulcanized layer. The layer exposes the blind via and the partially cured layer. Subsequently, a first catalyst layer is formed on the vulcanized layer and the wiring layer exposed by the patterned mask layer. Subsequently, the patterned mask layer and the patterned mask layer are removed. a vulcanization layer below. Next, performing a first chemical deposition to form a first conductive layer conformally on the catalyst layer. Thereafter, performing a second chemical deposition to form a second conductive layer on the first conductive layer, Two conductive coverage In addition, the first conductive layer fills the blind hole. According to the method for fabricating the circuit board according to the embodiment of the invention, the method for forming the electric layer is, for example, performing a pressing step to form a dielectric layer on the substrate. An electrical layer and a metal layer, wherein the dielectric layer is between the substrate and the metal layer. Then, the metal layer is removed. Thereafter, a laser drilling step is performed to form a blind via in the dielectric layer. In the method for fabricating the circuit board, the dielectric layer and the circuit layer exposed by the blind via may be surface-treated after forming the blind via and before forming the vulcanization layer. The circuit board according to the embodiment of the invention In the production method, the surface treatment described above is, for example, a desmear process and/or a coarse saccharification process 201244570. The method for fabricating a circuit board according to an embodiment of the present invention, wherein the material of the catalyst layer is, for example, palladium. In the method for fabricating the circuit board according to the embodiment of the present invention, the method for forming the catalyst layer is, for example, performing a third chemical deposition. The circuit according to the embodiment of the present invention The method for forming the above vulcanization layer is, for example, a vulcanization treatment on a dielectric layer. The present invention further provides a wiring board including a substrate having a first line layer, a dielectric layer, a vulcanization layer, and a second circuit layer. The dielectric layer is disposed on the substrate and covers the first circuit layer, and the dielectric layer has a blind hole. The blind hole exposes a portion of the first circuit layer. The vulcanization layer is conformally disposed on the partial dielectric ^a The second circuit layer is disposed on the vulcanization layer and the first line: layer exposed by the blind via. The second circuit layer includes a catalyst layer, a first conductive layer, and a second conductive layer. The catalyst layer is conformally disposed in the vulcanization layer. And the first conductive layer is disposed on the first conductive layer and covers the first conductive layer. In addition, the second conductive layer is disposed on the first conductive layer. The layer fills the blind via. The portion of the second conductive layer that is located in the blind via has a recess, and the depth of the recess is less than or equal to 5 μηη. The edge of the second conductive layer has a distance X beyond the edge of the first conductive layer below it, the thickness of the second conductor layer on the dielectric layer is Υ, and the ratio of Υ to X is between 6 and 1 〇. . According to the circuit board of the embodiment of the invention, the material of the catalyst layer is, for example, la. According to the circuit board of the embodiment of the present invention, the material of the first conductive layer is, for example, a circuit board according to the embodiment of the present invention, and the material of the second conductive sound 201244570 is, for example, copper. The distance of the edge of the second conductive layer of the wiring board as described in the embodiment of the present invention beyond the edge of the first conductive layer below it is, for example, between 2 μm and 3 μm. Based on the above, when the circuit layer is formed on the dielectric layer, the vulcanization layer is formed on the dielectric layer and then patterned by using a patterned mask layer having a line pattern as a mask to form a vulcanized layer. Catalyst layer. The patterned mask layer and the underlying vulcanized layer are then removed. Next, chemical deposition is performed to form a first conductive layer on the catalyst layer that chemically bonds with the catalyst layer. Thereafter, chemical deposition is performed to form a second conductive layer on the first conductive layer. Therefore, the formed wiring layer (consisting of the catalyst layer, the first conductive layer and the second conductive layer) can have a desired wiring pattern without additionally using an etching process for patterning, thereby reducing production. Cost and avoid pollution to the environment. In order to make the above features and advantages of the present invention more comprehensible, the following detailed description of the embodiments of the present invention will be described in detail below. [Embodiment] FIG. 1D is a cross-sectional view of a circuit board according to an embodiment of the invention. First, please refer to ®1 lA, which has a circuit layer a Γ _. The substrate 100 is, for example, a dielectric core, (dieiectric _). The first surface 1 and the second surface layer leg are arranged on the first surface, and the line is on the second surface i〇〇b. The material of the wiring layer i〇2a, 102b 7 201244570 is, for example, a metal. In the embodiment, the substrate 100 is a substrate having two circuit layers, but the invention is not limited thereto. In other embodiments, the substrate 1 can also have multiple layers of circuitry. Referring to FIG. 1A, a pressing step is performed to press the metal layer 1 onto the first surface 1 〇〇 & of the substrate 1 ,, and the metal layer 106 b and the dielectric layer 1 The crucible 4b is pressed against the second surface 100b of the substrate 1''. The dielectric layer i〇4a covers the wiring layer 丨〇2a, and the dielectric layer i〇4b covers the wiring layer 102b. The material of the metal layer 10a and the metal layer 106b is, for example, copper. Then, please refer to FIG. 1B to remove the metal layer 1 and the metal layer 1〇6b. The method of removing the metal layer 106a and the metal layer 106b is, for example, a chemical etching and/or mechanical polishing process. Thereafter, a laser drilling step is performed to form the blind vias i 8a in the dielectric layer 104a and to form the blind vias 8b in the dielectric layer 1 . The laser drilling step is performed, for example, using a carbon dioxide (c〇2) laser. The blind hole 108a exposes part of the wiring layer 1〇2a, and the blind hole 1 smashes out part of the wiring layer l〇2b. In addition, after the blind holes 1〇8a and the blind holes 1〇8b are formed, part of the circuit layers l〇2a and blind holes i〇8b exposed to the dielectric layers 104a, 1〇4b and the blind holes 1〇8a may also be used. The exposed portion of the wiring layer 1〇2b is subjected to surface treatment 110. The surface treatment 11 is, for example, a desmear process to remove the resin remaining after the laser drilling. The surface treatment 110 may also be a roughing process for micro-etching the blind via legs and the exposed circuit layers 102a and 102b to increase the surface roughness of the circuit layers 1〇2a and 1〇2b. Adhesion to subsequent metal plating. In addition, the above-mentioned 201244570 roughening process can also be carried out after the desmear process. Next, referring to Fig. 1C', a vulcanization layer 112a is conformally formed on the dielectric layer 10a, and a vulcanization layer 112b is formed on the dielectric layer 104b. The vulcanization layer 112a, 112b is formed by, for example, vulcanizing the dielectric layer 1, for example, 104b. Then, a patterned mask layer 114a is formed on the vulcanized layer 112a, and a patterned mask layer n4b is formed on the vulcanized layer 112b. The patterned mask layer 114a has a wiring pattern that exposes the blind vias 1a and 8a and the partially cured layer 112a. The patterned mask layer 114b has a line pattern that exposes the blind vias 108b and the partially cured layer 112b. The material of the patterned mask layer U4a and the patterned mask layer 114b is, for example, a photoresist material. Referring to FIG. ic, after the patterned mask layers 114a, U4b are formed, the catalyst layer 115a' and the patterned mask layer are formed on the vulcanized layer U2a and the wiring layer 102a exposed by the patterned mask layer 114a. A catalyst layer 115b is formed on the vulcanized layer 112b exposed by the servant and the wiring layer i〇2b. The material of the catalyst layers 115a, 115b is, for example, palladium. The method of forming the catalyst layers U5a, U5b is, for example, chemical deposition. Thereafter, referring to FIG. 1D, the patterned mask layers 114a, U4b and the underlying vulcanization layers 112a, 112b are removed. The method of removing the patterned mask layers U4a, (10) and the vulcanized layers 112a, (10) therebelow is, for example, an experimental de-filming liquid such as oxyhydrogen. Qian, Sasa Chemical deposition, conformally forms a conductive layer U6a on the catalyst layer 115a, and conformally forms a conductive layer U6b on the catalyst layer. The materials of the conductive layers 116a, U6b are for example recorded. In particular, the conductive layer U6a can be chemically bonded to the catalyst layers 115a, 115b, respectively, so that the adhesion between the conductive layer 116 & 201244570 and the catalyst layer 115a and the conductive layer 116b and the catalyst layer 115b can be improved. Adhesion between. Thereafter, an electroless plating treatment is performed to selectively form the conductive layer 118a on the conductive layer 116a, and selectively form the conductive layer 118b on the conductive layer 116b. The material of the conductive layers 118a, 118b is, for example, copper. In this step, the conductive layers 118a, 118b are formed only on the conductive layers 116a, 116b, and the conductive layers 118a, 118b completely cover the conductive layers 116a, 116b, respectively. Further, the conductive layers 118a, 118b fill the blind vias 108a, 108b, respectively. In the present embodiment, the conductive layer U8a and the underlying conductive layer 116a and the catalyst layer 115a constitute the wiring layer 12A, and the conductive layer 118b and the conductive layer U6b and the catalyst layer 115b under it constitute the wiring layer 120b. In the present embodiment, since the materials of the conductive layer 116a and the conductive layer ii8a are both metal, the conductive layer U8a can be effectively attached to the conductive layer 116a after the conductive layer 118a is formed. Likewise, the conductive layer iigb can be effectively attached to the conductive layer 116b. In addition, since the conductive layer 116a and the catalyst layer 115a and the conductive layer 116b and the catalyst layer U5b have better adhesion, the wiring layer 120a can be firmly disposed on the dielectric layer 104a, and the line is made. The layer 12〇b can be firmly disposed on the dielectric layer 104b, thereby solving the problem of peeling off the wiring layer from the dielectric layer, thereby improving the reliability of the element. Further, in the present embodiment, when the catalyst layers U5a and 115b are formed, the patterned mask layers n4a and 1b of the line pattern are formed as a mask, and are continuously formed on the catalyst layer 115a. Conductive layers 116a, 116b on 115b have the desired wiring (4). Thus, the subsequent formation of the conductive layers U8a, 118b by chemical deposition on the conductive 201244570 layers 116a, 116b, respectively, "the formed wiring layers 120a, 120b also have the desired line pattern" without further etching The process is to pattern the circuit layers 120a, 12〇b, so that the production cost can be effectively reduced, and contamination of the etchant oblique environment can be avoided. It is to be noted that since the conductive layers 118a, 118b are formed by chemical deposition, the width and thickness of the formed conductive layers 118a, 118b can be controlled by adjusting the number of processes at the time of chemical deposition. The following & will be described in detail by taking the circuit layer 120a as an example. 2 is a cross-sectional view of a wiring layer on a dielectric layer, in accordance with an embodiment of the invention. Referring to FIG. 2, when the conductive layer 118a is selectively formed on the conductive layer 116a by chemical deposition, the formed conductive layer 118 can be controlled by the process parameters of the silk chemical deposition: and: appropriate width and thickness. For example, in the present implementation, the process parameters of the chemical deposition are such that the edge of the conductive layer U8a is beyond the edge of the conductive layer 116a of the solder, and the thickness of the conductive layer 118a of the dielectric layer is γ. The ratio to χ is between. In an embodiment, the enthalpy can be controlled to be between 2 and ,, and Υ is controlled to be about 20 μm. μ does not think. Referring to Fig. 3', the conductive layer 1 is located in the blind hole = and the branch has the recess 122. The process of adjusting the chemical deposition requires: the depth z of the J recess m is less than or equal to 5 μm to meet the flattening 11 201244570. Although the invention has been disclosed by way of example, it is not intended to limit the invention, any technical field. The scope of protection of the present invention is defined by the scope of the appended claims, and the scope of the invention is intended to be limited by the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are cross-sectional views showing a manufacturing process of a circuit board according to an embodiment of the invention. 2 is a cross-sectional view of a wiring layer on a dielectric layer, in accordance with an embodiment of the invention. 3 is a cross-sectional view of a wiring layer in a blind via, in accordance with an embodiment of the invention. [Description of main component symbols] 100: Substrate 100a: First surface 100b: Second surface 102a, 102b, 120a, 120b: Circuit layers 104a, 104b: Dielectric layers 106a, 106b: Metal layers 108a, 108b: Blind holes 110: Surface treatment 112a, 112b: vulcanization layers 114a, 114b: patterned mask layer
S 12 201244570 115a、115b :觸媒層 116a、116b、118a、118b :導電層 122 :凹陷 X :距離 Y :厚度 Ζ :深度 13S 12 201244570 115a, 115b: catalyst layer 116a, 116b, 118a, 118b: conductive layer 122: recess X: distance Y: thickness Ζ: depth 13