201244003 、發明說明.： 【發明所屬之技術領域】 本舍明係關於一種§己憶體技術，尤指一種具有今形 (circle-segment)剖面之埋入式位元線以及位於埋入式位元線上方之 垂直電晶體的4F2 s己憶體單元，以及埋人式位元線和垂直電晶體的 製作方法。 【先前技術】 為增進積體電路之運作速度且同時符合消肢對於翻化電子 裝置的需求，於轉體裝置之電晶體的尺寸持續縮減。由於電 晶體的尺寸制、，電電子通道區之長度亦隨之減少，因此將 可能造成電晶體發生嚴重的短通效應，以及電晶體之開啟電流 (ON current)的降低。 為解決上述問題，習知技射包括增加電子通之雜濃产^ 作法，細’此作法則減電流的增加，科辦轉體裝^ 可靠度。另-種作法置-垂直電晶體結構，例如··形成垂ρ 晶體結構在基底的輯射，此作法可改善频電路之運作速心 及積集度(integration)，且減缓短通道效應。因此，如何改善= 晶體的結構設計从電子通道區之電流㈣實馳關麵 進之課題。 201244003 【發明内容】 ’ 本發明之目的之一在於提供-種埋入式位元線的結構以及一種 垂直電晶體的結構，以改善積體電路之運作速度及積集度。 本發明之一較佳實施例係提供一種形成埋入式位元線的方法，包 括下列步驟。提供—基底，域底具有-條狀區域(line-shaped region)在基底之條狀區域帽成__條狀溝渠，其巾條狀溝渠具有 侧壁以及絲。然後，加大條狀溝渠之底面，使底面形成一弧 狀底面。接下來’在鄰近弧狀底面的基底中形成一換雜區(d叩㈣ area)，且在摻雜區旁形成一埋入式導電層。 本發明之另-較佳實施例係提供一種垂直電晶體。垂直電晶體包 括-基底、-閘極、-第—源極區、—第二源極區、—祕區、一 通道區以及祕介電層。基底具有—溝渠，且間極設置於此溝渠 十源㈣設置在雜τ方的基底巾，其中源麵包含—第一源極 區以及-第二源極區’且第一源極區和第二源極區均包含有一半月 形(hdf-m_)剖面。沒極區言史置於閘極上。通道區設置於間極之兩 側，並位於源極d以及汲極區之間。閘極介電層設置於_區以及 通道區之間。 本發明所提供之方法可同時形成埋入式位元線以及淺溝渠隔離 .(sh.Wtrenchlsolatlon’ STI)，有助於簡化垂直電晶體之生產步 驟。此外，本發明所提供之方法也具備自對準校正㈣恤 201244003 之效果’因此’可更精麵成埋人植元線，有助於改善垂直電晶 體之特性。 【實施方式】 為使熟習本發明所屬技術領域之—般技藝者能更進—步了解本 發明’下文制舉本㈣之較佳實施例，並配合賴圖式，詳細說 明本發明的構成内容及所欲達成之功效。 凊參考第1圖。第1圖繪示了本發明之一較佳實施例之垂直電晶 體的不意圖。如第1圖所示，垂直電晶體3〇〇包括一基底3〇2、一 閘極304、一源極區306、一汲極區3〇8、一通道區314、一閘極介 電層316以及兩介電層318/320。 基底302具有一溝渠322，且閘極304、閘極介電層316、介電 層318以及介電層320均設置於溝渠322中。溝渠322具有一頂部 322a、一中間部322b以及一底部322c。在本實施例中，介電層320 係設置於溝渠322之頂部322a，介電層318係設置於溝渠322之底 部322c，而閘極介電層316係設置於溝渠322之中間部322b的一 側壁上。也就是說，閘極304係被介電層320、介電層318以及閘 極介電層316所環繞。 源極區306設置在基底302，且位於閘極304下方。介電層318 設置在閘極304以及源極區306之間’亦即使源極區3〇6與閘極3〇4 201244003 絕緣。其中源極區306包含一第一源極區306a以及一第二源極區 306b ’且第一源極區306a和第二源極區306b均包含一摻雜區319 以及一埋入式位元線321。請繼續參考第1圖所示的剖面示意圖， 摻雜區319具有一新月形(crescent)剖面，埋入式位元線321具有一 弓形(circle-segment)剖面’以共同形成各自具有一半月形(half_m〇〇n) 剖面的第一源極區306a以及第二源極區306b。在本實施例中，第 一源極區306a中半月形剖面的弧狀部份與第二源極區3〇6b中半月 形的5瓜狀部份彼此相向(confront) 〇 汲極區308設置於閘極304上。介電層320設置在閘極304以及 汲極區308之間’亦即使汲極區308與閘極304絕緣。在本實施例 中，汲極區308包含兩個摻雜區312以及一導電塊31〇。例如：兩 摻雜區312設置在閘極304兩側之基底302中，更詳細地說，兩摻 雜區312係設置在溝渠322之頂部322a的兩側，被介電層320分隔。 而導電塊310設置在基底302上，且電性連接兩換雜區312。 通道區314設置於閘極304之兩側，並設置於源極區306以及汲 極區308之間。而閘極介電層316設置於閘極304以及通道區314 之間。 基底302可包括由石夕、石夕蟲晶層、石夕鍺層、石夕覆絕緣(go〗)層或 其他半導體基底材料所構成的基底。閘極3〇4可包括金屬例如：銀 (Ag)、銅(Cu)、鎢(W)、鈦(Ti)鉑(Pt)、或其組合，或多晶矽。源極區 201244003 306之摻雜區319的導電型和汲極區遍之摻雜區312 &導電型相 同，例如：源極區306的導電型和沒極區，的導電型均為N型。 源極區306的埋入式位元、線切卩及汲極區通的導電塊31〇均可 由導電物質例如.金屬或多晶砍所構成。閘極介電層3丨6、介電層 318/320可由氧化石夕、氮化石夕或其他適合的絕緣材料所構成。值得注 意的是’垂直電晶體3GG之材料及結構不以上述為限。 清參考第2圖。第2断示了本發明之—較佳實關之垂直電晶 體陣列的不意圖。如第2圖所示’垂直電晶體陣列包括一基底 402、複數個垂直電晶體4〇1、複數條閘極線4〇4、複數條埋入式位 元線406以及一隔離結構424。基底4〇2及垂直電晶體4〇1之實施 樣態如前所述。 隔離結構424例如：一淺溝渠隔離_11〇评如11吐^1此〇11，311) 設置於基底402中，且圍繞各垂直電晶體4〇卜隔離結構424可由 氧化發、氮化碎或其他適合的絕緣材料所構成。閘極線4〇4互相平 行且沿一第一方向D1設置於基底402中。閘極線4〇4連接位於同 一行的各垂直電晶體401，且形成各垂直電晶體4〇1中的各閘極 3〇4(如第1圖所示）。埋入式位元線406互相平行且沿一第二方向 D2設置於閘極線4〇4下方的基底4〇2中。在本實施例中，第一方向 D1與第二方向D2實質上互相垂直。埋入式位元線406連接位於同 一列的各垂直電晶體401。請再參考第2圖沿第二方向132之剖面示 ,¾圖，一第一埋入式位元線4〇6a以及一第二埋入式位元線均 8 201244003 第有:弓錄。第-埋入式位元線之 弧 埋入式位元線娜之弓形剖面恤狀部份彼此相向 而Γ埋人式_4G6⑺亀的翻線_ 挪以及第—埋人式位元線懈之弓形剖_橫割線部份則 刀別面對隔離結構424，且直接接觸隔離結構似。 第3圖至，圖物本發明之—較佳實施例之埋人式位元線 =作方法示賴’其中第4圖至㈣崎示了沿第3圖Μ,線 ’又之剖面示意圖。 、 如第3圖所示，提供一基底502。基底502可包括由矽、石夕遙晶 層、石夕鍺層、石夕覆絕緣卿)層或其他半導體基底材料所構成的基 -基底502具有複數個條狀區域恤6_也叩6(1吻〇11)5〇3。在本實 知例中’條狀區域503互相平行且沿第二方向D2設置。在接下來 的步驟中’複數個條狀溝渠將形成於基底5〇2之條狀區4 5的中。 支如第4圖所示，在基底5〇2之條狀區域5〇3中形成複數個條狀溝 木505。形成條狀溝渠5〇2的方法包括下列步驟，例如，進行一微 衫蝕刻製程以形成一圖案化硬遮罩5〇7，然後，將圖案化硬遮罩5〇7 作為遮罩對基底502進行一蝕刻製程以形成條狀溝渠5〇5。各條狀 /冓渠505具有一侧壁5〇9以及一底面511。 如第5圖所示’在基底5〇2以及條狀溝渠505之側壁5〇9上形成 201244003 -襯墊層(敝)513。襯墊層513之材料包括金屬氧化物例如：氧化 铭’且形成該襯塾層513的步驟包含一原子層沉積製程㈣恤一 deposition，ALD)，但不以此為限。隨後，進行一溼侧步驟以加大 條狀溝渠5〇5之底面5丨卜舉例來說，祕刻步驟包括以氣氣酸 (hydrogenfluoride，HF)對條狀_ 5〇5之底面犯進行等向祕 刻，並使用襯塾層5!3作為遮罩’使得底面如形成一狐狀底面 仍’其中弧狀底面515大體上具有—圓形剖面。由於弧狀底面515 係藉由渔触刻步驟加大底面511而形成，部份的弧狀底面515將位 於條狀區域5〇3以外的區域。此外，襯墊層S13可保護條狀溝渠5〇5 之側壁509，避免側壁509受到蝕刻。 如第6圖所示，在基底502上形成一物質層517以填滿條狀溝渠 5〇5。物質層爪可包括多晶石夕，且形成物質層爪的步驟包含化學 氣相沉積(chemicaWapordeposition，CVD)製程或物理氣相沉積 (PhyS1CalvapOTdeposltlon ’ PVD)製程以提供良好的溝渠填充效果。 接下來，如第7圖所示，進行一退火製程細職㈣使位於物質 中的摻質擴散至基底5〇2，以形麟轉恤__切9， 歸去除物質層5Π。換雜區519具有—環狀剖面，且位於鄰近狐 =㈣的基請中。在其他實施例中，換雜㈣可經由其 法=成，例如：離子佈植(聰implant)製程錢相摻雜㈣和 細觸㈣括：軸_㈣提供-摻雜氣 L狀底面515暴露在摻雜氣體中並進行摻雜，然後進行一退 201244003 火製程’以形成鄰近弧狀底面S1S的摻雜區sl9。推雜氣體可包括 例如.珅(As)。在其他實施例中，也可在上述的祕刻步驟前，形 成另外的摻雜區（圖未示)於條狀溝渠5〇5之側壁5〇9旁。 如第8圖所示，以一沉積製程形成一導電層501在基底5〇2上。 導電層501可為-金屬層，且金屬層包含鈦(Ή)或氛化欽⑺风。在 本實施例中，導電層501可沿著弧狀底面515以及條狀溝渠5〇5之 側壁509共形性(conformally)形成’也就是說，導電層5〇1也會形成 在條狀區域503以外的部份弧狀底面515上。條狀溝渠505未被導 電層501完全填滿，但不以此為限’在其他實施例中，條狀溝渠5〇5 也可被導電層501完全填滿。 如第9圖所示，進行一乾蝕刻製程，以移除位於條狀區域5〇3 中的導電層501、襯墊層513以及摻雜區519。在本實施例中，乾蝕 刻製程也可進一步穿過弧狀底面515 ’移除位於弧狀底面515下方 在條狀區域503中的基底502。 如第10圖所示，形成一絕緣層以填滿條狀溝渠505，絕緣層包 括例如：氧化矽’並進行一平坦化製程例如：化學機械研磨 (chemical mechanical polish，CMP)製程’移除絕緣層、導電層 5〇1、 襯塾層513、圖案化硬遮罩507 ’以在條狀區域503中分別形成複數 個隔離結構524例如：淺溝渠隔離；以及在摻雜區519旁形成一埋 入式位元線521，掺雜區519以及埋入式位元線521可共同形成一 11 201244003 源極區506。源極區506對應於隔離結構524並列.設置，亦即一第 一源極區506a以及一第二源極區506b會形成於兩隔離結構524之 間。請繼續參考第圖，第一源極區506a以及第二源極區5〇6b 均包含有-半月形剖面，且第-源極區5G6a之半月形剖面的弧狀部 份與第二源極區506b之半月形剖面的弧狀部份彼此相向 (confront)，而第一源極區506a之半月形剖面的橫割線(secamline) 部份以及第二源極區506b之半月形剖面的橫割線部份則分別面對 隔離結構524 ’且直接接觸隔離結構524。此外，也可增加推雜區 519的摻雜面積’使相鄰的兩摻雜區519包括第1 原極㊣5編之摻 雜區519以及第二源極區涵之摻雜區519彼此電性連接以形成一 連續摻雜區。 _如上所述’本發贿供—可同_顏_、獻式位元線以及 隔離結構的製作方法。接下來，本發縣_提供—形成垂直電晶 體的製作方法’並結合第3圖至第1Q圖所示之製作方法。請參考第 圖至第15圖。第11圖、第12圖、第13圖、第14圖以及第15 圖繪不了本㈣之—触實施例之垂直電晶的製作方法之上視圖。 弟 11Α 圖、赏 ι〇ΛΓσι 一、Α圖、第13Α圖、第14Α圖以及第15Α圖分別續 丁了 '口第U圖、第12圖、第13圖、第14圖以及第15圖的Α_Α， 線段之剖面示音闻 _ 、 丁‘思圖。第11Β圖、第12Β圖、第13Β圖、第14Β圖 、 圖刀別繪示了沿第11圖、第12圖、第η圖、第14 Ϊ 以及第15圖的Α 一 'Β線段之剖面示意圖。第13C圖、第14C圖以及 第15C圖分別洛_ 乃'了沿第13圖、第14圖以及第15圖的c_c，線我 12 201244003 之剖面示意圖。 如第11圖、第11A圖以及第11B圖所示’根據第3圖至第1〇 圖所不之製作方法，隔離結構524以及源極區506已形成於基底502 中。接下來，如第12圖、第12A圖以及第12B圖所示，圖案化基 底502以形成複數個溝渠523於基底502中’且形成複數個隔離結 構526於溝渠523中，其中隔離結構526突出於基底502之一表面。 之後，形成一圖案化遮罩528於基底502上，且圖案化遮罩528暴 露部份基底502。在本實施例中，隔離結構526可由氮化石夕、氧化 矽或其他適合的絕緣材料所構成；圖案化遮罩528可由氧化矽構成。 如第13圖、第13A圖、第13B圖以及第13C圖所示，圖案化遮 罩528可用於移除部份部份基底5〇2以形成複數個溝渠522於基底 502中。其中溝渠522係沿一第二方向D2延伸，且第二方向£)2實 質上垂直-第-方向D1，但不以此為限。 隨後’去除圖案化遮罩528與隔離結構526的突出部分以平坦化 基底502。在本實施例中，可先採用一乾蝕刻製程或其他適合的方 法以部分去除圖案化遮罩528與隔離結構526，之後，再採用一化 學機械研磨製程或其他適合的方法以去除剩餘的圖案化遮罩528 與隔離結構526。 接下來，如第14圖、第14A圖、第14B圖以及第14(：圖所示， 13 201244003 形成複數個介電層518於溝渠522之底部522c，以及形成各閘極介 電層516於溝渠522之中間部522b的一側壁上。之後，形成各閘極 線504於溝渠522中。如第14圖及第14B圖所示，閘極線504沿 第二方向D2互相平行，設置於基底402中且位於源極區506上方。 接著’形成介電層520於溝渠522之頂部522a以覆蓋閘極線504。 在本實施例中，介電層518/520、閘極介電層516可由氧化矽構成， 介電層518/520可經由化學氣相沉積製程形成，閘極介電層516可 經由熱氧化(thermal oxidation)製程形成；而閘極線504可由金屬構 成，並經由化學氣相沉積製程形成。 如第15圖、第15A圖、第15B圖以及第15C圖所示，形成複數 個沒極區508於基底502中。本實施例形成汲極區508的方法包括 下列步驟。首先，形成摻雜區512在溝渠522之頂部522a兩側的基 底502中，且摻雜區512被介電層520分隔，接著，形成導電塊51〇 於基底502上’且導電塊510電性連接摻雜區512。摻雜區512與 源極區506的摻雜區(圖未示)具有相同的導電型，例如：可藉由進 行一植入(implantation)步驟，將N型摻質佈植至基底502中而形成， 此時，摻雜區512將具有N型矽晶層。導電塊510可由多晶矽構成， 並經由化學氣相沉積製程形成。此外，摻雜區512也可藉由一擴散 (diffUs丨on)步驟形成。 形成汲極區508後’通道區514即形成於各閘極線504之兩側， 並位於一相對應的源極區506以及一相對應的汲極區508之間。閘 14 201244003 極介電層516設置於通道區514以及閘極線504之間。據此，完成 一垂直電晶體。 細上所述’本發明提供一形成埋入式位元線以及垂直電晶體的方 法。此方法可同時形成埋入式位元線以及淺溝渠隔離，有助於簡化 垂直電晶體之生產步驟。此外，本發明所提供之方法也具備自對準 校正(self-alignment)之效果，因此，可更精確形成埋入式位元線，有 助於改善後續形成的裝置之運作速度。本發明也提供—具有埋入式 位元線的新穎垂直電晶體結構。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均輕化與修飾，皆闕本發明之涵蓋範圍。 【圖式簡單說明】 第1圖繪示了本發明之一較佳實施例之垂直電晶體的示意圖。 =圖繪示了本發明之—較佳實施例之垂直電晶體_的示意圖。 七至第10圖繪不了本發明之一較佳實施例之埋入式位元線 作方法示意圖。 取 第^圖、第12圖、第13圖、第14圖以及第15圖綠示了本發明之 一較佳實施例之垂直電晶的製作方法之上視圖。 示了。、儿笛第12A圖第13A圖、第14A圖以及第15八圖分別綠 線/圖、第12圖、第13圖、第14圖以及第i_a-a， 綠奴之剖面示意圖。 201244003 第11B圖、第12B圖、第13B圖、第14B圖以及第15B圖分別繪 示了沿第11圖、第12圖、第13圖、第14圖以及第15圖的B-B’ 線段之剖面示意圖。 第13C圖、第14C圖以及第15C圖分別繪示了沿第13圖、第14 圖以及第15圖的C-C’線段之剖面示意圖。 【主要元件符號說明】 300 垂直電晶體 302 基底 304 閘極 306 源極區 306a 第一源極區 306b 第二源極區 308 >及極區 310 導電塊 312 摻雜區 314 通道區 316 閘極介電層 318 介電層 319 摻雜區 320 介電層 321 埋入式位元線 322 溝渠 322a 頂部 322b 中間部 322c 底部 400 垂直電晶體陣列 401 垂直電晶體 402 基底 404 閘極線 406 埋入式位元線 406a 第一埋入式位元線 406b 第二埋入式位元線 424 隔離結構 501 金屬層 502 基底 503 條狀區域 16 201244003 504 閘極線 506 源極區 506b 第二源極區 508 及極區 509 側壁 512 摻雜區 514 通道區 516 閘極介電層 518 介電層 520 介電層 522 溝渠 522b 中間部 523 溝渠 526 隔離結構 D1 第一方向 505 條狀溝渠 506a 第一源極區 507 圖案化硬遮罩 510 導電塊 511 底面 513 襯墊層 515 弧狀底面 517 物質層 519 摻雜區 521 埋入式位元線 522a 頂部 522c 底部 524 隔離結構 528 圖案化遮罩 D2 第二方向 17201244003, invention description.: [Technical field to which the invention pertains] The present invention relates to a § memory technology, especially a buried bit line having a circle-segment profile and a buried bit A 4F2 s memory cell of a vertical transistor above the line, and a method of fabricating a buried bit line and a vertical transistor. [Prior Art] In order to increase the operating speed of the integrated circuit and at the same time comply with the need for the tamper-removing electronic device, the size of the transistor in the swivel device continues to decrease. Due to the size of the transistor, the length of the electron-electron channel region is also reduced, which may cause a serious short-pass effect of the transistor and a decrease in the ON current of the transistor. In order to solve the above problems, the conventional technique includes increasing the complexity of the electron-passing method, and the method of reducing the current is reduced by the method of turning on the body. Another method is to set the vertical-transistor structure, for example, to form a sinusoidal crystal structure on the substrate. This method can improve the operation speed and integration of the frequency circuit and slow down the short channel effect. Therefore, how to improve the structure of the crystal from the current in the electron channel area (four) to achieve the problem. 201244003 SUMMARY OF THE INVENTION One object of the present invention is to provide a structure of a buried bit line and a structure of a vertical transistor to improve the operating speed and the degree of integration of the integrated circuit. A preferred embodiment of the present invention provides a method of forming a buried bit line, including the following steps. Providing a substrate having a line-shaped region at the bottom of the substrate is formed into a strip-shaped trench having a side wall and a wire. Then, the bottom surface of the strip-shaped trench is enlarged to form an arc-shaped bottom surface. Next, a replacement region (d) is formed in the substrate adjacent to the curved bottom surface, and a buried conductive layer is formed beside the doped region. Another preferred embodiment of the present invention provides a vertical transistor. The vertical transistor includes a substrate, a - gate, a - source region, a second source region, a secret region, a channel region, and a secret dielectric layer. The substrate has a trench, and the interpole is disposed on the trench source (4), and the source surface includes a first source region and a second source region, and the first source region and the first source region Both source regions contain a half-moon (hdf-m_) profile. The history of the Noji District is placed on the gate. The channel region is disposed on both sides of the interpole and between the source d and the drain region. The gate dielectric layer is disposed between the _ region and the channel region. The method provided by the present invention can simultaneously form buried bit lines and shallow trench isolations (sh. Wtrenchlsolatlon' STI), which helps to simplify the vertical transistor production steps. In addition, the method provided by the present invention also has the effect of self-aligning correction (4) shirt 201244003 'so' can be more refined into a buried seed line, which helps to improve the characteristics of the vertical electric crystal. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to enable those skilled in the art to which the invention pertains, the present invention can further understand the preferred embodiment of the present invention, and the composition of the present invention will be described in detail in conjunction with the drawings. And the effect that you want to achieve.凊 Refer to Figure 1. Fig. 1 is a schematic view showing a vertical electric crystal according to a preferred embodiment of the present invention. As shown in FIG. 1, the vertical transistor 3A includes a substrate 3〇2, a gate 304, a source region 306, a drain region 3〇8, a channel region 314, and a gate dielectric layer. 316 and two dielectric layers 318/320. The substrate 302 has a trench 322, and the gate 304, the gate dielectric layer 316, the dielectric layer 318, and the dielectric layer 320 are disposed in the trench 322. The trench 322 has a top portion 322a, an intermediate portion 322b, and a bottom portion 322c. In this embodiment, the dielectric layer 320 is disposed on the top 322a of the trench 322, the dielectric layer 318 is disposed on the bottom 322c of the trench 322, and the gate dielectric layer 316 is disposed on the middle portion 322b of the trench 322. On the side wall. That is, the gate 304 is surrounded by the dielectric layer 320, the dielectric layer 318, and the gate dielectric layer 316. The source region 306 is disposed on the substrate 302 and under the gate 304. The dielectric layer 318 is disposed between the gate 304 and the source region 306' even if the source region 3〇6 is insulated from the gate 3〇4 201244003. The source region 306 includes a first source region 306a and a second source region 306b′. The first source region 306a and the second source region 306b each include a doped region 319 and a buried bit. Line 321. Referring to the cross-sectional view shown in FIG. 1, the doped region 319 has a crescent profile, and the buried bit line 321 has a circle-segment profile to form a half moon each. The first source region 306a and the second source region 306b of the half-m〇〇n profile. In this embodiment, the arcuate portion of the half moon-shaped cross section in the first source region 306a and the five melon portions of the half moon shape in the second source region 3〇6b are disposed opposite each other to the bungee region 308. On the gate 304. The dielectric layer 320 is disposed between the gate 304 and the drain region 308' even if the drain region 308 is insulated from the gate 304. In the present embodiment, the drain region 308 includes two doped regions 312 and a conductive block 31A. For example, two doped regions 312 are disposed in the substrate 302 on both sides of the gate 304. More specifically, the two doped regions 312 are disposed on both sides of the top 322a of the trench 322 and are separated by a dielectric layer 320. The conductive block 310 is disposed on the substrate 302 and electrically connected to the two replacement regions 312. The channel region 314 is disposed on both sides of the gate 304 and disposed between the source region 306 and the gate region 308. The gate dielectric layer 316 is disposed between the gate 304 and the channel region 314. The substrate 302 may comprise a substrate composed of a stone slab, a stone stalk layer, a stone slab layer, a stone slab insulating layer or other semiconductor substrate material. The gate 3〇4 may include a metal such as silver (Ag), copper (Cu), tungsten (W), titanium (Ti) platinum (Pt), or a combination thereof, or polycrystalline germanium. The doped region 319 of the source region 201244003 306 has the same conductivity type and the drain region as the doped region 312 & the conductive type and the non-polar region of the source region 306 are all N-type. . The buried bit of the source region 306, the wire cut and the conductive block 31 of the drain region can be formed of a conductive material such as metal or polycrystalline cut. The gate dielectric layer 3丨6 and the dielectric layer 318/320 may be formed of oxidized oxide, nitrided or other suitable insulating material. It is worth noting that the material and structure of the vertical transistor 3GG are not limited to the above. Refer to Figure 2 for details. The second is a schematic representation of the preferred embodiment of the vertical electrical crystal array of the present invention. As shown in Fig. 2, the vertical transistor array includes a substrate 402, a plurality of vertical transistors 4〇1, a plurality of gate lines 4〇4, a plurality of buried bit lines 406, and an isolation structure 424. The implementation of the substrate 4〇2 and the vertical transistor 4〇1 is as described above. The isolation structure 424 is, for example, a shallow trench isolation _11 〇 如 如 1 1 1 〇 , , , , , 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕 围绕It is composed of other suitable insulating materials. The gate lines 4〇4 are parallel to each other and disposed in the substrate 402 along a first direction D1. The gate lines 4〇4 are connected to the respective vertical transistors 401 in the same row, and each of the gates 3〇4 of the vertical transistors 4〇1 is formed (as shown in Fig. 1). The buried bit lines 406 are parallel to each other and are disposed in the substrate 4〇2 below the gate lines 4〇4 in a second direction D2. In the present embodiment, the first direction D1 and the second direction D2 are substantially perpendicular to each other. The buried bit line 406 connects the vertical transistors 401 in the same column. Please refer to the cross-sectional view of the second direction 132 in FIG. 2, the 3⁄4 diagram, a first buried bit line 4〇6a and a second buried bit line are all 8 201244003. The arc-embedded bit line of the first-buried bit line is a bow-shaped section of the navy section, which is opposite to each other and is buried in the _4G6 (7) 翻 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The arcuate section _ cross-cutting line portion faces the isolation structure 424 and is directly in contact with the isolation structure. Fig. 3 is a cross-sectional view showing the line of the present invention in the preferred embodiment of the present invention. As shown in FIG. 3, a substrate 502 is provided. The substrate 502 may include a base-substrate 502 composed of a layer of enamel, a stellite layer, a sapphire layer, or other semiconductor substrate material, and has a plurality of strip-shaped area shirts 6_叩6 ( 1 kiss 〇 11) 5 〇 3. In the present embodiment, the strip regions 503 are parallel to each other and are disposed in the second direction D2. In the next step, a plurality of strip channels will be formed in the strips 45 of the substrate 5〇2. As shown in Fig. 4, a plurality of strip-shaped grooves 505 are formed in the strip-like regions 5〇3 of the substrate 5〇2. The method of forming the strip trenches 5〇2 includes the following steps, for example, performing a micro-shirt etching process to form a patterned hard mask 5〇7, and then patterning the hard mask 5〇7 as a mask to the substrate 502 An etching process is performed to form strip trenches 5〇5. Each strip/channel 505 has a side wall 5〇9 and a bottom surface 511. As shown in Fig. 5, a 201244003-liner layer 513 is formed on the substrate 5〇2 and the side walls 5〇9 of the strip-shaped trenches 505. The material of the backing layer 513 includes a metal oxide such as oxidized and the step of forming the lining layer 513 includes an atomic layer deposition process (ALD), but is not limited thereto. Subsequently, a wet side step is performed to increase the bottom surface of the strip-shaped trench 5〇5. For example, the secret step includes the use of hydrogen fluoride (HF) for the bottom surface of the strip _ 5〇5, etc. To the secret, and using the lining layer 5! 3 as a mask 'so that the bottom surface is formed as a fox-like bottom surface, the arc-shaped bottom surface 515 has a substantially circular cross section. Since the curved bottom surface 515 is formed by enlarging the bottom surface 511 by the fishing touch step, a portion of the curved bottom surface 515 will be located outside the strip region 5〇3. In addition, the pad layer S13 can protect the sidewall 509 of the strip trench 5〇5 from being etched. As shown in Fig. 6, a substance layer 517 is formed on the substrate 502 to fill the strip trenches 5〇5. The material layer jaws may comprise polycrystalline spine, and the step of forming the material layer jaws comprises a chemical vapor deposition (CVD) process or a physical vapor deposition (PhyS1Calvap OTdeposltlon' PVD) process to provide good trench fill. Next, as shown in Fig. 7, an annealing process is performed (4) to spread the dopant in the material to the substrate 5〇2, and to remove the material layer 5Π. The changeover zone 519 has an annular profile and is located adjacent to the base of the fox = (4). In other embodiments, the substitution (4) may be via its method =, for example, ion implantation (chong implant) process, money phase doping (four) and fine touch (four): axis - (four) providing - doping gas L-shaped bottom surface 515 exposure Doping in the doping gas, and then performing a retreat 201244003 fire process 'to form a doped region sl9 adjacent to the arcuate bottom surface S1S. The dopant gas may include, for example, ruthenium (As). In other embodiments, additional doped regions (not shown) may be formed beside the side walls 5〇9 of the strip trenches 5〇5 prior to the above-described secreting step. As shown in FIG. 8, a conductive layer 501 is formed on the substrate 5〇2 by a deposition process. The conductive layer 501 may be a - metal layer, and the metal layer contains titanium (Ή) or atmosphere (7) wind. In this embodiment, the conductive layer 501 can be formed conformally along the curved bottom surface 515 and the sidewall 509 of the strip trench 5〇5. That is, the conductive layer 5〇1 is also formed in the strip region. A portion of the curved bottom surface 515 other than 503. The strip trenches 505 are not completely filled by the conductive layer 501, but are not limited thereto. In other embodiments, the strip trenches 5〇5 may also be completely filled by the conductive layer 501. As shown in FIG. 9, a dry etching process is performed to remove the conductive layer 501, the pad layer 513, and the doping region 519 located in the strip region 5〇3. In the present embodiment, the dry etching process may further remove the substrate 502 located in the strip region 503 below the curved bottom surface 515 through the curved bottom surface 515'. As shown in FIG. 10, an insulating layer is formed to fill the strip trench 505, and the insulating layer includes, for example, yttrium oxide and performs a planarization process such as a chemical mechanical polish (CMP) process to remove the insulating film. a layer, a conductive layer 〇1, a lining layer 513, and a patterned hard mask 507' to form a plurality of isolation structures 524 in the strip regions 503, for example, shallow trench isolation; and a buried trench 519 is formed adjacent to the doped region 519 The input bit line 521, the doped region 519, and the buried bit line 521 can collectively form an 11 201244003 source region 506. The source regions 506 are arranged side by side with respect to the isolation structure 524. That is, a first source region 506a and a second source region 506b are formed between the two isolation structures 524. Referring to the figure, the first source region 506a and the second source region 5〇6b each include a -half-shaped profile, and the arc-shaped portion of the half-moon profile of the first source region 5G6a and the second source The arcuate portions of the half-moon profile of the region 506b face each other, and the secamline portion of the half moon profile of the first source region 506a and the transverse line of the half moon profile of the second source region 506b Portions are respectively facing the isolation structure 524' and directly contacting the isolation structure 524. In addition, the doping area 519 of the dummy region 519 may be increased such that the adjacent two doping regions 519 include the doping region 519 of the first original positive 5 and the doping region 519 of the second source region. Sexually connected to form a continuous doped region. _ As mentioned above, 'the bribes of the bribes' can be combined with the _ _ _, the occupant line and the isolation structure. Next, the present invention provides a method of forming a vertical electric crystal, and combines the manufacturing methods shown in Figs. 3 to 1Q. Please refer to the figure to figure 15. 11th, 12th, 13th, 14th, and 15th is a top view of the manufacturing method of the vertical electro-crystal of the embodiment of the present invention. The younger brother, the 〇ΛΓ 赏 〇ΛΓ ι ι Α Α 赏 赏 赏 赏 赏 赏 赏 赏 第 第 第 第 第 第 第 第 第 第 第 第 第 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Α_Α, the section of the line shows the sound _, Ding's figure. The 11th, 12th, 13th, and 14th drawings show the sections along the 11th, 12th, 11th, 14th, and 15th schematic diagram. Fig. 13C, Fig. 14C, and Fig. 15C are respectively a cross-sectional view of the c_c along the 13th, 14th, and 15th, line 12 201244003. As shown in Fig. 11, Fig. 11A, and Fig. 11B, the isolation structure 524 and the source region 506 are formed in the substrate 502 according to the fabrication method of Figs. 3 to 1B. Next, as shown in FIG. 12, FIG. 12A, and FIG. 12B, the substrate 502 is patterned to form a plurality of trenches 523 in the substrate 502' and a plurality of isolation structures 526 are formed in the trenches 523, wherein the isolation structures 526 protrude. On one surface of the substrate 502. Thereafter, a patterned mask 528 is formed on the substrate 502, and the patterned mask 528 exposes a portion of the substrate 502. In the present embodiment, the isolation structure 526 may be comprised of nitride, yttria or other suitable insulating material; the patterned mask 528 may be comprised of yttria. As shown in Figures 13, 13A, 13B, and 13C, the patterned mask 528 can be used to remove portions of the substrate 5〇2 to form a plurality of trenches 522 in the substrate 502. The trench 522 extends along a second direction D2, and the second direction £)2 is substantially perpendicular to the first direction D1, but is not limited thereto. The patterned mask 528 and the protruding portion of the isolation structure 526 are then removed to planarize the substrate 502. In this embodiment, a dry etching process or other suitable method may be used to partially remove the patterned mask 528 and the isolation structure 526, and then a chemical mechanical polishing process or other suitable method to remove the remaining patterning. Mask 528 and isolation structure 526. Next, as shown in FIG. 14, FIG. 14A, FIG. 14B, and FIG. 14 (: 13, 201244003, a plurality of dielectric layers 518 are formed on the bottom 522c of the trench 522, and each gate dielectric layer 516 is formed. A sidewall of the intermediate portion 522b of the trench 522 is formed. Thereafter, each gate line 504 is formed in the trench 522. As shown in Figures 14 and 14B, the gate lines 504 are parallel to each other in the second direction D2 and are disposed on the substrate. 402 is located above the source region 506. Next, a dielectric layer 520 is formed on the top 522a of the trench 522 to cover the gate line 504. In this embodiment, the dielectric layer 518/520 and the gate dielectric layer 516 can be The ruthenium oxide is formed, the dielectric layer 518/520 can be formed through a chemical vapor deposition process, the gate dielectric layer 516 can be formed via a thermal oxidation process; and the gate line 504 can be formed of a metal and passed through a chemical vapor phase. The deposition process is formed. As shown in Fig. 15, Fig. 15A, Fig. 15B, and Fig. 15C, a plurality of non-polar regions 508 are formed in the substrate 502. The method of forming the drain region 508 in this embodiment includes the following steps. Forming a doped region 512 on both sides of the top 522a of the trench 522 In the bottom 502, the doped region 512 is separated by the dielectric layer 520, and then the conductive block 51 is formed on the substrate 502' and the conductive block 510 is electrically connected to the doped region 512. The doped region 512 and the source region 506 The doped regions (not shown) have the same conductivity type, for example, can be formed by implanting an N-type dopant into the substrate 502 by performing an implantation step, in which case the doping region 512 will There is an N-type twin layer. The conductive block 510 may be formed of polycrystalline germanium and formed by a chemical vapor deposition process. Further, the doped region 512 may also be formed by a diffusion (diffUs) step. Channel region 514 is formed on each side of each gate line 504 and is located between a corresponding source region 506 and a corresponding drain region 508. Gate 14 201244003 The pole dielectric layer 516 is disposed in the channel region 514. And a gate line 504. According to this, a vertical transistor is completed. The present invention provides a method for forming a buried bit line and a vertical transistor. This method can simultaneously form a buried bit. Line and shallow trench isolation helps simplify the production steps of vertical transistors. In addition, the method provided by the present invention also has the effect of self-alignment, so that the buried bit line can be formed more accurately, which helps to improve the operating speed of the subsequently formed device. Provided - a novel vertical transistor structure having a buried bit line. The above description is only a preferred embodiment of the present invention, and all of the lightening and modification according to the scope of the present invention are based on the present invention. Coverage. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a vertical transistor of a preferred embodiment of the present invention. The figure shows a schematic view of a vertical transistor _ of the preferred embodiment of the invention. 7 to 10 illustrate a schematic diagram of a buried bit line method in accordance with a preferred embodiment of the present invention. Fig. 12, Fig. 13, Fig. 14, Fig. 14, and Fig. 15 are green views showing a top view of a method of fabricating a vertical electro-crystal according to a preferred embodiment of the present invention. Shown. Fig. 12A, Fig. 13A, Fig. 14A, and Fig. 15th, respectively, are green line/graph, 12th, 13th, 14th, and i_a-a, respectively. 201244003 Sections 11B, 12B, 13B, 14B, and 15B illustrate the B-B' line along the 11th, 12th, 13th, 14th, and 15th, respectively. Schematic diagram of the section. 13C, 14C, and 15C are schematic cross-sectional views taken along line C-C' of the 13th, 14th, and 15th, respectively. [Main component symbol description] 300 vertical transistor 302 substrate 304 gate 306 source region 306a first source region 306b second source region 308 > and polar region 310 conductive block 312 doped region 314 channel region 316 gate Dielectric layer 318 dielectric layer 319 doped region 320 dielectric layer 321 buried bit line 322 trench 322a top 322b intermediate portion 322c bottom 400 vertical transistor array 401 vertical transistor 402 substrate 404 gate line 406 buried Bit line 406a first buried bit line 406b second buried bit line 424 isolation structure 501 metal layer 502 substrate 503 strip region 16 201244003 504 gate line 506 source region 506b second source region 508 Polar region 509 sidewall 512 doped region 514 channel region 516 gate dielectric layer 518 dielectric layer 520 dielectric layer 522 trench 522b intermediate portion 523 trench 526 isolation structure D1 first direction 505 strip trench 506a first source region 507 patterned hard mask 510 conductive block 511 bottom surface 513 pad layer 515 arcuate bottom surface 517 material layer 519 doped region 521 buried bit line 522a top 522c bottom 524 isolation structure 528 patterned mask D2 second direction 17