TW201232548A - Memory architecture of 3D array with improved uniformity of bit line capacitances - Google Patents

Abstract

A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in which a bit line structure couples the plane positions to bit lines. Each bit line is coupled to at least two different plane positions to access memory cells at two or more different plane positions.

Description

201232548

1 W/4/9FA VI. Description of the Invention: [Technical Field of the Invention] [0002] The present invention is a high-density memory device, and more particularly a memory device in which multiple planes of a plurality of memory cells are used A 3D array is provided. [Prior Art] [0003] As the critical dimensions of devices in integrated circuits shrink to the limits of general memory cell technology, designers have been looking for techniques for stacking multiple memory cell planes to achieve greater storage capacity and more. Low bit unit cost. For example, Lai et al., "Multilayer Stackable Thin Film Transistor NAND Flash Memory", published at the International Electron Devices Conference of the Electrical and Electronic Engineering Society, December 11-13, 2006 ("A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory," IEEE Int' 1 Electron Devices Meeting, 11-13 Dec. 2006); and Jung et al., December 11-13, 2006, at the Electrical and Electronics Engineering Society "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single", "International Dielectrics Conference, "3D Stacked NAND Flash Memory Technology for Stacking Single Crystal Layers on ILD and TAN0S Structures for Nodes Beyond 30 nm" Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node", IEEE Int' 1 Electron Devices Meeting, 11-13 Dec. 2006), applying thin film transistor technology to charge trapping technology. [0004] Moreover, Johnson et al., published in the November 31, 2003, in the Journal of the Solid State Circuits of the Electrical and Electronic Engineering Society, No. 11

1 512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory CellsM IEEE J. of Solid-State Circuits, vol. 38, no. 11, Nov. 2003), cross-point array technology has been applied to anti-fuse memory. In the design described by Johnson et al., a plurality of layers of word lines and bit lines are provided that have memory elements at the intersections. The memory component includes a P+ type polycrystalline germanium anode connected to the word line and an N-type polycrystalline germanium cathode connected to the bit line, wherein the anode and the cathode are separated by an antifuse material. [0005] In the process described by Lai et al, Jung et al., and Johnson et al., there are several critical lithographic steps for each memory layer. Therefore, the number of critical lithographic steps required to fabricate the device is directly proportional to the number of layers implemented. Therefore, while the use of 3D arrays can achieve higher density benefits, higher manufacturing costs limit the use of this technology. [0006] Another structure for providing vertical NAND cells in charge trap memory technology is described in Tanaka et al., June 14-14, 2007, on pages 14-15 of the 2007 VLSI Technical Abstracts Symposium Technical Paper. "Bit Cost Scalable Technology with Punch'and Plug Process for Ultra High Density Flash Memory", 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 June 2007, pages: 14-15). The structure described by Tanaka et al. includes a multi-gate field-effect electric crystal structure having a vertical channel that operates like a NAND gate, using a niobium oxynitride 4 201232548

i w /4 /yPA (silicon-〇xlde-nitride_〇xide_silic〇n, s〇N〇s) Charge trapping technique creates a storage location in each gate/vertical channel interface. The memory structure is based on a columnar, such as a vertical channel, of a semiconductor material for a plurality of gate cells, wherein the lower selected gate is adjacent to the substrate and the upper selected gate is on the top. A plurality of horizontal control gates are formed using a planar electrode layer that intersects the column. Used as a planar power to control the gate, the layer does not require critical lithography, which saves cost. However, many critical lithographic steps are still required for each vertical unit. Also, the number of control gates stacked in this manner can be determined by factors such as the conductivity of the vertical channel and the programming and erase procedures used. [〇〇〇7] 3D Finger VG (VertiCal gate) NAND is a high-density 3〇 stackable flash architecture. However, the structure is asymmetrical for different locations of the array, such as different planar locations of the array. The bit lines respectively coupled to the same plane position of the same block in the array 1 have different bit line capacitances (CBL). The different bit line capacitances of these different bit lines create difficulties in sensing storage in the memory cell. (4) [0008] Therefore, the 3D integrated circuit memory structure provided is preferably low in manufacturing cost, and includes reliable and very small memory components, and an improved process window (pr〇cess wind〇w) , wherein the process window refers to a process window associated with the serialization of the memory cell series having the gate structure. Stomach 201232548

TW7479PA SUMMARY OF THE INVENTION [0009] Various embodiments provide a 3D memory array such as a 3D Finger VG (vertical gate) NMD. [0010] In the case of the singularity, the bit line is lightly connected to the sequence of different layers in the 3D memory array for transformation. For example, in a configuration order in which a bit line runs through a plurality of distinct memory blocks, the bit lines have different sequences in different memory blocks, and the different sequences couple the bit lines to the 3D memory array. The different layers (of coupling t〇the different layers of the 3D memory array are modified? Because different plane positions in the array have different capacitances, and in the configuration in which the bit lines run through multiple different memory blocks And because the difference in capacitance between the same layer will traverse the different regions 2 inverse =: so the bit line of the same plane position of different blocks in the mother bar coupling array will have different from other bit lines Bit iine capacitances (CBL). Different sequences connect different plane positions of different blocks to bit lines, and (4) sequences of some columns will traverse different blocks to change with different plane positions. The difference between the capacitors is averaged off. This averaging ensures that the bit line capacitances of different bit lines are consistent, which promotes the sense of the slave bits and the values stored in the memory cells. The elementary lines (eg, like the bit lines located in the metal layer 3) have an average capacitance that coincides with the other bit lines. [1] A first aspect according to the present invention relates to a memory device, including a substrate a plurality of semiconductor materials with a stack, a plurality of turns, a plurality of memory elements, and a plurality of bit line structures. 6 201232548

W/4/VPA The bulk material strip is placed on top of the substrate. The π 堆 V π π 为 为 为 为 为 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该The f is separated by an insulating material in a plurality of [0013] stomach words (the line spans the surface of the stack and is conf〇rmal), and the d and the memory device through the semiconductor device The material core and the word lines establish a 3D matrix of memory cells - column t [0015] side bit line structure system bit line structure is this: - the end of the heap ^ 'the ten The surface position is coupled to the plurality of bit lines. Each bit line of the bit line is transferred to at least two different plane positions of the plane position. - 卞回j 017 ] Wherein, each of the bit lines of the bit lines has at least two different phase out-of-plane positions of the different stacks of conductor materials in the stack including: -th semiconductor: stack-first-plane The position and the second semiconductor strip stack plane position such that the first semiconductor strip stack and the j two semiconductor strip stack are different memory blocks. Each of the bit lines is flat, and the conductor material has at least two different phases of the different stacks in the stack. The at least two different planes The system includes a first semiconductor: a first planar position and a second semiconductor strip stack, the first semiconductor strip stack and the second semiconductor being separated by the word lines Access by the yuan line. 201232548

TW7479PA

[0019] In an embodiment, the memory cells are disposed along the strips of semiconductor material in the NAND string. [0020] In one embodiment, the memory cells are disposed along the bit line structures and the plurality of source lines of semiconductor material between the source structures. [0021] In one embodiment, the distinct capacitances characterize the different planar locations of the planar locations. [0022] In an embodiment, the stacks are separated into a plurality of memory blocks by the bit line structures. [0023] In one embodiment, the semiconductor material strips are stacked with a specific semiconductor strip and a combination of a plurality of word lines of the word lines to identify a particular memory of the memory cell 3D array. unit. [0024] In one embodiment, the memory devices include a charge-trapping structure, the charge trapping structure includes a tunneling layer, a charge trapping layer, and a Blocking layer. [0025] In another aspect of the invention, a memory device includes a substrate, a plurality of semiconductor material strip stacks, a plurality of word lines, a plurality of memory elements, and a plurality of bit line structures. [0026] The stack of semiconductor material strips is over the substrate. The stacks are ridged and include at least two strips of semiconductor material separated by an insulating material in a plurality of planar locations. [0027] The word lines are arranged across the stacks and have 8 201232548

1W7479PA Plane conforming to these stacks. [0028] The semiconductor material strips located in the interface areas of the s-sea are passed through the array. *...Hai 兀 兀 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 建立 δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ δ 些 些The line structure has a plurality of sequence=to two-two distinct sequences of the planar positions. Each of the sequences (4) has the bit lines, and the line structure of the line structure is coupled to the planes of the bit lines. The order of the positions [0=0] In an embodiment, the memory units are disposed along the strips of semiconductor material in the string of cells. 031] In the embodiment, the memory units are The bits are disposed between the plurality of incoming structures along the semiconductor material. [0032] In an embodiment, the different capacitances depict features of the different planar positions of the surface locations. [003] In an embodiment, the sequence of different sequences of the bit line structures averages the features of the dissimilar plane positions of the two plane positions that are subtracted from the bit fields. [0034] In an embodiment, the bit line structure and the order of the bit lines of the bit lines are coupled One of the bit lines across the line structure from the second end to the first end of the corresponding one of the bit line structure [〇〇35] in - embodiments, the plurality of stack-based structure to the plurality of bit 201232548

TW7479PA is divided into a plurality of memory blocks β [0036] force-embodiment, wherein the semiconductor material strips are stacked with a specific semiconductor strip and a combination of a particular word line of the word lines is selected to identify Memory unit 31) One of the arrays of specific memory cells. The κ Confucian device system includes a charge-charge. Figure 7J shows, in one embodiment, a Mixian straight trap structure, the charge trap structure including a tunneling trap layer and a barrier layer. In accordance with an aspect of the invention, a memory-memory device includes: - a 3D integrated circuit memory array having a plurality of memory cells at a plurality of planar locations; a plurality of bit line structures a plurality of columns having a reduced planar position, the sequences comprising at least two distinct sequences, each of the sequences depicting one of the bit line structures coupled to the plurality of bits The sequential features of the planar locations of the metalines. [0041] In an embodiment, the memory cells of the array are disposed along the strips of semiconductor material in a NAND string. In the embodiment, the memory cells of the array are disposed along the strip of the inscription material between the bit line structures and the plurality of source lines. In one embodiment, the distinct capacitances characterize the different planar locations of the surface locations. [0044] In an embodiment, the plurality of different sequences of the bit line structures average the different planes depicting the planar positions 201232548

I W/4/yPA face position characteristics of these different capacitances. [0045] In an embodiment, the order of the bit line structure and the planar positions of the bit lines is from the first end of the bit line structure to the bit One of the second ends of the line structure. [0046] In one embodiment, the array is separated into a plurality of memory blocks by the bit structures. In one embodiment, a combination of one of the plurality of semiconductor material strips in the array and a particular word line of the plurality of word lines in the array is used to identify the array. A certain memory unit. [0048] In one embodiment, the memory elements of the array comprise charge trap structures, the charge trap structures comprising a tunneling layer, an electrical prayer trap layer, and a barrier layer. [0049-0052] According to an aspect of the invention, a body device includes: a 3D integrated circuit memory array having bits; a plurality of memory cells in a plurality of planar positions; a plurality of bits The plurality of bit lines are coupled to at least two different plane positions of the dissimilar plane positions, and the unit cells are at the at least two different plane positions. In one embodiment, the memory cells of the array are disposed along the strips of semiconductor material in a NAND string. [0054] In the embodiment, the memory cells of the array are disposed between the bit line structures and the plurality of source lines between the plurality of source lines. 201232548

TW7479PA

[0055] In one embodiment, the distinct capacitances characterize the different planar positions of the planar locations. [0056] In the 9-embodiment, the array is separated into a plurality of memory blocks by a plurality of bit line structures. [0057] In an embodiment, a combination of a specific semiconductor strip of the semiconductor material strip stack and a specific word line of the word lines in the array is used to identify the array. A certain memory unit. In one embodiment, the memory elements of the array comprise charge trap structures, the charge trap structures comprising a pass-through layer, a charge trap layer, and a resist layer. [0059] Various embodiments have multiple stacked layer numbers. For example, for an eight-layer vertical gate, the sequence B1(1), bl(2), BL(3), BL, which indicates that the bit line (bit Hne, BL) is coupled to different layers of the memory block. (4), BL(5), BL(6), BL(7), BL(8) can be transformed in different blocks such that the bit line capacitance of each bit line is averaged. This minimizes the difference in capacitance of each metal bit line to achieve a stable sensing margin. [0060] With regard to other aspects of the invention and its advantages, reference is made to the following figures, embodiments, and patent applications. [Embodiment] [0089] A detailed description of an embodiment with reference to the drawings will be provided below. [0090] FIG. 1 is a 3D programmable resistance memory array 2X2 part 12 201232548

l W747VHA: The fill material in the perspective & is removed from the pattern so that the semiconductor strip stack of the 3D array and the vertical word lines can be displayed. In this 钊':’, there are only two planes. However, the number of planes can be extended. As shown in FIG. 1, the memory array is fabricated on an integrated circuit substrate having an insulating layer of '_10', wherein the semiconductor or other structure is Foundation (not shown). The memory 1c includes a plurality of stacks of semiconductor strips, 12, 13, and 14 separated by insulating materials 2, 22, 23, and 24. The stacks are ridges extending from the gamma axis, as shown, such that the semiconductor strips 11-14 can be configured as = cell trains. The semiconductor strips u and 13 can be used as a memory cell string in the first memory. The semiconductor strips 12 and 14 can be used as a string of memory cells in the second memory plane. The memory material layer 15, ΪΞίΐίϊ material 'in this case, the anti-fuse material is applied to a plurality of ", and in other examples at least to the semiconductor strip 3, the two lines are 16 and 17 vertical Across a number of semiconductors: Yufeng U. The word fields 16 and 17 have a plurality of semiconductor strip faces that fill the trenches formed by the edges of the plurality of stacks (ie, 20 in the figure), and the semiconductor strips u_i4, the surface and the word line 16 are interposed on the stack. And a two-layer array of interface areas where the sides of the 丨7 are intersected. Layers of Shi Xi Compounds 18 and 19 (i.e., Shi Xihua Crane, Shi Xihua Cobalt, and Titanium Telluride) may be formed on the top surfaces of the word lines 16 and 17. [0091] The memory material layer 15 may be composed of an anti-fuse material, such as a non-fossil, oxynitride or other oxide; the thickness of the layer 15 of material is about 5 to about 5 nm. Memory material materials 15 can also use other anti-fuse materials, such as tantalum nitride. The semiconductor 11-12 may be a semiconductor material of the first conductivity type (ie, ?). 13 201232548

The TW7479PA word lines 16 and 17 can be a second conductivity type (i.e., n-type) semiconductor material. For example, the semiconductor strips 11-14 can be fabricated using p-type polyliths. Alternatively, the word lines 16 and Π can be fabricated using corresponding heavily doped n+-type polysilicon. . The width of the semiconductor strip should provide enough space for the depletion layer to support diode operation. Therefore, the memory cell unit including the rectifier formed by the programmable anti-fusing silk layer P-N junction (p-N juncti〇n) is formed in an array of intersections between the polysilicon ribbon and the line. The programmable anti-solving filament layer is located between the anode and the cathode. (This is an English sentence structure, which is not suitable for Chinese writing.) In other embodiments, different programmable resistive memory materials can be used, including tungsten oxide on tungsten or doped metal oxide semiconductor strips. Transition metal oxide. These materials can be programmed and erased and can be implemented in jobs that store multiple bits per cell. 2 shows a cross-sectional view taken from the χ_ζ plane of the memory cell formed in the intersection of the word line 16 and the semiconductor strip 14. The active regions 25 and 26 are formed on the two sides between the word line 16 and the strip 14. In the natural state, the antifuse material layer 15 has a high electrical resistance. After the "flat" process, the anti-filament material is decomposed, causing either or both of the active regions 25 and 26 (active regi〇n) in the anti-wire material to exhibit a low resistance state. In the embodiment described herein, each memory cell has two active layers 25 and 26, each located at each edge of the semiconductor strip 14. Figure j shows a χ-γ plane wear pattern of the memory cell formed at the intersection of the word line 16 and the semiconductor strip 14. Figure 3 also shows that the sub-element line labeled as sub-element 16 passes through the anti-fuse material layer 15 to reach the semiconductor ^ 201232548

ί W /4/ypA A [0093] as shown in Fig. 3, the electron flow continued with the solid arrow, flowing from the material type = 6 into the p-type semiconductor strip 'and then along the semiconductor strip (-arrow) ^ ^ should be the amplifier (sense Qing Lifier), in which the electron stream: ^ to indicate the state of the selected memory unit. The use of a layer of about 1 nm thick silica dioxide as an anti-solvent material is very unique... Try to use this subject. Wherein the programming pulse can comprise a pulse of about 1 millisecond: 5 to 7 volts, and the on-wafer control circuit describes the lower 4 and the portion of Figure 18. The read pulse is applied under the control of a wafer. Where the read pulse can include 1 to 2 workers == the slash is dependent on its configuration. The wafer is controlled on soil, field, and L; the following is applied to the portion of Figure 18. The read pulse may be tied to the programming pulse. b ^0094] Head 4 is a schematic diagram showing the 2 planes of the memory unit, each symbol: i has: = yuan. The memory cell represents the anti-shine wire 2" between the anode and the cathode with a diode 1 line with a broken line. The first conductor field 53 located at the word lines 6A and 61 and the semiconductor strips 51 and 52. The second stack of 54 and the semiconductor strip 55 i are separated from each other by the intersection of the two planes, and the two planar memory cells are formed into ◦ and 61 as the first word line (w〇rdiine, wl) and " :::Line WLn+1 'and the first to third stacks are in the array of the first layer and the second layer, but the first plane of the Bu Li-Mu recall unit includes; 2η, η+ι and η +2. Symbols 3〇 and 31, memory on the semiconductor tape U-body 52, P Γ memory cells 32 and 33, and memory banks on + 56 and 35. Memory cell, 201232548

The TW7479PA 2 surface includes the memory cells on the semiconductor strip 51 and the memory cells 42 and 43 on the 4b and 2 body strips 53, and the s-resonant units 44 and 45 on the semiconductor strip 55. Such as the cabinet Shen·-, Xuan-gu μ map 7F 'as the character line tied η: = 60' including the vertical extension part 6〇_卜6〇一2 and 6〇_3, its ^ should be " on the stack The extensions are located between the grooves in the groove as shown in the figure to make the words (10) (10) along the (four) planes of the three materials to the memory unit. An array having a plurality of layers can be implemented as described herein to make a very high density memory method possible or to reach a terabits chip per wafer. 5 is a perspective view of a portion of a 3D charge trap memory array 2x2 in which the fill material is removed from the pattern to display the semiconductor strip stack and vertical word lines that make up the 3D array. In this picture, only two layers are shown. However, the number of layers can be expanded to be very large as shown in FIG. 5. The memory array is fabricated on an integrated circuit substrate having an insulating layer 110, wherein the insulating layer 110 is based on a semiconductor or other structure (not drawn) Show). The memory array includes a plurality of stacks of semiconductor strips 1U, 112, 113 and U4 separated by insulating materials 121, 122, 123 and 124. The stacks are ridges extending from the gamma axis, as shown, such that the semiconductor strips 11 can be configured as a series of memory cells. The semiconductor strips 111 and 113 can be used as a memory cell string in the first memory plane. Semiconductor strips 112 and 114 can be used as a string of memory cells in the second memory plane. [0096] The insulating layer 121 interposed between the semiconductor strips 11A and U2 in the first stack and the insulating layer 123 interposed between the semiconductor strips 113 and 114 in the second stack have an effective oxidation of about 40 nm or more. 201232548

IW /4 / yHA effective oxide thickness (EOT), wherein the effective oxide thickness is based on the dielectric constant ratio of cerium oxide (rati〇〇f the ^dielectric constant) and the dielectric constant of the selected insulating material The thickness of the normalized insulating material. The term "about 40 nm" used for this purpose is to estimate the possible movement of about 1% or so, as is conventionally produced for this type of structure. The thickness of the insulating material can play a key role in reducing the interference between adjacent layer elements of the § hai structure. In some fine cases, the effective oxide thickness of the insulating material can be as small as 30 nm and at the same time between the layers There is enough isolation. [0 0 9 7] The memory material layer 115, such as a dielectric charge trap structure, is coated on a plurality of semiconductor strip stacks in this embodiment. A plurality of sub-element lines 116 and 117 are vertically disposed across a plurality of semiconductor strip stacks. The word lines 116 and Π 7 have surfaces conformal to the plurality of semiconductor strip stacks, filling the trenches formed by the plurality of stacks (ie, 120 in the figure), and causing the side fennel of the semiconductor strip m_114 on the stack And a multilayer array of interface regions at the intersections between the sides of word lines 116 and 117. Layers of Tellurides 118 and 119 (i.e., tungsten telluride, cobalt telluride, titanium telluride) may be formed on the top surfaces of word lines 116 and Π 7. [0098] A metal-oxide-semiconductor field effect transistor (M0SFET) cell can also be disposed in this manner, that is, by providing in the channel region on word lines 111-114. Nanowire or nanotube structure' as described by Paul et al. in the September 2007 issue of the Electrical and Electronic Engineering Society Electronic Devices, Vol. 54 No. 9 "Process Variations for Nanowire and Nanotube Devices Impact of a Process Variation on Nanowire and Nanotube 17 201232548 IW/4/yhV\

Device Performance" , IEEE Transactions on

The article is incorporated by reference as if fully set forth herein, as described in Electron Devices, Vol. 54, No. 9, September 2007. (This is an incorporated by reference'. An American manual that describes how to write a pre-case content. It is recommended to google "incorporated by reference" Chinese translation, and then in the form of a scrape (incorporate by reference) Marked out, this will be very clear) [0099] This can be fabricated in the nAND flash array of silicon-oxide-nitride-oxide-silicon (S0N0S) type δ hexamedron A 3D array of cells. A source, a drain, and a channel (channe 1 ) are formed in the Shi Xi semiconductor tape ιιι_ι 4, and the memory material layer 115 includes a dielectric layer 97 that can be formed by the formation of the dioxide, and a tantalum nitride. A charge storage layer 98 is formed, a blocking dielectric layer 99 formed of cerium oxide, and a gate including word lines 116 and 117. [0100] The semiconductor tape m-114 may be a P-type semiconductor material. The word lines 116 and 117 can be semiconductor materials having the same or different conductivity types (i.e., type ^). For example, the semiconductor strip 1U_U4 can be fabricated using a P-type polycrystalline germanium or a P-type epitaxial single crystal germanium, whereas the word lines (1) and 117 can be fabricated using a corresponding heavily doped p+ type polycrystalline germanium. [〇1〇1] In addition, the semiconductor strip m_114 may be a binary word line 116*117 which may be a semiconductor material having the same or different conductivity type (= 疋P+ type). This N-belt setting can achieve concealment 201232548

IW7479PA road (buried-channei) and consumption mode (depleti〇n chat) What is trapped in the memory soap TO. For example, the semiconductor strip U1_114 can be fabricated using N-type polycrystalline or N-type epidaxia singiecrystai slllcon, whereas the word lines ll6 and ι7 can be used with the corresponding heavily doped P+ type. Polycrystalline germanium manufacture. A typical f-conductor band doping concentration can be in the vicinity of 10 W, in the range of l〇7 cm3 to l〇19/cm3 in the usable embodiment. The use of N-type semiconductor strips is particularly advantageous in junction-free embodiments to increase conductivity along the NAND string and to allow for higher read currents. ^〇1〇2]_ Thus, a suffix unit including a field effect transistor having a charge storage structure is formed in a cross-point 3D array. A semiconductor strip and word line of about 25 nm width are used, and the gap between the ridges is about 25 nm. A device having tens of layers (ie, 32 layers) can reach 10,000 in a single wafer. The capacity of billions of dollars. [0103] The memory material layer 115 can include other charge storage structures. For example, a bandgap ^gin^ered SONOS (BE-S0N0S) charge storage structure can be used that includes a dielectric tunneling layer 97 that includes a pour under zero bias. A composite of materials of the "U" shaped valence band. In an embodiment, the synthetic tunneling layer includes a first layer called a tunneling layer, a second layer called a band of fset layer, and a layer called a tunneling layer. The third layer of the isolation layer. Here, the hole tunneling layer of the layer 115 in the example includes two, 矽 on the side of the semiconductor strip, which is formed by, for example, in-situ steam generation method with selective nitride (in-situ steam generati〇) n, IS%), which deposits nitric oxide in the surrounding environment during deposition. 19 201232548

J W/4/VKA fire (post deposition NO anneal) can also increase the use of nitric oxide. The thickness of the first layer which is the day of the dioxide is less than 2 〇 a, and more preferably less than or equal to 15 Å. A representative embodiment may have a thickness of 丨〇 a戍 12A. [0104] The tape-shifting layer in the present embodiment includes a nitride nitride layer disposed on the tunneling layer of the hole, which is formed by, for example, low-pressure chemical vapor deposition (LPCVD). For example, it is at 680. (: DiChlorosiiane, DCS) and Armonia (NH〇 precursors in temperature. In an alternative process, the offset layer includes the use of a similar process with a nitrous oxide precursor. The manufactured yttrium oxynitride. The thickness of the yttrium nitride nitride offset layer is less than 30 A, or more preferably 25 A or less. [0105] The isolation layer in this embodiment includes ruthenium dioxide, which is placed at a high temperature, for example, using LPCVD. Oxidation (hi gh temperature (10) 'soil as HTO) deposition method formed on the tantalum nitride offset layer. The thickness of the ceria barrier layer is less than 35A' or better than 25A. Such a three-layer tunneling layer The inverted U-shaped band energy band (band energy 丨 丨 丨 曰 曰 [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ Zone _ conduction hole tunneling, the valence band energy level; ^ will increase the valence band energy level after the first position to effectively eliminate the first position after the synthetic wear-through dielectric hole tunneling barrier Such a structure establishes an inverted U shape in a three-layer tunneling dielectric layer. With energy level, and making electric field assisted hole tunneling at high speed possible, Mengxi is effectively in the absence of electric field or small electric field induced by other operations' (for example, in the slave unit) Read data or program adjacent to #20 201232548

When the TW7479PA unit is used, it avoids the leakage of charge by synthesizing the tunneling dielectric. [0107] In a representative device, the memory material layer includes an energy gap, a synthetic tunneling dielectric layer including a germanium dioxide layer having a thickness of less than 2 nanometers and a thickness of less than 3 nanometers. The tantalum nitride layer and the dioxide layer having a thickness of less than 4 nm. In one embodiment, the synthetic tunneling dielectric layer comprises an ultrathin SiO2 layer (ie, less than or equal to 5A): an ultrathin tantalum nitride layer N1 (ie, less than or equal to 3 〇A) and super The valence band level of about 2. 6 eV is increased by an offset of less than or equal to 15 A from the interface with the semiconductor body. The 02 layer penetrates the N1 layer from the charge through the lower valence band energy level (higher hole tunneling barrier) and the higher conduction band energy level at the second offset (ie, about 30A to 45A from the interface). Layer separation. An electric field sufficient to induce tunneling of the hole raises the valence band energy level after the second position to a level effective to eliminate the tunneling barrier, which is because the first position is farther from the interface. Therefore, the 02 layer does not significantly interfere with the electric field-assisted hole tunneling' while improving the ability of the design tunneling dielectric to block the spill during the low field (1〇w field). [〇1〇8] The charge trapping layer in the memory material layer 115 in this embodiment includes tantalum nitride having a thickness greater than 50 A, (who includes a charge trapping layer?? Silicon nitride??), for example, A tantalum nitride of about 7 Å is formed by LPCVD. Other charge trapping materials and structures may also be employed, including, for example, bismuth oxynitride (Six〇yNz), silicon-richnitride, cerium-rich oxide (siHc〇n_rich oxide), and annihilated nanoparticle. The trap layer of (embedded nano-particles) and so on. 201232548

I W7479PA

[0109] The barrier "electrical layer" in the memory material layer 115 in this embodiment includes a layer of oxidized stone having a degree greater than 50 A, including, for example, wet from a nitride by a wet furnace oxidation process. About 90A formed by wet conversion. It can also be implemented in other embodiments by high temperature oxidation or LPCVD ruthenium dioxide. Other barrier dielectrics can include materials with high λ: coefficient, such as oxidized. In a representative embodiment, the tunnel tunneling layer may be 13 A thick SiO2; the offset layer may be 2 〇a thick nitrite; the isolation layer may be 25 A thick oxidized电荷; the charge trap layer may be 7 〇 A thick tantalum nitride; and the barrier dielectric layer may be 90 A thick ruthenium dioxide. The material used in the word lines 116 and 117 is P+ type polysilicon (work) The function (work function) is about 5.leV). [01 Π] FIG. 6 shows the χ_ζ plane taken from the charge trapped memory cell formed on the word line 116 and the semiconductor strip 114 interface. Active charge trapping region 125 and 126 are formed in two of the bands 114 between the word lines 116 and 114 In the embodiment described herein, as shown in FIG. 6, each of the memory cells is a double gate field effect transistor having active charge storage regions 125 and 126 and is located on each side of the semiconductor. The electrons shown in solid arrows in the figure; t/p; 14 semiconductor strips flow to the sense amplifier, where the electron current can be measured 'to indicate the state of the selected memory cell. [0112] Figure 7 shows A cross-sectional view of the 设γ plane formed by the charge trapping memory cells formed on the interface between the word lines 116 and 117 and the semiconductor strip 114. The current path down the semiconductor strip 114 is also shown in the figure. The channel region of the word line is doped with respect to the source and the drain of the conductivity type, and is used as the word line of the word line ι 6 and 22 201232548

The source/drain regions 128, 129, and 13 I between I W/4/VFA 117 may also be "no junction". In a junctionless embodiment, the charge trap field effect transistor can have a P-type channel structure. Also, source and pole doping can be performed in a self-aligned implant after the word line is formed in some embodiments. [0113] In an alternative embodiment, the semiconductor strip lu_114 can be implemented in a junctionless arrangement using a lightly doped N-type semiconductor body, thus providing a hidden channel field effect transistor that can operate in the full mode, and It has a naturally shifted lower threshold distribution of the charge trapping unit. [0114] FIG. 8 is a diagram showing a plane of a memory cell having nine charge trapping units in a NAND configuration. A schematic diagram that represents a cube that can be included, multi-planar, and tilde. The word line 160 and the body of the memory cell used as the word line center -1 and WLn: the second/first stack, the second stack of the semiconductor strip, and the intersection of the second stack of the semiconductor V. [〇Π5] $揞髀留_ 7n in the first plane NAND string of the memory unit „ 卞 电 电 、 、 、 、 、 、 、 、 、 、 、 、 体 体 体 体 体 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 74 and the memory cells 76, 77 in the series on the semiconductor strip. Each of the _ series is ia% 11 (^ 1 ^ 90 and ^ are connected to either side of the NA pin trains 70 and 71). The second plane of the mid-surface memory cell corresponds to the cube- in this example, and includes a method similar to the first plane set at 嶋23 201232548

TW7479PA Tandem memory unit (ie 80, 82 and 84). Included in the t-picture is not used as the word line 161 of the word line wLn. The vertical extension of the material of the trench 120 between the stacks is the memory cell that connects the sub-twist line 161 to the interface region in the trench between the semiconductors 1 in all planes (cells 71, 74 in the first plane) And 77). [〇上18]纟 The memory cell string in the adjacent stack is at the bit line end_to-souixe line end ^•ientat1Gn and the source line end-to-bit The end of the line is alternated (lighter "ine end-to-bU line end 〇rientati〇n" alternates. [〇ii9] bit line BLn&BLn_1 (that is, 96) is the end of the memory string, and the string The column selection means are adjacent. For example, in the top memory plane, the bit line BL· is the end of the memory cell string having the tandem selection transistor rib and (10). In contrast, the bit line is not Connected to the trace 88 (trace), because the adjacent stacked string is alternated between the bit line end-to-source line end and the source line end_to_bit line end. Therefore, for this series, The corresponding bit line is connected to the other end of the string. In the memory plane at the bottom, the bit line BLh is the end of the memory cell string having the corresponding series selection transistor. [0120] Select transistors 85 and 89 in this setting between the respective NAMD series and string select line (SSL) SSLh A connection between SSLns. Similarly, a similar serial selection transistor on the bottom plane in the cube is connected between the respective NAND string and the string select line SSLh& redundancy in this setup. 106 and 108 connect different ridges to each memory unit in series 24 201232548

The gates of the select transistor are serially selected in I w /4/yPA and the select signals SSLrn, sSLn and SSLn+1 are provided in this embodiment. ',' [0121] In contrast, tandem selection transistors are not 88' because the adjacent stacked strings are at the bit line end -:: Guide and source line end-to-bit line ends Alternate between. Therefore, instead of the tandem column, the corresponding tandem selection transistor is connected to the tandem end. The NAND strings with memory cells 74 and 74 are also in series; there are serial selection devices on their terminals (not shown). The wire 88 ends with a source line 107. [0122] The ground selection transistors 9〇_95 are disposed in the nmd series of the ground selection transistors 72, 75, 78 and the corresponding second planar ground selection transistors are disposed at the second end of the surface series. Therefore, the grounding k body is all on both ends of the $ memory string. The transistor is selected based on the particular end of the memory string to ground the memory line, or to the serial selection device and the bit line. The ground selection signal GSL 159 in this embodiment is coupled to the gate of the ground selection transistor 9 " 5, and can be implemented using the same method as the word lines (10) and 161 (where 159 and 162) Also grounding options or GSL). The serial selection transistor and the ground selection transistor can use the same dielectric stack as the gate oxide, as in some of the memory cells of the implementation of column I. In other instances, a typical gate oxide layer is used. And 'channel length and width can be adjusted according to the designer's needs to provide the switching function of the transistor. ^0124] Figure 9 is a perspective view of an alternative structure as in Figure 5. Reference numerals of similar structures are repeatedly used in this figure, and the description will not be repeated here. 25 201232548

TW7479PA is different from FIG. 5 in that the surface ΠΟΑ of the insulating layer 110 and the side faces 113A and 114A of the semiconductor stripes 113 and 114 are exposed between the word lines 116 serving as word lines. The result of the last name engraving process. Thus, the 'memory material layer 115' can be completely or partially engraved between word lines without compromising operation. However, it is not necessary in some structures to form a dielectric charge trap structure through the memory layer 115 # similarly described herein. Figure 10 is a cross-sectional view of the memory cell in the X-Z plane similar to Figure 6. Figure 10 is the same as Figure 6 and shows a structure similar to that of Figure 9, which can be obtained in the cross-section of the memory cell implemented in the structure of Figure 5. Figure 11 is a cross-sectional view of the memory cell in the X-Y plane similar to Figure 7. The difference between Fig. 11 and Fig. 7 is that the memory material along the side (i.e., 114A) sides 128a, 129a, and 13A of the semiconductor strip 114 can be removed. [0126] Figures 12-16 illustrate the basic flow stages of implementing a 3D memory array as described above, using only two pattern masking steps for the critical calibration steps formed by the array. In the figure, the formation of the insulating layer 21 〇, = 2 214 and the semiconductor layer 211 and 213 alternately deposited in the wafer array region, for example, by deposition (deposition), is shown. According to such an embodiment, the semiconductor layers 211 and 213 can be implemented using i f1 or p-type doped polycrystalline or singular single crystal. The insulating layers 21, 212, and 214 may be implemented using, for example, eves, other oxides 11 or I cuts. These layers can be formed in a very low pressure, including the low pressure chemical rolling phase deposition process available in the art. 26 201232548

1 W/4/yPA

[0127] FIG. 13 shows the result of a first lithographic patterning step for shaping a semiconductor strip with a plurality of ridge stacks 250, wherein the semiconductor strips are implemented using the materials of the semiconductor layers 211 and 213, and are The insulating layers 212 and 214 are separated. In-depth, a high aspect ratio and a plurality of layers of trenches can be formed on the stack using a process using a carbon hard mask and a reactive ion etching lithography basis. in. [0128] Although not shown in the figure, the "system" of the memory string is defined as the bit line end-to-source line end guide and the source line end-to-bit line end guide. . [0129] FIGS. 14A and 14B relatively show the next stage of an embodiment including a programmable resistive memory structure such as an anti-fuse cell structure, and including a programmable charge trap memory structure such as s〇N〇s type The next *-stage of the consistent embodiment of the memory early structure. [0130] FIG. 14A shows the result of a deposition of a memory material layer 215 in one embodiment. In this embodiment, the memory material includes a single layer similar to the anti-fuse structure shown in FIG. . In another embodiment, an oxide process is used instead of a blanket deposition to form an oxide on the exposed side of the semiconductor strip, wherein the oxide is used as a memory material. [0131] FIG. 14B shows the results of layer 315 cladding deposition, including a multilayer charge trapping structure comprising tunneling layer 397, charge trapping layer 398, and barrier layer 399, as described above with respect to FIG. As shown in Figures 14A and 14B, memory layers 215 and 315 sink in a conformal manner.

The TW7479PA accumulates on the semiconductor strip with a ridged stack. [0132] FIG. 15 shows the effect of the height-ratio filling step, in which a layer 225 is formed using a conductive material to be used as a word line; and a lightning material is, for example, an N-type or P-type doped polysilicon. Also, 矽 = 226 may be formed over the layer in embodiments utilizing polysilicon. Illustrated in this figure, the (four) 220 between the ridge stacks is used for the high-altitude two-layer deposition technique, such as polycrystalline germanium low-pressure chemical vapor deposition, in the illustrated embodiment, even if the height-height ratio is The narrow groove is narrow to about 10 nm. [0133] FIG. 16 shows the result of a second slab engraving step for shaping a complex digital element line 260 used as a word line in a 3D memory array. The second slab engraving step utilizes a single size for the array. A trench that is masked between the sub-element lines and has a south-to-width ratio. The polysilicon can be etched using an etching process which is highly selective to germanium and ceria. Therefore, the same mask is used to etch through the conductive and insulating layers using an altern etch process, and terminates on the insulating layer 21 as a foundation.曰 [0134] In this step, the ground selection line can also be shaped. In this step, the gate structure controlled by the series selection line can also be formed, that is, the gate structure is conformal to the individual semiconductor strip stacks. [0135] The optional fabrication step includes forming a hard mask on the complex digital line and forming a hard mask on the gate structure. The hard mask can be formed using a relatively thin layer of tantalum nitride or other material that blocks the ion implantation process. After the hard mask is formed, implantation can be performed to increase the doping concentration in the semiconductor strip and the stairstep structure.

TW7479PA J, = reduce the resistance along the current path of the semiconductor strip == two causes the implant to penetrate into the bottom of the semiconductor strip = cover the semiconductor strip from the stack. [0136] Subsequently, the hard mask is removed and exposed = the structural layer on the structure. After forming an interlayer dleiectric on the top of the array, the vias (v(4) are formed in the vias, for example, using tungsten-filled contact plugs (_Plug) to reach the gate structure, such as SSL. Line-like connection to the column decoder circuit. == It uses a word line, - a bit line and a strip SSL line to access the selected unit ^3D„ft.«4j(piane Dec〇dinglth+〇d®^" No.: Special.: — 01一.—一(四)第69°_门 [图Η is an 8-layer vertical J that has been simulated and tested J: ^ Η 8 M~S_charge trapping device Department PUch ^, 。. Channel is about 18 nm thick ^ 曰 with additional joints implanted, become the cover of the 曰曰 曰曰 夕 夕 而 而 而 而 而 而 — — — — — 无 无 无 无 无 无 无 无 无 无 无 无 无The insulating material between Luo and Luo is about 40 nm thick of bismuth dioxide: Γ multi-line to provide the interpole. ssl and off-device have a line and I technology 70 long channel length. The test device implemented 32 characters Engraved i and: 3, ND series. Because of the tapered side wall of the strip used to form the groove 1 of the structure, and because the ^ + is etched more bands Material between shaking table 'in FIG 17 so that the lower belt is larger than the width of the upper band width 29,201,232,548

TW7479PA degrees. [0138] Figure 17 shows different layers of a 3D structure having different side dimensions. This different side dimension between the layers is the source of the different capacitances between the different layers of the 3D structure. 18 is a simplified block diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit line 875 includes a 3D programmable resistive-access memory (RAM) 860 (RRAM) implemented as described herein over a semiconductor substrate having bit line end-to-source line ends The alternate memory is guided in series with the source line end-to-bit line end and is located at either end of the tandem select line gate structure stack over all other stacks. Column decoder 861 is coupled to a plurality of word lines 862 and is disposed along a row of memory array 860. Row decoder 863 is coupled to a plurality of SSL lines 864 disposed along rows corresponding to the stacks in memory array 860 to read and program data from memory cells in array 860. Planar decoder 858 is coupled to the complex planes in memory array 860 on bit line 859. A address is provided on bus 865 to row decoder 863, column decoder 861, and plane decoder 858. The sense amplifier and data-in data structure in block 866 is coupled to row decoder 863 via data bus 867 in this embodiment. The lean material is supplied from the input/output bee on the integrated circuit 875 through the data input line 871, or from a data source internal or external to the other integrated circuit 875 to the data input structure in block 866. In the illustrated embodiment, the integrated circuit includes other circuitry 874, such as a general purpose processor or application specific application circuitry, or a system-on-a-system that provides programmable resistor cell array support (system-on- A-chip) A combination of functional modules. Information from the box 201232548

The sense amplifier in the i W7479PA 866 is output through the data ("- ο milk is supplied to the input/output port on the integrated circuit 875, or to the data destination inside or outside the body circuit 875. 八八, [0140] The controller implemented in the embodiment of the bias setting state machine 869 (_ 肆 肆 ^ ^ emaChlne) is used for one or more voltage suppliers to generate or provide a bias voltage U application, such as reading The programming voltage is taken. t The specific-purpose logic circuit in the technology is realized. In the example, the controller includes a general-purpose processor, and the benefits can be implemented on the same integrated circuit. The general purpose processor executes a computer program to control the operation of the device. In another embodiment, a combination of a specific purpose logic circuit system and a general purpose processor can be utilized to implement other controllers. A block diagram of an integrated circuit in accordance with an embodiment of the present invention. Integrated circuit circuit 975 includes a 3d T flash memory bank 96 having alternating memory string alignment on a semiconductor substrate as described herein. Q, and located at either end of the stack of tandem select line gate structures with all other stacks, the so-called alternation: the tandem train is oriented to the bit line end - to the source line end and source,: The line end is directed. The column decoder 961 is rotated to the plurality of lines of the second line 962' and is disposed along the columns in the memory array. The line solver 963 is transferred to the line corresponding to the stack in the memory array_ The plurality of SSLs, edges 964 are set to fetch the programming data from the memory in array 960. The planar decoder 958 it passes the bit line 959 == the multiple planes in the array _. In the bus 965 (bus ) The upper edge is provided to the row decoder 963 (column decoder), column decoding 31 201232548

TW7479PA 961 (row decoder) and plane decoder gw (plane decoder). The sense amplifier and data input structure in block 966 is coupled to row decoder 963 via data bus 967 in this embodiment. The data is provided from the input/output port on integrated circuit 975 through data input line 971, or from a data source internal or external to other integrated circuit 975 to the data input structure in block 966. In the illustrated embodiment, the integrated circuit includes other circuitry 974, such as a general purpose processor or a special purpose application circuit for the programmable interconnect unit. The data is provided from the sense amplifier in block 966 through the data output line 972 to the input/output ports on the integrated circuit 975, or to the data destinations internal or external to the integrated circuit 975. [0142] The controller applied in the embodiment of the bias setting state machine 969 is used to control the application of the supply voltage through the partial housing generated or provided by one or more of the cells. , erase, program, erase verify, and program verify voltage. The controller can be implemented using a specific purpose logic circuit (10) in the knower technology. In the - replacement 歹 1 'controller includes a general-purpose processor, the controller can be implemented on the integrated circuit, and the same computer program is used to control the operation of the device: another: the other device executes the real == series The combination of the circuitry and the general purpose processor is selected by the continuation of the directional line, the laterally directed series of lines parallel to the word line, and the longitudinally oriented bit line parallel to the strip of semiconductor material 32 201232548

The -3D MD flash memory array structure of the IW7479PA metal layer. =44] Head 20 is the cut of the 3DNAND flash memory array structure to remove the additional structure. Cattle: The insulator, the insulating layer is moved between the semiconductor strips in the ridge stack and removed between the ridge stacks of the semiconductor strip. [0145] The germanium layer array is formed over the insulating layer and includes a plurality of word lines 425-1, ..., 425-nl and 425 11, which are formed in a plurality of ridge-shaped stacks, and a plurality of word lines Used as word lines WLn, WLn 1 WL1. The plurality of ridge stacks include semiconductor strips 412, 4 Ray 1 = L4 ί415 ° The semiconductor strips in the same plane are connected to the stepped structure %. The character line number shown in 丄〇〃 146] is applied from the rear end of the structure to the front end / 曰 from 1 to ,, and is applied to even memory pages. For the odd-numbered hidden page, the sub-line numbers are gradually reduced from Ν to 1 from the back end of the structure to the front end. _Upper 0147] The stepped structures 412α, 413Α, 414Α and 415Α are semiconducting = the end of the strip, for example the end of the semiconductor strips 412, 413, 414 and 415. As shown, these ladder structures 412, 413, 414, and 415 are electrically coupled to different bit lines to connect the decoding circuitry to the selection planes in the array. These stepped structures 412A, 413A, 414A, and 415A can be scribed while forming a plurality of ridge stacks. The ladder structures 4〇2Β, 4〇3β, 4〇4b, and 4〇5β are semi-conductive, and the end of the band is, for example, the end of the semiconductor strips 402, 403, 404, and 405. As shown in the figure, these step structures 402B , 403B, 404B, and 405B (4) connected to different bit lines to connect the decoding circuitry to 33 201232548

The selection plane in the TW7479PA array. These stepped structures 402B, 403B, 404B, and 405B can be scribed while forming a plurality of ridge stacks. [0149] Any given semiconductor strip stack is not coupled to the stepped structures 412A, 413A, 414A, and 415A, or coupled to the stepped structures 402B, 403B, 404B, and 405B, but is not coupled to both. The semiconductor strip stack has one of the two opposite guides of the bit line end-to-source line end guide or source line end-to-bit line end guide. For example, the stack of semiconductor strips 412, 413, 414, and 415 has bit line end-to-source line end steering, while the stack of semiconductor strips 402, 403, 404, and 405 has source line-to-bit lines. End oriented. [0150] The stack of conductor strips 412, 413, 414, and 415 ends at one end by stepped structures 412A, 413A, 414A, and 415A, through SSL gate structure 419, gate select line GSL426, and word line 425-1WL To 425-N WL, the gate select line GSL427, and then end at the other end through source line 428. The stack of semiconductor strips 412, 413, 414, and 415 does not reach the stepped structures 402B, 403B, 404B, and 405B. [0151] The stack of semiconductor strips 402, 403, 404, and 405 ends at one end by stepped structures 402B, 403B, 404B, and 405B, through SSL gate structure 409, gate select line GSL427, and word line 425-NWL To 425-1 WL, gate select line GSL426, then end at the other end through the source line (covered by other parts of the illustration). The stack of semiconductor strips 402, 403, 404, and 405 does not reach the stepped structures 412A, 413A, 414A, and 415A. [0152] As described in detail in the previous figures, the memory material layer separates the word lines 425-1 to 34 from the semiconductor strips 412-415 and 402-405.

I w /4 /yKA 425 n. The ground routing lines GSL 426 and GSL 427 are conformed to a plurality of ridge stacks, similar to word lines. [0153] One end of each stack of the semiconductor strip ends with a stepped structure' and ends with the source line as the other end. For example, the stack of semiconductor strips 412, 413, 414, and 415 end through one of the stepped structures 412A, 413A, 414A, and 415, and end through the source line 428 at the other end. At the proximal end of the figure, a portion of the semiconductor strip stack ends through the stair structures 402B, 403B, 404B, and 405B, while all other portions of the semiconductor strip stack end through the source line. At the end of the figure, all of the other portions of the semiconductor strip stack structure him, side, side, and the same portion; the m-band stack ends through the source line. [0154] The bit line and the tandem selection line are formed on the metal layers mu, ml2, and ML3' and are discussed in the more obvious lower view. [0155] A transistor is formed between the step structures 412a, 413a, 4i4a and the word line 425-1. In the transistor, the semiconductor strip (that is, the "channel region" is used as the channel region. The SSL gate structure (ie, 419 and 4〇9) is shaped during the same step of forming the sub-line 425 1 to 425-n. The top surface of the line 4 is etched 427, and the layers of the two memory materials 415 formed on the gate structures 409 and 419 are used as gate electrodes of the transistors to select the ridges in the array. Selecting gates 21 and 221 will show the side view of the 3D n_ and the body array structure shown in Fig. 20. Fig. 21 shows all three metals 35 201232548

TW7479PA layer MU, ML2 and ML3. Figure 22 shows the lower two metal layers Mu and ML2, t removing the third metal layer MU such that the other metal layers comprise [0157] the first metal layer ML1 comprises a longitudinal guide parallel to the semiconductor material strip. Serial selection line. The MU string select lines are connected to different Ss1 gate structures through the short vias (ie, 4〇9 and [0158]. The second metal layer ML2 includes a tandem select line having a lateral direction parallel to the word line. (4) The ML2 serial selection line is connected to different ML 1 serial selection lines through the short vias. [0159] After combining, these Mu string selection lines and serial selection lines allow the selection of signals using the serial selection signal. Fixed stacking. A [0160] first metal layer]^! also includes two source lines having lateral orientation parallel to the word line. [0161] Finally, the third metal layer ML3 includes a strip of semiconductor material parallel to Longitudinally oriented bit lines. Different bit lines are electrically connected to different stages of the ladder structures 412A, 413A, 414A and 415A and 402B, 403B, 404B and 405B. These MU bit lines allow the use of bit line signals. Selecting a specific horizontal plane of the semiconductor strip. [0162] Because the specific word line allows the character line to select a particular column plane of the memory unit, the triple combination of the word line signal, the bit line money, and the tandem selection line signal Sufficient from memory Shan array element selected specific memory cell selection. 36

201232548 ί w/4/yeA

[0163] FIGS. 23-26 illustrate a parallel string selection line parallel to the semi-conducting 髀鹛 from the "dry 兀 、 、, gate-oriented « jtl ^ ^ ^ , " scoop longitudinally directed string selection line to μ _ A first 3D NAND flash memory array structure that leads to a progressively higher metal layer of the bit line. Figure 23-26 shows the second 3D _ flash memory array 1 ^ Figure 20-22 shows the -3D ΝΑΝ]) flash memory =, it is convenient to view 'Figure 26 step-by-step shift Except for all three metal layers ML1, ML2 and ML3. However, the second 3D-picture flashing hidden body array shown in FIG. 6 shows 32 word lines, while the first 3D-NAND flash memory array shown in FIG. 2〇_22 shows 8 characters. line. Others have different numbers of word lines, bit lines, and tandem selection lines, and correspondingly different numbers of semiconductor strip stacks and the like. And i°i66] and the second 3d nand flash memory shown in FIG. 23_26 shows that the first 3D shown in FIGS. 20-22 is connected to the different stages of the step structure by the poly-plug. NAND flash memory array = shows the metal contact inspection that connects the ML3 bit line to different steps of the ladder structure. [0167] Further, the second 3dnand flash memory array shown in FIG. 23-26 has a serial selection line to the ML1 decoder and a serial selection line through the SSL gate structure on the ML2, and FIG. As shown in Fig. 22, the 3D MND flash memory array has a serial selection line leading to the decoding of the pirates in the anus 2 and a serial selection line leading to the SSL gate structure on the ML1. [0168] FIG. 27 is a first 3D NAND flash memory of FIGS. 20-22.

TW7479HA array structure design. Point [Stone: 2 Λ Figure 27 in the design diagram] The semiconductor strip stack is shown as a straight strip. The adjacent semiconductor strip stacks alternate between the bit line end-to-source line end guide and the source line end-to-bit line end guide. Part of the semi-conductor: band: two from the top bit line structure running to the bottom of the source line junction t-junction semiconductor strip stack from the top of the source line structure to the bottom of the bit line structure. =70] The t-semiconductor strip is stacked with horizontal word lines and horizontal m lines GSL (even) and GSL (odd). Covering the semiconductor strip stack structure. The SSL interpole structure is a stack of all conductor strips at the top of the semiconductor strip and covers the stack of germanium conductor strips at the bottom end of the semiconductor strip. In both cases, the electrical connection between the SSL gate junction conductor strip stack and the bit line contact structure corresponding to the stack. [〇m] The character line number of the heart 'from the top of the figure to the bottom of the figure is sequentially from N to N. The face is used for even memory pages. For odd-numbered memories, the sub-line numbers are gradually reduced from N to 1 from the top of the figure to the bottom of the figure. =, production word line, ground selection line and SSL gate structure Straight running ML1 SSL queue selection line. The overlay says that the string s = is the horizontally running ML2 SSL serial selection line. Although the ML2 serial selection line is displayed as the end of the corresponding serial selection line in order to make it easy to view the structure, '(4) the hungry string selection is selected to be more extended. [The hunger string selection line is transmitted from the solution.,, Nickname, while ML1 SSL serial select line is coupled to these decoders 38 201232548

The TW7479PA signal is routed to a specific SSL gate structure to select a particular semiconductor strip stack. [0Π3] Override the ML1 SSL serial selection source line of even numbers.疋 数 号码 and [0174] $ one step, covering the NGO 2 SERIAL SELECTION line is the ML3 bit line connected to the step contact structure (stepped c〇n plus, picture) at the top and bottom ends (no Shown in the figure). Through the step contact structure, the bit line can select a particular plane of the semiconductor strip. 28 is a layout diagram of the second 3D NAND flash ticker array structure of FIGS. 23-26. The second 3D_== memory array structure shown in Fig. 28 is roughly similar to the first flash surface structure shown in Fig. 27. However, the second 3d face shown in FIG. 28 has a serial selection line to the (four) decoder column select line and the ^ main, upper SSL gate structure, and the ί flash memory structure shown in FIG. There is a k, '· and a tandem selection line to the ML1_LSSL interpole structure to the ML2 decoder.瞌 [丨〇176] Figure 29 is a plan view of a 3D memory array. In the half pitch shown = 32 nm and X half pitch = 43 nm. There are 4 memory layers in the 3D VG N D. The core material in the array (core ^ Wcy) is about 67% (66 贶, with the ssl interpole, GS^SL and BL contacts on it). The single-order unit (7) (1) day, lb/c) has a density of 32 Gb. The wafer size is approximately 76 mm2.剡, FIG. 30 illustrates a laterally directed string selection line parallel to the word line, a longitudinal guide string selection line parallel to the semiconductor strip, and a progressive metal layer of the longitudinal guide bit line of the 31)=3 body material strip. ', flash 5 recalled array structure. 3G is similar to Figure 23. Figure 39 201232548

The change of TW7479PA 30 compared to FIG. 23 is to increase the first set of array layer numbers (1)_(4) to the bit lines, and to add the second set of array layer numbers (1)_(4) to include the step structure. Bit line structure of 402B, 403B, 404B, and 405B. These array layer number groups are used to show that a particular bit line is electrically connected to a particular array layer location. [0178] FIG. 30 shows a memory block having a sequence of positional positions of 2, 3, and 4 planes. Correspondingly, as the bit line structure traverses from the first end to the second end, successively numbered bit lines 4 (that is, numbered from left to right, right to left, or other consecutive order) are used by The step contact structure (also referred to as a bit line structure) is coupled to the plane position 丨_4 (that is, numbered from top to bottom, bottom to top, or other order) ^ [0179] FIG. 31 has a specific bit The 3D NAND flash memory array structure design diagram of the bit line indicated by the number of the line access array layer. In the example shown, as with the four bit lines that are traversed sequentially (that is, numbered from left to right, right to left, or other order), the bit lines are also in plane positions 1, 2, and 3. And 4 to mark. Therefore, as the four bit lines that traverse sequentially, the bit lines are also coupled to the plane positions 1-4 by a step contact structure (also referred to as a bit line structure) displayed in a dashed box. It is numbered from top to bottom, bottom to top or other order). [0180] FIG. 32 is a structural diagram of a bit line 3D NAND flash memory array having numbered arrays accessed by bit lines, showing adjacent bits having different sequences coupled to the array layer. The block of the line. [0181] Figure 32 shows a translation sequence with different bit line structures having planar positions. For example, the different bit line structure planes displayed 201232548 TW7479PA have different sequences of 1, 2, 3, and 4; 2, 3, 4, and 1; and 3, 1, and 2. Correspondingly, the bit line running from the top to the bottom and connected to different f-element structures is connected to the plane positions 1, 2 and 3 (in order from the bit line structure to the bottom bit line structure) The two left-handed lines running from the top to the bottom and connected to different bit line structures are connected to =Ϊ, set 2/3 and 4 (from the top line structure to the bottom line structure); The two left sides run from top to bottom and are connected to different bit lines to form green two: , ? ' is connected to plane positions 3, 4 and 1 (in order from the top bit '0 'Ζ & bit line structure) The fourth left line runs from the top to the bottom to the different bit line structure, and is connected to the plane position 2 (in order from the top bit line structure to the bottom bit line structure). And above: 8:] "In some embodiments, the number of the bit line structure is selected so that each word line is like another character: the so-called capacitance' is because the connection is the same as the other bits. The plane position combination of the line. The same: the upper 8 ί embodiment includes a different number of bit lines and different numbers of _ connected to the bit line of the bit line For example, double or quadratic. The invention has been described in detail with reference to the preferred embodiments and examples, which are intended to illustrate and not to limit the invention, without departing from the spirit and scope of the invention. Applicant's application for the exclusive protection of the invention 201232548

TW7479PA BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a 3D memory structure as described herein, including a plurality of planes of a strip of semiconductor material disposed parallel to the Y-axis and disposed in a plurality of ridge stacks, memory on the side of the semiconductor strip. The body layer and the plurality of word lines having a conformal bottom surface and disposed across the ridge stacks. Figure 2 is a cross-section of the memory cell taken from the χ_ζ plane in the structure of Figure 1. Figure 3 is a cross-section of a memory cell taken from the χ-γ plane of the structure of Figure 1. Fig. 4 is a view showing the memory of the structure having the structure of Fig. 1 based on an antifuse. Figure 5 is a perspective view of the 3D NAND flash memory structure described herein, including a plurality of semiconductor strips t-planes parallel to the gamma axis and disposed in a plurality of ridge stacks, and a charge trapping memory on the side of the semiconductor strip The body layer and the plurality of lines having a conformal bottom surface and disposed across the ridge stacks. 6 is a cross section of the memory cell taken from the χ_ζ plane in the structure of FIG. 5. FIG. 7 is a memory cell taken in the Χ-Υ plane of the structure of FIG. 5, and FIG. 8 is a diagram showing the structure of FIG. 5 and FIG. NMD flash memory overview. ~, 9 is another perspective view of the 3DNAND flash memory structure similar to that of Figure 5, in which the memory layers are removed from between the word lines. 42 201232548

I W/4/ypA Figure 10 is a cross section of the memory cell taken from the X-Z plane in the structure of Figure 9. Figure 11 is a memory unit wearing surface taken from the Χ-Υ plane in the structure of Figure 9. Figure 12 illustrates the first stage of a process for fabricating a memory device similar to that of Figures 1, 5 and 9. Figure 13 is a diagram showing the second stage of a process similar to that of the memory devices of Figures 1, 5 and 9. Wang Fig. 14 shows the three stages of the process of manufacturing a memory device similar to that of Fig. 1. Figure 14 is a three-stage diagram showing a procedure for fabricating a memory device similar to that of Figure 5. Figure 15 is a diagram showing the third stage of manufacturing similar to the drawing. 1, 5, and 9 § Reconstruction device diagram 16 shows the fourth stage of the process of manufacturing a memory device similar to that of Figures 5, 9 and 9, followed by a hard mask and a selective implant Another stage of the steps. Figure Π is a transmission electron nncroscope (TEM) of a 3D MAND flash memory array: 8 is the product of a 3D visibly and privately resisted hidden body array with row, column and plane decoding circuitry. A schematic diagram of the body circuit. Figure 19 is a diagram including a row, column and plane decoding circuit system.

A schematic diagram of the integrated circuit of the TW7479PA surface flash memory array. Figure 20-22 shows the green metal layer of the first and tandem selection lines: = two: IS in the semiconductor material strip, transversely parallel to the character two D flash memory array junction semiconductor material strip The tandem selection line and the longitudinal direction - Fig. 23-26 is the green height of the first-other θ tandem selection line; the layer 2: Ν = the bit line of the semiconductor material strip of the semiconductor material strip. The heart selection line and the tool are longitudinally parallel to Fig. 27. The design of Fig. 2-2 is the design of the Xizhe c\ rv structure. The first 3D surface flash memory array NAND flash memory array is shown in Fig. 23- 26 of the design of the second 3d structure. Figure 29 is a plan view of a 3D memory array. Figure 30 is a diagram showing a 3D Μ N D flash memory array structure accessed by bit lines and having bit lines labeled by array layer numbers. Figure 31 is a block diagram of a 3D NAND flash memory array structure accessed by bit lines and having an array layer number designation. 32 is a design diagram of a 3D NAND flash memory array structure accessed by bit lines and having an array layer number designation, and showing adjacent blocks having bit lines coupled to the array layers in different sequences. . [Main component symbol description] 201232548

TW7479PA 10, 110, 210, 212, 214: insulating layers 11-14, 5b 56, 11b 114: semiconductor strips 15, 115, 215, 315: memory material layers 16, 17, 60-61, 116, 117 , 160, 161, 260: word line 18, 19, 118, 119, 226: telluride 20, 120, 220: trench 21-24, 121-124: insulating material 25, 26: active area 30-35, 40-45: Memory cells 60-1 to 60-3: word line extensions 97, 397: tunneling dielectric layers 98, 398: charge storage layers 99, 399: blocking dielectric layers 125, 126: charge design Trap area 12 8 -13 0 . Source / j: and polar regions 82, 84 : memory cells of 70, 71, 73, 74, 76, 77, 80 in the NAND string

9 6 : Bit line, 90-95: Ground selection

85, 89: Tandem Selective Transistor 88: Leading Wire 106, 108: Tandem Select Line 107: Source Line 159, 162: Ground Select Signal 113A, 114A: Side of Semiconductor Strip 110A: Surface of Insulation 45 201232548

TW7479PA 128a-130a: regions 211, 213 along the side of the semiconductor strip: semiconductor layer 250: ridge stack 225 of semiconductor strip: layer 8 5 8 , 9 5 8 · planar decoder 96, 859, 959: bit line 860 960: Memory arrays 861, 961: Column decoders 862, 962: Word lines 863, 963: Row decoders 864, 964: Tandem select lines 865, 965: Bus bars 866, 966: Blocks 867, 967: Data bus 868, 968: blocks 869, 969: bias setting state machine 871, 971: data input lines 872, 972: data output lines 874, 974: other circuit systems 875, 975: integrated circuits 402-405, 412 -415 : Semiconductor strip 402B-405B, 412A-415A: stepped structure 409, 419: tandem select line gate structure 426, 427: ground select line 4254~425-N: word line 428: source line 46

Claims (1)

201232548 TW7479PA VII. Patent application scope: I—memory device, comprising: a s-resonant array with memory cells at a plurality of plane positions; a plurality of bit line structures having a plurality of plane positions And a sequence comprising at least two distinct sequences, each of the sequences depicting a sequence characteristic of the planar positions of the bit line structures coupled to the bit lines. 2. The memory device of claim 1, wherein the memory cells of the array are disposed along the half of the strip of conductor material in the NAND string. 3. The memory device of claim 1, wherein the memory cells of the array are disposed along the plurality of semiconductor material strips between the bit line structures and the plurality of source lines. 4. The memory device according to claim 1, wherein the phase of the electric valley is characterized by a different plane position of the planar positions. 5. The memory device of claim 1, wherein the different sequences of the sequences of the bit line structures are averaged and the different planar positions of the planar positions are Characteristic differential capacitance. 6. The memory device according to claim 1, wherein the I»Hai 兀 line structure is coupled to the plane positions of the bit lines, and the one of the 70 line structures An end spans a second end corresponding to one of the bit line structures. 47 201232548 I W/4/yPA 7. In the first application of the patent scope, the array is a block of the memory device described herein. The 7° line structure is separated into a plurality of memory areas b. The semiconductor materials in the ith column of the claim i are in the column _ and the one of the word lines in the array is stopped; Special:: Conductor selection, used to identify the county in the array:: The combination of the special scorpion reading selects a specific memory unit of the early morning J. In the memory device of the first aspect of the invention, the memory device of the first aspect of the invention includes a plurality of charge traps; and a resistive layer. A memory device according to the invention of claim 4, comprising a substrate; a plurality of semiconductor material strips stacked in a ridge shape, and comprising a strip of conductive material "separated from a plurality of planar locations" An integer number of word lines disposed across the stacks and having a conformal surface with the stacks; and a plurality of memory elements located in the interface area, The memory device establishes a memory array of the memory cells through the strips of semiconductor material and the word lines; wherein the bit line structures are located at the ends of the stacks. 11. A memory device, The method includes: a memory array having a plurality of memory cells in a plurality of plane positions; 201232548 1 W/4/yPA; half-face bit lines, each of which is left to be different Less two different a planar position 'and accessing the memory cells at the at least two phase/tenth position. 12. The memory device of claim 2, wherein the memory cells of the array are The semiconductor device is disposed along the plurality of semiconductor material strips, wherein the memory devices of the array are along the bit line structure and the plurality of memory devices. The semiconductor material strips are disposed between the source line structures. 14. The memory device of claim 4, wherein the main electric valley system traces the dissimilar planar positions of the planar positions According to the memory device described in item n of the patent application, the :Hai array is separated into a plurality of memory blocks by the bit line structure. Up to _^6. The memory device according to the eleventh aspect, wherein the combination of the specific semiconductors in the array of semiconductor materials in the array and the specific word lines of the word lines in the (four) column is used To identify a particular memory cell in the array 17. The memory device of claim 2, wherein the memory elements of the array comprise a plurality of charge trapped two-charge δ-recessed structures including a pass-through layer and a charge A sinking layer and a barrier layer. 49 201232548 TW7479PA, comprising: i8. The memory device according to claim 2, wherein the plurality of semiconductor material strips are stacked on the substrate, and the two semiconductor material strips are ridged. The material booklet is separated from the parent by a plurality of plane positions. · The coffin is separated by an insulating material: a memory array with a ==2=span=: G body 7 早 early; The bit line structures are located at the ends of the stacks. And "9 this application for the memory device described in item 18 of the special-profit range" 2: The mother-strip line of the two-strip line is coupled: at least two different planes of the different stacks in the stack: = = = the planar position comprises a first flat center of a first semiconductor strip stack and a second planar position of a second semiconductor strip stack, such that the w-th body strip stack and the memory block.宜马相异1 is =0. As described in claim 18, the memory device described in claim 18, each of the 70-line bits is connected to at least two different layers of the semiconductor material stack Heap # a planar position, wherein the two phases are included, the second planar position of the first planar bit body strip stack of the first semiconductor strip stack, such that the ... The stack is accessed by the distinct group of character lines of the sub-lines.