201230333 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電晶體及其製作方法，特別是指 一種具有低米勒電容之超級介面的功率電晶體及其製作方 法。 【先前技術】 功率電晶體（power metal-oxide-semiconductor field transistor)是一種利用多數載子（majority carrier)導電，並以201230333 VI. Description of the Invention: [Technical Field] The present invention relates to a transistor and a method of fabricating the same, and more particularly to a power transistor having a low interface of a low Miller capacitance and a method of fabricating the same. [Previous technology] A power metal-oxide-semiconductor field transistor is a type of electricity that utilizes a majority carrier and
電壓控制電流的元件’具有開關速度快、高頻性能佳，及 能承受高電壓等優點，因此，通常並聯多數個功率電晶體 而作為輸入電壓為數十至數千伏特的功率開關電路運用。 參閱圖1，目前的功率電晶體i包含一汲極結構丨丨、一 形成於該汲極結構11上的磊晶結構12、一閘極結構i3，及 一源極結構14，以下以n型的功率電晶體i作說明。 該沒極結構11是選自n型半導體材料並Μ晶的方式 形成。 s亥磊晶結構12包括一形成於該汲極結構丨丨上且具有打 型電性的第―區121、—形成於該沒極結構11上並與該第 一區12U目鄰且具有μ電性的第二區122 '一形成於該第 —區122頂面且具有η型電性的源極區123,及-形成於該 第二區122頂面且具有ρ型電性的接觸區124。其中，η型 電性表示該區域具有η型半導體㈣的電特性，ρ型電性表 不該區域為具有ρ型半導體材料的電特性。 义 該4二區122具有-連結於該汲極結冑11上的基部 201230333 125，及一位於該第一區121及該源極區i23間的重摻雜部 126，該重摻雜部126的載子濃度大於基部125的載子濃度 〇 έ亥閘極結構13包括一介電層131，及一導電層132, 該介電層131形成於該第一區121的頂面及該第二區 的頂面且未被該源極區123及該接觸區124覆蓋之區域’ 該導電層132形成於該介電| 131上並可對外電連接而可 接受來自外界的電能。—般，介電層131是二氧化石夕構成 ’導電層13 2是多晶石夕構成。 該源極結構14與該閘極結構13的導電層132間隔且 彼此絕緣地形成於該源極區123及該接觸區124頂面，並 以可導電的材料，例如鎢，構成而可對外電連接。 當分別給予該閘極結構13的導電層132及該汲極結構 11對應該源極結構14 m電壓時，電子自該没極結構^ 流經該磊晶結構12的第一區121與第二區122的基部 所形成的超級介面（super juncti〇n)、重摻雜部126，及該源 極區123而形成導電通路；此時，該具n型電性的第二區' 12i提供通路，且可藉由該第—㊄121及連結該第_區⑵ 與該基部125形成超級介面之空乏區作為電子流的緩衝， 進而使該功率電晶體i在給以電壓的環境下正常作動。 上述的功率電晶體1是先以一第一 η型蟲晶層體作為 汲極結構U，並於餘極結構u上心晶的方式形成―較 該第-η型蟲晶層體的載子濃度低的第二。型蟲晶層體。 接著，在該第二n型蟲晶層體頂面以飯刻的方式形成 201230333 至乂 渠’並同時界定以n型蟲晶層體構成的第-區121 2於該溝渠底部以晶的方式填覆滿Ρ型半導體材料而 形成第二區122。 然後於該第一區121頂面形成介電層131，及導電層 132構成閘極結構13。 之後，利料成的閘極結構13作為罩幕，以離子佈植 t方式植人濃度較填覆滿該溝渠的ρ型半導體材料的載子 濃度高的載子，而將該第二區122界定出連結該沒極結構 的基。Ρ 125及重摻雜部126 ;並類似地以離子佈植的方式 在該第二區122頂面形成源極區ι23。 最後’用絕緣材料自第二區122及源極區123丘同界 定的表面向上形成中間層後，於該中間層頂面以姓刻的方 式形成與閘極結構13的導f層132 _且絕緣的連接孔， 再以離子佈植时切祕職m，並料接孔巾填覆鷄 (於業界慣稱為“接觸插塞”）而成為源極結構Η，完成 該功率電晶體1的製作。 目刖功率電晶豸i的主要問題在於：形成超級介面的 第一區121與第二區122時，是利用钱刻後配合蠢晶方式 填入P型半導體材料，而轰晶的製程成本較高、且執行技 術也較困難，此外，蝕刻會造成後續形成的超級介面不平 整，及/或有晶格缺陷而為「不連續面」，進而 動，此外，第一、二區一的連接面為異質= 為第一、二區121、.122的構成材料不同），如此導致電荷 易被抑制（trap)而累積於超級介面，進而造成功率電晶體^ 5 201230333 作動時電机的不穩定、不可預測’以及漏電流的問題 此外，由於受限於製程，目前的功率電晶體ι的 閘極結構Π的介電層131直接接觸 而以成功率m具有較大岐極與閘極間電容 長開啟/關閉的時間。 【發明内容】 因此，本發明之目的，即在提供一種作動穩定、開啟/ 關閉反應快速的具有低米勒電容之超級介面的㈣μ胃 的製作方法。 Ba 此外’本發明之另-目&，即在提供—種作動穩定、 開啟/關閉反應快速的具有低米勒電容之超級介面的功率電 晶體。 於是，本發明之一種具有低米勒電容之超級介面的功 率電晶體的製作方法’包含以下五步驟。 首先，在一具有第一電性的半導體材料所形成的第— 層體上，用具有相反於第一電性之第二電性的半導體材料 形成一第二層體。 接著，於該第二層體上依序以介電材料和導電材料形 成一介電層，及一形成於該等介電層上的導電層。 再來，自該導電層的表面向下形成一深度至該第二層 體且用絕緣材料界定形成的連接孔，及一與該連接孔間隔 的溝渠。 繼續，在該溝渠内填覆一具有多數載子而成第—電性 的半導體材料後，進行熱處理使該等載子擴散進入該第二 201230333 層體中而使該第二層體形成 及一保持第二電性的第二區 導體材料。 —轉變為第一電性的第一區， ，然後移除填覆該溝渠中的半 最後’在對應該連接孔的 有第一電性並與該第—區間隔 料於該連接孔中，製得該具有 率電晶體。 第二區頂部形成一轉變為具 的源極區，再填覆一導電材 低米勒電容之超級介面的功The voltage-controlled current element has the advantages of fast switching speed, high frequency performance, and high voltage tolerance. Therefore, a plurality of power transistors are usually connected in parallel as a power switching circuit having an input voltage of several tens to several thousands of volts. Referring to FIG. 1, the current power transistor i includes a drain structure structure, an epitaxial structure 12 formed on the gate structure 11, a gate structure i3, and a source structure 14, and the following is an n-type The power transistor i is described. The electrodeless structure 11 is formed by being selected from an n-type semiconductor material and twinned. The s-earth crystal structure 12 includes a first region 121 formed on the gate structure and having a pattern-type electrical property, formed on the pillar structure 11 and adjacent to the first region 12U and having μ An electrically conductive second region 122' is formed on the top surface of the first region 122 and has an n-type electrical source region 123, and a contact region formed on the top surface of the second region 122 and having p-type electrical properties 124. Here, the n-type electrical property indicates that the region has electrical characteristics of the n-type semiconductor (four), and the p-type electrical property indicates that the region has electrical characteristics of the p-type semiconductor material. The 4 second region 122 has a base 201230333 125 connected to the drain crest 11 and a heavily doped portion 126 between the first region 121 and the source region i23. The heavily doped portion 126 The carrier concentration is greater than the carrier concentration of the base 125. The gate structure 13 includes a dielectric layer 131 and a conductive layer 132. The dielectric layer 131 is formed on the top surface of the first region 121 and the second The top surface of the region is not covered by the source region 123 and the contact region 124. The conductive layer 132 is formed on the dielectric|131 and can be electrically connected to the outside to receive electrical energy from the outside. Generally, the dielectric layer 131 is composed of silica dioxide and the conductive layer 13 2 is composed of polycrystalline stone. The source structure 14 is spaced apart from the conductive layer 132 of the gate structure 13 and is insulated from each other on the top surface of the source region 123 and the contact region 124, and is made of an electrically conductive material, such as tungsten, and can be externally charged. connection. When the conductive layer 132 of the gate structure 13 and the gate structure 11 are respectively corresponding to the voltage of the source structure 14 m, electrons flow from the first structure 121 and the second region of the epitaxial structure 12 from the gate structure A super interface (super juncti), a heavily doped portion 126, and the source region 123 formed by the base of the region 122 form a conductive path; at this time, the n-type second region '12i provides a path And the vacant region forming the super interface with the base portion 125 and the base portion 125 can be used as a buffer for the electron flow, and the power transistor i can be normally operated under the environment of giving a voltage. The power transistor 1 described above is formed by using a first n-type crystal layer as the gate structure U and forming a crystal on the remnant structure u to form a carrier smaller than the first-n type insect layer. The second is low in concentration. Insect crystal layer. Then, on the top surface of the second n-type crystal layer, a 201230333 to a trench is formed in a rice-like manner, and at the same time, a first region 1212 composed of an n-type crystal layer is defined as a crystal at the bottom of the trench. The second region 122 is formed by filling the germanium-type semiconductor material. Then, a dielectric layer 131 is formed on the top surface of the first region 121, and the conductive layer 132 constitutes the gate structure 13. Thereafter, the gate structure 13 is formed as a mask, and the carrier having a higher concentration of the carrier than the p-type semiconductor material filling the trench is implanted by the ion implantation method, and the second region 122 is implanted. A base that links the infinite structure is defined. Ρ 125 and heavily doped portion 126; and similarly, source regions ι23 are formed on the top surface of the second region 122 by ion implantation. Finally, after the intermediate layer is formed upward from the surface defined by the second region 122 and the source region 123, the conductive layer is formed on the top surface of the intermediate layer in a manner of a surname with the gate layer 132 of the gate structure 13 Insulated connection hole, and then cut the secret m when ion implantation, and fill the hole to fill the chicken (known in the industry as "contact plug") to become the source structure Η, complete the power transistor 1 Production. The main problem of witnessing the power transistor 豸i is that when the first region 121 and the second region 122 of the super interface are formed, the P-type semiconductor material is filled by using the money engraving and the stupid crystal method, and the process cost of the blasting is relatively high. High, and the implementation of the technology is also more difficult, in addition, the etching will cause the subsequent formation of the super interface is not flat, and / or have lattice defects as a "discontinuous surface", and then move, in addition, the first and second zone one connection The surface is heterogeneous = the composition materials of the first and second regions 121 and .122 are different), so that the charge is easily trapped and accumulated in the super interface, thereby causing the instability of the motor when the power transistor ^ 5 201230333 is actuated. In addition, due to the limitation of the process, the dielectric layer 131 of the current power transistor ι has a direct contact with the dielectric layer 131 and has a large drain and gate capacitance at a success rate m. Long on/off time. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method for fabricating a (four) μ stomach having a super interface with a low Miller capacitance that is stable in operation and fast in on/off. Further, the invention of the present invention provides a power transistor having a low interface of a low Miller capacitance which is stable in operation and on/off. Thus, the method of fabricating a power transistor having a super interface of low Miller capacitance of the present invention comprises the following five steps. First, a second layer body is formed on a first layer body formed of a semiconductor material having a first electrical property by a semiconductor material having a second electrical property opposite to the first electrical property. Then, a dielectric layer and a conductive layer formed on the dielectric layers are sequentially formed on the second layer by a dielectric material and a conductive material. Further, a connection hole is formed downward from the surface of the conductive layer to the second layer and defined by an insulating material, and a trench spaced from the connection hole. Continuing, after filling the trench with a semiconductor material having a plurality of carriers and forming a first electrical property, heat treatment is performed to diffuse the carriers into the second layer of 201230333 to form the second layer body and A second electrical conductor material that maintains a second electrical property. - converting to the first region of the first electrical property, and then removing the filling of the half of the trench last 'the first electrical property corresponding to the connecting hole and spacing the first region into the connecting hole, The rate transistor is obtained. The top of the second region forms a source region that is converted into a device, and is filled with a conductive material.
^卜’本發明—種具有低米勒電容之超級介面的 電曰曰體包含-汲極結構、—路徑結構、—源極結構，及一 閘極結構。 ㈣極結構以具有第—電性的半導體材料所形成。 該路徑結構以半導體材料構成並與該沒極結構連姓， =路徑結構包括一具有第一電性的第一區、一具有相；於 第-電性之第二電性的第二區，及一遠離該沒極結構並也 該第一區間隔且具有第一電性的源極區，該第一、二區的 界面是晶格連續面。 該源極結構與該源極區連結並用於對外電連接。 δ亥閘極結構包括一形成在該路徑結構上並與該第二區 連結的介電層，及—形成在該介電層上並與該源極結構絕 緣的導電層。 曰本發明之功㉛：提㈣的製#方法製作一種具有完整 晶格連續超級介面的具有低米勒電容之超級介面的功率電 曰曰體，減；電子因超級介面的晶格缺陷而被侷限的機率， 、a加4具有低米勒電容之超級介面的功率電晶體的作動 201230333 穩定度與崩潰電壓，同時增加開啟/關閉反應速度。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之二個較佳實施例的詳細說明中，將可 清楚的呈現。 在本發明被詳細描述之前，要注意的是’在以下的說 明内今中’類似的元件是以相同的編號來表示。 ’本發明一種具有低米勒電容之超級介面 的製作方法之一第一較佳實施例是製作出 參閱圖2、3 的功率電晶體 如圖3所彔沾 如圖3所示的功率電晶體2。 先請參閱圖2,該具有低米勒電容之超級介面的功率電 日曰祖2包3及極結構21、一與該没極結構21連結且以半 導aa材料構成的路徑結構22、一與該路徑結構22連結的源 極結構24，及一形成在該路徑結構22上的閘極結構23。 該汲極結構21以具有第一電性的半導體材料並以磊晶 的方式形成’以該第-較佳實施制製得的具有低米勒電 容之超級介面的功率電晶體2而言，該具有第一電性的半 導體材料即η型半導體材料β 該路徑結構22包括一具有第一電性的第一區221、一 具有第二電性且形成於該汲極結構21上的第二區222，及 一形成於該第二區222頂面_ 頂面且與該第一區221以該第二區The present invention - an electrical interface having a low interface of a low Miller capacitance comprises a drain structure, a path structure, a source structure, and a gate structure. (4) The pole structure is formed of a semiconductor material having a first electrical property. The path structure is composed of a semiconductor material and has a surname with the non-polar structure, and the path structure includes a first region having a first electrical property, a phase having a phase, and a second region having a second electrical property of the first electrical property. And a source region away from the gate structure and also spaced apart from the first region and having a first electrical property, wherein the interfaces of the first and second regions are lattice continuous faces. The source structure is coupled to the source region and used for external electrical connection. The delta gate structure includes a dielectric layer formed on the path structure and coupled to the second region, and a conductive layer formed on the dielectric layer and insulated from the source structure.功 31 31 : : : : : : : : : : : 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 The limited probability, a plus 4 power amplifier with a low interface of low Miller capacitance, operates 201230333 stability and breakdown voltage, while increasing the on/off reaction speed. The above and other technical contents, features and effects of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention. Before the present invention is described in detail, it is to be noted that the same elements in the following description are denoted by the same reference numerals. A first preferred embodiment of a method for fabricating a super interface having a low Miller capacitance is to fabricate a power transistor as shown in FIGS. 2 and 3, as shown in FIG. 2. Referring to FIG. 2, the power interface of the super interface with a low-Miller capacitor, the second package 3 and the pole structure 21, a path structure 22 connected to the gateless structure 21 and composed of a semi-conductive aa material, A source structure 24 coupled to the path structure 22, and a gate structure 23 formed on the path structure 22. The drain structure 21 is formed by a semiconductor material having a first electrical property and epitaxially forming a power transistor 2 having a low interface of a low Miller capacitance prepared by the first preferred embodiment. The semiconductor material having the first electrical property, that is, the n-type semiconductor material β, the path structure 22 includes a first region 221 having a first electrical property, and a second region having a second electrical property and formed on the gate structure 21 222, and a top surface _ top surface of the second region 222 and the second region with the first region 221
201230333 一區221而使該第一區221與該没極結構21 μ以第二區 222作為間隔。該第二電性相反於該第_電性而為ρ型電性 〇 ，該第二區222具有-連結㈣極結構21的基部奶、 一形成於該基部225上的重摻雜部如，及—形成於該重推 雜部226上並與該源極區如連結且與該第—區221間隔 的接觸區咖。該接觸區224以具有第二電.性的半導體材料 所形成，該接觸區224的第二電性的載子濃度大於該重換 雜部226的第二電性的載子濃度，且”㈣冑226的第 -電性的載子濃度大於該基部225的第二電性的載子濃度 ，該接觸區224及該源極區223皆與該重摻雜部226連社 並與該基部225間隔。 ° 、該源極結構24連結該源極區功與該接觸區似，且 以可導電的材料例如鶴形成（於業界慣稱為“接觸插塞，，） ，並可與外界電連接。 土 該閉極結構23包括一形成於該路徑結構22 部以和該第-區221共同界定的頂面的介電層231」形 成於較電層231上的導電層232，及—形成於 扣側周面的絕緣壁233。該介電層231與該絕緣壁加可 由例如二氧化石夕、氮化石夕’或此等材料的組合所構成，該 導電層232以導電材料例如多晶石夕構成，而該導電層232 错由該絕緣壁233與該源極結構24間隔且電不連接。 :施加塗該間極結構23的導電層232對應該源極 -構24’及該沒極結構21對應該源極結構“時，電荷經 201230333 該路徑結構22的第一區22i與該第二區222的基部225形 成的超級介面而電導通；此外，電荷可藉由該第一區221 與該基部225間形成之超級介面的空乏區，及該第一區221 與該沒極結構21間形成的空乏區作為電子流的緩衝，進而 使該具有低米勒電容之超級介面的功率電晶體2可在施加 高電壓時正常作動。 述的-有低米勒電谷之超級介面的功率電晶體2的 製作方法在經過以下本發明第一較佳實施例的說明後，當 可更加清楚的明白。 參閲圖3、圖4、圖5,首先’進行步驟以，以編 方式依序用第-、二電性的半導體材料形成預定作為没極 結構的第，25,及一連結於該第一層體25上的第 二層體26’ ’再於該第二層體26頂面以離子佈植的方式植 入具有第二電性的载子，而將該第二層體26區分為一純磊 晶層262及一井層261。 參閱圖3、圓6,接續進行步驟32，於該第二層體％ 的井層261頂面依序形成一選自絕緣材料的介電層231、一 以導電材料所構成的導電層232,及—硬遮幕層23〇接著 ，利用微影及_等製程將該介電層231的其中一部份， 及對應該部份之介電層231的導電層232與硬遮幕層W 移除，而使該第二層體26的部份頂面裸露，再於該第二層 體26上^導電層232的側周面形成—絕緣壁加(如圖7所 不）在„亥第-較佳實施例中，該導電層加是選自多晶石夕 ，該介電層231與絕緣壁233選自二氧化石夕、氮化石夕，及 £ 10 201230333 其組合為材料所製成。 參閱圖3、圖7,接著，進行步驟33,依序利用微影及 钮刻專製程自該第二層體26裸露的頂面依序往下形成— '果 度至該純蟲晶層262的溝渠27,及-與該溝渠27間隔且深 度至該井層261的連接孔28。由於該導電層加頂面連处 該硬遮幕層234，故若於形成該溝渠27及該連接孔μ的^ 程中，曝光機台在對準時產生偏移，該介電層231及 電層加亦有該絕緣壁233及該硬遮幕層234的保護，而 可避免在㈣溝渠27,及域連接孔28時受到破壞；即該 硬遮幕層234在上述微影及敍刻製程時可提供為自我對準 (self align)，以保護該導電層232及該介電層η〗的完整 性，及增進形成該溝渠27與該連接孔28的位置精確程度 〇 參閱圖3、圖8,繼續，進行步驟34,在該溝渠27内 及該連接孔28内填覆滿一具有第—電性的半導體材料291 ’在該第—較佳實施财，填覆該溝渠27及該連接孔28 的半導體材料291是選自财玻璃（ph〇sph〇siHcate加 (B〇rophosphosilicate glass, BPSG)、摻料的碎玻璃，及其中之—組合為材料所製成。 接著進行熱處理製程，使填覆料料π及料接孔Μ 中具有第-電性的載子擴散進人該第二㈣％，進而使鄰 近該溝渠27之部份第二層體26由原本的第二電性轉變成 為相反於該第二電性的第一電性的第—區221，且鄰近該連 接孔28之部份第二層體26轉變成為相反於該第二電性的 201230333 第一電性的源極區223，再將該溝渠27中及該連接孔28中 具有第一電性的半導體材料移除，使該第一區22丨及該源 極區223的範圍固定不再擴大。其餘未形成該第一區221 及該源極區223之第二層體26的純磊晶層262界定為基部 225。第一層體26的井層261界定為重摻雜部226。而該第 區221及该第222間形成晶格完美且連續的超級介 面0 再需說明的是，若在該溝渠27中依序填覆二具有第一 電性的半導體材料291，且先填入的半導體材料的載子濃度 大於後續填人的半導體材料291的載子濃度，則可更精確 地調控該源極區223及該第—區221間的重摻雜部咖的 距離，即該第一較佳實施例所製得的具有低米勒電容之超 級介面的功率電晶冑2之通道的長度，並可避免該第一區 221與該源極區223接觸。 处1无早獨於該溝木以 =導料料與進行減理使載子擴散，再另㈣子佈㈣ =對應該連接孔28的第二層體26頂部而形成該源相 填m、圖9’最後’進行步驟35,在該溝渠27户 子 性物質292’使溝渠27内不再含有具電 以離子佈植的方式在對應該該連接孔以底部的_ 二，二成一較該重摻雜部226的載子濃度高的接_ =觸區224與該源極區223連結 (㈣金屬）填覆於該連接孔28而製_«_24 S. 201230333 而製得具有低米勒電容之 使該源極結構24可對外電連接 超級介面的功率電晶體2。 精由該重摻雜部226的載子濃度的控制 佳實施例製得的具有低米勒電容之超級介面的功率電= 的第一區221與該介電層如間重疊的區域較目前的功% 電晶體少，進而使沒極與問極間的電容值降低，進而顯著 降低在源極輸出的米勒電容。A region 221 of 201230333 causes the first region 221 and the gate structure 21 μ to be spaced apart by the second region 222. The second electrical property is a p-type electrical enthalpy opposite to the electrical conductivity, and the second region 222 has a base milk of the -connecting (quad) structure 21, and a heavily doped portion formed on the base 225, eg, And a contact area formed on the re-pushing portion 226 and connected to the source region and spaced apart from the first region 221. The contact region 224 is formed of a semiconductor material having a second electrical property, the second electrical carrier concentration of the contact region 224 being greater than the second electrical carrier concentration of the heavy swap portion 226, and "(4) The first-electrode carrier concentration of the crucible 226 is greater than the second electrical carrier concentration of the base 225, and the contact region 224 and the source region 223 are both connected to the re-doped portion 226 and to the base portion 225. The source structure 24 is connected to the source region and is similar to the contact region, and is formed of an electrically conductive material such as a crane (commonly referred to as "contact plug," in the industry) and can be electrically connected to the outside. . The gate structure 23 includes a dielectric layer 231 formed on the top surface of the path structure 22 to be defined by the first region 221, and a conductive layer 232 formed on the electrical layer 231, and is formed on the buckle The insulating wall 233 of the side peripheral surface. The dielectric layer 231 and the insulating wall may be formed by a combination of materials such as sulphur dioxide, sinter, or the like. The conductive layer 232 is formed of a conductive material such as polycrystalline slab, and the conductive layer 232 is wrong. The insulating wall 233 is spaced apart from the source structure 24 and is electrically disconnected. : when the conductive layer 232 coated with the interpole structure 23 is applied to the source-structure 24' and the non-polar structure 21 corresponds to the source structure "when the charge passes through the first region 22i and the second of the path structure 22 of 201230333 The super interface formed by the base 225 of the region 222 is electrically conductive; in addition, the charge can be separated by the depletion region of the super interface formed between the first region 221 and the base 225, and between the first region 221 and the non-polar structure 21 The formed depletion region acts as a buffer for the electron flow, so that the power transistor 2 having the low interface of the low Miller capacitance can operate normally when a high voltage is applied. The power of the super interface of the low Miller electricity valley is described. The method for fabricating the crystal 2 can be more clearly understood after the following description of the first preferred embodiment of the present invention. Referring to Figures 3, 4, and 5, the steps are first performed to be sequentially used in a sequential manner. The first and second electrically conductive semiconductor materials are formed to be predetermined as the electrodeless structure, 25, and a second layer body 26'' coupled to the first layer body 25 is further disposed on the top surface of the second layer body 26 Ion implantation is implanted with a second electrical carrier, and The second layer body 26 is divided into a pure epitaxial layer 262 and a well layer 261. Referring to FIG. 3 and circle 6, the step 32 is continued, and the top surface of the second layer body % 261 is sequentially formed. a dielectric layer 231 of a self-insulating material, a conductive layer 232 formed of a conductive material, and a hard mask layer 23, and then a portion of the dielectric layer 231 is formed by a process such as lithography and the like, and The conductive layer 232 and the hard mask layer W corresponding to the portion of the dielectric layer 231 are removed, and the top surface of the second layer body 26 is exposed, and the conductive layer 232 is further disposed on the second layer body 26. The side peripheral surface is formed - the insulating wall is added (as shown in FIG. 7). In the preferred embodiment, the conductive layer is selected from the group consisting of polycrystalline stone, and the dielectric layer 231 and the insulating wall 233 are selected from the group consisting of Semenium dioxide, nitrite, and £10 201230333 The combination is made of materials. Referring to FIG. 3 and FIG. 7, then, step 33 is performed to sequentially form the exposed top surface of the second layer body 26 sequentially by using the lithography and the button engraving process--the fruit to the pure insect layer 262. The trench 27, and the connection hole 28 spaced apart from the trench 27 and having a depth to the well layer 261. Since the conductive layer and the top surface are connected to the hard mask layer 234, if the trench 27 and the connection hole μ are formed, the exposure machine is offset during alignment, and the dielectric layer 231 and the electricity are generated. The layer also has the protection of the insulating wall 233 and the hard mask layer 234, and can be prevented from being damaged when the (4) trench 27 and the domain connection hole 28; that is, the hard mask layer 234 is in the above-mentioned lithography and engraving process. The self-alignment can be provided to protect the integrity of the conductive layer 232 and the dielectric layer η, and to improve the positional accuracy of forming the trench 27 and the connection hole 28. Referring to FIG. 3 and FIG. 8. Continue, proceeding to step 34, filling the trench 27 and the connection hole 28 with a semiconductor material 291 having a first electrical property, in the first implementation, filling the trench 27 and the connection The semiconductor material 291 of the hole 28 is selected from the group consisting of ph〇sph〇siHcate (BPSG), cullet fused glass, and the like, and the combination thereof is made of a material. The material having the first electric property in the material π and the material contact hole 扩散 diffuses into the second (four) %, thereby causing a portion of the second layer body 26 adjacent to the trench 27 to be transformed from the original second electrical property to a first electrical first region 221 opposite to the second electrical property, and adjacent to the connecting hole 28 A portion of the second layer body 26 is transformed into a first electrical source region 223 opposite to the second electrical region 201230333, and the first electrical semiconductor material in the trench 27 and the connection hole 28 is removed. The range of the first region 22 丨 and the source region 223 is not fixed. The remaining pure epitaxial layer 262 of the second layer 26 not forming the first region 221 and the source region 223 is defined as a base portion. 225. The well layer 261 of the first layer body 26 is defined as a heavily doped portion 226. The first region 221 and the second portion 222 form a lattice perfect and continuous super interface 0. It should be noted that, in the trench 27 The semiconductor material 291 having the first electrical property is sequentially filled, and the carrier concentration of the first filled semiconductor material is greater than the carrier concentration of the subsequently filled semiconductor material 291, so that the source region 223 can be more accurately regulated. And the distance between the heavily doped portions of the first region 221, that is, the first preferred embodiment The length of the channel of the power transistor 2 having the low interface of the low Miller capacitance, and avoiding the contact of the first region 221 with the source region 223. The portion 1 is independent of the trench wood = the material and the material Performing the reduction to diffuse the carrier, and then (4) the sub-cloth (4) = corresponding to the top of the second layer body 26 of the connection hole 28 to form the source phase filling m, FIG. 9 'final' proceeds to step 35, where the chamber is 27 The substance 292' causes the trench 27 to no longer contain electricity in the manner of ion implantation in the bottom corresponding to the connection hole _ 2, 2 to 1 is higher than the concentration of the carrier of the heavily doped portion 226 The region 224 is connected to the source region 223 ((4) metal) is filled in the connection hole 28 to make _«_24 S. 201230333, and the low-Miller capacitor is used to make the source structure 24 electrically connect to the super interface. Power transistor 2. The area of the first region 221 of the power interface having the low interface of the super-male capacitor prepared by the preferred embodiment of the carrier concentration of the heavily doped portion 226 is overlapped with the dielectric layer. The function % of the transistor is small, which in turn reduces the capacitance between the pole and the pole, which in turn significantly reduces the Miller capacitance at the source output.
另外，本發明是用填覆具有第一電性的半導體材料於 該溝渠27中，再利㈣處理製程使具有第—電性的載子擴 散進入該第二層體26中而形成第一 1 221及第二區切， 因此：除了製程成本、技術難度較低之外，第—區如及 第二區222構成的超級介面因為沒有經過敍刻破壞而是晶 格連續的完整連續面，所以電荷是不會被侷限地自該^ 結構21通過該第一、二區221、222形成的晶格連續面時 ’實質是通過晶格完整無缺陷且不存在多餘應力的區域， 而可供電荷作為理想的緩衝區域，因此，本發明具有低米 勒電容之超級介面的功率電晶體2的作動穩定度較佳並 具有杈快的開啟/關閉反應速度與較大之崩潰電壓，另外， 未施加電壓時，也不會有漏電流的狀況產生。 除此之外，本發明在蝕刻成型該溝渠27時並不需特別 控制精確程度，也不需刻意降低對該第二層體26晶格破壞 的程度’僅需形成所需結構態樣的溝渠27即可，如此，還 可以大幅減少控制蝕刻精準程度的設備及人力資源。 參閱圖11，本發明具有低米勒電容之超級介面的功率 13 201230333 電晶體2的製作方、、土 & '、一第二較佳實施例是與上例相似， 其不同處在於該步驟34中潜泪 中溝木27蝕刻得更深，使熱處理 後該第一區221接觸該沒極έ 程的氣氛、溫度，及蜮時門：或耩由控制熱擴散製 〇〇1 ^ 成寺間，而使路徑結構22的該第一區 八” Ί極’·、°構21連結，而使得具有低米勒電容之超級 ^面的功率電晶體2施加電I成電導通時，可自該沒極結 H面即開始緩衝漂移的電荷，進而增加該具有低米勒 今之超Ί1面的功率電晶體2的耐高電>1的程度。 —综上所述，本發明是提出—種新的、利用填覆具有預 電I·生特徵的半導體材料，並配合以熱處理的方式將載子 擴散而形成超級介面，從而製作具有低米勒電容之超級介 面的功率電晶體2的方法，如此製作出的具有低米勒電容 旦，超級”面的功率電晶體2的超級介面因未受蝕刻破壞、 影響’而可.更穩^、快速的作動，且具有更快的開啟/關閉 反應速度，另外，未施加電屡時，也不會有漏電流的狀況 產生’確貫達成本發明之目的。 准以上所述者，僅為本發明之較佳實施例而已，當不 .b 乂此限疋本發明貫施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一剖視示意圖，說明習知一功率電晶體； 圖2是一剖視示意圖’說明本發明一第一較佳實施例 所製作出的具有低米勒電容之超級介面的功率電晶體； 5 14 201230333 圖 圖 3是一流程圖 °兒明s亥第一較佳實施例； 二層體 圖 井層； 4是一剖視示意圖 I 5是一剖視示意圖 說明於一第一層體上形成一第 說明於該第二層體頂部形成_ 圖6是一剖視示意圖，說明於該第二層體頂面形成— 介電層、-導電層，及-石更遮幕層； 圖7是一剖視示意圖，Μ nn &In addition, in the present invention, the semiconductor material having the first electrical property is filled in the trench 27, and the carrier having the first electrical property is diffused into the second layer body 26 to form the first one. 221 and the second zone cut, therefore: in addition to the process cost and technical difficulty, the super interface formed by the first zone and the second zone 222 is a continuous continuous surface of the lattice because it has not undergone the destruction. The charge is not limited to the continuous surface of the lattice formed by the first structure and the second region 221, 222. The material is substantially free from defects in the crystal lattice and has no excess stress. As an ideal buffer region, therefore, the power transistor 2 having the low interface of the low Miller capacitance has better operation stability and has a fast on/off reaction speed and a large breakdown voltage, and is not applied. When the voltage is applied, there is no leakage current. In addition, the present invention does not require special control accuracy when etching the trench 27, nor does it need to deliberately reduce the degree of lattice damage to the second layer body 26 'only need to form a trench of the desired structural aspect. 27, so, can also greatly reduce the equipment and human resources to control the precision of etching. Referring to FIG. 11, the power of the super interface with low Miller capacitance of the present invention 13 201230333 transistor 2, the earth & ', a second preferred embodiment is similar to the above example, the difference lies in this step In the middle of the 34th, the ditch wood 27 is etched deeper, so that the first zone 221 contacts the atmosphere and temperature of the infinite process after the heat treatment, and the time gate is: or the 热 is controlled by thermal diffusion. And the first region of the path structure 22 is connected with the "b" poles and the structure 21, so that when the power transistor 2 having the low-Miller capacitance is electrically connected to the power transistor 2, it can be self-contained. The H-plane of the pole junction begins to buffer the drifting charge, thereby increasing the degree of high electric resistance >1 of the power transistor 2 having a low surface of the low-meter. Now, the present invention proposes A new method for fabricating a power transistor 2 having a low interface of a low Miller capacitance by filling a semiconductor material having a pre-charged I·sheng feature and mixing the carrier by heat treatment to form a super interface So produced with a low Miller capacitance, super "The super interface of the power transistor 2 is not affected by the etch and damage, but it can be more stable and fast, and has a faster on/off reaction speed. In addition, no power is applied and it is not applied. A situation in which a current leaks occurs will result in the achievement of the present invention. The above is only the preferred embodiment of the present invention, and is not limited to the scope of the present invention, that is, the simple equivalent of the scope of the invention and the description of the invention. Variations and modifications are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a conventional power transistor; FIG. 2 is a cross-sectional view showing a low Miller capacitance produced by a first preferred embodiment of the present invention. Super interface power transistor; 5 14 201230333 Figure 3 is a flow chart ° 儿明 shai first preferred embodiment; two-layer body map well layer; 4 is a cross-sectional view I 5 is a schematic cross-sectional view Forming a first layer on the top of the second layer. FIG. 6 is a cross-sectional view showing the formation of a dielectric layer, a conductive layer, and a stone on the top surface of the second layer. More shielding layer; Figure 7 is a schematic cross-sectional view, Μ nn &
圑垅明於該第二層體形成一連接 孔及一溝渠； 疋俠 ，說明先於該溝渠填覆一半導體 而形成一第一區，再移除該半導 圖8是一剖視示意圖 材料，再經由熱處理製輕 體材料；圑垅 于 于 该 该 该 该 该 于 该 该 该 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于And then heat-treating the light material;
9是一剖視示意圖， 說明於該溝渠填覆一電中性物9 is a schematic cross-sectional view illustrating the filling of an electrical neutral in the ditch
圖10是一剖視示意圖，說明本發明—第二較佳實施例 所製得的具有低米勒電容之超級介面的功率電晶體；及 圖U是一剖視示意圖，說明該第二較佳實施例的第一 區與該沒極結構接觸。 15 201230333 【主要元件符號說明】 1…… …·功率電晶體 225… •…基部 11…… …及極結構 226… •…重摻雜部 12.… 日日結構 23··· …·閘極結構 121… •…第一區 231… …·介電層 122… •…第二區 232… •…導電層 123… .…源極£ 233… •…絕緣壁 124… 接觸£ 234… •…硬遮幕層 125… •…基部 24•…. …源極結構 126… •…重摻雜部 25 ·.··· •…第一層體 13…… 閘極結構 26…… •…第二層體 131… …·介電層 261… •…井層 132… …·導電層 262… ο η..... —純蠢晶層 1 4 ...... …-妳徑結稱 …溝ίκ 2 ....... •…具有低米勒電容 28 •…連接孔 之超級介面的功率電晶體 291… •…半導體材料 21…… …汲極結構 292… •…電中性物質 22…… •…路徑結構 31 •，… …·步驟 221 · ，…第一區 32…… …·步驟 222 ··· •…第二區 33…… …·步驟 223 ·· …源極£ 34.… •…步驟 224 ··· ••接觸£ 35·.·，. •…步驟Figure 10 is a cross-sectional view showing a power transistor having a low interface of a low-Miller capacitor obtained by the second preferred embodiment; and Figure U is a cross-sectional view showing the second preferred The first zone of the embodiment is in contact with the electrodeless structure. 15 201230333 [Explanation of main component symbols] 1...... ...·Power transistor 225... •...base 11...and pole structure 226...•...heavily doped part 12....day structure 23·····gate Structure 121... •...first zone 231...·dielectric layer 122...•...second zone 232...•...conductive layer 123.....source £ 233... •...insulated wall 124...contact £ 234... •...hard Curtain layer 125... •...base 24•....source structure 126...•...heavy doped portion 25·····•...first layer body 13... gate structure 26... •... second layer Body 131...·Dielectric layer 261...•...well layer 132...··conductive layer 262... ο η..... — pure stupid layer 1 4 ...... ...- 妳 结 ... ... 沟Ίκ 2 ....... •...Power transistor 291 with low Miller capacitance 28 •...Super interface of the connection hole...•...Semiconductor material 21......汲 structure 292... •...Electrically neutral substance 22 ...... •...Path structure 31 •,...Steps 221 · ,...First zone 32...Steps 222 ··· •...Second zone 33...Steps 2 23 ·· ...source £ 34.... •...step 224 ··· ••Contact £ 35·.·,.