201239960 六、發明說明： 【發明所屬之技術領域】 本發明係關於-種形成金屬閘極之方法。本發明特別是 關於-種使用選擇性㈣，在實質上不影響經摻雜之替代材 料之情況下，移除未經摻雜之替代材料， 之方法 題 了避免凹穴在㈣時’橫向侵料成底切之問 【先前技術】 在半導體元件”作過財，常 義所需7C件的位置。例如，在製造㈣ ^刻方法來定 (SRAM)的過程中， 〜思機存取記憶體 -般來說，如果要形成金輪：皮::接的結構。 敍刻步驟來分収義出第-金屬與第二^會先後使用兩次 置。 主屬閘極結構的位 在第—次的蝕刻過程中， 罩來保護不需錢刻的區域，來限制2刻步驟，會使用遮 際上，儘管有著遮罩的保護，敍刻劑除;：的作用範圍。實 料之外，也會無可避免地橫向侵制 4下移除標的材 罩邊緣的標的材料。此等橫向侵^結果#，特別是移除遮 ° ，在蝕刻步驟完成 201239960 會扭曲所欲形成凹 的性能。 美凹穴 【發明内容】 本發明於是提_決㈣ 過程中又實質上不影響週遭的材料。所以本：=料的 來形成實質上I底切之μ a w㈣方法可以用 用之凹穴。 以凹穴，特別是用來形成金屬閉極 :發:於是提出一種形成金屬閘極之方法。首 基材上整體地沉積一替代(―)材料: 域接選擇性地在替代材料中植入-捧質，而形成-摻質區 :。=，移除部份的替代材料，而暴露出部分的基材並形 二=極。替代閉極中包含介於第-區域與第二區域間 厚^ 再來，於暴露之基材上形成圍繞替代閘極之- 電層。繼續，進行—選擇性蝴步驟，而移除替代閘 筮一口第ϋ域’以形成第一凹穴。蝕刻步驟實質上不移除 -區域與摻質區域，使得第一凹穴不延伸至摻質區域。然 201239960 後，使用第/材料組填入第一凹穴中，以形成第一金屬閘極。 在本發明一實施例中’摻質可以為三族（ΠΙ)元素或是 碳。在本發明另一實施例中’可以使用遮罩來覆蓋替代材料 之第二區威，以便進行選擇性蝕刻步驟。在本發明又一實施 例中，在完成第一金屬閘極後又繼續移除替代閘極中之第二 區域與摻質麁域，以形成一第二凹穴，更使用第二材料組填 入第二凹六中’以便形成與第一金屬閘極鄰接之第二金屬閘 極。在本發明再一實施例中，可以同時或是前後移除替代閘 極中之第>哆域與摻質區域。在本發明又另一實施例中，第 一金屬閘極 < 以為PM〇S與NMOS其中之一者，而第二金 屬閘極為另外一者。第一金屬閘極與第二金屬閘極可以位於 一靜態隨機存取記憶體中（SRAM)。 本發明使用選擇性蝕刻，在實質上不影響經摻雜之替代 材料之情况卞，移除未經摻雜之替代材料，而形成實質上無 底切之凹六。然後，實質上無底切之凹穴即適合建構成良好 之金屬閘極。使用本發明方法可以避免凹穴在触刻時附帶的 橫向侵蚀’ 造成遮罩邊緣的下方底切之問題。 【實施方式】 請參考第MG圖，例示本發卿成金相極方法之例 示性步驟。首先請參考第丨圖，提供—基材101。基材101 201239960 通常是一種半導體材料，例如矽晶圓或絕緣層上覆矽 (Silicon-On Insulator，SOI)等。其次，在基材101上整體地依 序形成一介電層以及一替代（dummy )材料110。介電層包 含一般介電常數介電層102及/或高介電常數介電層103,而 替代材料110目前用來暫時替代將來金屬閘極（圖未示）的 位置，所以屬於一種犧牲性（sacrificial)材料，例如可以為 未經摻雜的矽。可以使用習知之沉積方法，來全面性地 (blanket)形成具有適當厚度之替代材料110。此外，基材 101中可形成有所需之摻雜井、淺溝渠隔離（STI) 104等之 結構，在此不多加贅述。在替代材料110與高介電常數介電 層103之間尚可形成一層視情況需要之阻障/蝕刻停止層。此 層的材料可為TiN、SiN...等等。此層可以增加替代材料110 與高介電常數介電層103材料之間的匹配性及/或在後續步 驟中移除替代材料110時作為蝕刻停止層之用。 之後，請參考第2圖，選擇性地在替代材料110中植入 一適當之摻質121，例如硼、鋁等三族（III)元素或是碳， 而形成一摻質區域120。摻質區域120的位置較佳會預先經 過規劃，而位於將來電性不同又鄰接之金屬閘極，例如PMOS 與NMOS (圖未示）之邊界區域上。例如，在植入前可以先 使用一光阻等之遮罩131保護其他區域，而後在暴露出之區 域中植入所需要之摻質121。隨後，再移除遮罩131。 201239960 接著，請參考第3圖，移除部份的替代材料11〇，而暴 露出部分的基材101，使得替代材料11〇成為島狀之替代閘 極no。替代閘極110包含第一區域ln、第二區域112與 位於第一區域U1與第二區域112間之摻質區域。第一 區域111與第二區域112則用以形成預定之PM0S與 NMOS。淺溝渠隔離辦即為第一區域lu與第二區域ιΐ2 部份的隔離結構。摻質區域12〇會位於絕緣的隔離結構，如 淺溝渠隔離1G4上。例如，可以使用另—遮罩132保護替代 閘極no，而經由蝕刻步驟移除替代材料11〇多餘的部份。 餘刻完成時，遮罩132可以暫時先保留住。遮罩132可以包 含一金屬材料或介電材料’例如氮紐、氮切或碳化石夕等。 再來，請參考第4圖’在完成替代閘極11G後，可以視 晴况需要進行所需之源極/汲極換雜步驟，於是在替代問極 110兩旁暴露出之基材101中形成所需之源極/祕140。較 =為，在替代閘極11〇之第一區域⑴與第二區域⑴兩 it!出之基材1〇1中分別形成一組不同導電型的源極/沒 ， 此時’遮罩132即會在源極/汲極摻雜步驟中保護替 代閘極110，而不參盥摻雜步 , y、° 雜/驟。此外，視產品規格與製程 =ίΓ例另可形成有所需之側壁子結構、淺摻雜區、 自對準金屬魏物及/或嵌人式蟲晶層（職sed咖lal201239960 VI. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of forming a metal gate. In particular, the present invention relates to the use of selectivity (IV) to remove undoped replacement materials without substantially affecting the doped replacement material, the method of which avoids the lateral intrusion of the pockets at (iv) The material is cut into the undercut [Prior Art] In the semiconductor component, the position of the 7C piece is required for the common sense. For example, in the process of manufacturing (4) engraving method (SRAM), - Generally speaking, if you want to form a gold wheel: the skin:: the structure of the connection. The step of the engraving to divide the meaning of the -metal and the second ^ will be used twice. The position of the main gate structure is in the first time During the etching process, the cover protects the area that does not need to be engraved, to limit the 2 steps, and the use of the mask, even with the protection of the mask, the scope of the engraving agent:: Inevitably laterally invade the target material at the edge of the target material cover. This lateral intrusion result #, especially the removal of the mask, and the completion of the etching step 201239960 will distort the desired concave properties. Pocket [invention] The present invention then proposes In fact, it does not substantially affect the surrounding materials. Therefore, the material is used to form a pit that is substantially i-cut by the μ a w (four) method. The recess is used to form a metal closed pole: A method of forming a metal gate is proposed. A substitute (-) material is integrally deposited on the first substrate: the domain is selectively implanted in the substitute material, and the - dopant region is formed: Except for some of the alternative materials, a portion of the substrate is exposed and shaped as a second electrode. The alternative closed electrode includes a thickness between the first region and the second region, and then forms a surrounding gate on the exposed substrate. Pole - the electrical layer. Continuing, performing a selective butterfly step, and removing the replacement gate a second region 'to form a first recess. The etching step does not substantially remove the - region and the dopant region, such that the first The recess does not extend to the dopant region. After 201239960, the first material is filled into the first recess using the /material group to form the first metal gate. In an embodiment of the invention, the dopant may be a tri-family (ΠΙ) Element or carbon. In another embodiment of the invention 'can be covered with a mask Forming a second region of the material to perform a selective etching step. In still another embodiment of the present invention, after the first metal gate is completed, the second region of the replacement gate and the dopant region are further removed. To form a second recess, and further use the second material group to fill the second recess 6 to form a second metal gate adjacent to the first metal gate. In still another embodiment of the present invention, In the other embodiment of the present invention, the first metal gate <is one of PM 〇S and NMOS, and the second The metal gate is one of the other. The first metal gate and the second metal gate can be located in a static random access memory (SRAM). The invention uses selective etching without substantially affecting the doped alternative material. In the event that the undoped replacement material is removed, a substantially void-free recess is formed. Then, a recess having substantially no undercut is suitable for constructing a good metal gate. The use of the method of the present invention avoids the problem of the undercut of the edge of the mask caused by the lateral erosion accompanying the pocket during engraving. [Embodiment] Please refer to the MG diagram to illustrate an exemplary procedure of the method of the invention. First, please refer to the figure, which provides a substrate 101. Substrate 101 201239960 is typically a semiconductor material such as a germanium wafer or a Silicon-On Insulator (SOI). Next, a dielectric layer and a dummy material 110 are integrally formed on the substrate 101 in this order. The dielectric layer comprises a general dielectric constant dielectric layer 102 and/or a high-k dielectric layer 103, and the replacement material 110 is currently used to temporarily replace the position of a future metal gate (not shown), so it is a sacrifice. (sacrificial) material, for example, may be undoped germanium. The alternative material 110 having a suitable thickness can be blanketed using conventional deposition methods. In addition, the structure of the desired doping well, shallow trench isolation (STI) 104, etc. may be formed in the substrate 101, and will not be further described herein. A barrier/etch stop layer as desired may also be formed between the replacement material 110 and the high-k dielectric layer 103. The material of this layer may be TiN, SiN, etc. This layer can be used as an etch stop layer to increase the matching between the alternative material 110 and the high-k dielectric layer 103 material and/or to remove the replacement material 110 in subsequent steps. Thereafter, referring to Fig. 2, a suitable dopant 121, such as a group III (III) element such as boron or aluminum, or carbon is selectively implanted in the substitute material 110 to form a dopant region 120. The location of the dopant region 120 is preferably planned in advance, and is located on a boundary region of a metal gate that is different in incoming and adjacent, such as a PMOS and an NMOS (not shown). For example, a mask 131 such as a photoresist may be used to protect other regions prior to implantation, and then the desired dopant 121 may be implanted in the exposed region. Subsequently, the mask 131 is removed. 201239960 Next, referring to Fig. 3, a part of the substitute material 11〇 is removed, and a part of the substrate 101 is exposed, so that the substitute material 11〇 becomes an island-shaped substitute gate no. The replacement gate 110 includes a first region ln, a second region 112, and a dopant region between the first region U1 and the second region 112. The first region 111 and the second region 112 are used to form a predetermined PMOS and NMOS. The shallow trench isolation is the isolation structure between the first region lu and the second region ιΐ2. The dopant region 12〇 will be located in an isolated isolation structure, such as a shallow trench isolation 1G4. For example, an alternative mask 132 can be used to protect the replacement gate no, while the excess portion of the replacement material 11 is removed via an etching step. When the moment is completed, the mask 132 can be temporarily retained. The mask 132 may comprise a metallic material or a dielectric material such as nitrogen, nitrogen or carbon stone. Then, please refer to Figure 4, after completing the replacement gate 11G, the required source/drain replacement step can be performed according to the sunny condition, so that it is formed in the substrate 101 exposed on both sides of the replacement electrode 110. The source/secret 140 required. Comparing =, in the first region (1) and the second region (1) of the replacement gate 11〇, a source of different conductivity types is formed in the substrate 1〇1, and the mask is 132. That is, the replacement gate 110 is protected in the source/drain doping step, without the doping step, y, ° miscellaneous/excited. In addition, depending on the product specifications and process = otherwise, the required sidewall substructure, shallow doped region, self-aligned metal material and/or embedded human crystal layer may be formed.
Wer)等之結構，在此亦不多加贅述。 8 201239960 請參考第5圖，然後，初步形成層間介電層⑼覆 露之基材101，並同時圍繞替代問極u '、 層15。並不會覆蓋替代開極110。例如，可二^ 電層150來完全覆蓋暴露之基物、遮罩m與 然後，再進行-平坦化製程，移除部份之層 =，使得遮罩132暴露出來。所以，層間介電層15〇_ 罩132大約具有相同之高度。或是，移除部份之層間介電； 150時一併移除遮罩132,所以層間介電層15〇與替代= no大約具有相同之高度，如第6圖所示。’代間極 =續’請參考第6圖，進行—選擇性_步驟，而移除 替代間極no中之第一區域U1，以形成第一凹穴⑴。例 如，可以先使用一蝕刻遮㈣完全覆蓋第二區域⑴ 至部份之摻質區域12G，但是完全暴露出第—區域⑴ 擇性敍刻步驟對未經摻雜處理之區域，即第—區域⑴ 相對較高祕刻率，所以實質上不會移除受到_遮罩⑶ 保濩的第二區域112與蝕刻率相對較低的摻質區域心因 此’第-凹穴113不會延伸至摻質區域12()，因此沒有橫向 蝕刻（lateral etching)而於敍刻遮罩133下方產生底切的缺 點此處所&之「實質上不會移除」#刻率相對較低的推質 區域120係意味著’在此選擇性触刻步驟下，第一區域⑴ 與掺質區域⑽祕刻率比會大於至少％。此等㈣率比會 根據蝕刻劑的不同、蝕刻溫度的不同而有所改變。 201239960 在本實施例中’可以使用祕财式，例如使用驗㈣ 刻劑，來執行選擇性移除替代閘極110中之楚一 〜弟一區域111之 蝕刻步驟。適合之蝕刻劑可以是稀釋氫氟酸（DHF)搭配氨 水、或疋鼠乳化四甲基叙溶液（tetramethylammonium hydroxide，TMAH)。例如，先使用稀釋氫氟酸（DHF)，在 室溫下進行預蝕刻。之後，再使用鹼性蝕刻劑，選擇性完全 移除第一區域111，以形成第一凹穴113。蝕刻完成後，即 可移除蝕刻遮罩133。或者是，可以使用乾蝕刻與濕蝕刻混 合的方式，例如先使用乾蝕刻、再進行濕蝕刻來執行選擇性 移除替代閘極110中之第—區域lu之蝕刻步驟。 然後，請參考第7圖，使用第一材料組161填入第一凹 穴113中，以形成第一金屬閘極16〇。若有多餘之第一材料 組161會覆蓋層間介電層15〇日寺，還可以進行一平坦化製程 來移除多餘之第-材料組161而暴露出層間介電層15〇。第 材料組161可以包含功函數閘極金屬層ι63與低電阻金屬 164。功函數閘極金屬層163可以為單—金屬層或是複合金 屬層。經由第一材料組161中功函數閘極金屬M3之適當組 口 ’即可調整第-金屬間極⑽具有適當之功函數。適當之 局介電常數介電層1〇3與功函數閘極金屬材料⑹為本技藝 人士所知。 201239960 在另-個實施财，請參考第7A圖，其例示一剖視圖。 在移除替代閘極則中之第一區域1U之後與使用第一材料 .，且161填入第一凹六113之前，可以先形成口形之高介電常 數介電層103。賴才形成韻數騎金屬層⑹與低電阻 金屬164。在此情況下，原本形成在#代材料下方的高介電 常數介電層便不用形成。 …接下來，請參考例示另—方向側視圖之第8圖，再一次 進行敍刻步驟，而移除替代閘極110中之第二區域112與摻 質區域120,以形成第二凹穴出。可以使編刻與心 刻混合的方式’或者是直接❹祕財式，例如使用驗性 姓刻劑，在沒有遮罩之情形下來移除替代閘極UG中之第二 ^域^與摻質區域12〇。適合之_劑可以是較高溫度; 相對於第—區域⑴之選擇性_)之氫氧化四 :土叙减（tetramethylamnlonium hydroxide，TMAH)，或 是其他氫氧化四烷基銨溶液。 」然後’請參考第9圖’再使用第二材料組16 6填入第二 凹穴115中，以形成第二金屬閘極165。若有 ^组⑽會覆蓋層間介電層⑼時，也可以進行二平坦㈣ 私來移除夕餘之第二材料組166而暴露出層間介電層150。 I:枓組166可以包含功函數閘極金屬層167與低電阻金 屬。功函數閘極金屬層16?可以為單一金屬層或是複合 11 201239960 金屬層。經由第二材料組166中功函數閘極金屬167之適當 組合，即可調整第二材料組166具有適當之功函數。 如果第一金屬閘極160為PMOS與NMOS其中之一者， 而第二金屬閘極165即為另外一者，相對應地，第一金屬閘 極160與第二金屬閘極165兩旁的源極/汲極140則分別具有 相對應的P型或N型導電性。於是第一金屬閘極16〇與第二 金屬閘極165即可以為靜態隨機存取記憶體中（sram)鄰 接之閘極’且第一金屬閘極160與第二金屬閘極165係直接 接觸並以功函數閘極金屬彼此電連接。適當之高介電常數介 電層103與功函數閘極金屬材料163/167為本技藝人士所 知，例如高介電常數介電層103是選自矽酸铪氧化合物 (HfSiO)、碎酸铪氮氧化合物(HfSiON)、氧化給(HfO)、氧化 鑭(LaO)、鋁酸鑭(LaAlO)、氧化锆(ZrO)、矽酸鍅氧化合物 (ZrSiO)、結酸給(HfZrO)或其組合，N型功函數閘極金屬材 料較佳選自氮化鈦(TiN)、碳化钽(TaC)、氮化鈕(TaN)、氮化 矽鈕(TaSiN)及鋁等所構成的群組，p型功函數閘極金屬材料 較佳選自由氣化鈦(TiN)、鎢(W)、氮化鎢（WN)、舶（Pt)、鎳 (Ni)、釕(Ru)、碳氮化钽(TaCN)或碳氮氧化鈕(TaCNO)所構成 的群組。 當第一金屬閘極160與第二金屬閘極165皆已完成後， 就可以繼續形成用於電連接第一金屬閘極16〇與第二金屬閘 12 201239960 極165之源極/汲極14〇之接觸插塞π〇。例如，請參考第1〇 圖’先形成層間介電層150完全覆蓋第一金屬閘極 160與第 二金屬閘極165’接下來形成暴露源極/汲極14〇之接觸洞（圖 未示）。然後，在接觸洞填入適當之導電材料，完成接觸插 塞170。視情況需要，接觸插塞17〇與源極/汲極14〇之間還 可以預先形成金屬矽化物（圖未示）。 請參考第11-17圖，例示本發明形成金屬閘極方法之另 一種例示性步驟，其特點在於使用光阻界定硬遮罩之圖案與 使用一低電阻金屬同時填滿原先替代材料所佔據之區域，以 形成第一金屬閘極與第二金屬閘極。首先請同時參考第u 圖與第12圖，第11圖中之切線A_A，展開後即呈現第12圖 之剖視圖。提供一基材1〇1。基材1〇1通常是一種半導體材 料’例如矽晶圓或絕緣層上覆矽（Silic〇n_〇nInsulat〇r，s〇i) 等。基材101被層間介電層150所覆蓋。基材1〇1中包含源 極/汲極140與淺溝渠隔離104。基材1〇1上已經形成有相鄰' 之替代材料110，基材101上另外還有主動區域1〇5。替代 材料110與主動區域1〇5交會之處，即為日後金氧半導體閘 極所在之處。 替代閘極1110中包含替代材料110、包含氮化矽之密封 層116、側壁子117、蝕刻停止層118與視情況需要之一般 介電常數介電層102或是高介電常數介電層1〇3。替代閘1 13 201239960 2110中亦包含有替代材料、包含氮化矽之密封層、側壁子、 蝕刻停止層與視情況需要之介電層，但因簡化之故而未繪 出。側壁子117可以為單一或是複合結構。 基材101已經預先進行過化學機械研磨，使得替代閘極 1110/2110與層間介電層150之頂面同平面，同時替代閘極 1110/2110部分的頂面還會暴露出來。替代材料110目前用 來暫時替代將來金屬閘極（圖未示）的位置，所以屬於一種 犧牲性（sacrificial)材料，例如可以為未經摻雜的石夕。基材 101中另外還可形成有所需之摻雜井等之結構，在此不多加 贅述。 在替代材料110與高介電常數介電層103之間尚可形成 一層視情況需要之阻障/触刻停止層。此層的材料可為TiN、 SiN...等等。此層可以增加替代材料110與高介電常數介電 層103材料之間的匹配性及/或在後續步驟中移除替代材料 110時作為蝕刻停止層之用。替代閘極1110可以為NMOS 或PMOS其中一者，而替代閘極2110即為另一者。 第12A圖繪示第11圖中之切線B-B’之剖視圖。請參考 第12A圖，選擇性地在替代材料110中植入一適當之摻質 121，例如硼、鋁等三族（III)元素或是碳，而形成一摻質 區域120。摻質區域120的位置較佳會預先經過規劃，而位 14 201239960 於將來電性不同又鄰接之金屬閘極’例如PM〇s與nm〇s (圖未示）之邊界區域上’例如位於淺溝渠隔離刚之上。 例如，在植入前可以先使用一光阻等之遮罩（圖未示）保護 其他區域’而後在暴露出之區域中植入所需要之摻質⑵。 隨後’再移除遮罩。 之後’請參考第13圖，先在層間介電層⑼上全面性 地沉積遮罩m，例如氮化鈦硬遮罩，再全面性地沉積氧化 物134 ’例如二氧化石夕。還要使用圖案化之光阻…來選擇 性地覆蓋替代閘極ni〇/211()(NM〇MpM〇s)其中一者。 第13圖綠示圖案化之光阻135覆蓋替代閘極2110。接下來 就可以使用圖案化之光阻135來圖案化遮罩i3i，例如❹ 钮刻步驟’將級135之圖案轉移至遮罩i3i上，隨後即可 移除光阻135。 接著，請參考第14圖，經由遮罩ΐ3ι之保護，以鞋刻 ^驟移除暴露之替代閘極⑴〇或211〇其中一者之替代材料 由於遮罩131的保護，祇有替代閘極111G與2110其 中一者之替代材料11〇才會被移除。帛14圖例示祇有替代 =極1110中之替代材料110被移除而形成第-凹穴113,而 替代閘極2UG中之替代材料11G被保留。 第MA圖繪示第11圖中之切線B-B，之剖視圖。由於遮 15 201239960 罩131與摻質區域120之保護，所以此次之蝕刻步驟實質上 不會移除受到蝕刻遮罩131與摻質區域12〇保護的替代閘極 2110與钱刻率相對較低的摻質區域12〇。因此，第一凹穴n3 不會延伸至摻質區域120，因此沒有橫向蝕刻（lateral etching) 而於蝕刻遮罩131下方產生底切的缺點。 此處所指之「實質上不會移除」蝕刻率相對較低的摻質 區域120係意味著，在此選擇性蝕刻步驟下，第一區域1U 與摻質區域120的蝕刻率比會大於至少5〇。此等蝕刻率比會 根據蝕刻劑的不同、蝕刻溫度的不同而有所改變。 在本實施例中，可以使用濕蝕刻方式，例如使用鹼性蝕 刻劑’來執行選擇性移除替代閘極111〇之蝕刻步驟。適合 之钱刻劑可以是稀釋氫氟酸（DHF)搭配氨水、或是氫氧化 四甲基録溶液（tetramethylammonium hydroxide，TMAH) 〇 例如，先使用稀釋氫氟酸（DHF)，在室溫下進行預餘刻。 之後’再使用鹼性蝕刻劑’選擇性完全移除替代閘極m〇， 以形成第一凹穴113。或者是，可以使用乾蝕刻與濕蝕刻混 合的方式，例如先使用乾蝕刻、再進行濕蝕刻來執行選擇性 形成替代閘極1110中第一凹穴113之蝕刻步驟。 再來，請參考第15圖，在蝕刻遮罩131之保護下，就 可以在第一凹穴113中填入所需之第一功函數閘極金屬層 201239960 163。第15A圖緣示第11圖中之切線B-B’之剖視圖。如果 使用全面性地沉積方式（blank deposition )，第一功函數閘極 金屬層163還會覆蓋遮罩131。視情況需要，此時可以依據 建立PM0S或是NM0S之計畫，填入對應之適當第一功函 數閘極金屬層163。所以第一功函數閘極金屬層163可以是 N型功函數閘極金屬材料，或是p型功函數閘極金屬材料， N型功函數閘極金屬材料較佳選自氮化鈦(TiN)、碳化组 (TaC)、氮化钽(TaN)、氮化矽钽(TaSiN)及鋁等所構成的群 組’ P型功函數閘極金屬材料較佳選自由氮化鈦(TiN)、嫣 (W)、氣化鎢(WN)、鉑（Pt)、鎳(Ni)、釕(Ru)、碳氮化鈕(TaCN) 或碳氮氧化组(TaCNO)所構成的群組。 請參考第16圖，然後，使用另一只圖案化光阻135來 覆蓋未被遮罩131所保護的部分，所以圖案化光阻丨35會覆 蓋第一凹穴113與部份之第一功函數閘極金屬層163。第16八 圖繪示第11圖中之切線B_B，之剖視圖。視情況需要，圖案 化光阻135中可能包含底部抗反射層（BARC)。 繼續，隨即利用圖案化光阻135作為遮罩，剝除暴露之 第一功函數閘極金屬層163與與遮罩131。於是，另一個替 代閘極（圖中例示替代閘極2110)以及其中之替代材料11〇 便會暴露出來。隨後。圖案化光阻丨35便可以加以移除。 17 201239960 然後，請參考第17圖，完全移除暴露出來之替代材料 110與摻質區域120而形成第二凹穴115。接下來，使用第 二功函數閘極金屬167層填入第二凹穴115中，同時也會順 便填入第一凹穴113中。然後，再使用一低電阻金屬164同 時填滿原先替代閘極1110與2110所佔據之區域，即第一凹 穴113與第二凹穴115中，以分別形成第一金屬閘極16〇與 第一金屬閘極165。 接下來，例如使用化學機械研磨法來移除多餘之第一功 函數閘極金屬163、第二功函數閘極金屬層167層與低電阻 金屬164後，即完成了所需之第一金屬閘極16〇與第二金屬 閘極165。如果第一金屬閘極160為PMOS與NMOS其中之 者，則第一金屬閘極165即為另外一者，相對應地，第一 金屬閘極160與第二金屬閘極165兩旁的源極/汲極14〇則分 別具有相對應的P型或N型導電性。於是第一金屬閘極16〇 與第二金屬閘極165即可以為靜態隨機存取記憶體中 (SRAM)鄰接之閘極。 適當之而介電常數介電層1〇3與功函數閘極金屬材料 M3/167為本技藝人士所知，例如高介電常數介電層是 選自矽酸铪氧化合物(HfSiO)、矽酸铪氮氧化合物(Hfsi〇N)、 氧化給(Hf〇)、氧化爛(LaO)、紹酸鋼(LaAlO)、氧化錯(Zr〇)、 矽酸锆氧化合物（ZrSi0)、鍅酸铪(HfZr〇)或其組合，n型功 18 201239960 函數閘極金屬材料較佳選自氮化鈦(TiN)、碳化钽(TaC)、氮 化组(TaN)、氮化矽鈕(TaSiN)及鋁等所構成的群組，p型功 函數閘極金屬材料較佳選自由氮化鈦(TiN)、鎢（w)、氮化鎢 (WN)、#(Pt)、鎳(Ni)、釕(RU)、碳氮化鈕(TaCN)或碳氮氧 化钽(TaCNO)所構成的群組。 當第一金屬閘極160與第二金屬閘極165皆已完成後， 就可以繼續形成用於電連接第一金屬閘極16〇與第二金屬閘 極165之源極/汲極140之接觸插塞no。例如，請參考第1〇 圖所示。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾’皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1-10圖例示本發明形成金屬閘極方法之例示性步驟。 第11-17圖例示本發明形成金屬閘極方法之例示性步驟。 【主要元件符號說明】 101基材 102 —般介電常數介電層 103向介電常數介電層 1 〇4淺溝渠隔離 201239960 105主動區域 110替代材料 110替代閘極 1110替代閘極 2110替代閘極 111第一區域 112第二區域 113第一凹六 115第二凹穴 116密封層 117側壁子 118蝕刻停止層 120摻質區域 121摻質 131遮罩 132遮罩 133蝕刻遮罩 134氧化物 135光阻 140源極/汲極 150層間介電層 160第一金屬閘極 161第一材料組 20 201239960 163功函數閘極金屬層 164低電阻金屬 165第二金屬閘極 166第二材料組 167功函數閘極金屬層 168低電阻金屬 170接觸插塞The structure of Wer et al. is not mentioned here. 8 201239960 Please refer to Figure 5, and then initially form the substrate 101 covered by the interlayer dielectric layer (9), and at the same time surround the alternative layer u ', layer 15. It does not cover the alternative opening 110. For example, the electrical layer 150 can be used to completely cover the exposed substrate, the mask m and then the planarization process, removing portions of the layer = such that the mask 132 is exposed. Therefore, the interlayer dielectric layer 15 〇 罩 132 has approximately the same height. Alternatively, some of the interlayer dielectric is removed; at 150 o'clock, the mask 132 is removed, so the interlayer dielectric layer 15 大约 has approximately the same height as the replacement = no, as shown in FIG. </ br> </ br> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; For example, an etch mask (4) may be used to completely cover the second region (1) to a portion of the dopant region 12G, but the first region (1) is selectively exposed to the undoped region, ie, the first region. (1) Relatively high secret rate, so the second region 112 protected by the _mask (3) and the dopant region having a relatively low etching rate are not substantially removed. Therefore, the 'first-cavity 113 does not extend to the doping. The region 12(), so there is no lateral etching, and the undercut is generated under the mask 133. Here, the "substantially not removed" # relatively low-pushing region The 120 series means that under this selective etch step, the ratio of the first region (1) to the dopant region (10) will be greater than at least %. These (four) rate ratios vary depending on the etchant and the etching temperature. 201239960 In the present embodiment, the etching step of selectively removing the region 111 of the replacement gate 110 can be performed using a secret type, for example, using a test (four) engraving. Suitable etchants can be diluted hydrofluoric acid (DHF) with ammonia or tetramethylammonium hydroxide (TMAH). For example, pre-etching is performed at room temperature using diluted hydrofluoric acid (DHF). Thereafter, the first region 111 is selectively removed completely using an alkaline etchant to form the first recess 113. After the etching is completed, the etch mask 133 can be removed. Alternatively, the etching step of selectively removing the first region in the replacement gate 110 may be performed by dry etching and wet etching, for example, using dry etching followed by wet etching. Then, referring to Fig. 7, the first material group 161 is used to fill the first recess 113 to form the first metal gate 16A. If the excess first material group 161 covers the interlayer dielectric layer 15 〇日寺, a planarization process may be performed to remove the excess first-material group 161 to expose the interlayer dielectric layer 15 〇. The first material group 161 may include a work function gate metal layer ι63 and a low resistance metal 164. The work function gate metal layer 163 may be a single metal layer or a composite metal layer. The inter-metal interpole (10) can be adjusted to have an appropriate work function via the appropriate group ' of the work function gate metal M3 in the first material group 161. Suitable dielectric constant dielectric layers 1〇3 and work function gate metal materials (6) are known to those skilled in the art. 201239960 In another implementation, please refer to FIG. 7A, which illustrates a cross-sectional view. The lip-shaped high dielectric constant dielectric layer 103 may be formed first after removing the first region 1U in the replacement gate and before using the first material . Lai Cai formed a rhyme number riding metal layer (6) and low resistance metal 164. In this case, the high dielectric constant dielectric layer originally formed under the #代材料 is not formed. Next, please refer to the eighth diagram illustrating the other side direction, and the engraving step is performed again, and the second region 112 and the dopant region 120 in the replacement gate 110 are removed to form a second recess. . The way in which the engraving and the heart can be mixed is either directly or secretly, for example, using an artificial surname, and removing the second field and the dopant in the replacement gate UG without a mask. Area 12〇. Suitable agents may be higher temperatures; tetramethylamnlonium hydroxide (TMAH) relative to the selectivity of the first region (1), or other tetraalkylammonium hydroxide solution. Then, please refer to Fig. 9 and fill the second pocket 115 with the second material group 16 6 to form the second metal gate 165. If the ^ group (10) covers the interlayer dielectric layer (9), it is also possible to perform a second flat (four) private removal of the outer second material group 166 to expose the interlayer dielectric layer 150. I: The germanium group 166 may include a work function gate metal layer 167 and a low resistance metal. The work function gate metal layer 16 can be a single metal layer or a composite 11 201239960 metal layer. The second material set 166 can be adjusted to have an appropriate work function via a suitable combination of work function gate metals 167 in the second material set 166. If the first metal gate 160 is one of the PMOS and the NMOS, and the second metal gate 165 is the other one, correspondingly, the source of the first metal gate 160 and the second metal gate 165 The /poles 140 have corresponding P-type or N-type conductivity, respectively. Thus, the first metal gate 16 〇 and the second metal gate 165 may be sram adjacent gates in the static random access memory and the first metal gate 160 is in direct contact with the second metal gate 165 And the work function gate metals are electrically connected to each other. Suitable high dielectric constant dielectric layer 103 and work function gate metal material 163/167 are known to those skilled in the art. For example, high dielectric constant dielectric layer 103 is selected from the group consisting of bismuth citrate (HfSiO) and acid. Niobium oxynitride (HfSiON), oxidized (HfO), lanthanum oxide (LaO), lanthanum aluminate (LaAlO), zirconia (ZrO), niobium oxynitride (ZrSiO), acid (HfZrO) or In combination, the N-type work function gate metal material is preferably selected from the group consisting of titanium nitride (TiN), tantalum carbide (TaC), nitride nitride (TaN), tantalum nitride (TaSiN), and aluminum. The p-type work function gate metal material is preferably selected from the group consisting of titanium oxide (TiN), tungsten (W), tungsten nitride (WN), Pt (Pt), nickel (Ni), ruthenium (Ru), and niobium carbonitride. A group consisting of (TaCN) or a carbon oxynitride button (TaCNO). After the first metal gate 160 and the second metal gate 165 have been completed, the source/drain 14 for electrically connecting the first metal gate 16 and the second metal gate 12 201239960 pole 165 can be continuously formed. 〇 contact plug π〇. For example, please refer to FIG. 1 'the first interlayer dielectric layer 150 is completely covered with the first metal gate 160 and the second metal gate 165' to form a contact hole exposing the source/drain 14 ( (not shown) ). Contact plug 170 is then completed by filling the contact hole with a suitable conductive material. A metal halide (not shown) may be formed in advance between the contact plug 17A and the source/drain 14 视 as occasion demands. Referring to Figures 11-17, another exemplary step of forming a metal gate of the present invention is illustrated, which is characterized by the use of a photoresist to define a pattern of a hard mask that is filled with a low-resistance metal while filling the original replacement material. a region to form a first metal gate and a second metal gate. First, please refer to the tangential line A_A in Fig. 11 and Fig. 12, Fig. 11 at the same time, and the cross-sectional view of Fig. 12 is presented. A substrate 1〇1 is provided. The substrate 1〇1 is usually a semiconductor material such as a germanium wafer or an overlying insulating layer (Silic〇n_〇nInsulat〇r, s〇i). The substrate 101 is covered by an interlayer dielectric layer 150. Source/drain 140 and shallow trench isolation 104 are included in substrate 1〇1. An adjacent material 110 has been formed on the substrate 1〇1, and the active region 1〇5 is additionally provided on the substrate 101. Where the alternative material 110 meets the active region 1〇5, it is where the MOS gate is located. The replacement gate 1110 includes an alternative material 110, a sealing layer 116 including tantalum nitride, a sidewall spacer 117, an etch stop layer 118, and a general dielectric constant dielectric layer 102 or a high dielectric constant dielectric layer 1 as the case may be. 〇 3. Alternative Gate 1 13 201239960 2110 also includes alternative materials, a sealing layer comprising tantalum nitride, a sidewall spacer, an etch stop layer, and a dielectric layer as desired, but are not shown for simplicity. The side wall sub-117 can be a single or composite structure. The substrate 101 has been previously chemically mechanically ground so that the replacement gate 1110/2110 is flush with the top surface of the interlayer dielectric layer 150, and the top surface of the portion of the gate 1110/2110 is exposed. The alternative material 110 is currently used to temporarily replace the location of future metal gates (not shown) and is therefore a sacrificial material, such as may be undoped. A structure of a desired doping well or the like may be additionally formed in the substrate 101, and will not be described herein. A barrier/touch stop layer as desired may also be formed between the replacement material 110 and the high-k dielectric layer 103. The material of this layer may be TiN, SiN, etc. This layer can be used as an etch stop layer when the matching between the alternative material 110 and the high-k dielectric layer 103 material is increased and/or when the replacement material 110 is removed in a subsequent step. The alternate gate 1110 can be one of an NMOS or a PMOS, and the alternate gate 2110 is the other. Fig. 12A is a cross-sectional view showing a tangent B-B' in Fig. 11. Referring to Figure 12A, a suitable dopant 121, such as a Group III (III) element such as boron or aluminum, or carbon is selectively implanted in the replacement material 110 to form a dopant region 120. Preferably, the position of the dopant region 120 is pre-planned, and the bit 14 201239960 is on a boundary region of a metal gate that is different in proximity and is adjacent to, for example, PM 〇s and nm 〇s (not shown). The trench is isolated just above. For example, a mask such as a photoresist (not shown) may be used to protect other regions prior to implantation and then implant the desired dopant (2) in the exposed region. Then remove the mask again. Thereafter, please refer to Fig. 13, firstly depositing a mask m, such as a titanium nitride hard mask, on the interlayer dielectric layer (9), and then depositing an oxide 134' such as a sulphur dioxide. A patterned photoresist is also used to selectively cover one of the alternative gates ni〇/211() (NM〇MpM〇s). The green patterned photoresist 135 of Fig. 13 covers the replacement gate 2110. Next, the patterned photoresist 135 can be used to pattern the mask i3i, for example, the 钮 buttoning step 'transfers the pattern of the stage 135 onto the mask i3i, and then the photoresist 135 can be removed. Next, please refer to Figure 14, through the protection of the mask ,3ι, to remove the exposed substitute gate (1) 〇 or 211 之 one of the alternative materials, due to the protection of the mask 131, only the replacement gate 111G 11替代, which is an alternative to 2110, will be removed. The Fig. 14 exemplifies that only the replacement material 110 in the alternative pole 1110 is removed to form the first pocket 113, and the replacement material 11G in the replacement gate 2UG is retained. Fig. MA is a cross-sectional view showing a tangent B-B in Fig. 11. Due to the protection of the cover 15 201239960 cover 131 and the dopant region 120, the etching step of this time does not substantially remove the replacement gate 2110 protected by the etch mask 131 and the dopant region 12 与 and has a relatively low engraving rate. The dopant region is 12〇. Therefore, the first recess n3 does not extend to the dopant region 120, so there is no disadvantage of lateral etching to create undercut under the etch mask 131. The term "substantially not removing" the dopant region 120 having a relatively low etching rate as referred to herein means that the etching ratio of the first region 1U to the dopant region 120 is greater than at least in this selective etching step. 5〇. These etching rate ratios vary depending on the etchant and the etching temperature. In the present embodiment, the etching step of selectively removing the gate 111 turns can be performed using a wet etching method, for example, using an alkaline etchant. Suitable money engraving agents can be diluted hydrofluoric acid (DHF) with ammonia or tetramethylammonium hydroxide (TMAH). For example, first use diluted hydrofluoric acid (DHF) at room temperature. Pre-remaining. The replacement gate m is then selectively removed completely using an alkaline etchant to form a first recess 113. Alternatively, an etching step of selectively forming the first recess 113 in the replacement gate 1110 may be performed by dry etching and wet etching, for example, using dry etching followed by wet etching. Further, referring to Fig. 15, under the protection of the etch mask 131, the first work function gate metal layer 201239960 163 can be filled in the first recess 113. Fig. 15A is a cross-sectional view showing a tangent line B-B' in Fig. 11. The first work function gate metal layer 163 also covers the mask 131 if a full thickness deposition is used. Depending on the situation, at this time, according to the plan for establishing PM0S or NM0S, fill in the corresponding first work function gate metal layer 163. Therefore, the first work function gate metal layer 163 may be an N-type work function gate metal material or a p-type work function gate metal material, and the N-type work function gate metal material is preferably selected from titanium nitride (TiN). The group of P-type work function gate metal materials consisting of carbonization group (TaC), tantalum nitride (TaN), tantalum nitride (TaSiN) and aluminum is preferably selected from titanium nitride (TiN) and tantalum. (W), a group consisting of tungsten carbide (WN), platinum (Pt), nickel (Ni), ruthenium (Ru), carbon nitride (TaCN) or carbonitride (TaCNO). Referring to FIG. 16, then, another patterned photoresist 135 is used to cover the portion not protected by the mask 131, so the patterned photoresist 35 covers the first recess 113 and a portion of the first work. Function gate metal layer 163. Figure 16 shows a cross-sectional view of the tangent B_B in Fig. 11. A patterned anti-reflective layer (BARC) may be included in the patterned photoresist 135 as needed. Continuing, the patterned photoresist 135 is used as a mask to strip the exposed first work function gate metal layer 163 and the mask 131. Thus, another alternate gate (illustrated as an alternate gate 2110 in the figure) and the replacement material 11 therein are exposed. Subsequently. The patterned photoresist 35 can be removed. 17 201239960 Then, referring to Fig. 17, the exposed substitute material 110 and the dopant region 120 are completely removed to form a second pocket 115. Next, a second work function gate metal 167 layer is used to fill the second recess 115, and is also easily filled into the first recess 113. Then, a low-resistance metal 164 is used to simultaneously fill the regions occupied by the original replacement gates 1110 and 2110, that is, the first recess 113 and the second recess 115, respectively, to form the first metal gate 16 and the first A metal gate 165. Next, after removing the excess first work function gate metal 163, the second work function gate metal layer 167 layer and the low resistance metal 164, for example, using a chemical mechanical polishing method, the required first metal gate is completed. The pole 16 〇 and the second metal gate 165. If the first metal gate 160 is one of the PMOS and the NMOS, the first metal gate 165 is the other one, and correspondingly, the source of the first metal gate 160 and the second metal gate 165 The drains 14 具有 have corresponding P-type or N-type conductivity, respectively. Thus, the first metal gate 16 〇 and the second metal gate 165 can be gates adjacent to the SRAM. Suitably, the dielectric constant dielectric layer 1〇3 and the work function gate metal material M3/167 are known to those skilled in the art. For example, the high-k dielectric layer is selected from the group consisting of bismuth citrate (HfSiO) and ruthenium. Acid bismuth oxynitride (Hfsi〇N), oxidation (Hf〇), oxidized lanthanum (LaO), sulphuric acid steel (LaAlO), oxidized (Zr〇), zirconium oxynitride (ZrSi0), bismuth ruthenate (HfZr〇) or a combination thereof, n-type work 18 201239960 The function gate metal material is preferably selected from the group consisting of titanium nitride (TiN), tantalum carbide (TaC), nitrided group (TaN), tantalum nitride (TaSiN) and A group of aluminum or the like, the p-type work function gate metal material is preferably selected from the group consisting of titanium nitride (TiN), tungsten (w), tungsten nitride (WN), #(Pt), nickel (Ni), yttrium. A group consisting of (RU), carbon nitride (TaCN) or tantalum oxynitride (TaCNO). After the first metal gate 160 and the second metal gate 165 have been completed, the contact between the source/drain 140 for electrically connecting the first metal gate 16A and the second metal gate 165 can be continuously formed. Plug no. For example, please refer to the figure in Figure 1. The above are only the preferred embodiments of the present invention, and all changes and modifications made by the scope of the present invention should be covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-10 illustrate exemplary steps of a method of forming a metal gate of the present invention. Figures 11-17 illustrate exemplary steps of a method of forming a metal gate of the present invention. [Main component symbol description] 101 substrate 102 - General dielectric constant dielectric layer 103 to dielectric constant dielectric layer 1 〇 4 shallow trench isolation 201239960 105 active region 110 replacement material 110 instead of gate 1110 instead of gate 2110 replacement gate Pole 111 first region 112 second region 113 first concave six 115 second recess 116 sealing layer 117 sidewall spacer 118 etch stop layer 120 dopant region 121 dopant 131 mask 132 mask 133 etch mask 134 oxide 135 Photoresist 140 source/drain 150 inter-layer dielectric layer 160 first metal gate 161 first material group 20 201239960 163 work function gate metal layer 164 low-resistance metal 165 second metal gate 166 second material group 167 work Function gate metal layer 168 low resistance metal 170 contact plug