201234363 六、發明說明： 【發明所屬之技術領域】 本發明大體上係關於記憶體裝置。更特定言之，本發明 係關於具串聯互連磁性隨機存取記憶體（「mram」）單元 之記憶體裝置。 【先前技4餘】 鑑於發現在料溫度下具有一強磁阻之磁性穿隧接面， MRAM裝置已成為越來越受關注㈣象。裝置提供 數種益處，諸如更快速寫入及讀取、非揮發性及對電離賴 射不敏感。因此，MRAM裝置日益取代基於—電容器之一 電荷狀態之記憶體裝置’諸如動態隨機存取記憶體裝置及 快閃記憶體裝置。 在一習知實施方案中，-MRAM裝置包含一 mram單元 陣列，該等MRAM單元之各者包含—磁性穿随接面，該磁 性穿隨接面由被一薄絕緣層分開的—對鐵磁層形成。一鐵 磁層（所謂的參考層）之特徵為在一固定方向上之一磁化， 且其他鐵磁層（所謂的儲存層）之特徵為在寫人裝置時（諸如 藉由施加一磁場)改變的一方向上之一磁化。當參考層及 儲存層之各自磁化反平行時，磁性穿随接面之一電阻係高 的’即具有對應於-高邏輯狀態「i」之—電阻值％“。 另方面’备各自磁化平行時，磁性穿随接面之電阻係低 的’即具有對應於-低邏輯狀態「〇」之一電阻值、一 AMh之—邏輯狀態係藉由比較其電阻值與一參"考電 阻值Rref而讀取’該參考電阻值^係自一參考單元或參考 162187.doc 201234363 單70之-群組導出且表示高邏輯狀態「】」與低邏輯狀態 「0」之間的—中間電阻值。 在一習知MRAM單元中，通常由一相鄰反鐵磁層交換偏 置一參考層，其特徵為該反鐵磁層之一臨限溫度丁⑽。在 低於該臨限溫度Tbr下，藉由該反鐵磁層之交換偏置而釘 紮該參考層之一磁化，藉此保持該參考層之磁化在一固定 方向上。在高於該臨限溫度Tbr下，該交換偏置實質上消 失，藉此解除釘紮該參考層之磁化。因此且為了避免資料 遺失，該習知MRAM單元之一操作溫度窗具有由該臨限溫 度TBR定義的一上界。 在經實施以熱協助切換（r TAS」）之一河尺八河單元之情 況下，通常亦由另一反鐵磁層交換偏置一儲存層，該另一 反鐵磁層相鄰於該儲存層且特徵為小於臨限溫度丁⑽之一 Β»限皿度TBS。在低於該臨限溫度Tbs下，藉由該交換偏置 而釘紮該儲存層之一磁化，藉此禁止該儲存層之寫入。藉 由將該MRAM層加熱至高於該臨限溫度Tbs(但低於Tbr)而 貫行寫入，藉此解除釘紮該儲存層之磁化以允許諸如藉由 施加一磁場而寫入。該MRAM單元接著隨著施加該磁場而 冷卻至低於該臨限溫度Tbs，使得該儲存層之磁化在該經 寫入方向上「凍結」。 雖然提供多種益處，但一習知丁八8型MRAM裝置經受特 疋缺點。具體言之，—寫入操作溫度冑係由Tbr_t的定義 且因此文限於上端處之臨限溫度Tbr及下端處之臨限溫度 Tbs。因為對用於交換偏置之反鐵磁材料之實踐限制，故 162187.doc 201234363 該寫入操作溫度窗可相當受限，諸如受限於小於2〇〇。〇或 小於1 50eC之一範圍。此外，在一 TAS型MRAM單元陣列之 情況下’個別單元之特性可歸因於製造可變性而跨該陣列 改變。此可變性可導致該陣列之臨限溫度丁⑽及Tbs之一分 佈（例如其至多可達到±3(rc )，藉此進一步減小該寫入操 作溫度窗。此外’此可變性可影響跨該陣列之磁性穿隧接 面之一電阻且可導致該陣列之電阻值Rmin及Rmax之一分 佈，藉此在讀取期間複雜化一個別單元之一量測電阻值與 參考電阻值Rref之間的一比較。因此，在製造期間可需 要一緊密容差控制，且此緊密容差控制可轉化成較低製造 良率及較高製造成本。 在此背景下，需要開發本文描述的記憶體裝置及相關方 法。 【發明内容】 本發明之一態樣係關於一種記憶體裝置。在一實施例 中，該記憶體裝置包含串聯地電連接之败細單元，:等 MRAM單元之各者具有―儲存磁化方向及—感測磁化方 向。在一寫入操作期間，該等MRAM單元之多者係藉由 換該等MRAM單元之該等儲存磁化方向而平行地寫入。 -讀取操作期間’該等MRAM單元之一特定者係藉由相 於該等MRAMU之該㈣者之儲存磁化方向改曰變該 MRAM單元之該特定者之感測磁化方向而讀取。 本發明之另-態樣係關於一種操作一記憶體裝置之 法。在-實施例中’該方法包含在該記憶料置中提供 I62187.doc 201234363 數個串聯互連MRAM單元。該方法亦包含在一寫入操作期 間，將該等MRAM單元之各者之一儲存磁化方向自—啟始 邏輯狀態切換至另一邏輯狀態以儲存一多位元資料值之一 各自部分。該方法進-步包含在一讀取操作期間，相對於 該等MRAM單元之-選定者之儲存磁化方向*改變該等 MRAM單元之該選定者之一感測磁化方向以判定由該等 MRAM單元之該敎相存㈣乡位元㈣狀該部分。 亦考量本發明之其他態樣及實施例。先前摘要及下文詳 細描述並不意味著將本發明限於任何特定實施例而是僅意 味著描述本發明之一些實施例。 【實施方式】 為了更好地瞭解本發明之—些實施例之本質及目的 結合隨附圖式參考下文詳細描述。 ， 下文U應用於關於本發明之—些實施例描述的一些態 樣。本文同樣可擴展此等定義。 如本文使用，單數術語「一 「一 齡m 入 個J及該」包含複 數參考物’除非上下 件之引用τ… 。因此’例如，-物 仵之引用了包含多個物件， 一 卞除非上下文另有清楚指示。 文使用’術浯「集」係指一或多個 因此，例如，—物#a ;仟您票合。 隼之… 包含一單一物件或多個物件。- 集之物件亦可稱為該集 同。在-些例項中… 集之物件可相同或不 性。 '、之物件可共用—或多個共同特 如本文使用 術語「實質上 」及「實質」係指 一相當可 162187.doc 201234363 觀程度或範圍。當結合一事件或境況使用時，術語可係指 精確地發生該事件或境況之例項以及近似發生該事件或境 況之例項，諸如考量本文描述的實施例之典型製造容差或 可變性。 如本文使用，術語「相鄰」係指接近或鄰接。相鄰物件 可彼此隔開或可實際上彼此接觸或彼此直接接觸。在一些 例項中，相鄰物件可彼此一體形成。 如本文使用，術語「連接」（「connect」'「connected」 及「connection」）係指一可操作耦合或連結。經連接物件 可彼此直接耦合或可諸如經由另一物件集而彼此間接耦 合。 如本文使用，術語「主族元素」係指族IA(或族丨）、族 ΠΑ(或族2)、族IIIA(或族13)、族IVA(或族14)、族^(或族 1 5)、族V〗A(或族1 6)、族VIIA(或族！ 7)及族vmA(或族i 8) 之任何者中之化學元素。主族元素有時亦稱為3塊元素或p 塊元素。 如本文使用，術語「過渡金屬」係指族IVB(或族4)、族 VB(或族5)、族VIB(或族6) '族VHB(或族7)、族…仙（或 族8、9及10)、族IB(或族U)及族ΠΒ(或族12)之任何者中之 化學元素。過渡金屬有時亦稱為d塊元素。 如本文使用，術語「稀土元素」係指Sc、γ、La、Ce、201234363 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a memory device. More particularly, the present invention relates to memory devices having serially interconnected magnetic random access memory ("mram") cells. [Previous technology 4] In view of the discovery of magnetic tunnel junctions with a strong magnetic reluctance at the material temperature, MRAM devices have become more and more concerned (4). The device provides several benefits, such as faster writing and reading, non-volatile, and insensitive to ionizing radiation. Therefore, MRAM devices are increasingly replacing memory devices based on one of the charge states of capacitors such as dynamic random access memory devices and flash memory devices. In a conventional implementation, the -MRAM device includes an array of mram cells, each of the MRAM cells including a magnetic wear-and-match surface that is separated by a thin insulating layer. The layer is formed. A ferromagnetic layer (so-called reference layer) is characterized by being magnetized in one of the fixed directions, and other ferromagnetic layers (so-called storage layers) are characterized by changes in the writing of the device (such as by application of a magnetic field) One of the ones is magnetized upward. When the respective magnetizations of the reference layer and the storage layer are anti-parallel, the resistance of one of the magnetic wear-fed surfaces is high, that is, the resistance value % corresponding to the -high logic state "i". When the magnetic wear-through surface has a low resistance, that is, it has a resistance value corresponding to the -low logic state "〇", and an AMH--the logic state is compared with the resistance value and the reference resistance value. Rref reads 'this reference resistance value ^ is derived from a reference unit or reference 162187.doc 201234363 single 70-group derived and represents the high resistance between the high logic state "" and the low logic state "0" - intermediate resistance value . In a conventional MRAM cell, a reference layer is typically exchanged by an adjacent antiferromagnetic layer, characterized by one of the antiferromagnetic layers being temperature limited (10). Below this threshold temperature Tbr, one of the reference layers is magnetized by the exchange bias of the antiferromagnetic layer, thereby maintaining the magnetization of the reference layer in a fixed direction. Above this threshold temperature Tbr, the exchange bias is substantially lost, thereby unlocking the magnetization of the reference layer. Therefore, and to avoid data loss, one of the conventional MRAM cell operating temperature windows has an upper bound defined by the threshold temperature TBR. In the case of a river ruler unit that is implemented with a thermally assisted switching (r TAS), a storage layer is typically also biased by another antiferromagnetic layer exchange, the other antiferromagnetic layer being adjacent to the The storage layer is characterized by a TBS that is less than a threshold temperature (10). Below this threshold temperature Tbs, one of the storage layers is magnetized by the exchange bias, thereby inhibiting the writing of the storage layer. The writing is performed by heating the MRAM layer above the threshold temperature Tbs (but below Tbr), thereby unlocking the magnetization of the storage layer to allow writing, such as by applying a magnetic field. The MRAM cell is then cooled to below the threshold temperature Tbs as the magnetic field is applied, such that the magnetization of the storage layer "freezes" in the written direction. While providing a number of benefits, a conventional D8-8 MRAM device suffers from a particular disadvantage. Specifically, the write operation temperature is defined by Tbr_t and is therefore limited to the threshold temperature Tbr at the upper end and the threshold temperature Tbs at the lower end. Because of the practical limitations imposed on the exchange of biased antiferromagnetic materials, the write operation temperature window can be quite limited, such as limited to less than 2 〇〇. 〇 or a range of less than 1 50eC. Moreover, in the case of a TAS type MRAM cell array, the characteristics of the individual cells can be varied across the array due to manufacturing variability. This variability may result in a distribution of the threshold temperature (10) and Tbs of the array (eg, up to ±3 (rc), thereby further reducing the write operating temperature window. Further, this variability may affect the cross One of the magnetic tunneling junctions of the array is electrically resistive and can cause one of the resistance values Rmin and Rmax of the array to be distributed, thereby complicating between the measured resistance value of one of the cells and the reference resistance value Rref during reading. A comparison. Therefore, a tight tolerance control may be required during manufacturing, and this tight tolerance control can translate into lower manufacturing yields and higher manufacturing costs. In this context, the memory devices described herein need to be developed. And related methods. One aspect of the present invention relates to a memory device. In an embodiment, the memory device includes a smashing unit electrically connected in series, and each of the MRAM cells has a The magnetization direction is stored and the magnetization direction is sensed. During a write operation, the plurality of MRAM cells are written in parallel by swapping the storage magnetization directions of the MRAM cells. A particular one of the MRAM cells is read by changing the sense magnetization direction of the particular one of the MRAM cells relative to the storage magnetization direction of the (4) of the MRAMUs. The aspect is directed to a method of operating a memory device. In an embodiment, the method includes providing a plurality of serially interconnected MRAM cells in the memory device. The method also includes a write operation. During the period, one of the MRAM cells stores the magnetization direction from the initial logic state to another logic state to store a respective portion of one of the multi-bit data values. The method further includes reading During operation, one of the selected ones of the MRAM cells is changed in relation to the storage magnetization direction of the selected one of the MRAM cells* to sense the magnetization direction to determine the coherent state of the MRAM cells (4) township (4) The other aspects and embodiments of the present invention are also considered in the foregoing. The invention is not limited to any particular embodiment, but is merely meant to describe some embodiments of the invention. Means for better understanding of the nature and purpose of the embodiments of the present invention are described in detail below with reference to the accompanying drawings, in which U is applied to some aspects described in connection with the embodiments of the present invention. The definitions are extensible. As used herein, the singular term "a", "a", "includes", "includes", and "includes", unless the reference to the upper and lower parts is τ... so 'for example, the reference to the object contains multiple Objects, 上下文 卞 上下文 卞 。 。 。 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文 文- The objects of the set can also be called the same set. In some of the items... the objects of the set can be the same or not. ', the objects may be shared - or a plurality of common features as used herein, the terms "substantially" and "substantial" means a degree or range that is comparable to 162187.doc 201234363. When used in connection with an event or circumstance, the term may refer to an instance of the event or circumstance that occurs precisely, and an instance that approximates the event or circumstance, such as to consider the typical manufacturing tolerances or variability of the embodiments described herein. As used herein, the term "adjacent" refers to proximity or abutment. Adjacent items may be spaced apart from each other or may actually be in contact with each other or in direct contact with each other. In some instances, adjacent objects may be integrally formed with one another. As used herein, the term "connected" ("connected" and "connected") refers to an operative coupling or linkage. The connected objects may be directly coupled to each other or may be indirectly coupled to one another, such as via another set of objects. As used herein, the term "main group element" refers to the group IA (or family group), family group (or group 2), group IIIA (or group 13), family IVA (or group 14), group ^ (or group 1). 5), a chemical element in any of the family V A (or group 16), family VIIA (or family! 7), and family vmA (or family i 8). The main family element is sometimes referred to as a 3-block element or a p-block element. As used herein, the term "transition metal" refers to group IVB (or group 4), group VB (or group 5), group VIB (or group 6) 'group VHB (or group 7), family...xian (or group 8) , 9 and 10), chemical elements in any of the family IB (or group U) and the family group (or group 12). Transition metals are sometimes also referred to as d-block elements. As used herein, the term "rare earth element" means Sc, γ, La, Ce,
Pr、Nd、Pm、Sm、Eu、Gd、Tb、Dy、H。、Er、Tm、Yb 及Lu之任何者。 MRAM裝置 162187.doc 201234363 首先關注圖卜其圖解說明根據本發明之一實施例實施 的一記憶體裝置。在圖解說明的實施例中，該記憶體裝置 係一 MRAM裝置100,其包含— MRAM單元1〇2。為了便於 表不且為了激發該MRAM裝置1〇〇及其他mram裝置之特 定益處及功能，在圖1中圖解說明該單一MRAM單元〗〇2, 然考量諸如可依一互連方式包含多個“尺八河單元。 在圓解說明的實施例中，MRAM單元1G2經實施以進行 自我參考操作，其中可基於該黯趟單元1〇2内之磁化之 一相對對準且在無需比較一參考單元或參考單元之一群組 之一外部電阻值之情況下實行一讀取操作。如下文進一步 說明，該MRAM單元102之自❹考實施方案允許忽略具 固疋磁化之參考層，且因此允許在無一臨限溫度丁br 之情況下或無關於一臨限溫度Tbr而操作該mram單元 102。以此方式，可極大地擴展該mram裝置之—操作 溫度窗，以允許在高環境溫度下操作或允許更快速寫入。 此外，4 MRAM裝置100可承受對製造可變性之一更大不 敏感性，藉此增大製造良率且降低製造成本。此外，該 MRAM單元102之自我參考實施方案允許該MRAM單元102 與相似地實施成一垂直堆疊或一水平陣列的其他單 元互連，如下文進一步說明。 MRAM單元1〇2實施為一磁性穿隧接面，且包含一感測 層104、一儲存層1 〇6及一分隔層1〇8，該分隔層⑺&安置在 該感測層1〇4與該儲存層106之間。考量該MRAM單元102 之其他實施方案。例如，該感測層104及該儲存層1 〇6之相 I62l87.doc 201234363 對位置可反轉，該儲存層106安置在該感測層1〇4上方。 感測層104及儲存層106之各者包含一磁性材料及特定古 之鐵磁類型之一磁性材料或由該磁性材料形成。一鐵磁= 料之特徵可為具一特定矮頑磁性之一實暫卜 只貝工昱十面的磁 化，此指示一磁場之一量值以繼其經驅動在一方向上飽和 之後反轉該磁化。大體而言，該感測層1〇4及該儲存層〖％ 可包含相同鐵磁材料或不同鐵磁材料。如在圖！*圖解說 明，該感測層104包含一軟鐵磁材料，即具有—相對低矯 頑磁性（諸如不大於約〇.〇1奥斯特）之一鐵磁材料，而該儲 存層106包含一硬鐵磁材料，即具有一相對高矯頑磁性（諸 如大於約0.01奥斯特）之一鐵磁材料。以此方式，該感測層 104之一磁化可容易在低強度磁場下在讀取操作期間改 變’同時該儲存層106之一磁化保持穩定。合適鐵磁材料 包含具有或不具有主族元素之過渡金屬 '稀土元素及其等 合金。例如，適合鐵磁材料包含鐵（「Fe」）、鈷 (C〇j )、鏢（「Ni」）及其等合金（諸如坡莫合金（或 Ni8〇Fe2。）；基於 Ni、Fe及硼（「B」）之合金；C〇9〇Fe|。：及 基於Co、Fe及B之合金）^在一些例項中，基於川及以（及 視需要B)之合金可具有比基於Co及Fe(及視需要b)之合金 更小的一矯頑磁性。該感測層i 〇4及該儲存層i 〇6之各者之 一厚度可在奈米（「nm」）範圍中，諸如自約i nm至約2〇 nm或自約1 nm至約10 nm。考量該感測層1〇4及該儲存層 106之其他實施方案。例如，該感測層i 〇4及該儲存層丨〇6 之任一者或兩者可依相似於所謂的合成反鐵磁層之一方式 I62I87.doc •10· 201234363 包含多個子層。 刀隔層108用作一穿隧接面，且包含一絕緣材料或由一 絕緣材料形成。合適絕緣材料包含氧化物，諸如氧化鋁 (例如’ A丨2〇3)及氧化鎂（例如，MgO)。該分隔層108之一 厚度可在奈米範圍中，諸如自約1 nm至約i〇nme 在圖解說明的實施例中，MRAM單元1〇2經實施以儲存 對應於一對邏輯狀態之一者之資料^換言之，該MRAM單 元102係一單位元單元，其儲存一單位元資料值，然亦考 量用於儲存多位元資料值之多位元實施方案。根據該 MRAM單元102之單位元實施方案，該儲存層1〇6具有可在 對應於該對邏輯狀態之一對方向之間切換之一儲存磁化。 參考圖1，5亥MRAM單元1 02亦包含一釘紮層11 〇，該釘紮 層110相鄰於該儲存層106而安置，且當該釘紮層110内或 忒釘紮層110附近之一溫度低於一臨限溫度Tbs(諸如阻擋 溫度、一尼爾溫度或另一臨限溫度）時透過交換偏置而穩 定化沿著該對方向之一特定者之儲存磁化。當該溫度處於 或问於该臨限溫度TBS時，該釘紮層no解除釘紮或去耦合 該儲存磁化方向，藉此允許儲存磁化方向切換至該對方向 之另一者。相比之下，省略相鄰於感測層1〇4之此一釘紮 層，且因此該感測層104具有在實質上無交換偏置之情況 下解除釘紮及容易改變之一感測磁化方向。該釘紮層j ^ 〇 包含一磁性材料及特定言之反鐵磁類型之一磁性材料或由 該磁性材料形成。合適反鐵磁材料包含過渡金屬及其等合 金》例如，適合反鐵磁材料包含基於錳（「Mn」）之合金， I62187.doc • II - 201234363 諸如基於银（「Irj )及Μη之合金（例如’ IrMn);基於Fe及 Μη之合金（例如’ FeMn);基於鉑（「Pt」）及Μη之合金（例 如，PtMn);及基於Ni及Μη之合金（例如，NiMn^在一些 例項中’基於Ir及Mn(或基於Fe及Μη)之合金之臨限溫度 TBS可在約120。(：至約220。〇或約150°C至約200。(：之範圍 中，且可小於基於Pt及Mn(或基於Ni及Μη)之合金之臨限溫 度TBS，其可在約300°C至約35〇°c之範圍中。因為解除釘 紮感測磁化方向，故該臨限溫度TBS可經選擇以在無一臨 限溫度丁⑽之情況下或無關於一臨限溫度Tbr而適應一所要 應用，該臨限溫度TBR將另外設定一操作溫度窗之一上 界。 仍參考圖1 ’ MRAM裝置100亦包含一跡線集（或帶狀導 體）以提供寫入及讀取功能。具體言之，一位元線116係在 感測層104側上電連接至MRAM單元102,且實質上平行於 一場線112，該場線112安置在MRAM單元102下方且在儲 存層106側上磁性地連接至Mram單元102。在圖解說明的 貫施例中，該場線112包含一包殼114，該包殼114形成相 鄰於該場線112之側面及底部之場線112之一外部且用於將 一磁場集中朝向該MRAM單元102。該包殼114包含一磁性 材料及特定言之鐵磁類型之一磁性材料或由該磁性材料形 成。該MRAM裝置100進一步包含一電晶體118，該電晶體 118係透過一帶120而在該儲存層側上電連接至MR 單το 1 02 ^該電晶體1丨8可在一阻擋模式（〇FF)與一飽和模 式（ON)之間切換，藉此允許一電流流動通過該mram單元 162l87.doc -12· 201234363 102。 在TAS型寫入操作期間，藉由經由位元線}丄6而施加一 加熱電流使之通過MRAM單元1〇2而加熱該mram單元 1〇2，電晶體118處於一飽和模式。該河尺八河單元1〇2加熱 至高於釘紮層m之臨限溫度TBS之—溫度，使得解除釘紮 儲存層1 06之-磁化。同時或繼一短時間延遲之後，場線 Π2經啟動以引發一寫入磁場122自一啟始方向切換至另一 向，、體。之，一寫入電流經施加通過該場線丨丨2以引 發該寫人磁場122以據此切㈣存磁化方向。因為可根據 該寫入磁場】22對準該儲存磁化方向，故該儲存磁化方向 可根據-寫人編碼方案在多個方向之間切換。—可能寫入 編碼方㈣用隸達約刚。之—對方向實施，使得邏輯狀 態「0」指派至該對方向之__者，且邏輯狀態4」指派至 該對方向之另一者。 ^ 1-f m it vj ，一· ν ,，別电晶骽u 8切… 至:阻擋模式以禁止電流流動通過mram單元iQ2，藉此 V部該MRAM早疋1〇2。可在冷卻該廳鳩單元⑻期間維 =入磁場122,且—旦該難鹰單元㈣冷卻至低於釘 、no之臨限溫度Tbs，則可撤銷啟動該寫人磁場122。 由騎紮層11()之交換偏置而釘紮料磁化方向， 、疋向保持穩定以保留經寫入資料。 可^寫人操作之其他實施方案。例如，舰Μ單元102 一施具有具一相對高縱橫比（諸如約1.5或！.5以上）之 一各向異性形狀。在該MRAM單元⑽之此—各向異性形 I62I87.doc -13- 201234363 狀實施方案中，健在成# 储存⑽^可在無冑㈣層110之情況 下切換且可保持穩定。作為另-實例，可藉由使用所謂的 自旋轉移力矩（「STT」）效果經由位元線ιΐ6而施加一寫入 電流使之通過該MRAM單元嶋實行—寫人操作。在此 STT型寫人㈣中，該寫人電流可藉由穿過-極化磁性 層（未圖解說明）或穿過感測層1Q4而變為自旋㈣，且可根 據I寫入電"IL之一自旋極化定向而切換儲存層1 〇6之一磁 化。用自旋極化寫人電流切換儲存層磁化亦可組合一 Μ 型寫入操作’諸如藉由將該mramj^iq2加熱至高於臨 限溫度TBS且接著施加該自旋極化寫入電流使之通過該 MRAM單元 1〇2。 在MRAM單7L102之-讀取操作期間，場線112經啟動以 引發一讀取磁場丨24以改變感測層1〇4之一磁化。具體言 之’-讀取電流經施加通過該場線112以引發該讀取磁場 124以據此改變感測磁化方肖。因》該感測層刚經受較少 交換偏置或不經受父換偏置，故該感測磁化方向可容易地 在低強度磁場下及低於臨限值溫度Tbs之一溫度下改變， 同時儲存磁化保持穩定在一經寫入方向上。 對於特定實施方案，在多個讀取循環中實行MRAM單元 1〇2之讀取操作，其中場線112經啟動以引發與一寫入編碼 方案相容之讀取磁場124。因為可根據該讀取磁場124而對 準感測磁化方向，故該感測磁化方向可根據該寫入編碼方 案（諸如一對方向移位達約18〇。之一寫入編碼方案）在多個 方向之間接連地切換。以此方式，感測磁化可自對應於該 162187.doc 14 201234363 寫入編碼方案之該對方向之一者之一啟始方向切換至對應 於该寫入編碼方案之該對方向之另一者之另一方向。 作為各讀取循環之部分，藉由經由位元線丨丨6而施加，一 感測電流使之通過MRAM單元1 02而判定感測磁化方向與 儲存磁化方向之間的一對準程度，電晶體U8處於一飽和 模式。對於一特定讀取循環及感測磁化之一特定方向，當 施加感測電流時跨該MRAM單元102量測一所得電壓產生 該MRAM單元1〇2之一電阻值。替代地，藉由跨該mram 單凡102施加一電壓且量測一所得電流而判定一電阻值。 當感測層104及儲存層1〇6之各自磁化反平行時，該mram 單元102之一電阻值通常對應於一最大值，即Rmax，當各 自磁化平行時，該MRAM單元1〇2之一電阻值通常對應於 一最小值，即Rmil^當各自磁化在反平行與平行之間時’ 該MRAM單元1〇2之一電阻值通常在、^與心^之間。多個 璜取循環之電阻值經處理以判定哪個感測磁化方向產生一 最小電阻值，藉此產生該儲存層1〇6之一經寫入方向且基 於哪個邏輯狀態指派至該經寫入方向而產生其經儲存資料 值。可使用（例如）結合一取樣/保持電路之一合適控制器來 實行電阻值之處理。 上文說明的MRAM單元1〇2之讀取操作係自我參考的， 此係因為可在無需比較一參考單元或參考單元之一群組之 If况下基於该MRAM單元1 〇2内之磁化之相對對準而實行 該讀取操作。因此，該讀取操作較不易複雜化及發生鑑於 製造可變性之錯誤。該MRAM單元1〇2之自我參考實施方 162187.doc 15 201234363 案亦允許省略具一固定磁化之一參考層，且因此允許在無 一臨限溫度tbs之情況下或無關於一臨限溫度Tbs而操作該 MRAM單元1〇2。以此方式，該乂尺入肘單元1〇2之一操作溫 度窗可極大地擴展（諸如）至至多約400。(：或400。(：以上之溫 度°此外且鑑於該經擴展操作溫度窗，可在寫入期間（諸 如）依具有小於約1〇奈秒之一持續時間之一脈衝之形式施 加一高強度加熱電流，藉此允許更快速寫入β 考量讀取操作之其他實施方案。例如，可以一單一讀承 循環達成更快速讀取，儘管涉及比較一參考電阻值。在該 單一讀取循環期間，可沿著一預定讀取方向（諸如沿著一 寫入讀取方案之一對方向之一者）對準感測磁化，且可比 較MRAM單元1〇2之-所得電阻值與—參考電阻值u，該 參考電阻值Rref表示Rfna)^Rmin之間的一令間電阻值。可基 於該MRAM單元1G2之電⑯值是大於^(此指示相對於該 預定讀取方向之-反平行對準）還是小於K此指示相對於 該預定讀取方向之一平行對準)而判定儲存層1〇6之—經寫 入方向及其經儲存資料值。作為另—實例，可相對於 定讀取方向且在不完全反轉其方向之情況下藉由施加—交 替感測電流而「擺動」▲測磁化。在此，該交替 可引發一變化讀取磁場，且單元1〇2之一電阻值 可隨著感測磁化藉由該變化讀取磁場而「擺動」而 改變。可基於該_單元102之該變化電阻值相對於令 父替感測電流是同相還是異相而判定儲存層ι〇6之 入方向及其經储存資料值^ *·'' I62187.doc -16- 201234363 接著關注圖2，其圖解說明根據本發明之另一實施例實 施的一 MRAM裝置200。在圖解說明的實施例中，該 MRAM裝置200包含配置成一垂直堆疊204a的多個MRAM 單元202a、202b及202c。相鄰於該垂直堆疊204a的是另一 垂直堆疊204b，該另一垂直堆疊204b可包含依相似於該等 MRAM單元202a、202b及202c之一方式配置的多個MRAM 單元。該MRAM裝置200之垂直堆疊實施方案允許多個 MRAM單元配置在彼此之上，藉此達成該等MRAM單元對 一給定佔據面積之一更高密度。雖然在圖2中圖解說明兩 個垂直堆疊2〇4a及204b，但考量更多或更少垂直堆疊可包 含在該MRAM裝置200中。為了便於展示，下文說明主要 關於該垂直堆疊204a，儘管說明亦適用於包含在該MRAM 裝置200中之其他垂直堆疊。同樣，依相似於參考圖1說明 的MRAM裝置100之一方式實施該MRAM裝置200及包含在 該MRAM裝置200中之MRAM單元之特定態樣，且下文不 重複該等態樣。 參考圖2 ’ MRAM單元202a、202b及202c安置在垂直堆 疊204a之各自層處’該MRAM單元202a安置在一頂層（或一 第三層）處，該MRAM單元202b安置在一中間層（或一第二 層）處’且該該MRAM單元202c安置在一底層（或一第一層） 處。在s亥垂直堆疊204a内，該等MRAM單元202a、202b及 202c串聯地電連接，藉此允許在寫入及讀取操作期間一共 同加熱電流流動通過該等MRAM單元2〇2a、202b及202c » 在一 TAS型寫入操作期間，一共同加熱電流可經施加通過 162I87.doc 201234363 該等MRAM單元202a、202b及202c以平行地寫入該等 MRAM單元2〇2a、2〇2b及2〇2c之多者，從而導致較低功率 消耗同時保持一想要之寫入速度。此外，該等MRAM單元 202a、202b及202c之自我參考實施方案及可變感測磁化之 提供允許選擇及探測該等MRAM單元202a、202b及202c之 一個別者，藉此促進該等串聯互連MRAM單元202a、202b 及202c之讀取操作同時保留降低功率消耗之益處。 在圖解說明的實施例中，MRAM裝置200亦包含一跡線 集（或帶狀導體）及一電晶體216以提供寫入及讀取功能。具 體言之，一位元線214係在MRAM單元202a側上串聯地電 連接至MRAM單元202a、202b及202c，且該電晶體216係 在MRAM·單元202c侧上串聯地電連接至MRAM單元202a、 202b及202c。該位元線214用作由該等MRAM單元202a、 202b及202c共用的一共同位元線，且該電晶體216用作由 該等MRAM單元202a、202b及202c共用的一共同電晶體。 此共用位元線2 1 4及此共用電晶體2 16之實施方案保留有價 值的佔據面積且降低製造成本。參考圖2，該MRAM裝置 200進一步包含一場線集，即：一場線218a，其安置在該 MRAM單元202a下方且磁性地連接至該MRAM單元202a ; 一場線218b，其安置在該MRAM單元202b下方且磁性地連 接至該MRAM單元202b ;及一場線218c，其安置在該 MRAM單元202c下方且磁性地連接至該MRAM單元202c。 雖然在圖2中未圖解說明，但該等場線21 8a、218b及218c 之各者可包含一包殼，該包殼用以將一磁場集中朝向該等 162l87.doc -18- 201234363 MRAM單元202a、202b及202c之一各自者。 仍參考圖2,透過一跡線集（或帶狀導體）及一通孔集而 電連接安置在垂直堆疊204a之不同層處之組件。具體言 之，位元線214係透過一通孔220而電連接至MRAM單元 202a。又’ MRAM單元202a係透過一帶206a、一對通孔 208a及210a以及一跡線212a而電連接至MRAM單元202b , 且s亥MRAM卓元202b係透過一帶206b、一對通孔208b及 210b以及一跡線212b而電連接至MRAM單元202c。同樣 地’該MRAM單元202c係透過一帶206c、一對通孔208c及 210c以及一跡線212c而電連接至電晶體216。該等通孔 208&、2081?、208(：、210&、21015及210(：以及跡線212&、 2 1 2b及21 2c提供電連接功能以及間隔以容納該等場線 218a、218b及218c。 考量垂直堆疊之其他實施方案。例如，雖然在圖2中圖 解說明MRAM單元202a、202b及202c之三層及相關組件， 但考量更多或更少層可包含在該垂直堆疊2〇4a中。作為另 一實例，可省略通孔210a、210b及2 10c之一或多者，同時 保持間隔以容納場線218a、21 8b及218c。作為一進一步實 例’該等場線21 8a、218b及21 8c之一或多者可用作為跨多 個垂直堆疊（諸如垂直堆疊2〇4a及204b)共用的一共同場 線。 在一 TAS型寫入操作期間，可藉由經由位元線2丨4施加 一共同加熱電流使之通過MRAM單元202a、202b及202c而 加熱垂直堆疊204a，電晶體216處於一飽和模式。該等 162187.doc -19· 201234363 MRAM單元202a、202b及202c加熱至高於一臨限溫度TBS 之一溫度，使得解除釘紮該等MRAM單元202a、202b及 202c之儲存磁化。同時或繼一短時間延遲之後，場線 218a、218b及218c經啟動以引發寫入磁場以根據一寫入編 碼方案切換儲存磁化方向，諸如一對方向對應於邏輯狀態 「0」及邏輯狀態「1」之寫入編碼方案。例如，該MRAM 單元202a之儲存磁化方向可自邏輯狀態「0」切換至邏輯 狀態「1」，該MRAM單元202b之儲存磁化方向可自邏輯狀 態「1」切換至邏輯狀態「0」，且該MRAM單元202c之儲 存磁化方向可自邏輯狀態「0」切換至邏輯狀態「1」。一 旦儲存磁化方向切換至其等經寫入方向，則該電晶體216 切換至一阻擋模式以禁止電流流動通過該垂直堆疊204a， 藉此將該等MRAM單元202a、202b及202c冷卻至低於該臨 限溫度TBS且保持儲存磁化沿著其等經寫入方向。以此方 式，一多位元資料值（諸如「101」）可以一單一寫入循環寫 入至該等MRAM單元202a、202b及202c中，該等MRAM單 元202a、202b及202c之各者儲存該多位元資料值之一各自 部分β 在一讀取操作期間，MRAM單元202a、202b及202c之一 個別者經選擇性地處理以判定由該MRAM單元儲存的一多 位元資料值之一各自部分。倘若（例如）該MRAM單元202a 被讀取，則場線2 1 8a經啟動以引發一讀取磁場以改變該 MRAM單元202a之一感測磁化方向》在該MRAM單元202a 之讀取操作期間，場線21 8b及2 18c可保持撤銷啟動以降低 162187.doc -20· 201234363 功率消耗，且該等MRAM單元及職之感測磁化方向 7保持實質上不變更，除起因於熱攪動之可能變動及與由 该場線218a引發的讀取磁場之可能互動之外。 . 。在圖解說明的實施例中，在多個讀取循環中實行_颜 單^O2〇2a之讀取操作，其中該MRAM單元之感測磁化 方向係根據一寫入編碼方案而（諸如）在對應於邏輯狀態 0」與邏輯狀態「1」之一對方向之間接連地切換。作為 各讀取循¥之部分，藉由經由位元線214施加-感測電流 使之通過垂直堆疊204a而判定該]^11八]^單元川以之感測磁 化方向與儲存磁化方向之間的一對準程度，電晶體216處 於一飽和模式。對於一特定讀取循環及該MRAM單元2〇2a 之一特定感測磁化方向，跨該垂直堆疊2〇4a量測_所得電 壓（或一所得電流）產生該垂直堆疊2〇乜之—電阻值。該垂 直堆疊204a之電阻值包單元2〇2a、“孔及“以之 一串聯電阻貢獻，其中切換該MRAM單元2〇2a之感測磁化 方向，同時該等MRAM單元202b及202c之感測磁化方向保 持實質上不變更《當該MRAM單元2〇2a之感測磁化與儲存 磁化反平行時’該等MRAM單元202a、2〇2b及202c之串聯 電阻貝獻通常具有一最大值’諸如一局部最大值，且當該 MRAM單元202a之磁化平行時，該等MRAM單元202a、 202b及202c之串聯電阻貢獻通常具有一最小值，諸如一局 部最小值。多個讀取循環之電阻值經處理以判定哪個感測 磁化方向產生一最小電阻值，藉此產生該MRAM單元202a 之一經寫入方向及一多位元資料值之其經儲存部分。藉由 162187.doc -21 - 201234363 依一相似方式操作，該等MRAM單元202b及202c經處理以 判定由該等MRAM單元202b及202c儲存的多位元資料值之 各自部分’藉此允許在一逐層基礎上或一逐單元基礎上自 該垂直堆疊204a讀取該多位元資料值。 考量讀取操作之其他實施方案。例如，在MRAM單元 202a之一讀取操作期間，該MRAM單元202a之感測磁化方 向可改變’場線2 1 8b及21 8c經啟動以沿著一預定讀取方向 (諸如一寫入編碼方案之一對方向之一者）對準MRAM單元 202b及202c之感測磁化方向。以此方式，可讀取MRAM單 元202a ’同時減小其餘MRAM單元202b及202c的感測磁化 方向的變動的影響。作為另一實例，一多位元資料值可平 行地寫入至多個垂直堆疊中，該等垂直堆疊之各者儲存多 位元資料值之一各自部分。在—讀取操作期間，該多位元 資料值可自該等垂直堆疊平行地讀取，從而導致更快速寫 入0 圖3圖解說明根據本發明之一進一步實施例實施的一 MRAM裝置300。依相似於參考圖i及圖2說明的MRAM裝 置100及200之一方式實施該MRAM裝置300之特定態樣， 且下文不重複該等態樣。參考圖3，該MRAM裝置300包含 依一並排方式配置成一水平陣列3〇4的多個MRAM單元 302a、302b、302c及302d。在該水平陣列304内，該等 MRAM單元302a、302b、302c及3 02d串聯地電連接，藉此 允許在寫入及讀取操作期間一共同電流流動通過該等 MRAM單元302a、302b ' 302c及302d。儘管佔有比一垂直 162l87.doc -22· 201234363 堆疊實施方案更大的一佔據面積，但該MRAM裝置300保 留降低功率消耗之益處’同時允許以較低製造成本實施且 促進整合其他類型的MRAM單元。 在圖解說明的實施例中，MRAM裝置300亦包含：一位 元線314，其由MRAM單元302a、302b、302c及302d共用 且在MRAM單元302a側上串聯地電連接至MRAM單元 302a、302b、302c及 302d ;及一電晶體 316，其由 MRAM 單元302a、302b、302c及302d共用且在MRAM單元302d側 上串聯地電連接至MRAM單元302a、302b、302c及302d。 參考圖3 ’該位元線3 U係透過一通孔308a及一帶306a而電 連接至該MRAM單元302a。又，該MRAM單元302a係透過 一對通孔3 10a及3 10b以及一跡線3 12a而電連接至該MRAM 單元3〇2b，該MRAM單元302b係透過一共用帶306b而電連 接至該MRAM單元302c，且該MRAM單元302c係透過一對 通孔310c及310d以及一跡線312b而電連接至該MRAM單元 302d。且，該MRAM單元302d係透過一帶306c、一對通孔 308b及310e以及一跡線312c而電連接至該電晶體316。該 等通孔308a、308b及31 〇e及跡線312c提供電連接功能以及 間隔以容納一場線集，即場線3 1 8a、3 18b及3 18c及3 18d， 其等安置在該等MRAM單元302a、302b、302c及302d之各 自者下方且磁性地連接至該等MRAM單元302a、302b、 302c及302d之各自者。 考量水平陣列304之其他實施方案。例如，雖然在圖3中 圖解說明四個MRAM單元302a、302b、302c及302d，但考 162I87.doc •23- 201234363 量更多或更少MRAM單元可包含在該水平陣列取中。作 為另-實例Μ立元線314可安置在帶遍a上方而非該帶 购下方。作為額外實例，可省略通孔310a、310b、 3 1 0c、3 1 0d及 3 10e之一忐之土 β ^ 次多者’且％線318a、318b及318c 及318d之-或多者可用作跨多個水平陣列共用的_共同場 線。作為-進—步實例，可結合mram單元之—垂直堆疊 (諸如參考圖2說明的垂直堆疊2〇4勾而實施該水平陣列 304。 雖然已參考本發明之特定實施例描述本發明，但熟習此 項技術者應瞭解可在不背離如由隨附申請專利範圍定義的 本發明之真實精神及料之情況下作出多種變更且替換等 效^ °此外’彳作出許多修改以使物質、方法或程序之- 特定It況#料、組分適應於本發明之目的、精神及範 疇所有此等修改意欲於在本文所附之申請專利範圍之範 嘴内、。特定言《’雖然已參考依—特定次序執行的特定操 作描述本文揭示的方法，但將瞭解此等操作可在不背離本 發明之教示之情況下組合、細分或重新排序以形成一等效 方法。據此，㈣本文另有指示，否則操作之排序及分組 非本發明之限制。 【圖式簡單說明】 圖1圖解說明根據本發明之一實施例之包含一 單 元之一記憶體裝置。 圖2圖解說明根據本發明之另一實施例之包含配置成一 垂直堆疊的多個串聯互連MRAM單元之一記憶體裝置。 162187.doc • 24· 201234363 圖3圖解說明根據本發明之一進一步實施例之包含配置 成一水平陣列的多個串聯互連MRAM單元之一記憶體裝 置。 【主要元件符號說明】 100 磁性隨機存取記憶體（MRAM)裝置 102 磁性隨機存取記憶體（MRAM)單元 104 感測層 106 儲存層 108 分隔層 110 釘紮層 112 場線 114 包殼 116 位元線 118 電晶體 120 帶 122 寫入磁場 124 讀取磁場 200 磁性隨機存取記憶體（MRAM)裝置 202a 磁性隨機存取記憶體（MRAM)單元 202b 磁性隨機存取記憶體（MRAM)單元 202c 磁性隨機存取記憶體（MRAM)單元 204a 垂直堆疊 204b 垂直堆疊 206a 帶 162187.doc -25 - 201234363 206b 帶 206c 帶 208a 通孔 208b 通孔 208c 通孔 210a 通孔 210b 通孔 210c 通孔 212a 跡線 212b 跡線 212c 跡線 214 位元線 216 電晶體 218a 場線 218b 場線 218c 場線 220 通孔 300 磁性隨機存取記憶體（MRAM)裝置 302a 磁性隨機存取記憶體（MRAM)單元 302b 磁性隨機存取記憶體（MRAM)單元 302c 磁性隨機存取記憶體（MRAM)單元 302d 磁性隨機存取記憶體（MRAM)單元 304 水平陣列 306a 帶 162187.doc -26- 201234363 306b 306c 308a 308b 310a 310b 310c 310d 310e 312a 312b 312c 314 316 318a 318b 318c 318d 帶 帶 通孔 通孔 通孔 通孔 通孔 通孔 通孔 跡線 跡線 跡線 位元線 電晶體 場線 場線 場線 場線 162187.doc -27Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, H. Any of Er, Tm, Yb and Lu. MRAM device 162187.doc 201234363 First, attention is directed to a memory device implemented in accordance with an embodiment of the present invention. In the illustrated embodiment, the memory device is an MRAM device 100 that includes an -MRAM cell 1〇2. To facilitate the presentation of the particular benefits and functions of the MRAM device 1 and other mram devices, the single MRAM cell is illustrated in FIG. 1, but may be considered to include multiple "in an interconnected manner". The shakuhachi unit. In the illustrated embodiment, the MRAM unit 1G2 is implemented for self-referencing operations in which one of the magnetizations within the unit 1〇2 can be relatively aligned and without comparing a reference unit Or performing a read operation with an external resistance value of one of the groups of reference cells. As further explained below, the self-referential implementation of the MRAM cell 102 allows the reference layer with solid magnetization to be ignored, and thus The mram unit 102 is operated without a threshold temperature br or without a threshold temperature Tbr. In this way, the operating temperature window of the mram device can be greatly expanded to allow operation at high ambient temperatures. Or allow for faster writing. Furthermore, the 4 MRAM device 100 can withstand greater insensitivity to one of manufacturing variability, thereby increasing manufacturing yield and reducing manufacturing costs. In addition, the MRAM cell The self-referencing embodiment of 102 allows the MRAM cell 102 to be interconnected with other cells that are similarly implemented as a vertical stack or a horizontal array, as further described below. The MRAM cell 102 is implemented as a magnetic tunnel junction and includes a a sensing layer 104, a storage layer 1 〇 6 and a spacer layer 〇8, the spacer layer (7) & disposed between the sensing layer 1 〇 4 and the storage layer 106. Other embodiments of the MRAM cell 102 are considered For example, the sensing layer 104 and the phase I62l87.doc 201234363 of the storage layer 1 可6 are reversible, and the storage layer 106 is disposed above the sensing layer 1 〇 4. The sensing layer 104 and the storage layer 106 Each of them comprises or consists of a magnetic material and a magnetic material of a specific type of ferromagnetic type. A ferromagnetic material can be characterized as having a specific short coercivity. The magnetization of the surface, which indicates that a magnitude of a magnetic field is reversed after it is driven to saturation in one direction. In general, the sensing layer 1〇4 and the storage layer [% may comprise the same ferromagnetic material Or different ferromagnetic materials. As shown in the figure!* The sensing layer 104 comprises a soft ferromagnetic material, that is, a ferromagnetic material having a relatively low coercivity (such as not more than about 〇. 〇1 Oersted), and the storage layer 106 comprises a hard ferromagnetic material. a material, i.e., a ferromagnetic material having a relatively high coercivity (such as greater than about 0.01 Oersted). In this manner, one of the sensing layers 104 can be easily magnetized during a read operation during a low intensity magnetic field. 'At the same time, the magnetization of one of the storage layers 106 remains stable. Suitable ferromagnetic materials include transition metal 'rare earth elements with or without main group elements and their alloys. For example, suitable for ferromagnetic materials containing iron ("Fe"), cobalt (C〇j), darts ("Ni") and other alloys (such as permalloy (or Ni8〇Fe2). ); an alloy based on Ni, Fe and boron ("B"); C〇9〇Fe|. : and alloys based on Co, Fe and B) ^ In some cases, alloys based on Chuanhe (and optionally B) may have a smaller orientation than alloys based on Co and Fe (and optionally b) Recalcitrant. One of the thickness of each of the sensing layer i 〇 4 and the storage layer i 〇 6 may be in the range of nanometers ("nm"), such as from about i nm to about 2 〇 nm or from about 1 nm to about 10 Nm. Other embodiments of the sensing layer 1〇4 and the storage layer 106 are contemplated. For example, either or both of the sensing layer i 〇 4 and the storage layer 丨〇 6 may be similar to one of the so-called synthetic antiferromagnetic layers. I62I87.doc • 10· 201234363 includes a plurality of sub-layers. The blade spacer 108 serves as a tunneling interface and comprises an insulating material or is formed of an insulating material. Suitable insulating materials include oxides such as alumina (e.g., 'A丨2〇3) and magnesium oxide (e.g., MgO). One of the thicknesses of the spacer layer 108 can be in the nanometer range, such as from about 1 nm to about i〇nme. In the illustrated embodiment, the MRAM cell 1〇2 is implemented to store one of a pair of logic states. In other words, the MRAM unit 102 is a unit cell that stores a unit of data value, but also considers a multi-bit implementation for storing multi-bit data values. According to the unit implementation of the MRAM cell 102, the storage layer 〇6 has a storage magnetization that is switchable between one of the pair of directions corresponding to the pair of logic states. Referring to FIG. 1, the 5 MW MRAM cell 102 also includes a pinning layer 11 相邻 disposed adjacent to the storage layer 106 and in the vicinity of the pinning layer 110 or adjacent to the pinned layer 110. A storage magnetization along a particular one of the pair of directions is stabilized by an exchange bias when a temperature is below a threshold temperature Tbs (such as a blocking temperature, a one-inch temperature, or another threshold temperature). When the temperature is at or about the threshold temperature TBS, the pinning layer no unpins or decouples the storage magnetization direction, thereby allowing the storage magnetization direction to switch to the other of the pair of directions. In contrast, such a pinned layer adjacent to the sensing layer 1〇4 is omitted, and thus the sensing layer 104 has one of sensing that is unpinned and easily changed without substantial exchange bias. Magnetization direction. The pinning layer j ^ 包含 comprises or is formed of a magnetic material and, in particular, one of the antiferromagnetic types. Suitable antiferromagnetic materials include transition metals and their alloys. For example, suitable antiferromagnetic materials include manganese ("Mn") based alloys, I62187.doc • II - 201234363 such as alloys based on silver ("Irj" and Μη ( For example 'IRMn); alloys based on Fe and Μη (eg 'FeMn); alloys based on platinum ("Pt") and Μη (eg PtMn); and alloys based on Ni and Μη (eg NiMn^ in some examples) The threshold temperature TBS of the alloy based on Ir and Mn (or based on Fe and Μη) may be in the range of about 120. (: to about 220 〇 or about 150 ° C to about 200. (: in the range, and may be less than Based on the threshold temperature TBS of Pt and Mn (or based on Ni and Μη) alloys, which may range from about 300 ° C to about 35 ° C. Because the pinning sense magnetization direction is removed, the threshold temperature The TBS can be selected to accommodate a desired application without a threshold temperature (10) or without a threshold temperature TBR, which will additionally set an upper boundary of an operating temperature window. The 1' MRAM device 100 also includes a set of traces (or strip conductors) to provide write and read functions. In particular, a bit line 116 is electrically coupled to the MRAM cell 102 on the sensing layer 104 side and substantially parallel to the field line 112, which is disposed below the MRAM cell 102 and on the storage layer 106 side. Magnetically coupled to the Mram unit 102. In the illustrated embodiment, the field line 112 includes a cladding 114 that forms an exterior of one of the field lines 112 adjacent the sides and bottom of the field line 112. And for concentrating a magnetic field toward the MRAM unit 102. The cladding 114 includes or is formed of or consisting of a magnetic material and a magnetic material of a particular ferromagnetic type. The MRAM device 100 further includes a transistor 118, The transistor 118 is electrically connected to the MR single το 1 02 ^ on the side of the storage layer via a strip 120. The transistor 1 丨 8 can be switched between a blocking mode (〇FF) and a saturation mode (ON). Thereby, a current is allowed to flow through the mram unit 16l87.doc -12· 201234363 102. During the TAS type write operation, a heating current is applied through the bit line}丄6 to pass the MRAM cell 1〇2. Heating the mram unit 1〇2, the transistor 118 is in a saturation The temperature of the river is equal to the temperature of the threshold temperature TBS of the pinning layer m, so that the magnetization of the pinned storage layer 106 is released. At the same time or after a short time delay, the field line Π2 is activated to initiate a write magnetic field 122 to switch from a starting direction to another direction, a write current is applied through the field line 丨丨2 to induce the write human magnetic field 122 to be cut accordingly (4) Store magnetization direction. Since the storage magnetization direction can be aligned according to the write magnetic field 22, the storage magnetization direction can be switched between a plurality of directions according to the write-to-person coding scheme. - may be written to the coding side (four) with the arbitrage. The direction is implemented such that the logic state "0" is assigned to the __ of the pair of directions, and the logic state 4" is assigned to the other of the pair of directions. ^ 1-f m it vj , a · ν ,, don't be electro-crystal 骽 u 8 cut... To: Block mode to prohibit current flow through the mram unit iQ2, whereby the M part of the MRAM is earlier than 1〇2. The magnetic field 122 can be undoed during the cooling of the chamber unit (8) and the magnetic field 122 is entered into the field, and the hard-shell unit (4) is cooled to a temperature Tbs below the nail and no. The magnetization direction is pinned by the exchange bias of the riding layer 11 (), and the twist direction remains stable to retain the written data. Other embodiments of the human operation can be written. For example, the nacelle unit 102 has an anisotropic shape having a relatively high aspect ratio (such as about 1.5 or more..5 or more). In this embodiment of the MRAM cell (10), an anisotropic shape I62I87.doc -13 - 201234363, the active storage (10) can be switched in the absence of the (four) layer 110 and can remain stable. As a further example, a write current can be applied through the bit line ι6 via the bit line ι6 using a so-called spin transfer torque ("STT") effect to perform a write-through operation through the MRAM cell. In this STT type writer (4), the write current can be changed to spin (four) by passing through a polarization magnetic layer (not illustrated) or passing through the sensing layer 1Q4, and can be written according to I. One of the spin polarization orientations of IL switches one of the magnetizations of the storage layer 1 〇6. Switching the storage layer magnetization with a spin-polarized write current can also combine a 写入 type write operation 'such as by heating the mramj^iq2 above the threshold temperature TBS and then applying the spin-polarized write current Pass the MRAM unit 1〇2. During the MRAM single 7L102-read operation, field line 112 is activated to initiate a read magnetic field 丨 24 to change one of the sensing layers 1 〇 4 magnetization. Specifically, a read current is applied through the field line 112 to induce the read magnetic field 124 to change the sense magnetization square accordingly. Since the sensing layer has just undergone less exchange bias or is not subjected to the parent bias, the sensing magnetization direction can be easily changed at a low intensity magnetic field and below a threshold temperature Tbs, while The storage magnetization remains stable in the direction of writing. For a particular implementation, the read operation of MRAM cell 1〇2 is performed in a plurality of read cycles, wherein field line 112 is activated to initiate a read magnetic field 124 that is compatible with a write encoding scheme. Since the sense magnetization direction can be aligned according to the read magnetic field 124, the sense magnetization direction can be based on the write coding scheme (such as a pair of direction shifts up to about 18 〇. One of the write coding schemes) The directions are switched one after another. In this manner, the sense magnetization may be switched from one of the pair of directions corresponding to the one of the pair of directions written to the 162187.doc 14 201234363 to the other of the pair of directions corresponding to the write encoding scheme The other direction. As part of each read cycle, by applying a bit line 丨丨6, a sense current is passed through the MRAM cell 102 to determine an alignment between the sense magnetization direction and the storage magnetization direction. Crystal U8 is in a saturated mode. A particular direction of a particular read cycle and sense magnetization, a measured voltage across the MRAM cell 102 when a sense current is applied, produces a resistance value for the MRAM cell 1〇2. Alternatively, a resistance value is determined by applying a voltage across the mram unit 102 and measuring a resulting current. When the respective magnetizations of the sensing layer 104 and the storage layer 1〇6 are anti-parallel, a resistance value of the mram unit 102 generally corresponds to a maximum value, that is, Rmax, and when the respective magnetizations are parallel, one of the MRAM cells 1〇2 The resistance value generally corresponds to a minimum value, that is, when the respective magnetizations are between anti-parallel and parallel, the resistance value of the MRAM cell 1〇2 is usually between ^ and ^. The resistance values of the plurality of capture cycles are processed to determine which sense magnetization direction produces a minimum resistance value, thereby generating one of the storage layers 1 〇 6 in the write direction and based on which logic state is assigned to the written direction Produce its stored data values. The processing of the resistance value can be performed using, for example, a suitable controller in conjunction with a sample/hold circuit. The read operation of the MRAM cell 1〇2 described above is self-referential because it can be based on the magnetization in the MRAM cell 1 〇 2 without having to compare a reference cell or a group of reference cells. This read operation is performed with relative alignment. Therefore, the read operation is less complicated and erroneous in view of manufacturing variability. The self-referential implementation of the MRAM cell 1〇2 162187.doc 15 201234363 also allows omitting a reference layer with a fixed magnetization, and thus allows for a threshold temperature Tbs without or without a threshold temperature Tbs The MRAM cell 1〇2 is operated. In this manner, one of the operating temperature windows of the one-in-one elbow unit 1〇2 can be greatly expanded, such as up to about 400. (: or 400. (: above temperature ° in addition to and in view of the extended operating temperature window, a high intensity may be applied during writing, such as in the form of one pulse having a duration of less than about 1 nanosecond Heating the current, thereby allowing for faster writing of other embodiments of the beta-measurement read operation. For example, a faster read can be achieved with a single read cycle, although it involves comparing a reference resistance value. During the single read cycle, The sense magnetization may be aligned along a predetermined read direction (such as along one of the pair of write read schemes), and the resulting resistance value and the reference resistance value of the MRAM cell 1〇2 may be compared. u, the reference resistance value Rref represents an inter-resistance resistance value between Rfna)^Rmin. The electric 16 value based on the MRAM cell 1G2 may be greater than ^ (this indication is anti-parallel alignment with respect to the predetermined reading direction) And still less than K this indication is aligned in parallel with respect to one of the predetermined reading directions) and the storage direction of the storage layer 1 - 6 and its stored data values are determined. As another example, the magnetization can be "oscillated" by applying - alternately sensing the current with respect to the reading direction and without completely reversing its direction. Here, the altering may induce a change in the reading magnetic field, and a resistance value of the cell 1 〇 2 may change as the sensing magnetization "oscillates" by reading the magnetic field by the change. The input direction of the storage layer ι 6 and its stored data value can be determined based on the change resistance value of the _ unit 102 relative to whether the parent sensible current is in phase or out of phase. I62187.doc -16- 201234363 Next, attention is directed to FIG. 2, which illustrates an MRAM device 200 implemented in accordance with another embodiment of the present invention. In the illustrated embodiment, the MRAM device 200 includes a plurality of MRAM cells 202a, 202b, and 202c configured as a vertical stack 204a. Adjacent to the vertical stack 204a is another vertical stack 204b, which may include a plurality of MRAM cells configured in a manner similar to one of the MRAM cells 202a, 202b, and 202c. The vertical stacking implementation of the MRAM device 200 allows multiple MRAM cells to be placed on top of each other, thereby achieving a higher density of the MRAM cells for a given footprint. Although two vertical stacks 2〇4a and 204b are illustrated in FIG. 2, more or less vertical stacks may be included in the MRAM device 200. For ease of presentation, the following description relates primarily to the vertical stack 204a, although the description applies to other vertical stacks included in the MRAM device 200. Similarly, a specific aspect of the MRAM device 200 and the MRAM cell included in the MRAM device 200 is implemented in a manner similar to that of the MRAM device 100 described with reference to Fig. 1, and the same will not be repeated hereinafter. Referring to FIG. 2 'MRAM cells 202a, 202b, and 202c are disposed at respective layers of the vertical stack 204a'. The MRAM cells 202a are disposed at a top layer (or a third layer), and the MRAM cells 202b are disposed in an intermediate layer (or a The second layer is at 'and the MRAM cell 202c is disposed at a bottom layer (or a first layer). Within the s vertical stack 204a, the MRAM cells 202a, 202b, and 202c are electrically coupled in series, thereby allowing a common heating current to flow through the MRAM cells 2〇2a, 202b, and 202c during write and read operations. » During a TAS type write operation, a common heating current can be applied to the MRAM cells 2〇2a, 2〇2b, and 2〇 in parallel by applying the MRAM cells 202a, 202b, and 202c through the 162I87.doc 201234363. The majority of 2c, resulting in lower power consumption while maintaining a desired write speed. Moreover, the self-referencing embodiments of the MRAM cells 202a, 202b, and 202c and the provision of variable sensing magnetization allow for selection and detection of one of the MRAM cells 202a, 202b, and 202c, thereby facilitating the serial interconnections. The read operations of MRAM cells 202a, 202b, and 202c simultaneously retain the benefit of reduced power consumption. In the illustrated embodiment, MRAM device 200 also includes a trace set (or strip conductor) and a transistor 216 to provide write and read functionality. Specifically, one bit line 214 is electrically connected in series to the MRAM cells 202a, 202b, and 202c on the MRAM cell 202a side, and the transistor 216 is electrically connected in series to the MRAM cell 202a on the MRAM cell 202c side. , 202b and 202c. The bit line 214 is used as a common bit line shared by the MRAM cells 202a, 202b, and 202c, and the transistor 216 is used as a common transistor shared by the MRAM cells 202a, 202b, and 202c. The embodiment of the shared bit line 2 1 4 and the shared transistor 2 16 retains a valuable footprint and reduces manufacturing costs. Referring to FIG. 2, the MRAM device 200 further includes a field line set, that is, a field line 218a disposed under the MRAM cell 202a and magnetically connected to the MRAM cell 202a; a field line 218b disposed under the MRAM cell 202b. And magnetically connected to the MRAM cell 202b; and a field line 218c disposed under the MRAM cell 202c and magnetically coupled to the MRAM cell 202c. Although not illustrated in FIG. 2, each of the field lines 21 8a, 218b, and 218c may include a cladding for concentrating a magnetic field toward the 162l87.doc -18-201234363 MRAM cell One of each of 202a, 202b, and 202c. Still referring to Figure 2, the components disposed at different layers of the vertical stack 204a are electrically connected through a set of traces (or strip conductors) and a set of vias. In particular, bit line 214 is electrically coupled to MRAM cell 202a via a via 220. Further, the 'MRAM cell 202a is electrically connected to the MRAM cell 202b through a strip 206a, a pair of vias 208a and 210a, and a trace 212a, and the SRAM MRAM element 202b is transmitted through a strip 206b, a pair of vias 208b and 210b, and A trace 212b is electrically coupled to the MRAM cell 202c. Similarly, the MRAM cell 202c is electrically coupled to the transistor 216 through a strip 206c, a pair of vias 208c and 210c, and a trace 212c. The vias 208 &, 2081?, 208 (:, 210 & 21015 and 210 (: and traces 212 & 2 1 2b and 21 2c provide electrical connection functions and spacing to accommodate the field lines 218a, 218b and 218c. Consider other implementations of vertical stacking. For example, although three layers and associated components of MRAM cells 202a, 202b, and 202c are illustrated in FIG. 2, more or fewer layers may be included in the vertical stack 2〇4a. As another example, one or more of the vias 210a, 210b, and 2 10c may be omitted while maintaining spacing to accommodate the field lines 218a, 21 8b, and 218c. As a further example, the field lines 21 8a, 218b And one or more of 21 8c can be used as a common field line shared across multiple vertical stacks (such as vertical stacks 2〇4a and 204b). During a TAS-type write operation, by bit line 2 4 applying a common heating current to heat the vertical stack 204a through the MRAM cells 202a, 202b, and 202c, the transistor 216 is in a saturated mode. The 162187.doc -19· 201234363 MRAM cells 202a, 202b, and 202c are heated above one. One temperature of the threshold temperature TBS, so that The storage magnetization of the MRAM cells 202a, 202b, and 202c is unpinned. At the same time or after a short time delay, the field lines 218a, 218b, and 218c are activated to initiate a write magnetic field to switch the storage magnetization direction according to a write encoding scheme. For example, a write encoding scheme in which a pair of directions corresponds to a logic state "0" and a logic state "1". For example, the storage magnetization direction of the MRAM cell 202a can be switched from a logic state "0" to a logic state "1", The storage magnetization direction of the MRAM cell 202b can be switched from the logic state "1" to the logic state "0", and the storage magnetization direction of the MRAM cell 202c can be switched from the logic state "0" to the logic state "1". Once the magnetization direction is stored. Switching to its write direction, the transistor 216 switches to a blocking mode to inhibit current flow through the vertical stack 204a, thereby cooling the MRAM cells 202a, 202b, and 202c below the threshold temperature TBS. And keeping the storage magnetization along its writing direction. In this way, a multi-bit data value (such as "101") can be written to the MRAM cells 2 in a single write cycle. 02a, 202b, and 202c, each of the MRAM cells 202a, 202b, and 202c stores a respective portion of the multi-bit data value β. During a read operation, an individual of the MRAM cells 202a, 202b, and 202c Optionally processing to determine respective portions of one of the multi-bit data values stored by the MRAM cell. If, for example, the MRAM cell 202a is read, the field line 2 18a is activated to initiate a read magnetic field to change the sense magnetization direction of one of the MRAM cells 202a during the read operation of the MRAM cell 202a. The field lines 21 8b and 2 18c can be deactivated to reduce the power consumption of 162187.doc -20· 201234363, and the sensing magnetization directions 7 of the MRAM units and the functions remain substantially unchanged except for possible changes due to thermal agitation. And in addition to the possible interaction with the read magnetic field induced by the field line 218a. . . . In the illustrated embodiment, the read operation of the singularity ^O2 〇 2a is performed in a plurality of read cycles, wherein the sense magnetization direction of the MRAM cell is in accordance with a write coding scheme, such as in correspondence Switching between the logic state 0" and one of the logic state "1" pairs is successively switched. As part of each read cycle, by applying a sense current through the bit line 214 to pass it through the vertical stack 204a, it is determined that the transistor is sensed between the magnetization direction and the storage magnetization direction. The degree of alignment is such that the transistor 216 is in a saturated mode. For a particular read cycle and a particular sense magnetization direction of the MRAM cell 2〇2a, measuring the resulting voltage (or a resulting current) across the vertical stack 2〇4a produces the vertical stack 2〇乜-resistance value . The resistance value packet unit 2〇2a, “hole and” of the vertical stack 204a are contributed by one series resistance, wherein the sensing magnetization direction of the MRAM cell 2〇2a is switched, and the sensing magnetization of the MRAM cells 202b and 202c is simultaneously The direction remains substantially unchanged. "When the sense magnetization of the MRAM cell 2〇2a is anti-parallel to the storage magnetization, the series resistance of the MRAM cells 202a, 2〇2b, and 202c typically has a maximum value such as a local portion. The maximum value, and when the magnetizations of the MRAM cells 202a are parallel, the series resistance contributions of the MRAM cells 202a, 202b, and 202c typically have a minimum value, such as a local minimum. The resistance values of the plurality of read cycles are processed to determine which sense magnetization direction produces a minimum resistance value, thereby generating a stored portion of one of the MRAM cells 202a in the written direction and a multi-bit data value. By operating in a similar manner by 162187.doc -21 - 201234363, the MRAM cells 202b and 202c are processed to determine respective portions of the multi-bit data values stored by the MRAM cells 202b and 202c. The multi-bit data value is read from the vertical stack 204a on a layer-by-layer basis or on a cell-by-cell basis. Consider other implementations of the read operation. For example, during a read operation of one of the MRAM cells 202a, the sense magnetization direction of the MRAM cell 202a may change 'field lines 2 18b and 21 8c are activated to follow a predetermined read direction (such as a write encoding scheme) One of the pair of directions) aligns the sense magnetization directions of the MRAM cells 202b and 202c. In this manner, the MRAM cell 202a' can be read while reducing the effects of variations in the sense magnetization direction of the remaining MRAM cells 202b and 202c. As another example, a multi-bit data value can be written in parallel into a plurality of vertical stacks, each of which stores a respective portion of the multi-bit data value. During a read operation, the multi-bit data values can be read in parallel from the vertical stacks, resulting in a faster write to zero. Figure 3 illustrates an MRAM device 300 implemented in accordance with a further embodiment of the present invention. The particular aspect of the MRAM device 300 is implemented in a manner similar to one of the MRAM devices 100 and 200 described with reference to Figures i and 2, and such aspects are not repeated below. Referring to Figure 3, the MRAM device 300 includes a plurality of MRAM cells 302a, 302b, 302c, and 302d that are arranged in a horizontal array 3〇4 in a side-by-side manner. Within the horizontal array 304, the MRAM cells 302a, 302b, 302c, and 302d are electrically coupled in series, thereby allowing a common current to flow through the MRAM cells 302a, 302b' 302c during write and read operations. 302d. The MRAM device 300 retains the benefit of reduced power consumption while occupying a larger footprint than a vertical 162l87.doc -22.201234363 stacked implementation' while allowing implementation at lower manufacturing costs and facilitating integration of other types of MRAM cells. . In the illustrated embodiment, MRAM device 300 also includes a bit line 314 that is shared by MRAM cells 302a, 302b, 302c, and 302d and that is electrically coupled in series to MRAM cells 302a, 302b on the MRAM cell 302a side. 302c and 302d; and a transistor 316 shared by the MRAM cells 302a, 302b, 302c, and 302d and electrically coupled to the MRAM cells 302a, 302b, 302c, and 302d in series on the MRAM cell 302d side. Referring to Fig. 3', the bit line 3 U is electrically connected to the MRAM cell 302a through a via 308a and a strip 306a. Moreover, the MRAM cell 302a is electrically connected to the MRAM cell 3〇2b through a pair of vias 3 10a and 3 10b and a trace 3 12a, and the MRAM cell 302b is electrically connected to the MRAM through a common strap 306b. The cell 302c, and the MRAM cell 302c is electrically connected to the MRAM cell 302d through a pair of vias 310c and 310d and a trace 312b. Moreover, the MRAM cell 302d is electrically coupled to the transistor 316 via a strip 306c, a pair of vias 308b and 310e, and a trace 312c. The vias 308a, 308b and 31 〇e and the trace 312c provide electrical connection functions and spacing to accommodate a field line set, i.e., field lines 3 18 8 , 3 18b and 3 18c and 3 18d , which are disposed in the MRAM Each of the units 302a, 302b, 302c, and 302d is magnetically coupled to the respective ones of the MRAM units 302a, 302b, 302c, and 302d. Other embodiments of horizontal array 304 are contemplated. For example, although four MRAM cells 302a, 302b, 302c, and 302d are illustrated in FIG. 3, more or fewer MRAM cells may be included in the horizontal array fetch 162I87.doc • 23-201234363. As another example, the vertical line 314 can be placed above the belt pass a instead of below the purchase. As an additional example, one of the through holes 310a, 310b, 3 1 0c, 3 1 0d, and 3 10e may be omitted, and the % lines 318a, 318b, and 318c and 318d may be used. A common field line shared across multiple horizontal arrays. As a further example, the horizontal array 304 can be implemented in conjunction with a vertical stack of mram cells (such as the vertical stack 2 〇 4 hooks described with reference to Figure 2). Although the invention has been described with reference to specific embodiments of the invention, It will be appreciated by those skilled in the art that various changes can be made without departing from the true spirit and scope of the invention as defined by the appended claims. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Specific operations performed in a particular order are described herein, but it is understood that such operations can be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present invention. Accordingly, (4) Otherwise, the ordering and grouping of operations is not a limitation of the present invention. [Schematic Description of the Drawings] FIG. 1 illustrates the inclusion of a unit according to an embodiment of the present invention. Memory Device. Figure 2 illustrates a memory device including a plurality of series interconnected MRAM cells configured in a vertical stack in accordance with another embodiment of the present invention. 162187.doc • 24· 201234363 Figure 3 illustrates a A further embodiment includes a memory device of a plurality of series interconnected MRAM cells configured as a horizontal array. [Main Component Symbol Description] 100 Magnetic Random Access Memory (MRAM) Device 102 Magnetic Random Access Memory ( MRAM) unit 104 sensing layer 106 storage layer 108 spacer layer 110 pinning layer 112 field line 114 cladding 116 bit line 118 transistor 120 band 122 writing magnetic field 124 reading magnetic field 200 magnetic random access memory (MRAM) Device 202a magnetic random access memory (MRAM) unit 202b magnetic random access memory (MRAM) unit 202c magnetic random access memory (MRAM) unit 204a vertical stack 204b vertical stack 206a with 162187.doc -25 - 201234363 206b Strip 206c strip 208a via 208b via 208c via 210a via 210b via 210c via 212a trace 212b Trace 212c Trace 214 Bit Line 216 Transistor 218a Field Line 218b Field Line 218c Field Line 220 Via 300 Magnetic Random Access Memory (MRAM) Device 302a Magnetic Random Access Memory (MRAM) Cell 302b Magnetic Random Memory Memory RAM (MRAM) unit 302c Magnetic random access memory (MRAM) unit 302d Magnetic random access memory (MRAM) unit 304 Horizontal array 306a Band 162187.doc -26- 201234363 306b 306c 308a 308b 310a 310b 310c 310d 310e 312a 312b 312c 314 316 318a 318b 318c 318d with tape through hole through hole through hole through hole through hole through hole through hole trace trace line bit line transistor field line field line field line field line 162187.doc -27