TW201234180A - Cache coherency control method, system, and program - Google Patents

Abstract

Object To achieve cache coherency control that enables an increase in scalability of a shared memory multiprocessor system and an improvement in the cost performance while the cost of hardware and software is kept low. Solution In a system for controlling cache coherency of a multiprocessor system in which a plurality of processors share a system memory, each of the plurality of processors including a cache and a TLB, the processor includes a TLB controller including a TLB search unit that performs a TLB search and a coherency handler that performs TLB registration information processing when no hit occurs in the TLB search and a TLB interrupt occurs. The coherency handler includes a TLB replacement handler that searches a page table in the system memory and that replaces the TLB registration information, a TLB miss exception handling unit, and a storage exception handling unit. When the TLB interrupt is not a page fault, the TLB miss exception handling unit handles the TLB interrupt being a TLB miss interrupt occurring when no registration information having a matching address exists in the TLB and the storage exception handling unit handles the TLB interrupt being a storage interrupt occurring when registration information having a matching address exists in the TLB but access right is invalid.

Description

201234180 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to coherency control of cache memory, and in particular, regarding the control of the shared memory multi-processor pepper & Method, system and program for coherence. [Prior Art] A multiprocessor system simultaneously executes a plurality of tasks or programs (hereinafter referred to as "programs"). Each of the plurality of programs typically has a virtual address space for executing the program. The location in the virtual address space contains the address mapped in the physical address in the system memory. A single space in the memory is mapped to a plurality of virtual addresses in the multiprocessor. When each of the plurality of programs uses a virtual address, the addresses are converted to physical addresses in the system memory, and If there is no appropriate instruction or data for executing each of the programs in the cache memory of the processor, the hidden entity is captured and stored in the cache memory. In order to quickly convert virtual addresses in a multiprocessor system into a system. The so-called conversion look-aside buffer ( look-aside bUffer ' hereinafter referred to as "TLB") associated with the cache memory is used to obtain the appropriate address or information in the hidden body. The TLB is a buffer containing the conversion relationship between the virtual address and the physical address generated using the conversion algorithm. The use of TLB makes address translation very efficient. However, if the buffer is used in a symmetric multiprocessing (hereafter referred to as "201234180 "SMP") system, a non-coherence problem will occur. For a system in which a plurality of processors can read information from the shared system memory and write information to the shared system memory, the system must be small. To ensure that the memory system is turned off. That is, the non-coherence of the memory system 怂 system caused by the execution of a plurality of processors is not allowed. Each of the processors in the multiprocessor system typically contains a TLB for address translation associated with the cache memory. In order to maintain coherence, the shared memory mode in the system must carefully and consistently map changes on the TLB of a single processor in a multiprocessor to other processors. For multiprocessors, the coherence of the TLB can be maintained, for example, by using a process 11 interrupt ("intewessor interrupt") and software synchronization in the modification of all DLBs. This technology ensures memory coherence across the entire multiprocessor system. In a typical page memory system, the content of each TLB in a multiprocessor system reflects a portion associated with the cache memory that retains the contents of the page table of the system memory. Page (4) is often a memory mapping table 'The memory mapping table contains a virtual address or a virtual address segment, and the physical bit X page table associated with the virtual address further contains various other types of management materials, _ including page protection bit, valid item bit and various access control bits 'i such as T will clearly refer to the need for different tune (requires memory coherence: attribute) bit is defined as management data to statically configure whether the page is positive Need to be the same. However, this bit static configuration method can only effectively vibrate; a special program 4' allows these special programs to be controlled to the software, and the It body is rewritten 'because, except that the above bits need to be statically configured, 201234180 This bit must be statically configured in the entire system memory. In recent years, there have been a number of desktop PCs with a total of 2 yuan (cpus) & SMP-Linux (Linux is the trademark of τ〇(10) in the United States and other countries), and many applications have become popular. Shared memory multiprocessor, that is, SMp system, has been supported. Therefore, the increase in the number of processors in the system improves the throughput of the application and does not require rewriting the software. The general-purpose operating system (OS) that promotes SMP support (such as SMp Unux) has grown to a multiprocessor system that can control no less than one 24 processors. The amount of processing that can be improved by an increase in the number of processors and without the need to rewrite the features of the software is an advantage that does not exist in multiprocessor systems that do not share memory, such as clusters that use message passing programming. Therefore, SMP is a multiprocessor system suitable for protecting software assets. However, the scalability of SMP systems is lower than the scalability of packet-based messaging. This is because the cost of supporting the memory of the cache memory is significantly increased as the number of processors used by the SMP system to improve scalability is increased. Examples of hardware that supports cache coherency for SMP systems may include modified, exclusive, shared, invalid; MESI snoop protocol, which is used for tables. A shared bus on the PC and achieved by inexpensive hardware; and a directory-based agreement for cached coherent, non-uniform memory in large-scale distributed shared memory (DSM) Access (hereafter referred to as "CC-NUMA") and achieved by expensive hardware that integrates the inter-node connections of the special 201234180 with, for example, a protocol processor and directory memory. The increase in the number of processors using CC-NUMA leads to an increase in hardware costs, and as a result, the cost performance of multiprocessors decreases as the number of processors: increases. That is, CC_NUMA has low economic scalability. In contrast, because the cluster can be fabricated from standard components, the hardware cost per processor of the cluster is less expensive than the hardware cost of each processor that requires dedicated components of CC NUMA. In particular, if the cluster uses the messaging interface to rewrite the troublesome parallel application with high parallelism, the cluster with constant hardware cost per processor can perform parallel processing on a large scale. Non-Patent Document 1 describes a shared memory technology based on virtual memory (VM), which utilizes a memory management unit (mem〇ry management (hereinafter referred to as "MMU") included in a processor. In the hardware of the SMP system to improve the scalability and cost performance of the SMP system. This technique is applied to the non-cache memory coherence NUMA (hereinafter referred to as "NCC-NUMA" in Non-Patent Document 2). The non-cache memory coherent NUMA can use the same hardware as the cluster hardware. The VM-based shared memory technology handles the cache coherency in the same program, but the VM-based shared memory technology cannot. Handling cache memory gates between different programs 'Because the common use of write copy (C〇py_〇n_Write) technology maps the same physical page to multiple programs to support virtual addresses and manage memory Universal OS, so the data applicable to VM-based shared memory technology is limited to ensuring that the application is not shared by different programs. The cache is coherent. The change of S's clearly indicates that the data with the same virtual address space is shared by multiple processors, and in order to apply the technique to existing software, the application must be rewritten, thus generating Rewriting the additional software costs associated with the application. Therefore, VM-based shared memory technology cannot be applied to general-purpose computers, and the applicability of the technology is limited to specific uses and allows scientific calculations of new design programs. Patent Document 1 describes main memory A shared multiprocessor in which the addition of a small amount of hardware by providing a physical page mapping table eliminates or significantly reduces the need to broadcast TLB cleanups to control tlb consistency when rewriting page tables, and eliminates Or significantly reducing the traffic in the bus in the pipeline and the node and the pipeline staii associated with the TLB clearing. Patent Document 2 describes responding to a data transfer instruction (such as the M〇v instruction). Ability to access content addressable memory (such as cache memory (CACHE-M) or address translation buffer (TLB)) and invalidate the project Operation Patent Document 3 describes the introduction of a software to refer to a person's person's bottle, such as an address conversion pair, so that the conversion information can be inserted via the software, and the page fault handler can convert. The information is inserted into the page of your king's face-only directory and the information is inserted into the TLB, and the break-up is completed after the implementation of the page error processor routine 'when the next offer is the same; % When the T-wet address is located, there is no TLB missed and a TLB hit occurs. Citation List 201234180 _ Patent Literature [Patent Document (PTL) 1] Unexamined Patent Application Publication No. 2000-67009 [Patent Document (PTL) 2] Unexamined Patent Application Publication No. 8-320829 [Patent Document (PTL) 3] Unexamined Patent Application Publication No. 62-3357 - Non-Patent Literature (NPL) 1] Cache Coherence for Shared Memory Multiprocessors B from Karin Petersen and Kai Li, Newport Beach, April 1993, at the 7th International Parallel Processing Workshop of CA, Pages 1 to 18. Ased on Virtual Memory Support »" _ [Non-patent Literature (NPL) 2] "Shared Memory Computing on Clusters with Symmetric Multiprocessors and System Area Networks" by Leonidas Kontothanassis et al., ACM Computer Systems Journal (TOCS), August 2005 'No. 3, Vol. 23, pp. 301 to 335. [Technical Problem] Therefore, the object of the present invention is to achieve an increase in the scalability of a shared memory multiprocessor system and The cost-effectiveness of the cache can be improved while retaining the cost of the lower hardware and software. The objectives of the 201234180 invention include providing methods, systems, and program products for achieving coherent control of the cache memory. It is also an object of the present invention to achieve this cache memory coherence control via the use of an inexpensive hardware configuration. The object of the present invention further includes achieving the cache coherency control via software that is transparent from the application (i.e., without rewriting the application). Solution to Problem According to one embodiment of the present invention, a method for controlling coherency of a cache memory controls a cache coherency of a multiprocessor system in which a plurality of processors share system memory, the plurality of processors Each of the processors includes a cache memory and a TLB. When one of the plurality of processors processes Is to determine that the TLB interrupt does not occur, the method includes: when the registration information with the matching address exists in the TLB, the step of performing the T]LB missing exception via the processor The processing step processes the TLB interrupt as a TLB miss interrupt or when a registration information having a matching address exists in tlb but the authority is invalid. 'The storage exception processing step is performed via the processor, and the processing step processes the TLB interrupt as a storage interrupt. . The missing abnormality step may include the following steps: clearing the data of the cache memory, the cache memory line, the data of the cache memory, the cache memory line belongs to the physical page covered by the project, and when the coffee replacement is performed, The sacrifice project was evicted and discarded. The TLB missing exception processing step or the sub-anomaly processing (4) may include the following steps: determining whether the cause of causing a coffee leak or a storage interruption is to access the tTW port as a data access or an instruction fetch, and the decision (4) memory Body silk for data storage, to the plus 10 201234180

The entity page covered by the object provides the right to write, read, and execute. The TLB item is replaced or updated in conjunction with an access with a mutually exclusive constraint that excludes the physical page in the TLB of the other processor. Access Rights 0 Preferably, the step of providing permission to write, read, and execute with mutually exclusive constraints may include the steps of: providing processing steps with write, 4 fetch, and execute permissions with write invalid constraints . The step of providing the write, read, and execute permissions with write invalid constraints may include a mesi simulation processing step that provides permission to write, read, and execute with the constraints of the # MESI agreement. Preferably, the MESI analog processing step may include the steps of: determining whether the memory access is a data writer or a data read, and # determining whether the memory access is an entity that is accessed in the judgment when the data is read. The page read attribute is set to on, and the TLB directory memory retains the registration information of the TLB of the plurality of processors, Β Β 记 (4) 寻 find the physical page of the access and determine whether the tlb of the other processor has Permission to the physical page of the accessed entity. When the other processor has the write permission, the cleanup command is notified to the other processor via the interprocessor interrupt and the other processor clears the access limit and clears the directory memory. Others in ;; the write attribute of the silk physical page. The step of causing other processors to clear the permission to write to the accessed physical page may include the following steps:, === 复制 复制 复制 回 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且Write attribute. 201234180 Preferably, the MESI analog processing may include the following steps: when determining that the memory access is data writing, setting the physical page of the access in the processor tlb and the writing attribute to the TLB directory memory to Enable 'search for the physical page of the access in the TLB directory memory and determine whether the TLB of other processors has the right to read, write or execute the physical page of the access' when deciding that other processors have written to the physical page When entering, reading, or executing permissions, the inter-processor interrupt will clear the command to other processors and cause other processors to clear the read and execute permissions on the accessed physical page' and clear the tlb directory memory. The steps of reading, writing, and executing the physical page of the access of the TLB of other processors are the steps of the other processor to clear the right to read, write, and execute the accessed physical page. The following steps: causing other processors to copy and cache the data cache memory and invalidate, and disable the read and write of the physical page accessed in the TLB of other processors . Preferably, the TLB miss exception processing step or the storage exception processing step may include the steps of: determining whether the memory access causing the TLB miss interrupt or the storage interrupt is a data access or an instruction access, when determining the memory access as an instruction When accessing, 'determines whether the item in the page table in the system memory has the user write permission of the entity page generated by the instruction fetching ·^^ omission interrupt, when determining the item in the page table has When the user writes the permission, 'the KB of the other processor is determined to have the permission of the user to write to the entity page, and when the TLB of the other processor is determined to have the user's permission to write the user, via the processor 12 Interrupts between 201234180 notify the other processors of the cleanup command and cause other processors to clear the user write permission. When it is determined that the TLB of the other processor does not have the user write permission or after the step of causing the other processor to clear the user write permission, the TLB miss exception processing step or the storage exception processing step may include the following steps: The instruction cache memory of the accessing processor is invalid. The TLB Missing Exception Handling Step or the Storing Exception Handling Step may include the following steps when it is determined that the item in the page table does not have the user write permission or the step of invalidating the instruction cache memory of the processor that is accessed; : The execution attribute of the entity page generated by the instruction extraction in the TLB of the processor that accesses the TLB miss interrupt is set to ON, and the TLB directory memory retains the registration information of the TLB of the plurality of processors. Preferably, the MESI analog processing step may further comprise the step of: performing sequential access using the flag when searching for the TLB directory memory of the accessed physical page. With one embodiment of the present invention, a computer program product for cache coherency control is provided that causes a processor to perform each of the steps described above. According to another embodiment of the present invention, the system for controlling the coherency of the cache memory controls the cache coherency of the multiprocessor system, and the plurality of processors in the multiprocessing system share the system memory, the complex number Each of the processors includes a cache memory and a TLB. Each of the processors further includes a TLB controller including a tlb search unit and a coherent processor, the TLB search unit performing a TLB search 201234180 seek, and the coherent processor is not in life when the TLB search command is TLB registration information processing is performed when TLB_break occurs. The coherent processor includes a TLB replacement processor, a TLB missing exception handling unit, and a storage exception handling unit TLB replacement processor that searches the system memory for page tables and performs replacement on the TLB registration information. When the TLB_break is not a page fault, when the registration information with the matching address does not exist in the TLB, the TLB missing exception handling unit processes the TLB interrupt as a TLB miss interrupt, and when the registration information with the matching address exists Tlb _ When the access authority is invalid, the storage exception handling unit processes the TLB assertion as a storage interrupt. The TLB Missing Exception Handling Unit can clear the data of the cache memory. The cache memory line of the cache memory is the physical page covered by the victim 纟TLB project, #execution; The victim TLB project was evicted and discarded. Then each of the missing exception handling unit and the stored exception handling unit can determine whether the money access to the TLB missed or interrupted is (4) access or access 7 and 'when determining memory access is When accessing data, the entity can be written, retrieved, and executed by the entity covered by the TLB project. The TLB project is replaced with an access with a mutually exclusive constraint to replace or update the mutual The exclusion constraint excludes access to the physical page in the TLB of the other processor. Each of the TLB Missing Exception Handling Units, the Quaternary Storage Exception Handling Unit, can determine whether the memory access for the TLB miss in the wear or storage interrupt is a data access or an instruction access. When the memory access is an instruction access, it can determine whether the item in the page table in the system memory is 14 201234180. There is a user write permission for the physical page generated by the instruction and the TLB miss interrupt is generated. When the item of the shirt has the user write permission, it can be determined whether the TLB of the other processor has the permission to write to the user of the physical page, and when the TLB of the other processor is determined to have the user's writer When permissions are granted, the 'monthly commands' can be notified to other processors via interprocessor interrupts and cause other processors to clear the user write permission. The system for controlling the coherency of the cache memory may further include a directory memory that retains registration information for the TLBs of the plurality of processors and searches for the physical pages in the directory memory by the plurality of processors. Preferably, the multiprocessor system may include a plurality of nodes, each of the plurality of nodes may include a plurality of processors, system memory, and TLB directory s memory and flag processor, the system memory via The coherent shared bus is connected to a plurality of processors for sequentially accessing the TLB directory memory by a plurality of processors using the flag, and the TLB directory memory and the flag processor are connected to the coherent shared bus via the bridging mechanism. . The plurality of nodes can be connected to each other via the NCC-NUMA mechanism. Advantageous Effects of Invention With the present invention, it is possible to achieve a cache memory coherent control which enables an increase in the scalability of a shared memory multiprocessor system and which can be improved in cost performance while retaining the cost of a lower hardware and software. Specifically, a method for implementing the coherency control of the cache memory, a system 15 201234180 and a program product 'the cache coherency control can be achieved by using a software with a cheap hardware configuration, and the cache memory is coherent Control can be achieved without rewriting the application. [Embodiment] The best mode for carrying out the invention will be described in detail below with reference to the drawings. The following examples are not intended to limit the scope of the invention, and all combinations of the features described in the embodiments are not required to solve the problems. The invention may be embodied in many different forms and should not be construed as being limited to the embodiments disclosed herein. Identical parts and elements have the same element symbols throughout the description of the embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a multiprocessor system 100 that can be used to achieve cache coherency control in accordance with the present invention. The multiprocessor system 100 includes a plurality of processors 101, a memory bus 1 〇 2, and a system memory 103. The processor 101 is connected to the system memory 103 by a memory bus 〇2. Each of the (four) 101 includes a CPU 104, an MMU 105, and a cache memory 1〇6. MMU 1〇5 includes TLB 1〇7. The cache memory 1〇6 in the processor 101 holds the contents of the system memory 1〇3: part. For an SMP system such as a multiprocessor system, the processor 101 can read information from the system memory 并且1〇3 and write the data to the system memory, and needs to make the system memory 丨03 and the cache memory. The information and instructions in 106 are the same. Preferably, system memory 103 can have virtual page 16 201234180 address effectively mapped in system memory 1() 31 with page table 108β by using a plurality of items, ie, fragments of registration information in page table 108. To the physical address in system memory t. The system memory 103 includes a memory controller 1〇9 and exchanges and stores information related to the external storage device 12Q connected to the system memory 1G3, and also stores the information and stores it to the outside. Device 120 writes information. Each of the processors 101 can convert the virtual address in the instruction or data into the system memory 103 by copying the information contained in each of the items in the page 〇8 using the TLB 107. Physical address. Since TLB 1〇7 provides address information in the memory space, it is important to maintain the coherence between TLBs 1〇7 in multiprocessor system 100 in order to ensure proper operation of TLB 1〇7. Figure 2 is a block diagram showing a processor block having a cache memory coherent control system in accordance with one embodiment of the present invention. The cache memory 106 of the processor i 指令 includes an instruction cache 丨〇6, and a data cache memory 106". The processor 101 is connected to the TLB directory memory m, and all of the processors 1 can access the TLB directory memory 121 except for the 5 memory bus 102. The TLB directory memory 1S1 is one of copying information such as a physical page number, read/write/execute access authority, and valid state held in the TLB 107 of all the processors 101 and mapping the copied information. The global address can be referenced by the CPU 104 of all the processors 101, so that the local end processor 101 can check the TLB of the remote processor 101 without interrupting the inter-processor interrupt to the remote processor 101. 107 content. Each of the CPUs 104 has an operation mode (user mode) for executing an application program (AP) process 122, an operation mode 17 for executing the OS core process 124, and a management mode (administrator 桓10, ,,) Execute the operating mode of the interrupt handler. The coherent processor 126 is executed in a second mode from > The TLB controller 123 includes a TLB search unit 12s R _ and a coherency processor 126 for accessing the cache memory when the AP process 22 accesses the cache memory ι 6 or when the 〇 s core 24 accesses the cache memory The TLB search is performed at the time of the body 106, and the coherency processor 126 is configured to perform the registration information processing of the TLB 1〇7 when no interruption occurs in the search and an interruption occurs. The coherent processor 126 is external to the OS core processing 124 for processing page faults, as shown in FIG. TLB S Λ ^ r-. The first 125 includes the cache memory tag search unit. The 7 J. capture 5 recall tag search unit (7) is used to search for the cache tag in the middle of the search. When the cache memory tag is searched for in the middle of life, the cache memory search list is shown 127. The process 122 accesses the cache memory 1 () 6. When the cache memory tag is missing in the cache memory, the cache memory tag search unit 127 instructs the Ap process 122 not to access the cache memory 106' and access the system memory. 1 〇 3. The coherent processor 126 includes a TLB replacement processor 128, a missing exception processing list 70 129, and a storage exception processing unit 13G. The TLB replacement processor 128 includes a page table search unit 131 and a page fault decision unit 132. In the case where the TLB interrupt is found by the TLB search unit 125, the page table search unit 131 performs a search on the page table ι8 in the system memory 1〇3. The page error determining unit 132 determines whether or not a page fault has occurred by the search performed by the page table search unit. When the page fault decision sheet 18 201234180 decides that the free page table search unit 131 is executed, that is, the search for the stub is not page fault tlb m * when the page exists in the page table 108, the TLB misses the exception processing line coherency control. In the case where the two-time processing unit 130 is in the page table 108 and there is no one hundred months, a page fault occurs in the next TLV project page, and a TLB interrupt is not found in the TLB search, wherein the matching address item (ie, registration) Information) The situation that does not exist in the TLB is called "TLB Missing Interruption", and the item matching the address (that is, the registration information) exists in (10), but the access authority is invalid (4) "Storage towel break ^ Then, the missing exception processing unit 129 processes the TLB miss interrupt, and the storage exception processing unit 130 processes the storage interrupt. Because coherent processor 126 performs coherent control when no page faults occur, this technique differs from VM-based shared memory technology, which performs coherence when a page fault occurs. The 〇S core processing 124 includes a memory management unit Π3. When the page fault determination unit U2 performs a search decision page 3 face error by the page table search unit 131, the TLB replacement handler 128 generates a page fault interrupt and the memory management unit 1:33 of the OS core process 124 processes the page error 0 coherence. The TLB Missing Exception Handling Unit 129 and the Store Exception Handling Unit 130 of the processor 126 perform coherency control such that only the physical address registered in the TLB 107 in the local side processor 101 remains in the cache memory 106. Therefore, when the coherent processor 126 performs the TLB replacement, the overlaid page covered by the TLB item (which will be eviction and discarded as a victim) will be cleared, that is, the self-cache memory is copied back to the memory. (copied back) and invalidated. In addition, the read/write/execute permission (ie, registration information) of the physical page covered by the added tlb item is mutually exclusive, and the mutual exclusion constraint is excluded from the TLB 107 of the remote processor 1〇1. The access rights of the physical page. Examples of mutually exclusive constraints include write invalidation, specifically, the constraints of the MESI protocol. The MESI protocol is classified as a coherent protocol that writes invalid types. There are also write update types. Both types are available. The constraints of the MESI Agreement are described below. If you add this constraint, you don't need to handle the coherence until a TLB miss occurs. Because VM-based shared memory technology mutually exclusive caches logical pages held in page tables, this technique cannot resolve cohomology if the same physical page is mapped to a different logical page. When the TLB project, ie, the registration information is replaced, that is, when the Tlb miss interrupt and the storage interrupt are replaced or updated, the read/write/execute authority conforming to the MESI agreement is provided. For processors that are searched by the hardware-assisted page table, the TLB is only one of the cached page tables, and the cache coherency control is shown in Figure 2 for the use of the software-controlled TLB. The access-only access is set in TLB 1 〇 7, which corresponds to the mutual exclusion constraint from the mesi protocol in the access rights recorded in the page table. Therefore, the access rights recorded in the TLB 107 are the same as the access rights recorded in the page table 8 of the system memory 1 〇 3 or the access rights to the access rights. For TLB miss interrupt or storage interrupt, local processor I. The search for the TLB project (that is, the registration of the remote processor 需要1 20 201234180) is required to reference the TLB directory memory to conform to the mutual exclusion constraint of the meSI protocol. In order to prevent the plurality of processors 101 to synchronously update the TLB directory memory 121, it is preferable to use the order of the flag for accessing the TLB directory memory 1; The TLB directory memory 121 can preferably be implemented by a content addressable memory (CAM). For CAM, the search word containing the physical page number and the read/write/execute access permission bit and its search processor ID and TLB item number are the address input of the CAM. The bus used in the CAM access may preferably be a bus that is independent of the memory bus and dedicated to the CPU. Examples of the bus bar include a device control register (DCR) bus. Figure 3 is a schematic diagram showing the configuration of the TLB directory memory 121. The tlb directory memory 12 1 retains the item (ie, the registration information in the processor i) to allow each of the processors 1〇1 to track the item without interruption between processors (also That is, the registration information of the TLB 107 of other processors). Controlling the cache memory so that only pages of the item (i.e., registration information registered in tlb of each of the processors 1〇1) are cached, thus causing pages in each cache memory The state of use can be determined by searching for the TLB [〇7]. The TLB directory s-resonance 121 is mapped to the global address space to allow all processors 101 to access the TLB directory memory 121. Each item in the D-LB directory memory 121 includes valid status information 300 indicated by vs (active status), physical page number information indicated by pPN (physical page number) information 3〇1, and R/W/Ep (read Fetch/Write/Execute Protection) Indication 21 201234180 Read/Write/Execute Access Rights Protection Information 3 02. This information is the information that is reproduced from the corresponding information in the TLB 107 of all processors 101. At the left end, the address of the TLB directory memory 121 formed by the combination of the processor ID and the TLB item number is indicated; at the right end, the group corresponding to the items of the processor 0 to the processor N is indicated. The TLB directory memory 121 is used to search for the physical page number in the TLB 107 of the processor 101, thus enabling coherency in different programs to be processed. Preferably, the TLB directory δ mnemonic 121 can be implemented more quickly by the CAM to achieve the next two search operations: one search operation is to search for a matching page number and has a write permission page, and another search The action is to search for pages that match the physical page number and have read, write, or execute permissions. In the search, the search input word of the CAM contains the physical page number and permission to access the page' and the input in which the processor ID is connected to the TLB item number is input in the address input of the CAM. A bus that is occupied by the processor, such as a DCR bus, is suitable for the bus for accessing the cam. Fig. 4 is a flow chart (4A) schematically showing a method for controlling coherency of a cache memory according to an embodiment of the present invention. This method can be achieved by the processor ιοί, the TLB of the processor 10 is controlled via software, as shown in Figure 2. The program starts when the application accesses the cache memory (step 4 is completed) and the processor 101 performs the TLB search (step 4〇2). When the lifetime is in the TLB search, the processor 1〇1 searches for the memory tag of the hit tlb. item (step 4〇3). When a command day occurs in the cache memory tag search, the processor 101 indicates an access to the cache memory and access to the cache memory (step 404). In the winter memory tag search, there is no life in the cache memory: the standard: When the processor is missing, 'processor 1 () 1 indicates access to the system memory and: access to the system § memory (step 4〇 5). When the TLB interrupt is not generated in the search, step 402), the TLB interrupt is taken (the ι step 1 determines whether the TLB interrupt is a page fault (step 406). When the decision - the TLB interrupt is not a page fault, that is, (4) The page of the project (ie, the note) exists in the page table ("No" in step 4〇6). The processor 1CH uses the coherent processor to perform TLB miss exception handling or storage: the subroutine of exception handling ( When the TLB interrupt is determined to be a page fault ("YES" in step 406), the processor ι〇ι generates a page fault interrupt and uses the subroutine of the memory page error handling of the 〇s core processing (step early) Reading Figure 5 is a flow chart illustrating the eviction process for the victim TLB project () The victim TLB project is also missing from the tlb of the coherent processor: normal processing and storage exception handling (see Figure 4) Step 4〇7): Registration information in the ten formula. KB omission by the coherent processor “The subroutine of the processing begins with the entry of the tlb omission exception processing (step 5〇1), and the storage exception of the coherent processor The handling of the child's routine begins with Store exception handling (step 502). For TLB miss exception handling 'because the $ mesh (ie registration information) of the unmatched address exists in the TLB, the processor 101 performs the LB replacement of the imported matching item, and will also register the information from Page 1〇8 is imported to TLB 1〇7 (step) At this time, the TLB directory memory 121 update item is also registered 23 201234180 information. When TLB replacement is performed, when _, 仃τ is changed, processor 1G1 is cleared ( Copy and restore and invalidate) Local data is fast. The hidden line, the local data cache memory line belongs to the victim TLB, n, I i LB project (that is, the registration information to be evicted and discarded) The coverage is 1遐 (step 504). This allows only the project (that is, the registration information registered in TT R from 6) to be reliably cached in the local processor, and this is the same The need for control can be determined simply by checking the TLB of the remote processor in the event that the TLB misses the interrupted yarn, and the storage is interrupted. A calf "After step 504, the processor ι〇1 Decided to cause a TLB missed interruption or Whether the memory access of the interrupt is a data access or an instruction access (steps). When it is determined that the memory access is a data access, the processor 1 is cold > ^, and the benefit 1U1 is entered into the MESI. Simulated child

The routine 506 ("the thorns of the L-A" in step 505); and when the memory access is determined to be an instruction access, the processor 1G1 proceeds to the subroutine of the instruction cache memory coherent processing 507 ("Command" in step 5〇5). As briefly mentioned above, for both TLB miss interrupts and store interrupts, when replacing or updating a TLB entry (ie, registration information), it will conform to the mesi for mutual exclusion constraints (eg, write invalid) as described below. The protocol read/write/execute permission is set between the local end TLB and the remote TLB. • Shared Read-Only Data A number of processors can share reads and execute permissions on the same physical page. If a TLB interrupt occurs in the data read or instruction fetch and the remote processor has the right to write to the body page, the IP I notifies the remote processor of the cleanup command and causes the remote processor to clear the other Entity page write 24 201234180 Access rights. • Mutually exclusive control of written data When a processor has permission to write to a physical page, other processors do not have any kind of access to each page. In other words, the remote tlb does not have any type of access to the physical page that has write access to the local g TLB. Therefore, when the access to the writer is caused by an interruption or a storage interruption, the remote TLB is checked to determine whether the remote processor has access to the physical page; if the remote processor has the access authority, The IPI is used to enable the remote processor to clear the physical page data from the remote cache. Fig. 6 is a flow chart (6〇〇) of the MESI simulation process in an example in which the MESI agreement is imposed by the software control. When it is determined in Fig. 5 that the memory access is data access (in step 5〇5), the processor 101 proceeds to the sub-routine 5〇6 of the MESI analog processing and starts the processing (step 601). First, the processor 101 determines whether the erroneous access causing the TLB interrupt is a data write or a read (step 6 〇 2). When it is determined that the error access is data reading, the processor 101 uses the user-only read (UR) and the administrator-only read (SR) of the page table entry (PTE) in the page table 1-8. The bit masks the read (R) attribute of the item (ie, the registration information corresponding to the erroneously accessed physical page in the local TLB and TLB directory memory 121), and reads (R) The attribute setting is turned on (step 603). The processor 〇1 searches the TLB directory memory 121 for the erroneously accessed physical page and determines whether the remote tlb has the right to write (W) to the physical page (step 6〇4). When it is determined that the remote end 201234180 TLB does not have the right to write (W) ("No" in step 6〇4), the processing ends (step request).胄 When the remote TLB has the permission to write (5) (YES in step 6〇4), the processor 1〇1 processes the H notification cleanup command via the Ιρι and causes the remote processor to clear the write to the physical page. Human authority. That is, the remote processor copies the data cache memory back to the memory and disables the write (W) attribute of the entry (i.e., the registration information corresponding to the physical page in the remote TLB) (step 6-6). The transition from logical to physical address is left in the project in the remote TLB. Subsequently, the processor 101 clears the w attribute of the item (ie, the registration information corresponding to the physical page of the remote TLB in the TLB directory memory 121) (step 607), and the process ends (step when deciding (in step 602) When the error access is write, the processor 1〇1 is written by the user of the page table entry (PTE) in the page table 108 (UW) and the administrator writes (sw) the bit. The write (w) attribute of the item (ie, the registration information corresponding to the erroneously accessed physical page in the local end TLB 107 and the TLB directory memory 121) is hidden and the write (W) attribute is set. Turning on (step 609). Then, the processing benefit 101 searches for the erroneously accessed physical page in the TLB directory memory 121 and determines whether the remote TLB has read (R), write (W) or execute on the physical page ( X) authority (step 610). When it is determined that the remote TLB does not have the right to read (R), write (W), or execute (X) ("NO" in step 610), the process ends (step 605) when determining that the remote TLB has the right to read (R), write (W), or execute (X) (step 610) In the case of "Yes", the processor 101 indicates the clear command to the remote terminal 201234180 via the IPI, and does not provide access to the physical page to the remote device. The end processor clears the physical page data from the remote cache memory, that is, the remote processor copies the data cache memory back to the memory and invalidates it, and uses the device.

The R, W, and X attributes of R, Wn, and Bed's (e.g., corresponding to the registration information of the physical page in the remote TLB) are not used (step 611). The conversion from logical to physical address remains in the project in the remote location. Subsequently, the processor HH clears the RW and X genre of the item (i.e., the registration information corresponding to the physical page of the remote end in the tlb directory memory 121) (step 612), and the process ends (step 6〇8). ). In this way, a snoop transition (i.e., use of the snoop delete) of the read writer execution authority is set by constraining according to the MESI agreement. The decision step of restricting the occurrence of a broadcast snoop request is added, and the physical page covering the data may also be registered in the far case. The decision step is a problem when the Mesi agreement is implemented via hardware. Therefore, the MESI analog processing applied by the software control can be more scalable than the hardware-implemented MESI protocol. With the coherent processor of the cache coherency control according to an embodiment of the present invention, the coherence between the data cache and the coherence between the instruction cache and the data cache can be used. Get control. This is accomplished by invalidating the instruction cache memory line when the instruction fetch for the writable person page with the permission of the writer permits the TLB miss interrupt. Similar to Linux, in order to support, for example, a dynamic link library, the instruction cache needs to be co-located with the data cache. For 27 201234180

Linux only needs to invalidate the instruction cache when extracting a writable page in user space. Figure 7 is a flow chart showing the coherent processing of the memory of the instruction cache via software control (7〇〇). When it is determined in Fig. 5 that the memory access is an instruction access (in step 505), the processor 101 proceeds to the subroutine 507 of the instruction cache coherency processing and starts the processing (step 701). First, the processor 101 determines whether the PTE of the page table 108 has a write permission to the user of the physical page that caused the TLB miss interrupt to be generated by the instruction fetch (step 702). When it is determined that the PTE has the user write permission ("YES" in step 702), the processor ι〇1 determines whether the remote TLB has a write permission to the user of the physical page (step 703). When it is determined that the remote TLB has the user write permission ("YES" in step 703), the processor 110 indicates the cleanup command to the remote processor by the operation and causes the remote processor to clear the user write. Permissions. That is, the remote processor provides a data cache block store (dcbst) instruction for the data cache memory, stores the data cache memory line, and disables the w attribute in the remote TLB ( Step 704). The conversion from logical to physical address remains in the project in the remote TLB. Then, since it is determined in step 7〇3 that tlb does not have the user write permission (NO in step 7〇3), the processor ιοί is invalidated by the instruction cache memory class (instructi〇) n cache congruence Class invalidate; ". The local command cache memory is invalid (step 705). Subsequently, since it is determined in step 7〇2 that the PTE does not have the user write permission (step 7〇2) 28 201234180 "No"), processor 101 is executed by a user of the page table entry (PTE) (UX)

And the administrator executes (SX) bit open: A, M疋 hides the item (that is, corresponds to the physical page corresponding to the instruction in the local end TLB 107 Ά TLB ^ red ^ 13 directory C memory 121 to generate a TLB miss interrupt. The registration information) executes the (8) attribute and sets the execution (X) attribute to ON (step by step). Processing then ends (step 707). The TLB directory is a sequential access using the flag. This protection protects the TLB directory 3! 2 i is free from multiple treatments for stomach cramps and updates. The first is how to use the flag for the process of entering and exiting the coherent processor (800). The entry into the coherent processor is the processing start (step 801), the acquisition of the flag (step 8〇2), and the end of the process (step 803) » the exit to the coherent processor is the process start (step 804), providing the banner Notifying (step 8〇5), and processing ends (step 806), although the entire tlb directory memory 121 can be accessed by a single flag, in order to enhance the scalability of each of the plurality of processors and allow It is preferred that the processors simultaneously access the TLB directory memory 12 1 'and divide the flags to form a plurality of flags and assign the flags to the respective groups into which the physical pages are divided. For example, although the number of the page numbers is divided by S, the remaining number system is the flag 丨D, forming the s flag 5 tiger' and the divided physical pages are independently protected for each group. At this time, the following relationship is satisfied: Flag ID=mod (physical page number, S) where mod(a,b) represents the remainder when a is divided by b. Right apply this concept to numa (numa is distributed Chuanxiang memory 29 201234180 system charge) shell! Different RANA nodes can be assigned different flags. Only when remote access is performed can the remote TLB directory memory be referenced and the flag can be obtained; otherwise, the local TLB directory memory can be referred to and the flag can be obtained. For NUMA systems, the allocation of processor and physical memory operations is optimized such that the frequency of access to the local system memory is higher than the frequency of access to the remote system memory. For the application of the NUMA system, it is preferable to distribute both the TLB directory memory and the flag to the NUMA node. The distributed TLB directory memory records the local page number of the local system memory, and the ID of the processor that caches the local end system memory and the distributed flag protects the corresponding distributed tlb directory memory. Therefore, the remote TLB directory memory and the remote flag are referenced only when remote access occurs. Only local-side TLB directory memory and local-end flag can be used to handle other local-side access. The cost of co-ordinated support by hardware is lower for access to local system memory 'but the cost is higher for access to remote system memory. To solve this problem, a cheap snoop bus can be used for accessing the local end system memory and the cache coherency control according to the present invention is used for accessing the remote system memory, and is suitable for SMP and NCC-NUMA in an extended hybrid system. In other words, the hardware-assisted homology is used for accessing the local end system memory and the cache coherency control according to the present invention is used for accessing the remote system memory, and the overall coherent shared memory can be configured. Multiprocessor system. Figure 9 shows an example of a hybrid system that extends to SMP and NCC-NUMA. It has a multi-processor system. Each node includes a plurality of processors 901, system memory 903, & TLB directory memory 905 and flag processor 9〇6, the system memory 9〇3 is shared by the coherent bus (ie, shared bus) The coherent SMP 902) is coupled to the processor 〇1, and both the TH TLB directory memory 〇5 and the flag processor 〇6 are connected by the bridging mechanism 904 to the shared bus coherent SMP 902. A flag processor 906 is provided to allow a plurality of processors 9() 1 to sequentially access the TLB directory memory 〇5 by a flag. The nodes are connected to each other by the *ncc numa mechanism 9G7. Since the nodes are connected to each other by the inexpensive ncc numa mechanism 907, the shared memory multiprocessor system _ can increase the number of nodes, i.e., can improve scalability while preserving the cost of lower hardware. The number of items in the right TLB directory memory is not limited and the local system memory and the remote system memory are freely associated, and the size of the TLB directory memory is increased in proportion to the number of processors. For example, if 1024 are. Each of the processing states has a TLB of 1 24 items and 1 js η Λ items are 4 bytes, and the size of the tlb directory memory is calculated as 4 " (1024 processors, *〆,.~, ,15; (1024 items)* (4 bytes) called

In order to reduce the size of the TLB directory memory, for example, as shown in the first figure, if the system is applied to the NUMA system, it is allocated to the remote system memory (RSM) by each processor 1〇01. The number of TLb items 1 〇〇 2 for rSM is limited to the limit, and the remaining TLB items are used as the TLB project 1003 for lsm assigned to the local end system memory (LSΜ) by 31 201234180. The local-side TLB directory memory for the LSM includes the TLB directory replication project from the remote processor (RP), the number of restricted TLb entries', and the local-end processor (LP) that allocates the remaining TLB entries. The TLB catalog replicates the items and can reduce the size of these items and the number. Specifically, where the number of NUMA nodes is N, the number of TLB items per CPU is E' and the number of items assigned to the remote system memory from the tlb item is R, assigned to the local knowledge system § Recall The number of TLB items is, and therefore, the number of items of TLB directory memory per node is reduced from e*n to (N-1)*R+1*(ER). For the above example, when a 1024 値 processor is distributed to 256 NUMA nodes and a 4-way SMP structure is used for each node, if the number of TLB entries allocated to the remote TLB is limited to 16 ', then the TLB directory memory is The size is calculated as 8 i 4 KB by: (1020 processors) (16 items)* (4 bytes) + (4 processors)* (1008 items)* (4 bytes) = 8 1.4 KB When implemented on CAM, in the case of 45 nm semiconductor technology, the area required for the TLB directory memory is only 1 mm2 u as described above 'When performing the software-based cache memory according to the present invention In coherent control, 'because the shared memory multiprocessor system can be formed from inexpensive components such as general purpose components, the hardware cost can be controlled to the extent equivalent to the cluster' and the scalability can be improved. Search for small-scale TLB catalogs that only manage TLB information for each processor on the physical page. 32 201234180 Replica can handle multiple programs and eliminate the need to change applications, thereby improving scalability without additional software costs. Shrinkage. The invention has been described above to use embodiments. However, the technical scope of the present invention is not limited to the scope described for the embodiments. Various changes or modifications may be added to the embodiments, and modes having such changes or modifications may also be included in the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a multiprocessor system that can be used to achieve cache coherency control in accordance with the present invention. Figure 2 is a block diagram showing a cache memory coherent control system in accordance with one embodiment of the present invention. Figure 3 illustrates a schematic configuration of the TLB directory memory. Figure 4 is a flow diagram of a method for controlling coherency of a cache memory in accordance with one embodiment of the present invention. Figure 5 is a diagram of the TLB missing exception handling and storage exception handling performed by the coherent processor. ^ ^ ? ^ ^

The flow chart of the eviction process of the victim TLB project in the parent of the child. Fig. 6 is a flow chart showing the MESI simulation processing in the subroutine of each of the missing exception processing and the storage exception processing by the coherent processor. Fig. 7 is a flow chart showing the processing of the coherency processing of the instruction cache in the subroutine of the T) missing exception processing and the storage exception processing in the p] outline processing machine. 33 201234180 Figure 8 shows how to use the flag for the process of entering and exiting the coherent processor. Figure 9 illustrates a schematic configuration of a coherent shared memory multiprocessor system extending to a hybrid system of SMP and NCC-NUMA. Figure 1 illustrates the schematic configuration of the local end TLB directory memory of the LSM. [Main component symbol description] 100 multiprocessor system Γόι processor 102 memory Γ 03 system memory 104 CPU ' -- one T05 MMU 106 cache memory "06 ' ^ to make cache memory 106 " data cache memory _body 107 TLB 108 page table 109 memory controller 120 external storage device 121 TLB directory memory 122 application (AP, processing 123 TLB controller 124 〇s core processing 125 TLB search unit 126 coherent processor 127 cache memory Body Tag Search Unit 128 TLB Replacement Processor 129 TLB Missing Exception Handling Page 7L 130 Storage Exception Handling Unit 131 Page Table Search Single Tile ~~~~~' 132 Negative Error Determination Unit 133 Memory Management 300 Valid Status Information 301 Entity Page !! 302 Capture/Write/Execute Access Rights Protection Information 4〇〇----. Flowchart 401 Step 402 403 404 Step 405 Step 406 #骤~ 407 408 Step - 500 Flowchart 501 Step ~~~ 502 503 Steps ~~~~~~ 504 Step 505 Step ~ 506 Winter 507 Sub-Function ~~~ 34 201234180 600 Flowchart 601 Step 602 Step 603 Step 604 Step 605 Step 606 Step 607 Step 608 Step 609 Step 610 Step 611 Step 612 Step 700 Flowchart 701 Step 702 Step 703 Step 704 Step 705 Step 706 Step 707 Step 800 Flow 801 Step 802 Step 803 Step 804 Step 805 Step 806 Step 900 shared memory multiprocessor system 901 processor 902 shared bus coherent SMP 903 记忆 memory 904 bridging mechanism 905 TLB directory memory 906 flag processor 1000 local end TLB directory memory 1001 processor 1002 TLB project 1003 TLB project 35

Claims (1)

201234180 VII. Patent application scope: 1. A method for controlling the coherency of a cache memory of a multiprocessor system. In the multiprocessor system, a plurality of processors share a system ticker in the plurality of processors. Each includes a cache memory and a conversion lookaside buffer (TLB), the method comprising the steps of: when one of the plurality of processors determines a non-page fault - the interrupt occurs in a TLB search When a step of processing a TLB miss exception is performed by the processor, the processing step is to process the TLB interrupt as a coffee miss interrupt; or when the occurrence of the match information with the matching address exists in the coffee but access When the permission is grayed out, it is executed by the processor - the storage exception processing step is performed: the TLB interrupt is processed as a storage interrupt. Step 2 of the TLB Missing Exception in V. The method of claim 1 - ψ ^ ^ , 3⁄43⁄4 includes the following steps: · Clearing - the data of the cache body is cached, the memory of the cache The data is only as fast as the δ 忆 体 体 体 line belongs to a TLB project - entity $ victim TL ... line (four) when the victim TLB project is evicted and discarded. 3. According to the method disclosed in claim 2, the step B of the exception processing step of the B-legged exception processing includes the following steps: Deciding to cause the TLB missed interruption or the memory access of the cultivating cultivator to be 36 201234180 material access or instruction access; and when determining that the memory access is the data access, providing permission to write, read, and execute an entity page covered by the -TLB project, the TLB project and The access constraint with a mutually exclusive constraint is replaced or updated, the exclusive exclusion constraint excluding access to a physical page in the TLB of another processor, wherein the write, read, and The step of performing the privilege includes the steps of: providing a processing step of writing, a fetching, and executing 5 privilege with a write invalid constraint, wherein the write, read, and This step of performing this privilege includes the step of providing a MESI simulation processing step with the privilege of writing, reading, and executing with the constraints of the MESI protocol. 4. The method of claim 3, wherein the MESI analog processing step comprises the steps of: determining whether the memory access is a data write or a data read; when determining that the memory access is for the data read And a read attribute of the physical page of the access in the TLB of the processor is set to be on, and the TLB directory memory retains registration information of the tlbs of the plurality of processors; Searching for the physical page of the access in the directory memory and determining whether the TLB of the other processor has the right to write to the physical page of the access; when it is determined that other processors have the right to write, Inter-processor interrupt 37. The inter-processor interrupt notifies other processors to a cleanup command and causes other processing|g to clear the permission to write to the physical page of the access; and clear the memory of the TLB directory. One of the edge pages of the access of the TLB of the other processor in the body writes the attribute. 5. The method of claim 4, wherein the step of causing the other processor to clear the authority to write to the accessed page may include the following steps: causing other processors to cache the data The body copy is restored and does not need to be attributed to the S-text of the physical page of the access in the TLB of the other processor. 6. The method of claim 4, wherein the MESI simulation process comprises the following steps: when the § memory access is read for the data, the TLB of the processor is The physical page of the access and the write attribute of the TLB directory memory are set to be on; the physical page of the access is searched for the TLB directory memory and the TLB of the other processor is determined to have the access The privilege of reading, writing or executing the physical page; when it is determined that other processors have the privilege of writing X, reading or executing the physical page, an interrupt between the processors is notified of a clear command by the inter-processor interrupt . And the other processor clears the permission to read, write, and execute the physical page of the access; and 38 201234180 clears the access to the (four) of the other processors in the TLB directory memory. The read, write, and execute attributes of the physical page, wherein the step of causing other processing to clear the read and execute of the physical page read access to the physical page may include the step of causing other processors to The data cache is copied back and invalidated, and the read, write, and execute attributes of the physical page of the access to the other processor's TLB towel are disabled. 7. The method of claim 2, wherein the TLB miss exception processing step or the storing exception processing step comprises the steps of: determining whether the memory access causing the TLB miss interrupt or the storage interrupt is a data access or an instruction save When determining that the memory access is an access to the instruction, determining whether an item in one of the page tables in the system memory has the physical page that is extracted by an instruction to cause the TLB miss interrupt to be generated. User write permission; when deciding that the item in the page table has the user write permission, 'determine whether the TLB of the other processor has write permission to the user of the entity page; When the TLB of the other processor is determined to have the user write permission, an inter-processor interrupt notifies the other processor of a cleanup command and causes other processors to clear the user write permission. 8. The method of claim 7, wherein 'when determining that the other processor's 39 201234180 TLB does not have the user write permission or after causing the other processor to clear the user write permission, The TLB Missing Exception Handling Step or the Store Exception Handling Step includes the step of invalidating one of the processors instructing the access to the cache memory. 9. The method of claim 7 or claim 8, wherein the determining that the item in the page table does not have the user write permission or the instruction to cause the processor to perform the access After the step of invalidating the cache memory, the TLB miss exception processing step or the storage exception processing step includes the following steps: the TLB in the TLB of the processor that performs the access is extracted to make the TLB miss. The execution attribute of the physical page of the interrupt is set to be on, and the TLB directory memory retains the registration information of the TLBs of the plurality of processors. 10. The method of claim 4 or 5, wherein the MESI analog processing step further comprises the step of sequentially accessing a TLB directory memory using a flag above the search for the accessed physical page.每 Everything executed by the processor. 11 - a computer program product, the computer program product causing - the homology of the steps in the steps of any one of claims 1 to 10, comprising a total of 12 types for controlling a multiprocessor system Cache memory system - one of a plurality of processors in the multiprocessor system, one of the system memory caches and - TLB, 40 201234180, wherein each of the processors further includes a TLB control The TLB controller includes a TLB search unit and a coherent processor, the TLB search unit performs a TLB search, and the coherent processor performs the tlb registration information when the TLB search is not in the life and a TLB interrupt occurs. Processing, the coherent processor includes a TLB replacement processor, a TLB missing exception processing unit, and a storage exception processing unit. The TLB replacement processor searches a page of the system memory and performs replacement on the TLB registration information. When the TLB interrupt is not a page fault, when the registration information with a matching address does not exist in the 9TLB, the TLB missing exception handling unit will process the TLB interrupt. In order for a TLB miss interrupt to occur; and when the registration information with a matching address exists in the TLB but the access authority is invalid, the storage exception handling unit processes the TLB interrupt to generate a memory interrupt. U. The system of claim 12, wherein the missing exception handling unit clears the cache memory-data cache memory line, and the data cache memory of the cache memory belongs to the victim-sacrificial The T£B g-covers the physical page, which is evicted and discarded when the TLB replacement is performed. The system of claim 13, wherein each of the coffee omission exception processing unit and the storage exception processing unit determines to cause a (4) legacy 41 201234180 drain interrupt or the storage interrupt #, the yin M + t break Whether it is a data access or an instruction access. When it is determined that the memory access is the access, the right to write, read, and execute the physical page covered by the - item is provided, and the item is The access constraint with a mutually exclusive constraint is replaced or updated, the exclusive exclusion constraint excluding access to the physical page in the tlb of another processor, or when determining that the memory access is stored for the instruction Determining whether one of the items in the page table in the system memory has a write permission to the user of the physical page that is extracted by an instruction to cause the TLB to be missed; when deciding on the page When the item in the table has the permission of the user to write permission, 'determine whether the TLB of the other processor has the permission to write to the user of the entity page, and when the other TLB is determined to be (4) When the limit by - inter-processor interrupt to a processor and other clean-up command notice and causes other processor to clear the user write permission. 1 5. If you are asking for it! 2 to! The system of any of 4, wherein the system further has a TLB directory s memory, the TLB directory memory retaining registration information for the TLBs for the plurality of processors and the plurality of processors are at the TLB Searching for a physical page in the directory memory, the mid-day processor system includes a plurality of nodes, each of the plurality of nodes including the plurality of processors, the system memory 'and the TLB 42 201234180 The TLB directory memory and the flag are connected to the coherent shared bus, and the directory memory and the flag processor share bus are connected to the plurality of processors with a flag for using the system memory. Coherent coprocessors and the flag processor is configured to sequentially access the TLB directory machine by a bridging mechanism. The plurality of nodes are coherent with non-cache memory, non-uniform memory access (NCC-NUMA) The institutions are connected to each other. 43