201222899 六、發明說明： 【發明所屬之技術領域】 碎寺別是光電組件，及 此 本發明涉及一種電子組件 種組件之製造方法。 【先前技術】 具有半導體晶片之電子組件， β ^ 特別疋光電組件，户 操作時產生熱，該熱使電子組件之效率下降 ^在 較高功率種類之電子組件中，埶管 疋在 【發明内容】 一理將發生問題。 本發明的目的是提供一種電子組件，其 片產生的熱可快速地傳導至基板。 賵曰曰 上述目的藉由具有申請專利範圍第i項 組件和具有中請專利範圍第u項特徵之製 电子 的方法來達成。 電子組件 電子組件之其它形式和有利的佈置以及 製造方法描述在申請專利範圍各附屬項中。 、、的 不同的實施形式具有電子組件，其中半 生的熱可快速地傳導至基板。 aa片產 電子組件具有基板，該基板包括至少—半 曰 接觸層。在半導體晶片_接觸層上配豆曰曰片_ 邋舻曰μ从 且卞守體晶片。在丰 導體曰曰片-接觸層和半導體晶片之面 間配置-具有細孔之連接層。 《接觸面之 半導體晶片-接觸層可以是金屬 /或導埶枓〇 萄滑具有導電性及 “-i t 半導體晶片-接觸層具有金。半導體 曰 層可依據實施形式而以可測量的厚度存在^ 201222899 成為一種厚度幾乎消失的面。 在-較佳的實施形式中’電子組件是光電組 置於光電組件中的主 叶甲的丰導體日日片可以ΙΠ_ν_化合物 材料為主。半導 〇 导體ΒΒ片具有至乂 一發出電磁輻射的活性 區。活性區可以是pn_接面，雙異質結構，多重式量 、、°構（MQW-結構）或單一量子井結構（sqw結構）。量 結構是指：量子养「3、生1 U* ί、 曾 井（3-維）、里子線（2-維）和量子點（1_維）。 ^半導體晶片例如可設計成表面發射器，特別是所謂 :膜晶片，或體積式發射器，特別是藍寶石-體積式發射 薄膜晶片例如由公開文件w〇 2〇〇5〇81319αι中已為 人所知。纟光電組件(特別是具有㈣屬之鏡面層之組件 之製造期間若將半導體層序列之生長基板剝離，則此種 生長基板剝離下所製造的組件亦稱為薄膜 '组件。發 田射之半導體組件具有不同的^·ν_氮化物-半導體層 (特別是氮化鎵-層）之堆愚 ** 曰 隹且。溥層組件以未具備可吸收輻 射對之基板的方式構成， 且反射斋直接細*加在由不同的 Πι·ν·氮化物-半導體層之 β 體上 < 堆豐所構成的GaN-半導體本 藍寶石-體積式發。201222899 VI. Description of the Invention: [Technical Field to Be Invented] The Broken Temple is an optoelectronic component, and the present invention relates to a method of manufacturing an electronic component kit. [Prior Art] An electronic component having a semiconductor wafer, a β ^ special 疋 optoelectronic component, generates heat when the user operates, and the heat causes the efficiency of the electronic component to decrease. ^ In a higher power type electronic component, the 发明 疋】 A problem will occur. It is an object of the present invention to provide an electronic component in which the heat generated by the sheet can be quickly conducted to the substrate.赗曰曰 The above object is achieved by a method having the component of the i-th application of the patent scope and the electron-making having the characteristics of the item u of the scope of the patent application. Electronic Components Other forms and advantageous arrangements of electronic components and methods of manufacture are described in the accompanying claims. Different implementations have electronic components in which half of the heat can be quickly conducted to the substrate. The aa wafer electronic component has a substrate comprising at least a semi-ruthenium contact layer. The soy flakes _ 从 从 从 在 半导体 半导体 半导体 半导体 on the semiconductor wafer _ contact layer. A connection layer having pores is disposed between the surface of the abundance conductor-contact layer and the semiconductor wafer. The semiconductor wafer of the contact surface - the contact layer can be metal/or conductive and electrically conductive and "-it semiconductor wafer - the contact layer has gold. The semiconductor germanium layer can be present in measurable thickness depending on the implementation^ 201222899 becomes a face whose thickness almost disappears. In the preferred embodiment, the electronic component is the main conductor of the main leaf of the photoelectric group placed in the photoelectric component. The solar film can be mainly composed of ΙΠν_ compound material. The body piece has an active area that emits electromagnetic radiation to the first. The active area may be a pn_ junction, a double heterostructure, a multiple amount, a structure (MQW-structure) or a single quantum well structure (sqw structure). The structure refers to: quantum culture "3, raw 1 U* ί, Zengjing (3-dimensional), lining (2-dimensional) and quantum dots (1_dimensional). ^ Semiconductor wafers, for example, can be designed as surface emitters, In particular, so-called film wafers, or volumetric emitters, in particular sapphire-volume-emitting thin-film wafers, are known, for example, from the publication document 〇2〇〇5〇81319αι. 纟Optoelectronic components (especially with (4) genus Mirror When the growth substrate of the semiconductor layer sequence is peeled off during the manufacture of the components of the layer, the component fabricated under the growth substrate peeling is also referred to as a film 'component. The semiconductor component of the field has different ^·ν_nitride- The semiconductor layer (especially the gallium nitride-layer) is a stack of 愚 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 溥 组件 溥 组件 溥 组件 组件 组件 组件 组件 组件 组件 组件 组件 组件 组件 组件 组件 组件- GaN-semiconductor sapphire-volume type constituting the β-body of the nitride-semiconductor layer.
射态例如由專利文件 D EThe illuminating state is for example the patent document D E
i〇2〇〇6〇15788Al 中已為 A 人所知。於此，使用藍寶石作為 牛導體層序列用的生長基如 μ 卷板。相對於薄膜晶片而言，在 &寶石-體積式發射器中兮a Ε ▲ °亥生長基板在製造過程結束時 未由半導體層序列剝離。兮γ ^ e、#』1 , 。亥（生長）基板可使活性區中產 生的輕射通過。這樣可交Β I易使輻射由半導體晶片中經由I〇2〇〇6〇15788Al is already known to A. Here, sapphire is used as a growth substrate for the sequence of bovine conductor layers such as a μ-roll plate. In the & gem-volume emitter, the 兮a Ε ▲ ° growth substrate was not stripped by the semiconductor layer sequence at the end of the manufacturing process.兮γ ^ e, #』1 , . The (grown) substrate allows the light shot generated in the active region to pass. This allows for the exchange of radiation from the semiconductor wafer.
S -4- 201222899 =發出。半導體晶片因此形成為體積式轄射器。相 米道'面發射器而言’體積式輻射器中亦經由基板而由 j體晶片中發出可觀的輕射成份。相對於表面輻射器 °冑積式發射器中半導體晶片之發射面上的表面亮 度較小。 文件 WO 20050813 1 9Α1 和 DE 1〇2〇〇6〇 1 5788αι 之 曷丁内谷此處藉由爹考而收納在本申請案的揭示内容 在一較佳的實施形式中，具有細孔的連接層可導 熱。這樣特別有利，此乃因該半導體晶片中所產生的熱 :。特別決速地傳導至基板上。可使用藍寶石·體積式發射 Γ作為半導組日日片，其中具有細孔的連接層只用來與熱 形成接觸。 在另—較佳的實施形式中，具有細孔的連接層可導 …、且同％•可導電。這樣特別有利，此乃因除了可散熱以 外亦可使半導體晶片實現二個電性接觸區之一。可使用 薄膜晶片作為半導體晶·片。 在I較佳的實施形式中，具有細孔的連接層由銀構 成於是相對於由黏合劑（特別是銀導電的黏合劑或焊 劑）構成的連接層而言，導熱性可提高。具有細孔的銀層 未具備有機化合物。又，其在價值上較由Au8❶Sn2。構成 的焊劑（其由80重量百分比之金和2〇重量百分比之錫構 成）貴很多（10倍）。具有細孔之由銀構成的連接層具有介 於80 W/m*k和30〇 w/m*k之間的導熱率。該連接層中 存在的細孔越少且細孔越小，則導熱率越高。 201222899 可導電的黏合劑之導熱率介於1·5 W/m*k和2〇 W/m*k之間。焊劑之導熱率依據所使用的焊劑型態而介 於50和60 W/m*k之間。可使用含錫的合金（例如， SnAgCu)作為焊劑。或是，可使用Au8〇Sn20作為焊劑。S -4- 201222899 = Issued. The semiconductor wafer is thus formed as a volumetric susceptor. In the case of a phase-channel emitter, the volumetric radiator also emits a considerable amount of light-emitting components from the j-body wafer via the substrate. Relative to the surface radiator The surface of the semiconductor wafer in the convolution emitter has a small surface brightness. Document WO 20050813 1 9Α1 and DE 1〇2〇〇6〇1 5788αι 曷 内 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷The layer can conduct heat. This is particularly advantageous due to the heat generated in the semiconductor wafer: It is conducted to the substrate in a particularly fast manner. A sapphire/volume emitter can be used as a semi-conductive group day-to-day film in which a connection layer having pores is only used to make contact with heat. In a further preferred embodiment, the connecting layer having pores can be electrically conductive. This is particularly advantageous because, in addition to dissipating heat, the semiconductor wafer can be one of two electrical contact regions. A thin film wafer can be used as the semiconductor wafer. In a preferred embodiment of the invention, the connecting layer having pores is made of silver so that the thermal conductivity can be improved with respect to the connecting layer composed of an adhesive (especially a silver-conductive adhesive or solder). A silver layer having pores does not have an organic compound. Also, it is more valuable in value than Au8❶Sn2. The composition of the flux (which is composed of 80% by weight of gold and 2% by weight of tin) is much more expensive (10 times). The connecting layer made of silver having fine pores has a thermal conductivity of between 80 W/m*k and 30 〇 w/m*k. The smaller the pores present in the connection layer and the smaller the pores, the higher the thermal conductivity. 201222899 Conductive adhesives have a thermal conductivity between 1·5 W/m*k and 2〇 W/m*k. The thermal conductivity of the flux is between 50 and 60 W/m*k depending on the type of flux used. A tin-containing alloy (for example, SnAgCu) can be used as the flux. Alternatively, Au8〇Sn20 can be used as the flux.
AusoSnao之熔化溫度大約是280。(：。 換§之’本發明的核心構想在於，藉由銀層來取代 介於半導體晶片和基板上之半導體晶片-接觸層之間的 目前所使用的銀導電的黏合劑或目前使用的焊劑。 特別有利的是’具有細孔之銀層在大約2 5 0時由 燒結過程來產生。銀的熔點高很多，大約是在96〇它。 換言之’在燒結時出現流體相位。具有細孔之銀層在電 子組件之後來的表面安裝中穩定地保持在電路板（SMt 總成(Assembly))上且未溶化。在該電路板設有電子組科 以後，各電子組件以所謂回流（Refl〇w)_方法而焊接著。 於是，最多可達成26(TC之溫度。當在軟焊過程中使用 一種以錫為主之合金（除了 以外）作為晶片焊齊( 時，日曰曰片焊劑在表面安裝時溶化。這樣會造成晶片焊劑 之未界定的組織狀態且會造成熱問題和可靠性的問題。 作為另一方式，可使用由AhoSho構成的焊劑。 具有大約28(TC之熔點，因此在表面安裝時不會再炫"化\ 使用AusoSn^作為焊劑時的缺點是，一方面是高的價 格’此乃因金成份大約佔了 8〇 4量百分比。另一缺點 是，AwoSho在大約3〇(rc時被加工成晶片焊劑。在‘種 溫度時，預鑄模-殼體之殼體塑料將彩色化，這樣會使該 殼體塑料之反射率大大地下降。 7 -6 - 201222899 接 是 的 而 數 程 地 合 產 接 奈 孔 細 成 性 持 線 表 反 定 在-較佳的實施形式中，具有細孔之由銀構成的連 層所具有的厚度介於大約1微米和50微米之間，較佳 介於5微米和3〇微米之間。由於具有細孔之銀層之高 導熱率，則相對於目前使用之銀導電之黏合劑之厚度 言該具有細孔之銀層之厚度是一種相關性很少的； 。這樣就可以較大的容許度（t〇lerance)來達成簡易的製 。反之，在銀導電之黏合劑中熱阻隨著層厚度而大大 下降。因此，黏合劑須處理成儘可能薄，銀導電之黏 劑之厚度典型上是3微米至5微米。㈤半導體晶片所 生之熱之發散而言1〇微米的層厚度是有問題的。 在权佳的貝知形式中，具有細孔之由銀構成的連 層所具有的細孔的大小介於大約5〇奈米和大約丨〇〇〇 米之門、’田孔之較小的大小是有利的，此乃因隨著細 大小的下降，銀層之導熱率上升。同樣，儘可能小的 孔密度是有利的。細孔密度越小，則熱阻越小。 在-，佳的實施形式中’具有細孔的連接層由金構 。這樣是有利的，此乃因金具有類似於銀之有利的特 且同時不被氧化。這樣會使導熱率和導電率長期地保 成定值。 在一較佳的實施形式中’基板是一種導線架。此導 架可由銅構成’其導熱率大約是3〇〇 w/m*k。銅在其 面上可鍍銀，以使由半導體晶片所發出之電磁輻射之 射率提尚。銅亦可鍍金，以使導線架相對於氧化更穩 且使銅離子與半導體晶片保持成較遠。 在一較佳的實施形式中，導線架澆注在預鑄模殼體 201222899 中。預鑄模-殼體是—種濺鍍澆注體。濺鍍澆注是在大約 350°C以及800至2000巴（bar)時進行。預鎮模是由塑料 (特別是聚合物）構成且具有高達95%之反射率。預禱模 具有白色的色彩。預鑄模具有多種功能，其固定著導= 架的二個部#。預鑄模具有空腔，其底部上配置著半導 體晶片。空腔的側壁作為由半導體晶片所發出之電嵫輻 射之反射器。預鑄模之空腔提供澆注用的空間且防止該 澆注向側面延伸。該澆注體可具有發光物質。整體而言， 具有導線架之預鑄模-殼體可很簡易地且成本有利地加 工 〇 由於聚合物之有限的耐熱性，則在使用一預鑄模_ 冗又體時需使短時間的加工溫度不超過26(rc ^此條件能 以本發明之燒結過程來保持著，藉此可產生具有細孔= 銀層。 在一較佳的實施形式中，基板是一種陶瓷。可使用 導熱率大約是20 W/m*k之鋁·氧化物（A12〇3)、導熱率大 約是170 W/m*k之氮化鋁（A1N)、或導熱率大約是22〇 W/m*k之氮化硼（BN)作為陶瓷。陶瓷基板的使用是特別 有利的’此乃因陶瓷廣泛地對溫度具有敏感性。 本發明可特別有利地用於高功率種類的光電組件， 其電流大於3 0 0毫安。例如，本發明之具有細孔之連接 層可用於下述之OSRAM OS產品中：具有導線架和預鑄 模-殼體之組件，例如，AdvancedP〇werT〇PLED(Plus)，The melting temperature of AusoSnao is approximately 280. The core idea of the present invention is to replace the currently used silver conductive adhesive or the flux currently used between the semiconductor wafer and the semiconductor wafer-contact layer on the substrate by a silver layer. It is particularly advantageous that the 'silver layer with pores is produced by the sintering process at about 205. The melting point of silver is much higher, about 96 。. In other words 'the phase of the fluid occurs during sintering. The silver layer is stably held on the circuit board (SMt assembly) and is not melted in the surface mounting after the electronic component. After the electronic circuit is provided in the circuit board, the electronic components are called reflow (Refl〇). w)_ method is welded. Thus, a maximum of 26 (TC temperature can be achieved. When a tin-based alloy (except for) is used as a wafer soldering in the soldering process (when the solder paste is in the Dissolving during surface mounting. This can cause undefined tissue state of the wafer solder and can cause thermal problems and reliability problems. As another way, a flux composed of AhoSho can be used. It has about 28 (TC Point, so it will not be dazzled when the surface is installed. The disadvantage of using AusoSn^ as a flux is that it is a high price on the one hand, because the gold content accounts for about 8〇4%. Another disadvantage Yes, AwoSho is processed into wafer solder at approximately 3 〇. At the 'temperature, the shell-shell plastic will be colored, which will greatly reduce the reflectivity of the shell plastic. 7 -6 - 201222899 In the preferred embodiment, the thickness of the layer of silver having pores is about Between 1 micrometer and 50 micrometers, preferably between 5 micrometers and 3 micrometers. Due to the high thermal conductivity of the silver layer with fine pores, it has pores relative to the thickness of the currently used silver conductive adhesive. The thickness of the silver layer is a little correlated; thus, a larger tolerance can be achieved to achieve a simple system. Conversely, in a silver conductive adhesive, the thermal resistance greatly increases with the layer thickness. Decline. Therefore, the adhesive must be processed as much as possible. The thickness of the thin, silver conductive adhesive is typically from 3 microns to 5 microns. (5) The thickness of the layer of 1 〇 micron is problematic in terms of the heat divergence of the semiconductor wafer. The layer of silver made up of pores has a pore size of about 5 〇 nanometers and a gate of about 丨〇〇〇米, and the smaller size of the field hole is advantageous because The decrease in the fine size increases the thermal conductivity of the silver layer. Similarly, the pore density as small as possible is advantageous. The smaller the pore density, the smaller the thermal resistance. In the preferred embodiment, the connection with fine pores The layer is made of gold. This is advantageous because gold has the advantage of being similar to silver and is not oxidized at the same time. This will keep the thermal conductivity and electrical conductivity constant for a long time. In a preferred embodiment, the substrate is a lead frame. This guide can be made of copper 'its thermal conductivity is about 3 〇〇 w/m*k. Copper can be plated with silver on its surface to enhance the radiance of electromagnetic radiation emitted by the semiconductor wafer. Copper can also be gold plated to make the leadframe more stable with respect to oxidation and to keep copper ions away from the semiconductor wafer. In a preferred embodiment, the leadframe is cast into the die casing 201222899. The die-shell is a sputter cast body. Sputter casting is carried out at about 350 ° C and 800 to 2000 bar. The pre-mode is made of plastic (especially a polymer) and has a reflectivity of up to 95%. The prayer mode has a white color. The 預鑄 mold has multiple functions, which are fixed to the two parts of the guide frame. The crucible mold has a cavity with a semiconductor wafer disposed on the bottom. The sidewall of the cavity acts as a reflector for the ethigen radiation emitted by the semiconductor wafer. The cavity of the die provides space for casting and prevents the casting from extending to the side. The potting body can have a luminescent substance. Overall, the die-shell with leadframe can be easily and cost-effectively processed. Due to the limited heat resistance of the polymer, a short processing time is required when using a die. Not more than 26 (rc ^ this condition can be maintained by the sintering process of the present invention, whereby a fine pore = silver layer can be produced. In a preferred embodiment, the substrate is a ceramic. The thermal conductivity can be used to be approximately 20 W/m*k aluminum oxide (A12〇3), aluminum nitride (A1N) with a thermal conductivity of approximately 170 W/m*k, or nitridation with a thermal conductivity of approximately 22 〇W/m*k Boron (BN) is used as a ceramic. The use of ceramic substrates is particularly advantageous 'this is because ceramics are widely sensitive to temperature. The invention can be used particularly advantageously for high power types of optoelectronic components with currents greater than 300 millimeters. For example, the connection layer with pores of the present invention can be used in the OSRAM OS product described below: a component having a lead frame and a die-shell, for example, AdvancedP〇werT〇PLED(Plus),
Golden Dragon (Plus)，白金（piatinuin) Deagon 或鑽石Golden Dragon (Plus), white gold (piatinuin) Deagon or diamond
Dragon ;具有陶基板的組件，例如，〇sl〇n。 201222899 較佳的實施形式中，在 Advanced Power TOLLED中藉由具有細孔之由銀構成的連接層，相對於 由可導電的黏合劑槔成的連接層而言可使熱阻下降 4〇 /〇以樣可使光電流增加大約4%。這由以下事實即可 明白.藉由半導體晶片至導線架之較佳的散熱，則發光 物質可較 地文到加熱。發光物質的溫度越小，則其效 率越高。 电子組件可在半導體晶片和基板之間包括具有細孔 的連接層’此種電子組件之製造方法之不同的實施方式 至少具有以下步驟·· 首先，製備—種具有至少一半導體晶片·接觸層的基 板在„玄半V體晶片_接觸層上藉由分配或絲網印刷或壓 p或樣板印刷或黑玉（Jetten)而施加一種糊（或膏）。此糊 3有銀粒子、有機溶劑和有機母材（matrix)，有機母材中 埋置著銀粒子。銀粒子具有小於5微米之大小。這樣特 別有利，此乃因隨後的燒結是在大約小於25〇它之低的 溫度中進行’銀粒子越小，則可提供越佳的結果。銀粒 ^在繞結步驟之前以團塊或小球的形式存在著。在施加 ㈣之後，半導體晶片壓在該糊上，這亦稱為晶粒(Die)_ 附著。最後’對該糊進行燒結，以燒完該有機母材。在 该半導體晶片和該基板上之半導體晶片接觸層之間形 成一種可導熱的具有細孔之由銀構成的連接層以作為最 後的產品。 β 在特別有利的方式中，在燒結過程時產生儘可能小 之圓形細孔，其同時均勻地分佈在該連接層中。此 201222899 在較佳的實施方式中，在小於 氣壓中於通風檢士& 凤爐中對該糊進行燒結大 '瓜燒、，’σ特別是在預碡模-殼體中進行轉 殼體塑料未彩色化。 在一較佳的實施方式中，在將該 糊f之後且在燒結步驟之前進行一種 火疋^在正常大氣中於大約150。(：時在 1 〇 /刀鐘。此退火步驟用來將有機溶劑 機岭J的使用特別有利，此乃因其具 在低的溫度時將蒸發。 在—較佳的實施方式中，在燒結 /主材料（特別是矽樹脂或樹脂）來對固 體晶片進行澆注。 在一較佳的實施方式中，在半導 在濟注體上設定一主光學系統，特別 本發明之解法的不同實施例以 述。 【實施方式】 各圖式和實施例中相同' 相同形 組件分別設有相同的參考符號。圖式 各元件之間的比例未必依比例繪出。 易於了解之故，各圖式的一些元件已 圖1 a顯示電子組件i 〇〇a之剖面 Z以是光電組件。此電子組件刚“ °又有半導體晶片·接觸層1 1 〇a。半導3 250C時在正常大 約20分鐘。此種低 :特別有利，此乃因 半導體晶片壓在該 退火步驟。此種退 通風爐中進行大約 由該糊中排出。有 有高的蒸氣壓，其 步驟之後以一種洗 定在基板上的半導 體晶片之澆注之後 是透鏡 F將依據圖式來詳 式或作用相同的各 中所示的各元件和 反之’為了清楚且 予放大地顯示出。 圖。電子組件1 〇 〇 a I*有基板124，其上 蜜晶片_接觸層ll〇a -10- 201222899 具有可導電的及/或可導熱的材料。可使用金作為材料。 半導體晶片-接觸層110a具有介於〇 5微米和5微米之間 的厚度。在半導體晶片-接觸層j 1〇a上配置半導體晶片 1〇2。在半導體晶片_接觸層11〇3和該半導體晶片ι〇2之 面向該基板1 24之接觸面1 04之間配置一具有細孔之連 接層106。具有細孔之連接層1〇6具有導電性及/或導熱 性。具有細孔之連接層1〇6可由銀構成，其具有之厚度 介於大約1微米和大約50微米之間，較佳是介於5微米 和3 0微米之間。具有細孔之由銀構成之連接層丨〇6在其 整個體積上具有細孔1 〇 8，細孔的大小介於大約5 〇奈米 和大約10 0 〇奈米之間。 具有細孔之由銀構成之連接層丨〇6所具有的導熱率 介於 80 W/m*k 和 300 W/m*k 之間。 或是’具有細孔之連接層1 〇6可由金構成。 基板1 24是導線架，其洗注在預鑄模-殼體丨丨8中。 預鑄模-殼體1 1 8形成空腔。空腔之底部是由導線架（基 .板）124形成。半導體晶片1〇2配置在導線架（基板）124 上。半導體晶片102之遠離導線架（基板）124之面經由接 觸塾112和接合線1 16而與導線架上之接合墊1 26a導電 性地相連接。由金構成的接合墊126a所具有的厚度介於 〇.5微米和5微米之間。半導體晶片ι〇2藉由平坦的體積 洗注體1 20來澆注。在澆注體丨2〇上配置透鏡形式的主 光學系統1 2 2。 圖1 b顯示電子組件1 00b之剖面圖。圖1 b之實施例 是與圖1 a之實施例相同，除了半導體晶片-接觸層丨丨〇b 201222899 和接合墊126b具有不同的厚度以外。換言之，具有細孔 之由銀構成之連接層106直接設定在導線架（基板）124 上。類似地，該接合墊i丨6直接設定在導線架（基板）丨Μ 上。圖lb所示的實施例是有利的，此乃因該導線架（基 板)124和半導體晶片1〇2之間的熱連接和電性連接是直 接的，即，只藉由具有細孔之連接層丨〇6來達成◊這樣 可使半導體晶片102特別良好地將熱發散至導線架（基 板）124。 圖2顯示電子組件2〇〇之剖面圖。相對於圖1 &和圖 1 b而„ ，基板224疋陶瓷。本發明的核心是將熱最佳地 由半導體晶片202經由具有細孔之連接層2〇6而傳送至 基板（陶幻224。本發明的核心亦以圖2之實施例為基 準。半導體晶片202經由其接觸面2〇4而與具有細孔之 由銀構成的連接層206相連接。具有細孔之連接層2〇6 可導電地且可導熱地與半導體晶片_接觸層21〇相連接。 與圖lb不同’圖2之實施例中，具有未消失之厚度的可 導電的半導體晶片-接觸層210是必需的，此乃因陶瓷_ 基板224是電的絕缘體。第二電性接觸區藉由接合線216 來實現，其將半導體晶片202之遠離該基板224接觸墊 212之面與陶竟（基板）224上之接合墊226相連接。半導 體晶片202洗注在洗注體220中。在洗注體上配置透鏡 形式之主光學系統222。經由陶瓷-基板224而配置通孔 230、232 ’其中以可導電的材料來填充。在與通孔23〇、 224之遠離半導體晶片 層234、236。各接觸層 2 3 2電性相連的情況下’在基板 202之此側上配置金屬化之接觸 ，12- 201222899 234、236例如用來在電路板上形成接觸。半導體晶片2〇2 中所產生的熱主要發散至陶瓷（基板）224上。 圖3顯示電子組件（特別是光電組件）之製造方法的 流程圖。製造過程可在步驟S1至步驟S 7中說明。 步驟S1中製備基板124、224，其具有至少_半導 體晶片-接觸層1 l〇a、1 l〇b、210。 步驟S2中，在半導體晶片-接觸層i 1〇a、u〇b、21〇 上藉由分配或絲網印刷或壓印或樣板印刷或黑玉（Jetten 而施加一種糊（或膏）。此糊含有銀粒子、有機溶劑和有 機母材（matrix)。有機母材中埋置著銀粒子，這樣至少可 在銀粒子之間設定最小的封住作用。 步驟S3中使半導體晶片ι〇2、2〇2壓在該糊上。於 是’該糊變稠密。 在可選擇的步驟4中，使該糊退火以將有機溶劑由 S亥糊中排出。此退火在通風爐中於1 50°C時在正常大氣 中進行大約1 〇分鐘。 v k S 5中’對該糊進行燒結’這樣可造成一種具有 、、田孔之連接層106、206 »此燒結是在通風爐中於250°C 日夺 iT ^ 氧Τ進行大約20分鐘。在該燒結步驟中，將 有機母材烤 ri·» h,. 疋儿。各連接層1 〇6、206之多孔性和體積因此 大大地變小。又，丄 Χ形成所謂燒結頸，其可使各連接層1 06、 206之固定忸 古 &捉内。各燒結頸藉由表面擴散而形成於各 繞結粒子之間。 步驟 S f\ Ay 、， 中’固定在基板上的半導體晶片102、202 Μ —種译、Λ丄 ^ 料（特別是矽樹脂或樹脂）來澆注。 -13- 201222899 步驟S7中，主光學系統122、222(特別是透鏡）設定 在澆注體120、220上。 依據多個a把例來描述光電組件，以說明本發明所 依據的構想。各實施例因此不限於特定之特徵组合。當 數個特徵和佈置只與特殊的實施例或各別的實施例相結 合來說明時’各實施例分別可與其它實施例之其它特徵 相組合。同樣，在各實施例中，各別顯示的特徵或特殊 的佈置可省略或添加’只要—般的技術原則叮實現即可。 【圖式簡單說明】 圖1 a顯示電子組件之剖面圖，其具有導線架以作為 基板。 圖1 b顯示電子租件之剖面圖，其具有導線架以作為 基板。 圖2顯示電子組件之剖面圖，其具有陶篆以作為基 板。 圖3顯示本發明之電子組件之製造方法的流程圖。 【主要元件符號說明】 100a 電 子 組 件 100b 電 子 組 件 102 導 體 晶 片 104 接 觸 面 106 連 接 層 108 細 孔 110a 半 導 體 晶 片 -接 觸 層 110b 半 導 體 晶 片 -接 觸 層 -14- 201222899 112 接觸墊 116 接合線 118 預鑄模-殼體 120 _ 澆注體 122 主光學系統 124 導線架/基板 126a 接合墊 126b 接合墊 200 子組件 202 半導體晶片 204 接觸面 206 連接層 208 細孔 210 半導體晶片-接觸層 212 接觸墊 216 接合線 220 澆注體 222 主光學系統 224 陶瓷/基板 226 接合墊 230 通孔 232 通孔 234 接觸層 236 接觸層 -15-Dragon; a component with a ceramic substrate, for example, 〇sl〇n. In a preferred embodiment, in the Advanced Power TOLLED, the connection layer made of silver having pores can reduce the thermal resistance by 4 〇/〇 with respect to the connection layer formed by the electrically conductive adhesive. In this way, the photocurrent can be increased by about 4%. This is understood by the fact that the luminescent material can be heated to a higher level by the better heat dissipation from the semiconductor wafer to the lead frame. The lower the temperature of the luminescent substance, the higher the efficiency. The electronic component may include a connection layer having a fine hole between the semiconductor wafer and the substrate. A different embodiment of the manufacturing method of the electronic component has at least the following steps: First, preparing a semiconductor wafer/contact layer having at least one semiconductor wafer The substrate is applied with a paste (or paste) on the "semi-V-body wafer_contact layer" by dispensing or screen printing or pressing p or pattern printing or jade (Jetten). The paste 3 has silver particles, an organic solvent and Organic matrix, in which organic particles are embedded with silver particles. Silver particles have a size of less than 5 microns. This is particularly advantageous because subsequent sintering is carried out at temperatures as low as about 25 〇. The smaller the silver particles, the better the results are provided. The silver particles are present in the form of agglomerates or pellets before the winding step. After application (4), the semiconductor wafer is pressed against the paste, which is also called crystal Grain (Die)_attachment. Finally 'sintering the paste to burn out the organic base material. Forming a thermally conductive silver-containing pore between the semiconductor wafer and the semiconductor wafer contact layer on the substrate In the particularly advantageous manner, the resulting connecting layer is produced as a final product. In a particularly advantageous manner, circular pores which are as small as possible are produced during the sintering process, which are uniformly distributed in the connecting layer at the same time. This 201222899 is preferably implemented. In the method, the paste is sintered in a ventilated warrior & phoenix furnace at a temperature less than the air pressure, and the σ is particularly colored in the pre-die-shell. In a preferred embodiment, a fire is applied after the paste f and before the sintering step at about 150 in a normal atmosphere. (: at 1 〇/knife clock. This annealing step is used to place the organic solvent machine The use of Ridge J is particularly advantageous because it will evaporate at low temperatures. In a preferred embodiment, the solid wafer is cast in a sintered/primary material (especially a resin or resin). In a preferred embodiment, a primary optical system is set on the semiconducting body, and in particular, different embodiments of the solution of the present invention are described. [Embodiment] The same type of identical components are used in the drawings and the embodiments. Separate phase The reference symbols are not necessarily drawn to scale. It is easy to understand that some of the components of the various figures have been shown in Figure 1 a for the profile Z of the electronic component i 〇〇a to be an optoelectronic component. The component has "semiconductor wafer · contact layer 1 1 〇a. The half-conductance 3 250C is about 20 minutes normal. This low: is particularly advantageous because the semiconductor wafer is pressed in the annealing step. The process is carried out approximately from the paste. There is a high vapor pressure, and after the step, after the casting of the semiconductor wafer on the substrate, the lens F will be detailed or functionally the same according to the drawing. The various components and vice versa are shown for clarity and amplification. The electronic component 1 〇〇a I* has a substrate 124 on which the honey wafer _ contact layer ll 〇 a -10- 201222899 is electrically conductive and/or A material that can conduct heat. Gold can be used as the material. The semiconductor wafer-contact layer 110a has a thickness of between 5 microns and 5 microns. A semiconductor wafer 1〇2 is disposed on the semiconductor wafer-contact layer j 1〇a. A connection layer 106 having fine holes is disposed between the semiconductor wafer_contact layer 11A3 and the contact surface 104 of the semiconductor wafer 2 facing the substrate 14. The connection layer 1〇6 having fine pores has electrical conductivity and/or thermal conductivity. The connecting layer 1 〇 6 having fine pores may be composed of silver having a thickness of between about 1 μm and about 50 μm, preferably between 5 μm and 30 μm. The connecting layer 由6 made of silver having fine pores has fine pores 1 〇 8 in its entire volume, and the pore size is between about 5 〇 nanometers and about 100 〇 nanometers. The connection layer 由6 made of silver having fine pores has a thermal conductivity of between 80 W/m*k and 300 W/m*k. Alternatively, the connection layer 1 〇 6 having fine pores may be composed of gold. The substrate 1 24 is a lead frame that is filled in the die-shell 丨丨 8. The die-shell 1 18 forms a cavity. The bottom of the cavity is formed by a lead frame (base plate) 124. The semiconductor wafer 1〇2 is disposed on the lead frame (substrate) 124. The face of the semiconductor wafer 102 remote from the leadframe (substrate) 124 is electrically connected to the bond pads 1 26a on the leadframe via the contact pads 112 and bond wires 116. The bonding pad 126a composed of gold has a thickness of between 〇.5 μm and 5 μm. The semiconductor wafer 〇2 is cast by a flat volume of the immersion body 120. A main optical system 1 2 2 in the form of a lens is disposed on the casting body 2〇. Figure 1 b shows a cross-sectional view of electronic component 100b. The embodiment of Figure 1b is identical to the embodiment of Figure 1a except that the semiconductor wafer-contact layer 2012b 201222899 and bond pad 126b have different thicknesses. In other words, the connection layer 106 made of silver having pores is directly set on the lead frame (substrate) 124. Similarly, the bonding pad i丨6 is directly disposed on the lead frame (substrate) 丨Μ. The embodiment shown in FIG. 1b is advantageous because the thermal and electrical connections between the leadframe (substrate) 124 and the semiconductor wafer 1〇2 are direct, that is, only by the connection with the fine holes. The layer 6 is achieved so that the semiconductor wafer 102 can dissipate heat to the leadframe (substrate) 124 particularly well. Figure 2 shows a cross-sectional view of the electronic component 2A. With respect to Figures 1 & and Figure 1b, the substrate 224 is ceramic. The core of the present invention is to optimally transfer heat from the semiconductor wafer 202 to the substrate via the connection layer 2〇6 with pores (Tao 224 The core of the present invention is also based on the embodiment of Fig. 2. The semiconductor wafer 202 is connected via its contact surface 2〇4 to a connection layer 206 made of silver having pores. The connection layer having fine holes 2〇6 Conductively and thermally conductively connected to the semiconductor wafer-contact layer 21A. Unlike the embodiment of FIG. 2, an electrically conductive semiconductor wafer-contact layer 210 having an undisappeared thickness is necessary. The ceramic _ substrate 224 is an electrical insulator. The second electrical contact region is realized by a bonding wire 216 which is away from the surface of the semiconductor wafer 202 contacting the pad 212 and the ceramic substrate 224. The bonding pads 226 are connected. The semiconductor wafer 202 is washed in the rinsing body 220. The main optical system 222 in the form of a lens is disposed on the rinsing body. The through holes 230, 232' are disposed via the ceramic-substrate 224 Material to fill. In with through holes 23〇, 2 24 away from the semiconductor wafer layers 234, 236. Where the contact layers 2 2 2 are electrically connected, 'metallized contacts are disposed on the side of the substrate 202, 12-201222899 234, 236 are used, for example, to form on a circuit board. Contact. The heat generated in the semiconductor wafer 2〇2 is mainly radiated to the ceramic (substrate) 224. Fig. 3 shows a flow chart of a method of manufacturing an electronic component, particularly an optoelectronic component. The manufacturing process can be performed in steps S1 to S7. In the step S1, the substrate 124, 224 is prepared, which has at least the semiconductor wafer-contact layer 1 l〇a, 1 l〇b, 210. In the step S2, the semiconductor wafer-contact layer i 1〇a, u〇 Apply a paste (or paste) by dispensing or screen printing or embossing or pattern printing or black jade (Jetten). This paste contains silver particles, organic solvents and organic matrix. Silver particles are embedded in the material so that at least a minimum sealing effect can be set between the silver particles. In step S3, the semiconductor wafers ι 2, 2 〇 2 are pressed against the paste. Thus, the paste becomes dense. In optional step 4, the paste is annealed to The solvent is discharged from the paste. This annealing is carried out in a normal atmosphere at a temperature of 150 ° C for about 1 。 minutes. The vk S 5 'sintering the paste' can cause a kind of The connection layer of the holes 106, 206 » This sintering is carried out in a ventilated oven at 250 ° C for about 20 minutes. In this sintering step, the organic base material is baked ri·» h,. The porosity and volume of each of the connection layers 1 〇 6, 206 are thus greatly reduced. Further, the ruthenium forms a so-called sintered neck which allows the fixing of the respective connection layers 106, 206 to be captured. Each of the sintered necks is formed between the respective wound particles by surface diffusion. In the step S f \ Ay , , the semiconductor wafers 102, 202 fixed on the substrate are poured, and the materials (especially enamel resin or resin) are poured. -13- 201222899 In step S7, the main optical systems 122, 222 (especially lenses) are placed on the potting bodies 120, 220. The optoelectronic component will be described in terms of a plurality of examples to illustrate the concept on which the invention is based. Embodiments are therefore not limited to a particular combination of features. When several features and arrangements are only described in connection with a particular embodiment or various embodiments, the various embodiments can be combined with other features of other embodiments. Also, in the various embodiments, the individually displayed features or special arrangements may be omitted or added as long as the technical principles are implemented. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1a shows a cross-sectional view of an electronic component having a lead frame as a substrate. Figure 1 b shows a cross-sectional view of an electronic rental having a lead frame as a substrate. Figure 2 shows a cross-sectional view of an electronic component having a ceramic pot as a substrate. Figure 3 is a flow chart showing a method of manufacturing the electronic component of the present invention. [Main component symbol description] 100a electronic component 100b electronic component 102 conductor wafer 104 contact surface 106 connection layer 108 fine hole 110a semiconductor wafer-contact layer 110b semiconductor wafer-contact layer-14-201222899 112 contact pad 116 bonding wire 118 die- Housing 120 _ Casting Body 122 Main Optical System 124 Lead Frame/Substrate 126a Bonding Pad 126b Bonding Pad 200 Subassembly 202 Semiconductor Wafer 204 Contact Surface 206 Connection Layer 208 Pore 210 Semiconductor Wafer - Contact Layer 212 Contact Pad 216 Bonding Wire 220 Pouring Body 222 Primary Optical System 224 Ceramic/Substrate 226 Bonding Pad 230 Through Hole 232 Through Hole 234 Contact Layer 236 Contact Layer-15-