201220949 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種液晶面板上的閘驅動電路，特別是關於一 種運用於液晶面板上結合移位暫存器(shift register)與轉壓器(ievei shifter)的閘驅動電路。 【先前技術】 請參照第1圖，其所繪示為習知液晶面板及其相關控制電 馨 路示思圖。一般來說，液晶面板100包括一可視區域120、與 一不可視區域(虛線以外的區域)125。可視區域120包括中有 一像素陣列(pixel array) ’像素陣列中包括複數條閘極線(gate line，G1〜Gn)，以及複數條資料線(D1〜Dm)。再者，經由不可 視&域125的佈線’閘極線(G1〜Gn)可依序連接至閘驅動電路 220。同理，資料線(D1〜Dm)也依序連接至源驅動電路(s〇urce driving circuit)230。 再者，液晶面板100上還包括一轉壓器110，連接至閘驅 動電路220、源驅動電路230、以及時間控制器（timing ⑩ c〇ntroller)210。轉壓器11〇可根據時間控制器210所產生的時 間控制信號，將較低的高準位電壓(lower logical Hi voltage level)轉換為較高的高準位電壓（higher logical Hi voltage level)，並且輸入至閘驅動電路22〇以及源驅動電路23〇 〇因 此’閘驅動電路220輸出至閘極線(G1〜Gn)上的閘驅動信號 (gate driving signal)將具有較高的高準位電壓。 換句話說，習知閘驅動電路220與源驅動電路230的操作 電壓(operation voltage)皆為轉壓器110所輸出較高的高準位電 壓，因此消耗的功率(P=fxCxV2)會較大。 201220949 再者，較高的高準位電壓由轉壓器110輸出之後，必須經 過一段佈線(layout trace)之後才會輸入閘驅動電路220與源驅 動電路230 ’因此’會造成較高的高準位電壓衰減(decay)，並 且會影信號的品質(例如閘驅動信號的輸出波形失真）。 請參照第2A圖，其所繪示為習知液晶顯示系統相關控制 電路示意圖。信號控制器（signal controller)600接收視訊信號 (R、G、B、DE、Hsync、Vsync、MCLK)並產生第一控制信號 C0NT1、第二控制信號C0NT2、視訊資料dAT至閘驅動電路 400與源驅動電路5 00。轉壓器700接收較低的高準位電壓(Vin) 產生較高的高準位電壓(Vlog)至閘驅動電路4〇〇以及源驅動電 路500。再者，像素陣列3〇〇連接至閘驅動電路4〇〇以及源驅 動電路500。而源驅動電路5〇〇更連接至灰階電壓產生器(排吵 voltage generator)800以接收灰階電壓信號。 因此，源驅動電路500根據灰階電壓信號、第二控制信號 CONT2、視訊資料DAT、較高的高準位電壓Vi〇g，產生資料 佗號(D1〜Dm)至像素陣列300。而閘驅動電路根據第一控 制信號CQNT1與較高的高準位電壓vlQg產生閘驅動信號 (G1〜Gn)至像素陣列3〇〇。 睛參照第2B圖’其所綠示為習知轉壓器實際電路示意 圖。很明顯地，習知轉壓器的電路必須同時使用N型電晶體 (MN11、MN21、MN3丨、_32)以及 p 型電晶體(Μρι 丨、Mp21、 MP31、MP32)。 第2圖與第1圖具有相同的缺點，亦即，開驅動電路樣 與源驅動電路5〇〇的操作電壓皆為轉壓器彻所輸出較高的高 準位電壓Vlog，因此消耗的功率(p=fxCxV2)會較大。 再者，較而的高準位電壓Vlog由轉壓器7〇〇輸出之後， 201220949 必須經過一段佈線(layout trace)之後才會輸入閘驅動電路4〇〇 與源驅動電路500，因此，會造成較高的高準位電壓νι%衰 減，並且會影信號的品質(例如閘驅動信號的輸出波形失真 再者，習知的轉壓器必須同時使用N型電晶體與p型電 晶體’這將使得電路的設計與製作複雜化。 【發明内容】201220949 VI. Description of the Invention: [Technical Field] The present invention relates to a gate driving circuit on a liquid crystal panel, and more particularly to a combination of a shift register and a converter for use on a liquid crystal panel ( Ievei shifter) brake drive circuit. [Prior Art] Please refer to Fig. 1, which is a schematic diagram of a conventional liquid crystal panel and its associated control circuit. Generally, the liquid crystal panel 100 includes a visible area 120 and an invisible area (area other than a broken line) 125. The visible area 120 includes a pixel array. The pixel array includes a plurality of gate lines (G1 to Gn) and a plurality of data lines (D1 to Dm). Further, the wiring 'gate lines (G1 to Gn) via the non-viewable & field 125 can be sequentially connected to the gate driving circuit 220. Similarly, the data lines (D1 to Dm) are also sequentially connected to the source driving circuit 230. Furthermore, the liquid crystal panel 100 further includes a voltage converter 110 connected to the gate driving circuit 220, the source driving circuit 230, and the timing controller 210. The voltage converter 11 转换 can convert a lower high-level voltage to a higher high-level voltage Hi voltage level according to a time control signal generated by the time controller 210. And input to the gate drive circuit 22A and the source drive circuit 23, so that the gate drive signal outputted to the gate lines (G1 to Gn) by the gate drive circuit 220 will have a high high level voltage. . In other words, the operation voltages of the conventional gate driving circuit 220 and the source driving circuit 230 are both high high-level voltages output by the converter 110, so the power consumed (P=fxCxV2) is large. . 201220949 Moreover, after the higher high level voltage is output by the voltage converter 110, it must pass through a layout trace before inputting the gate driving circuit 220 and the source driving circuit 230 'so' will result in a higher standard. The bit voltage decays and the quality of the image signal (eg, the output waveform of the gate drive signal is distorted). Please refer to FIG. 2A, which is a schematic diagram of a related control circuit of a conventional liquid crystal display system. The signal controller 600 receives the video signal (R, G, B, DE, Hsync, Vsync, MCLK) and generates the first control signal C0NT1, the second control signal C0NT2, the video data dAT to the gate drive circuit 400 and the source. Drive circuit 5 00. The converter 700 receives a lower high level voltage (Vin) to generate a higher high level voltage (Vlog) to the gate drive circuit 4A and the source drive circuit 500. Further, the pixel array 3A is connected to the gate driving circuit 4A and the source driving circuit 500. The source drive circuit 5 is further connected to a gray scale voltage generator 800 to receive the gray scale voltage signal. Therefore, the source driving circuit 500 generates the data apostrophes (D1 DDm) to the pixel array 300 according to the gray scale voltage signal, the second control signal CONT2, the video data DAT, and the higher high level voltage Vi〇g. The gate driving circuit generates the gate driving signals (G1 GGn) to the pixel array 3 according to the first control signal CQNT1 and the higher high level voltage vlQg. The eye is shown in Fig. 2B', and its green color is shown as a practical circuit diagram of a conventional converter. Obviously, the circuit of the conventional converter must use both N-type transistors (MN11, MN21, MN3丨, _32) and p-type transistors (Μρι 丨, Mp21, MP31, MP32). The second figure and the first figure have the same disadvantages, that is, the operating voltages of the open driving circuit and the source driving circuit 5 are all the high-level voltage Vlog output by the converter, and thus the power consumed. (p=fxCxV2) will be larger. Moreover, after the higher high-level voltage Vlog is outputted by the voltage converter 7〇〇, the 201220949 must pass through a layout trace before inputting the gate driving circuit 4〇〇 and the source driving circuit 500, thereby causing Higher high-level voltage νι% attenuation, and the quality of the shadow signal (such as the output waveform distortion of the gate drive signal, the conventional converter must use both N-type transistor and p-type transistor) This complicates the design and fabrication of the circuit.
本發明之目的係提出-種液晶面板上賴驅動電路，而間驅 動電路係直接製作於液晶面板上，其包括複數個位移暫存器 register) ’每個位移暫存器皆包括一移位單元_ft _與^轉壓 器，而轉壓器可產生較高的高準位電壓並直接輸出至像素陣列。 】本發明係提出一種閘驅動電路，接收一第一電壓、一第二 ，壓、與互補的-第—時脈信號與—第二時脈信號，該第一時脈 與該第二時脈信號的高準位為—第三電壓，且該閘驅動電路 ^複數個移位暫存器，而一第n個移位暫存器包括：一第一 ^動^晶體’具有—閘極接收—第η控制信號叫及極接收該 ，一源極輸出-第η次級通知信號;-第二驅動 閘閘極接收該第11控制信號，一源極輸出-第η -欠級Ϊ Γί ’ —上拉單元，接收第η]移位暫存器的一第η-1 時\通松°^以及該第一時脈信號；纟中，豸上拉單元動作 驅動控制信賴啟該第—驅動電晶體以及該第二 作哲:—下拉單元，接收該第η控制信號、該第一時脈 ^元動;信號、該第二電厘’該下拉單元係在該上拉 J 3第：驅動電晶體以及該第二驅動電晶體;以及一轉壓 枚該Ϊ二^第三電晶體，閘極接收該第二時脈信號，源極接 一电坚，—第四電晶體，閘極與汲極接收該第一電壓， 201220949 源極連接至該第三電晶體汲極；一第五電晶體，閘極連接至該 第二電晶體汲極，源極接收該第二電壓，汲極連接至該第二驅 動電晶體汲極；以及一第六電晶體，閘極與汲極接收該第一電 壓，源極連接至該第五電晶體汲極；其中，該第一電壓大於 第三電壓，該第三電壓大於該第二電壓。 、 本發明係更提出-種閘驅動電路，包括依序連接的複數個 移位暫存器’該些移位暫存器中的奇數移位暫存器接收一第一 電壓、-第二電壓、與一第一時脈信號，該些移位暫存器中的偶 數移位暫存器接收該第一電壓、該第二電塵、與一第二時脈信 ^第-雜與該第二時脈信號互補，且該第__時脈信號與該 第-時脈信號的高準位為1三電壓，該閘驅動電路中的 個移位暫存器包括：一第一驅動電晶體，具有一閉極接收一第 η控制信號，-祕接收該第二時脈信號，—源極輸出 知㈣；—第二驅動電晶體，具有—閘極接收該第η控 机號’-源極輸出閘驅動信號；一上拉單元 暫存⑽—第η·1她1知信號；其中，該上拉單^ 第二驅動電晶體;一下拉單元，接收該第η二體 號、該第二電壓，該下拉單元係在該上拉單元= 動作’並控制該第n控制信號關閉該第： 笛-IT: 第二驅動電晶體;以及-轉壓器，包括:- 閘極接收該第二時脈信號，源極接收該第二電 Ϊ第=2=’·間3ΓΓ該第一賴，源極連接至 極.以汲極連接至該第二驅動電晶體沒 ° 八電晶體，閘極與汲極接收該第一電壓，源極連 201220949 接至該第五電晶體汲極；其中’該第一電壓大於該第三電壓， 該第三電壓大於該第二電壓。 為讓本發明之上述和其他目的、特徵和優點能更明顯易 懂’下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 為了要節省液晶顯示面板的成本，一種整合於液晶面板上 的閘驅動電路(gate driver on array，簡稱GoA)已經被應用於液 晶顯示面板。也就是說，在此種GOA面板上直接製作一閘驅 ⑩動電路(gate driving circuit)，因此可以節省外購閘驅動電路的 成本。 §青參照第3圖，其所繪示為本發明G〇A面板上的問驅動 電路的第一實施例。閘驅動電路9〇〇包括多個移位暫存器 901〜90n+l。第一移位暫存器901接收起始信號START後會 產生一第一閘驅動信號G1以及一第一次級通知信號(n=t stage notification Signa卜NS1)。而第二移位暫存器9〇2接收第 一次級通知信號NS1後會產生一第二閘驅動信號G2以及一第 二次級通知信號NS2。 同理，以第η移位暫存器為例，而第n移位暫存器如〇 接收前一級的第η-1次級通知信號NSn4後會產生一第η閘驅 動信號Gn以及一第η次級通知信號N s η至下一級移位暫存器 (第η+1移位暫存器90n+l)。因此，所有的移位暫存器皆可根 據前一級的次級通知信號而產生閘驅動信號，並輸出次級通^ 信號至下一級的移位暫存器。 根據本發明的第一實施例，每一個移位暫存器皆接收互補 的二個時脈信號C1、C2、一第一電壓(Vgg)、一第二電壓( 再者’二個時脈信號a、C2的高準位電壓為第三電壓(㈣。 201220949 t 1 ;二第一電壓(Vgg)大於第三電壓(VCC)，且第三電壓(Vcc) 大於第一電壓(Vss)。再者，第一實施例的開驅動電路中 所有移位暫存II輸出的閘驅動信號的高準位電麗為第壓 (Vgg)，而次級通知信號的高準位為第三電壓(Vcc)。 移位ΐίίΐ4目，其所繪示為本發明的第—實施例的第η 2Γ。^。括一移位單元_與一轉壓器 移位早％ 910包括一上拉單元912、—下拉單元914、 體Γ、與一第二驅動電晶體Τ2。第一驅動電晶㈣ 晶體取極接收轉壓請的輸幻m j S生 第η閘驅動信號Gn。 度土 上拉單元910包括-電晶體T3，電晶體Τ3 2 級通知信號NSn· W及極接收第—時脈信號α。神， η二疋12係根據第n-1次級通知信號NSn]與第一時脈信號The object of the present invention is to provide a driving circuit for a liquid crystal panel, and the driving circuit is directly formed on the liquid crystal panel, which includes a plurality of shift register registers. 'Each displacement register includes a shifting unit. _ft _ and ^ converter, and the converter can generate a high high level voltage and output directly to the pixel array. The present invention provides a gate driving circuit that receives a first voltage, a second voltage, a complementary - a first clock signal, and a second clock signal, the first clock and the second clock. The high level of the signal is - the third voltage, and the gate driving circuit is a plurality of shift registers, and the nth shift register comprises: a first ^ crystal ^ has - gate receiving - the nth control signal is called the pole receiving, the one source output - the nth secondary notification signal; the second driving gate receives the 11th control signal, a source output - the nth - the underlevel Ϊ Γ ί ' a pull-up unit that receives an η-1th shift register of the η] shift register and a first clock signal; and 豸, the pull-up unit actuates the drive control to trust the first-drive The transistor and the second device: a pull-down unit, receiving the ηth control signal, the first clock signal; the signal, the second device's pull-down unit is in the pull-up J3: drive a transistor and the second driving transistor; and a second transistor of the second transistor, the gate receiving the second clock signal, the source a second transistor, the fourth transistor, the gate and the drain receive the first voltage, the 201220949 source is connected to the third transistor drain; a fifth transistor, the gate is connected to the second transistor a source, the source receives the second voltage, the drain is connected to the second driving transistor drain; and a sixth transistor, the gate and the drain receive the first voltage, and the source is connected to the fifth transistor a drain; wherein the first voltage is greater than a third voltage, and the third voltage is greater than the second voltage. The invention further proposes a gate drive circuit, comprising a plurality of shift register sequentially connected, wherein the odd shift register in the shift register receives a first voltage, a second voltage And a first clock signal, the even shift register in the shift register receives the first voltage, the second dust, and a second clock signal The two clock signals are complementary, and the high level of the first __ clock signal and the first clock signal is one or three voltages, and one shift register in the gate driving circuit includes: a first driving transistor Having a closed-pole receiving an η-th control signal, - secretly receiving the second clock signal, - source output knowing (4); - a second driving transistor having a - gate receiving the η-control number "- source a terminal output gate driving signal; a pull-up unit temporarily storing (10) - a η·1 her-1 signal; wherein, the pull-up unit is a second driving transistor; and the pull-down unit receives the η nd body number, the first Two voltages, the pull-down unit is in the pull-up unit = action 'and controls the n-th control signal to turn off the first: flute-IT: second drive transistor And a voltage converter comprising: - a gate receiving the second clock signal, a source receiving the second power Ϊ = 2 = '· 3 ΓΓ the first lag, the source is connected to the pole. Connected to the second driving transistor, the gate and the drain receive the first voltage, and the source is connected to the fifth transistor drain of 201220949; wherein the first voltage is greater than the third voltage The third voltage is greater than the second voltage. The above and other objects, features and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Embodiment] In order to save the cost of the liquid crystal display panel, a gate driver on array (GoA) integrated in the liquid crystal panel has been applied to the liquid crystal display panel. That is to say, a gate driving circuit is directly fabricated on such a GOA panel, so that the cost of the purchased gate driving circuit can be saved. § 青 Referring to Figure 3, there is shown a first embodiment of the drive circuit on the G 〇 A panel of the present invention. The gate drive circuit 9A includes a plurality of shift registers 901 to 90n+1. The first shift register 901 receives a start signal START and generates a first gate drive signal G1 and a first secondary notification signal (n = t stage notification Signa NS1). The second shift register 9〇2 receives a first secondary notification signal NS1 and generates a second gate drive signal G2 and a second secondary notification signal NS2. Similarly, taking the nth shift register as an example, and the nth shift register, for example, receiving the n-1th secondary notification signal NSn4 of the previous stage, a η gate drive signal Gn and a first The n secondary notification signal N s η to the next stage shift register (n+1 shift register 90n+1). Therefore, all the shift registers can generate the gate drive signal according to the secondary notification signal of the previous stage, and output the secondary pass signal to the shift register of the next stage. According to the first embodiment of the present invention, each shift register receives two complementary clock signals C1, C2, a first voltage (Vgg), and a second voltage (again, 'two clock signals a, the high level voltage of C2 is the third voltage ((4). 201220949 t 1 ; the second first voltage (Vgg) is greater than the third voltage (VCC), and the third voltage (Vcc) is greater than the first voltage (Vss). In the open driving circuit of the first embodiment, the high level of the gate drive signal of the shift temporary storage II output is the first voltage (Vgg), and the high level of the secondary notification signal is the third voltage (Vcc). Shifting ΐ ΐ ΐ ΐ , , , , ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位 移位The pull-down unit 914, the body Γ, and a second driving transistor Τ2. The first driving transistor (4) the crystal electrode receives the switching voltage, the η gate driving signal Gn. The soil pulling unit 910 includes - The transistor T3, the transistor Τ3 2 notification signal NSn·W and the pole receiving the first-clock signal α. God, η2疋12 is based on the n-1th secondary notification signal NSn] First clock signal
Pn T2。 莉电日日體T1與第二驅動電晶體 未動接收第η控制信號如，且於上拉單元912 電壓(Vs \ Ϊ皁兀914將第η控制信號Pn持續地保持在第二 預定時間週期(predetermined ti j^= 914會卜 下=一電壓(Vss)並持、續地保持在第二賴㈣。 脈信二早；:= 括:電晶體T4 ’間極與沒極接收第-時 電晶間極與沒極接收第二時脈信號α，且 η控制俨號Pn 晶體Τ4源極；電晶體T6閘極接收第 苹Η。戒Ρη，雜連接至電晶體丁4源極，源極接收第二電 201220949 壓(Vss)，電晶體T7閘極連接至電晶體τ4源極，沒極 控制信號Ρη，源極接收第二電 電晶體Τ4源極，汲極連接丄二Τ8 =連接至 、二：電體=接:第二電壓⑽)。 π 電日日體τιο閘極接收第二時脈作號Pn T2. The Lithium solar body T1 and the second driving transistor are not movably receiving the ηth control signal, for example, and are maintained at the voltage of the pull-up unit 912 (Vs Ϊ 兀 兀 914 continually maintaining the η control signal Pn for a second predetermined time period (predetermined ti j^= 914 will be = a voltage (Vss) and hold, continue to remain in the second (four). Pulse two early;: = include: transistor T4 'interpolar and immersed to receive the first - hour The intergranular pole and the poleless receive the second clock signal α, and the η controls the source of the PPn crystal Τ4; the gate of the transistor T6 receives the Η Η. Ρ η, the impurity is connected to the source of the transistor D 4, the source Receiving the second power 201220949 voltage (Vss), the transistor T7 gate is connected to the transistor τ4 source, the gate control signal Ρη, the source receiving the second transistor Τ4 source, the drain connection 丄2Τ8 = connected to, Two: electric body = connected: the second voltage (10)). π electric Japanese body τιο gate receives the second clock number
-=第二卿ss):電晶體T11間極與汲= 、聖（gg)’源極連接至電晶體T10沒極；一電晶體T 電晶體Τ10汲極，源極接收第二電壓(Vss)，汲極； 號0，·電晶體T13閘極錢極接收第一 源極連接至電晶體Τ12汲極。 米-^照f 5圖’其所緣示為本發明第n移位暫存器中的信 = 、中，第—時脈信號C1與第二時脈信號C2互補， 且其咼準位電壓為第三電壓(Vcc)。 於時間點tl時，第η·!次—級通知號施」以及第 ^作C1·^出—第三電壓(Μ的高準位，使得上拉單元 =作，:拉早元914不動作。此時，第n控制信號 開啟第-驅動電晶體Ή與第二驅動電晶體Τ2。 持姨2間點t2 ’第一驅動電晶體T1與第二驅動電晶體Τ2 寺、，開啟’並且第二時脈信號〇輸出—第三電壓(vee)的 立’使得第η次級通知信號NSn輸出—第三電壓(vee) ，。同時，轉壓器92G動作，使得電晶體T1 T=，因此輸出信號〇為第一電壓_的高準位電= n閘輸出㈣Gn即為第-電壓(Vgg)的高準位。 於時間點t3，上拉單元912不動作，下拉單元914動作。 在、*-驅動電晶體T1與第二驅動電晶體T2關閉。第η 9 201220949 次級通知㈣NSn與第n _^健Gn回復為第二電壓 (Vss)。 根據本發明第-實施例’閘驅動電路中移位暫存器 了移位單元_以及轉壓器92G，且轉壓器係位於閘驅動電ς 中的最後-級(stage) ’因此可以有效地降低功率損耗並且防 止閘驅動信號的失真。再者，本發明中的電晶體皆為相同型態 的N型⑽變晶體’因此可大幅簡化閘轉電路的設計與製 4乍0 請參照第6圖’其所綠示為本發明G〇A面板上的問驅動 電路的第二實施例1驅動電路·包括多個移位暫存器 951〜95n+卜第-移位暫存器951接收起始錢start後會 產生-第-閘驅動信號⑴以及—第—次級通知信號舰。而 第二移位暫存器952接收第一次級通知信號_後會產生一 第二閘驅動信號G2以及一第二次級通知信號NS2。 同理’以第η移位暫存器為例，而第n移位暫存器95n 接收前一級的第n-1次級通知信號ν%」後會產生一第n閘驅 動信號Gn以及一第η次級通知信號NSn至下一級移位暫^器 (第n+1移位暫存$ 95㈣）。因此，所有的移位暫存器皆可根 ，前-級的次級通知信號而產生閘驅動信號，並輸出次級通知 信號至下一級的移位暫存器。 根據本發明的第二實施例，奇數的移位暫存器接收第一時 ，信號c卜第一電壓(Vgg)、第二電壓(Vss);偶數的移位暫存 器接收第二時脈信號C2、第一電壓(Vgg)、第二電壓(Vss)。再 ，，二個時脈信號C卜C2為互補關係，且其高準位電壓為第 ^電壓(Vcc)。其中，第一電壓(Vgg)大於第三電壓(Vcc)，且 三電壓(Vcc)大於第二電壓(Vss)。再者，第二實施例的閘驅動 201220949 ίΪ 有移位暫存11輸^㈣軸錢的高準位電壓 (Vcc) 〇 gg)，而次級通知信號的高準位為第三電壓 移位胃’其所繪示為本發明的第二實施例的第η 匕枯上拉早凡962、一下赵置分Q64、 够 一驅動電晶體了1、與一第二驅動電晶體Τ2 =:= 信號C2,源極產生第-次級通=號： 第：：獅收轉壓器970的輸出信號。,源極產生 前一^^96G包括—電晶體Τ3 ’電晶體Τ3 _與汲極接收 」，的第η-1 :人級通知信號NSl>1。亦即， 信號勵.1來動作，而當上拉單 體2 ^至—第三電壓(Μ並賴啟第—驅動電晶 體丁1與第二驅動電晶體T2。 下拉單元964接收第η控制信號Pn，且於 =，下”元964將第n控一持續地 第 預定時間週期(predetermined time _⑽ 如轉換為第二電離吻並持續地保持在第二電壓⑽)n。J㈣ 計^單元964包括：電晶體丁4，間極與沒極接收第-時 脈_ C2 ;電晶體丁5閉極接收第η控制信 二=時 至電晶體T4源極，源極接收第二電壓(^ / 連接至電晶體T4源極，祕接收第n控制^^體T6 f極 第二電壓(Vss) ; f晶體T7閘極連接至電^極、5收 連接至第-驅動電細源極，源極接收 201220949 ! \ j T8閘極連接至電晶體T4源極，沒極連接至第二驅動電 晶體Τ2源極，源極接收第二電壓(Vss)。 轉壓器970包括·一電晶體T1〇間極接收第二時脈信號 極接收第二電壓(Vss);電晶體Tu閘極無極接收第 一電壓(Vgg)，源極連接至電晶體T1〇汲極；一電晶體 極連接至電晶體Τ10沒極，源極接收第二電壓(Vss)，沒極產 生輸出信號0 ;電晶體T13閘極與沒極接收第—電 源極連接至電晶體Τ12汲極。 請參照第8圖’其所繪示為本發明第η移位暫存器 號示，圖。其中，第-時脈信號C1與第二時脈信號c2 : 且其尚準位電壓為第三電壓(Vcc)。 齡於時’第η·1次'級通知號购輸出第三電 壓(Vcc)的南準位，使得上拉單元動作，下拉單元⑽ 動作。此時，第η控制信號Ρη可開啟第一驅動電晶體丁 ^ 二驅動電晶體Τ2。 於時間點t2 ’第-驅動電晶體T1與第二驅動電 持續開啟，並且第二時脈信號（：2輸出一第三電壓(Μ) 位’使得第η次級通知信號NSn輸出一第三電壓(Vcc) 位。同時，轉壓器970動作，使得電晶體T1〇開啟 Τ12關閉’因此輸出信號〇為第一電壓(Vgg)的高準位，: η閘輸出信號Gn即為第一電壓(Vgg)的高準位。 第 於時間點t3，上拉單元912不動作，下拉單元914 此時，第-驅動電晶體T1與第二驅動電晶體T2關閉。 次級通知信號腿與第η _出信號Gn回復為第二= (Vss)。 电您 根據本發明第二實施例，閘驅動電路中移位暫存器中整人 201220949 了移位單兀960以及轉壓器970 ’且轉壓器係位於閘驅動電路 中的最後-級(stage) ’ ϋ此可財效地降低功率損耗，並且防 止閘驅動彳§號的失真。再者，本發明中的電晶體皆為相同型態 的Ν型薄膜變晶體’因此可大幅簡化閘驅動電路的設計與製 作。-=Second Qing ss): The transistor T11 is connected to the 汲=, sheng (gg)' source is connected to the transistor T10 immersed; a transistor T transistor Τ10 汲, the source receives the second voltage (Vss ), bungee; No. 0, · Transistor T13 gate poles receive the first source connected to the transistor Τ12 drain. The m-^ according to the f 5 diagram' is shown in the nth shift register of the present invention as the letter =, the middle, the first clock signal C1 and the second clock signal C2 are complementary, and the 咼 level voltage Is the third voltage (Vcc). At time t1, the η·! times-level notification number is applied and the second is C1·^--the third voltage (the high level of Μ, so that the pull-up unit=make, the pull-up element 914 does not operate) At this time, the nth control signal turns on the first driving transistor Ή and the second driving transistor Τ2. The 姨2 point t2 'the first driving transistor T1 and the second driving transistor Τ2 temple, turn on 'and the The second clock signal 〇 output—the third voltage (vee) of the third voltage (vee) causes the nth secondary notification signal NSn to output a third voltage (vee). At the same time, the transducer 92G operates such that the transistor T1 T=, thus The output signal 〇 is the high level of the first voltage _ = n gate output (4) Gn is the high level of the first voltage (Vgg). At the time point t3, the pull up unit 912 does not operate, and the pull down unit 914 operates. *-The driving transistor T1 and the second driving transistor T2 are turned off. The η 9 201220949 secondary notification (4) NSn and the nth _^ Gn return to the second voltage (Vss). According to the first embodiment of the present invention, the gate drive circuit The shift register has a shift unit _ and a voltage converter 92G, and the converter is located at the last stage of the gate drive ' In order to effectively reduce the power loss and prevent the distortion of the gate drive signal. Furthermore, the transistors in the present invention are all of the same type of N-type (10) crystals, thus greatly simplifying the design and manufacture of the gate-turn circuit. Referring to FIG. 6 'the green display is the second embodiment 1 driving circuit on the G 〇 A panel of the present invention. The driving circuit includes a plurality of shift registers 951 〜 95n + 卜 - shift register 951 After receiving the start money start, a -first-gate drive signal (1) and a --second notification signal ship are generated, and the second shift register 952 receives a first secondary notification signal_, and generates a second gate drive. The signal G2 and a second secondary notification signal NS2. Similarly, the nth shift register is taken as an example, and the nth shift register 95n receives the n-1th secondary notification signal ν% of the previous stage. Then, a nth gate drive signal Gn and an nth secondary notification signal NSn are generated to the next stage shift register (the n+1th shift register is $95 (four)). Therefore, all the shift registers are a root, pre-stage secondary notification signal generates a gate drive signal and outputs a secondary notification signal to the next stage of the shift According to the second embodiment of the present invention, when the odd shift register receives the first, the signal c is the first voltage (Vgg), the second voltage (Vss); the even number of shift registers are received. The second clock signal C2, the first voltage (Vgg), and the second voltage (Vss). Further, the two clock signals Cb and C2 are in a complementary relationship, and the high-level voltage is the voltage (Vcc). Wherein, the first voltage (Vgg) is greater than the third voltage (Vcc), and the three voltages (Vcc) are greater than the second voltage (Vss). Furthermore, the gate drive of the second embodiment 201220949 Ϊ has a shift temporary storage 11 (4) The high-level voltage of the axis (Vcc) 〇 gg), and the high-level of the secondary notification signal is the third voltage-shifted stomach, which is depicted as the η of the second embodiment of the present invention. Pull the early 962, the next Zhao set the Q64, enough to drive the transistor 1, and a second drive transistor Τ2 =:= signal C2, the source produces the first-second pass = number::: lion turn The output signal of the voltage converter 970. The source is generated by the first ^^96G including - transistor Τ 3 'transistor Τ 3 _ and drain receiving ”, the η-1: human level notification signal NS1 > That is, the signal excitation .1 acts, and when the pull-up unit 2 ^ to - the third voltage (Μ 赖 第 驱动 - drive transistor 1 1 and the second drive transistor T2. Pull-down unit 964 receives the η control The signal Pn, and the lower, lower ue 964 will be the nth control for a predetermined predetermined period of time (predetermined time _ (10) if converted to the second ionization kiss and continuously maintained at the second voltage (10)) n. J (four) count unit 964 Including: transistor D4, interpole and immersed receiving the first-clock _C2; transistor □5 closed-pole receiving the η control letter two = to the source of the transistor T4, the source receives the second voltage (^ / connection To the source of the transistor T4, secretly receive the nth control ^^ body T6 f pole second voltage (Vss); f crystal T7 gate is connected to the electrode, 5 is connected to the first-drive electric source, source Receive 201220949 ! \ j T8 gate is connected to the source of transistor T4, the gate is connected to the source of the second driver transistor Τ2, and the source receives the second voltage (Vss). The converter 970 includes a transistor T1〇 The interpole receives the second clock signal to receive the second voltage (Vss); the transistor Tu gate infinitely receives the first voltage (Vgg), and the source is connected to the transistor T1 Bungee pole; one transistor is connected to the transistor Τ10, the source receives the second voltage (Vss), and the output signal 0 is not generated; the transistor T13 gate and the immersed terminal are connected to the transistor Τ12 Please refer to FIG. 8 , which is a diagram showing the nth shift register of the present invention, wherein the first-clock signal C1 and the second clock signal c2 are: The third voltage (Vcc) is the south level of the third voltage (Vcc) when the 'nth-first-order' notification number is purchased, so that the pull-up unit operates and the pull-down unit (10) operates. The control signal Ρn can turn on the first driving transistor to drive the transistor Τ2. At the time point t2′, the first driving transistor T1 and the second driving power are continuously turned on, and the second clock signal (:2 output is a third The voltage (Μ) bit is such that the nth secondary notification signal NSn outputs a third voltage (Vcc) bit. At the same time, the voltage converter 970 operates such that the transistor T1 〇 turns on Τ 12 off 'so the output signal 〇 is the first voltage ( The high level of Vgg), the η gate output signal Gn is the high level of the first voltage (Vgg). T3, the pull-up unit 912 does not operate, and the pull-down unit 914 at this time, the first driving transistor T1 and the second driving transistor T2 are turned off. The secondary notification signal leg and the nth_out signal Gn are restored to the second = (Vss) According to the second embodiment of the present invention, in the gate drive circuit, the shift register is in the whole person 201220949, the shift unit 960 and the converter 970', and the converter is located in the last stage of the gate drive circuit. (stage) ' This can effectively reduce power loss and prevent distortion of the gate drive. Furthermore, the transistors in the present invention are all of the same type of germanium-type thin film crystals', so that the design and fabrication of the gate driving circuit can be greatly simplified.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明’任何熟習此技藝者，在;j；脫離本發明之精神和範圍 内’虽可作些許之更動錢飾，因此本發明之賴額當視後 附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖所緣7F為f知液晶面板及其相關控制電路示意圖。 第2A圖所繪示為習知液晶顯示系統相關控制電路示意圖。 第2B圖所繪示為習知轉壓器實際電路示意圖。" 第3圖所繪示為本發明G〇A面板上的閘轉電路的第一實施 第4圖所％示為本發明的第—實施例的第n移位暫存器。 構示為本發明第η移位暫存器中的信號示意圖。 =圖所繪示為本發明G〇A面板上的_動電路的第二實施 110轉壓器 125不可視區域 220閘驅動電路 【主要元件符號說明】 100液晶面板 120可視區域 210時間控制器 201220949 230 源驅動電路 300 像素陣列 400 閘驅動電路 500 源驅動電路 600 信號控制器 700 轉壓器 800 灰階電壓產生器 900 閘驅動電路 901〜90n+l 移位暫存器 910 移位單元 912 上拉單元 914 下拉單元 920 轉壓器 950 閘驅動電路 951〜95n+l 移位暫存器 960 移位單元 962 上拉單元 964 下拉單元 970 轉壓器Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is not intended to limit the scope of the invention. The scope of the invention is defined by the scope of the patent application. [Simple description of the drawing] Fig. 1 is a schematic diagram of the liquid crystal panel and its related control circuit. FIG. 2A is a schematic diagram showing a related control circuit of a conventional liquid crystal display system. Figure 2B is a schematic diagram showing the actual circuit of a conventional converter. " Fig. 3 is a view showing the first embodiment of the gate-turn circuit on the G〇A panel of the present invention. Fig. 4 is a view showing the nth shift register of the first embodiment of the present invention. The signal is a schematic diagram of a signal in the nth shift register of the present invention. = The figure shows the second implementation of the _ moving circuit on the G 〇 A panel of the present invention. 110 The voltage converter 125 invisible area 220 brake driving circuit [Main component symbol description] 100 liquid crystal panel 120 visible area 210 time controller 201220949 230 Source drive circuit 300 pixel array 400 gate drive circuit 500 source drive circuit 600 signal controller 700 converter 800 gray scale voltage generator 900 gate drive circuit 901~90n+1 shift register 910 shift unit 912 pull-up unit 914 pull-down unit 920 converter 950 gate drive circuit 951~95n+l shift register 960 shift unit 962 pull-up unit 964 pull-down unit 970 converter
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