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TW201220203A - Integrator circuit with inverting integrator and non-inverting integrator - Google Patents

Integrator circuit with inverting integrator and non-inverting integrator Download PDF

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Publication number
TW201220203A
TW201220203A TW100116489A TW100116489A TW201220203A TW 201220203 A TW201220203 A TW 201220203A TW 100116489 A TW100116489 A TW 100116489A TW 100116489 A TW100116489 A TW 100116489A TW 201220203 A TW201220203 A TW 201220203A
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Taiwan
Prior art keywords
capacitor
circuit
operational amplifier
potential
inverting
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TW100116489A
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Chinese (zh)
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TWI466028B (en
Inventor
Oh-Jin Kwon
Il-Hyun Yun
Seon-Woong Jang
Hyung-Cheol Shin
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Zinitix Co Ltd
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G06F3/038Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Position Input By Displaying (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Electronic Switches (AREA)

Abstract

A switched capacitor integrator circuit is disclosed. The switched capacitor integrator circuit comprises an inverting switched capacitor integrator circuit, and a non-inverting switched capacitor integrator circuit connected to the inverting switched capacitor integrator circuit. A sampling capacitor of the inverting switched capacitor integrator circuit is shared by the non-inverting switched capacitor integrator circuit.

Description

201220203 六、發明說明: 【發明所屬之技術領域】 本發明是有關於一種積分器電路(integrator circuit), 且特別是有關於一種抗雜訊(noise-robust)之積分器電路0 【先前技術】 諸如液晶顯示器(liquid crystal display)及有機發光 顯示器(organic light emitting display)之顯示裝置、可攜 式通訊裝置(portable communication device)、及資訊處理 裝置等是利用各種輸入裝置來執行其功能。作為一種此類 輸入裝置,觸控螢幕(touchscreen)裝置廣泛用於可攜式 電話、智慧型電話(smartphone)、掌上型(palm_size) pc 及自動櫃貝機(automated teller machine,ATM)中。 觸控螢幕藉由使手指、觸摸筆(tGueh pen)或尖筆 (_s)觸摸其螢幕以進行文字寫人或繪畫來執行所期望 之命令,並藉由選擇圖符(ieGn)來執行程式碼。觸控榮 幕裝置可錢手指或·筆衫已觸碰於其表面上,並判 斷觸碰位置。 j type)觸控螢 電阻式觸控勞幕之配置是將且㈣^ 測觸摸點。電阻式觸控螢it電阻之變化來感 赏I之侷限性在於,當觸摸壓力較 201220203 X|/lf 弱時,其不能夠感測觸摸輸入。 電容式觸控螢幕可藉由在玻璃或透明塑膠板之兩側或 一侧上形成電極來提供。電容式觸控螢幕可藉由以下方式 偵測觸摸點:在兩個電極之間施加電壓,然後在諸如手指 之物體觸摸其螢幕時,分析此二電極之間電容的變化。 電容式觸控螢幕需要具有一種用於量測在一個電極處 或兩個電極之間所形成之電容之電路才能感測一觸摸點。 此種電容量測電路一直主要用於量測各種電路或裝置之電 容。然而,由於各種可攜式裝置現在提供觸摸輸入介面’ 故用於感測使用者之觸摸或接近(proximity)之電容量測 電路之應用範圍正在擴大。 典型的可攜式電話之觸控螢幕所用之電容量測電路之 偈限性在於,周圍環境之變化所造成之各種雜訊會引起故 障(malfunction )。 【發明内容】 [技術問題] 本發明之貫施例提供電容式抗雜訊積分器電路以及使 用所述積分器電路中之一的輸入感測電路。 [解決問題之手段] 本發明提供一種抗雜訊之積分器電路。 本發明亦提供一種使輸入感測誤差減少的方法,所述 方法藉由對用於感測觸控螢幕輸人之感測器區塊(_沉 block)使用所述抗雜訊積分器電路來減少因觸摸輸入所產 生之雜訊而造成之輸入感測誤差。 4 201220203 很骤本叙明乙ί<5抓,死饮一稷槓分器電路巴秸: 第一運算放大器;第二運算放大器;以及電容器。所述第 一運算放大器與所述第二運算放大器之反相輸入端子被配 置成分別經由第一開關與第二開關而連接至所述電容器之 第一端子。所述電容器之第二端子被配置成分別經由第三 開關與第四開關而連接至第一電位與第二電位。所述第一 ,算放大器之所述反相輸人端子與輸出端子被配置成經由 第-反饋電容器而相互連接,所述第二運算放大器之所述 反相輸入端子與輸出端子則被配置成經由第二反饋電容器 而相互連接。且所述第-運算放大器與所述第二運算放^ 器之非反相輸入端子被配置成連接至第三電位。 所述第三電位可相同於所述第二電位。 ΐ 一重設關可被配置成與第—反饋電容器並聯地連 接於第-運异放大器之反相輸入端子與輸出端子之間,且 戶!己置成與第二反饋電容器並聯地連接於 第·^心之反相f人端子與輸出端子之間 所iil第:門二二=述第三開關可由第—時脈驅動,且 所述:開關與所述第四開關可由第二時脈驅動。 所u脈與所述第二時 (on-mterval)可交替地顯示於時 ^ 接通間隔之-部分與第二時脈 帛嫌之这些 同時出現。另-選擇為,之:可 處於接通狀態時,另-者可處於斷開狀ίτ械其尹之一 所述電容器可由形成於電容式觸控^中 201220203 jojyiyii 及驅動圖案形成。 所述電容器之兩個端子中連接至所述第一運算放大器 及所述第二運算放大器的一個端子可對應於所述感測圖 案。 . 所述感測圖案可相較於所述驅動圖案而設置於所述觸 控螢幕之外側。換言之,所述感測圖案可設置成較所述驅 動圖案更靠近諸如手指之類的觸摸物體。 所述電容器之兩個端子中連接至所述第一運算放大器 及所述第二運算放大器的一個端子可為藉由纜線或無線而 輸入之雜訊之流入路徑。 根據本發明之另一態樣,提供一種電容式觸控螢幕之 輸入感測電路,在所述電容式觸控螢幕中形成有感測圖案 及驅動圖案。所述輸入感測電路包括:第一運算放大器; 以及第二運算放大H 〇所述感酬案被配置成分 -開關而連接至所述第一運算放All之反相輸人端子、以 及經由第二開_連接至所述第二運算放大器之反相輸入 端子,。所述驅動ϋ案被配置成分別經由第三開關與第四開 關而連接至第-電位與第二電位。所述第—運算放大器之 7述反相輸入端子與輸出端子被配置成經由第一反饋電容 器而相互連接,且所述第二運算放大器之所述反相輸入端 子與,出端子經由第二反饋電容H而相互連接。且所述第 :運:放大器與所述第二運算放大器之非反相輸入端子連 接至第三電位。 j< 所述第1關與所述第三開關可由第一時脈驅動,且 6 201220203 所述第二開關與所述第四開關由第二時脈驅動。 。。根據本發明之又_態樣,提供—種開關電容器式積分 !!^路°所述開關電容器式積分器電路包括:反相開關電 夺器式積分器電路;以及非反相開關電容器式積分器電 路’其連接至所述反相開關電容器式積分器電路。所述反 相開關電容11式積分器電路之取樣電容H被所述非反相開 關電谷器式積分器電路共用。 j述反相開關電容器式積分器電路可對充電於所述取 樣電谷器中之電荷進行時間積分,以輸出負電壓,且所述 ,反相開_容器式積分H電路可對充電於所述取樣電容 器中之電荷進行時間積分,以輸出正電壓。 所述反相開關電容器式積分器電路之積分時間間隔之 至-部分可不交疊於所述非反相開關電容g式積分器電 路之積分時間間隔。 所述取樣電容器可由形成於電容式觸控螢幕中之感測 圖案與驅動圖案形成。 。所述取樣電容器之兩個端子中連接至所述反相開關電 容器式積分n·與所述非反相關電容器式積分器電路 的-個端子可為藉由、纜線或無線而輸人之雜訊之流入路 徑。 根據本發明之再-態樣,提供-種積分器電路。所述 積分器電路包括:電容器;充電/放電電路,連接至所述電 容器,以對所述電容器進行充電/放電;反相積分器電路, 連接至所述充電/放電電路;以及非反相積分器電路,連接 201220203 至所述充電/放電電路。 所述反相積分器電路可姐 進行時間積分,轉ib貞於所述電容11中之電荷 可對充電於所述電容器中非反相積分器電路 電壓。 之電何進仃時間積分’以輸出正 &所23可由形成於電容式觸控榮幕中之感測圖案 與驅動圖案形成。 所兩個端子中連接至所述反相積分器電路 與所述非反補分㈣路的―個軒可為藉㈣線或無線 而輸入之雜訊之流入路經。 所述反相積分器電路之積分時間間隔之至少一部分可 不交疊於所述非反相積分器電路之積分時間間隔。 所述電谷益之兩個端子中連接至所述第一運算放大器 及所述第二運算放大器的—個端子可對應於所述感測圖 案。 所述感測圖案可相較所述驅動圖案而設置於所述觸控 螢幕之外側。 根據本發明之另一態樣,提供一種積分器電路。所述 積分器電路包括:第一運算放大器;第二運算放大器;以 及電谷器。所述第一運算放大器與所述第二運算放大器之 反相輸入端子被配置成分別連接至所述電容器之第一端 子。所述第一運算放大器之所述反相輸入端子與輸出端子 被配置成經由串聯連接之第一反饋電容器與第一開闕而相 互連接,且所述第二運算放大器之所述反相輸入端子與輸 201220203 出端子則經由串聯連接之第二反饋電容器與第二開關而相 互連接。所述電容器之第二端子被配置成分別經由第三開 •關與第四開關而連接至第一電位與第二電位。且所述第一 運异放大H與所述第二運算放大II之非反相輸人端子連接 至第三電位。 所述第三電位可相同於所述第二電位。 第一重設(reset)開關可被配置成與第一反饋電容器並 聯地連接於第-運算放大H之反相輸人端子與輸出端子之 間且第一重设開關可被配置成與第二反饋電容器並聯地 連接於所述第二運算放大||之反相輸人端子與輸出端子之 間。 [本發明之有利效果] 、根據本發明之一實施例,當利用來自開關電容器式積 /刀器電路之輸出時,可減_訊積分效應(⑽ise_i tion effect)。 結^附圖閱讀下文的說明,可更詳細地理解本發明之 實例丨生貫施例。201220203 VI. Description of the Invention: [Technical Field] The present invention relates to an integrator circuit, and more particularly to a noise-robust integrator circuit 0 [Prior Art] Display devices such as liquid crystal displays and organic light emitting displays, portable communication devices, and information processing devices perform various functions using various input devices. As such an input device, a touchscreen device is widely used in a portable telephone, a smart phone, a palm_size pc, and an automated teller machine (ATM). The touch screen executes a desired command by touching a screen with a finger, a tJeh pen or a stylus (_s) to perform a written call or a drawing, and executes the code by selecting an icon (ieGn). . The touch screen device can touch the surface of the finger or the pen and judge the touch position. j type) Touch Firefly The configuration of the resistive touch screen is to measure the touch point. The limitation of the resistive touch strobe resistance is that the touch is not able to sense the touch input when the touch pressure is weaker than 201220203 X|/lf. Capacitive touch screens can be provided by forming electrodes on either or both sides of a glass or transparent plastic sheet. A capacitive touch screen can detect a touch point by applying a voltage between two electrodes and then analyzing the change in capacitance between the two electrodes when an object such as a finger touches its screen. Capacitive touch screens require a circuit for measuring the capacitance formed at one electrode or between two electrodes to sense a touch point. Such capacitance measuring circuits have been mainly used to measure the capacitance of various circuits or devices. However, as various portable devices now provide a touch input interface, the range of applications for sensing the touch or proximity of a user is expanding. The limitation of the capacitance measuring circuit used in the touch screen of a typical portable telephone is that various noises caused by changes in the surrounding environment may cause a malfunction. [Disclosure] [Technical Problem] A permeation embodiment of the present invention provides a capacitive anti-noise integrator circuit and an input sensing circuit using one of the integrator circuits. [Means for Solving the Problem] The present invention provides an anti-noise integrator circuit. The present invention also provides a method for reducing input sensing error by using the anti-noise integrator circuit for a sensor block (_sink block) for sensing a touch screen input. Reduce input sensing errors caused by noise generated by touch input. 4 201220203 Very sudden description of the ί & 5 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 死 第一 第一The inverting input terminals of the first operational amplifier and the second operational amplifier are configured to be coupled to a first terminal of the capacitor via a first switch and a second switch, respectively. The second terminal of the capacitor is configured to be coupled to the first potential and the second potential via the third switch and the fourth switch, respectively. The first, the inverting input terminal and the output terminal of the amplifier are configured to be connected to each other via a first feedback capacitor, and the inverting input terminal and the output terminal of the second operational amplifier are configured to be They are connected to each other via a second feedback capacitor. And the non-inverting input terminal of the first operational amplifier and the second operational amplifier is configured to be connected to a third potential. The third potential may be the same as the second potential. ΐ A reset can be configured to be connected in parallel with the first feedback capacitor between the inverting input terminal and the output terminal of the first-transmission amplifier, and the user has been placed in parallel with the second feedback capacitor. ^ The inversion of the heart between the human terminal and the output terminal iil: door 22 = the third switch can be driven by the first clock, and the switch: the switch and the fourth switch can be driven by the second clock. The u-pulse and the second-time (on-mterval) are alternately displayed at the same time as the portion of the on-interval interval and the second clock. Another - select as: it can be in the on state, the other can be in the disconnected state. One of the capacitors can be formed in the capacitive touch ^ 201220203 jojyiyii and the drive pattern. One of the two terminals of the capacitor connected to the first operational amplifier and the second operational amplifier may correspond to the sensing pattern. The sensing pattern may be disposed on an outer side of the touch screen compared to the driving pattern. In other words, the sensing pattern can be placed closer to a touch object such as a finger than the driving pattern. One of the two terminals of the capacitor connected to the first operational amplifier and the second operational amplifier may be an inflow path of noise input by a cable or wireless. According to another aspect of the present invention, an input sensing circuit for a capacitive touch screen is provided, in which a sensing pattern and a driving pattern are formed. The input sensing circuit includes: a first operational amplifier; and a second operational amplification H 〇 the sensing component is configured to be a switch-connected to the inverting input terminal of the first operational amplifier All, and The second open_ is connected to the inverting input terminal of the second operational amplifier. The drive mode is configured to be coupled to the first potential and the second potential via the third switch and the fourth switch, respectively. The inverting input terminal and the output terminal of the first operational amplifier are configured to be connected to each other via a first feedback capacitor, and the inverting input terminal and the output terminal of the second operational amplifier are via a second feedback The capacitors H are connected to each other. And the first amplifier and the non-inverting input terminal of the second operational amplifier are connected to a third potential. j< The first switch and the third switch may be driven by the first clock, and 6 201220203 the second switch and the fourth switch are driven by the second clock. . . According to another aspect of the present invention, a switched capacitor type integrated circuit is provided. The switched capacitor type integrator circuit includes: an inverting switch power repeller type integrator circuit; and a non-inverting switched capacitor type integral. The circuit 'connects to the inverted switched capacitor integrator circuit. The sampling capacitor H of the inverting switched capacitor 11 integrator circuit is shared by the non-inverting switching gate type integrator circuit. The reverse-phase switched capacitor-type integrator circuit can time-integrate the charge charged in the sampling grid to output a negative voltage, and the inverting open-container-type integral H circuit can be charged The charge in the sampling capacitor is time integrated to output a positive voltage. The integral portion of the integration time interval of the inverting switched capacitor integrator circuit may not overlap the integration time interval of the non-inverting switched capacitor g integrator circuit. The sampling capacitor may be formed by a sensing pattern and a driving pattern formed in the capacitive touch screen. . One of the two terminals of the sampling capacitor connected to the reverse-phase switched capacitor type integral n· and the non-reverse-correlation capacitor type integrator circuit may be mixed by cable, wireless or wireless The inflow path of the news. According to a re-state of the invention, an integrator circuit is provided. The integrator circuit includes: a capacitor; a charge/discharge circuit coupled to the capacitor to charge/discharge the capacitor; an inverting integrator circuit coupled to the charge/discharge circuit; and a non-inverting integral The circuit is connected to 201220203 to the charging/discharging circuit. The inverting integrator circuit can perform time integration, and the charge in the capacitor 11 can be charged to the non-inverting integrator circuit voltage in the capacitor. The electric power is integrated into the time integral ', and the output positive & 23 can be formed by the sensing pattern and the driving pattern formed in the capacitive touch screen. The "one" of the two terminals connected to the inverting integrator circuit and the non-reverse sub-fourth circuit may be an inflow path of the noise input by the (four) line or wireless. At least a portion of the integration time interval of the inverting integrator circuit may not overlap the integration time interval of the non-inverting integrator circuit. One of the two terminals of the electric valley that is connected to the first operational amplifier and the second operational amplifier may correspond to the sensing pattern. The sensing pattern may be disposed on an outer side of the touch screen compared to the driving pattern. According to another aspect of the present invention, an integrator circuit is provided. The integrator circuit includes a first operational amplifier, a second operational amplifier, and a battery. The inverting input terminals of the first operational amplifier and the second operational amplifier are configured to be coupled to a first terminal of the capacitor, respectively. The inverting input terminal and the output terminal of the first operational amplifier are configured to be connected to each other via a first feedback capacitor connected in series with a first opening, and the inverting input terminal of the second operational amplifier The output terminal of the 201220203 is connected to the second switch via a second feedback capacitor connected in series. The second terminal of the capacitor is configured to be coupled to the first potential and the second potential via the third on and off and the fourth switch, respectively. And the first differential amplification H and the non-inverting input terminal of the second operational amplification II are connected to a third potential. The third potential may be the same as the second potential. The first reset switch may be configured to be connected in parallel with the first feedback capacitor between the inverting input terminal and the output terminal of the first operational amplification H and the first reset switch may be configured to be second The feedback capacitor is connected in parallel between the inverting input terminal and the output terminal of the second operational amplifier ||. [Advantageous Effects of Invention] According to an embodiment of the present invention, when an output from a switched capacitor type tool/cutter circuit is utilized, the (10)ise_i tion effect can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS The examples of the present invention can be understood in more detail by reading the following description.

Jr檑為讓本發明之上述和其他目的、特徵和優點能更明顯 下文特舉較佳實施例,並配合所附圖式,作詳細說 明如下。 、111 【實施方式】 β 、下將參照附圖來描述本發明之某些實施例。儘管 ^具體實施例來描述本發明,然而,本發明之範圍並 义於此。因此,熟習此項技術者將易於理解,可在不 201220203 •/Vd/ a μ/暴The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. 111. Embodiments Certain embodiments of the present invention will be described below with reference to the accompanying drawings. Although the invention has been described in terms of specific embodiments, the scope of the invention is intended to be Therefore, those skilled in the art will be easy to understand, but not in 201220203 •/Vd/ a μ/

明中, 明中,技術用語僅用於解釋具體實例性實施例, 。在下文的說 外,而非用於 限制本發明。料有說縣,單細彡式之縣亦可包含複 數开4式。 圖1繪示觸控螢幕裝置, 本發明之實施例。 所述觸控螢幕裝置用於應用 如圖1所示,所述觸控螢幕裝置可包括觸控面板(t〇uch panel) 1、電谷量測電路200及觸摸破定部件3〇〇。 觸控面板1可包括多條感測信號線WD、乃、.、 ❼以及多條驅動信號線刀、及、_«、·..、石^,這些感測 信號線Γ/、;Κ2、Π、...、作與驅動信號線尤/、;^2、χ3、、 办被形成為相互絕緣。為方便起見,感測信號線與驅動信 號線在圖1中被顯示為線,但實際上可被實施為電極圖 案。術語「感測信號線」可與術語「感測線」及「感測電 極」互換使用,且術語「驅動信號線」可與術語「驅動線」 及「驅動電極」互換使用。在圖1中,顯示所述多條感測 信號線與驅動信號線相互絕緣並相交,但本發明並非僅限 於此。視具體實施方案而定,這些感測信號線與驅動信號 線可不彼此相交。 用來表示觸摸點之感測節點(sensing node ) 110可被 定義為一條感測信號線與一條驅動信號線之組合,且每一 感測節點110均包括節點電容器112。節點電容器112可 由相互絕緣且分離之感測信號線與驅動信號線形成。在圖 201220203 1中,將由第ζ·條驅動信號線與第y條感測信號線形成之節 點電容器112之電容表示為q·。 電容量測電路200電性連接至所述多條感測信號線 17、D、乃、…、仏以及驅動信號線刃、义2、、…、 办’以量測節點電容器112之電容q·。 該觸摸確定部件300根據由電容量測電路200所量測 之節點電容器112之電容來分析電容變化,以感測使用者 所觸摸之觸摸點。 圖2繪示圖1之觸控螢幕装置之實例。 圖2是概念性的配置圖,用於描述整個觸控螢幕裝置 中被直接觸摸之觸控螢幕面板的操作以判斷物體是否進行 觸摸輸入。感測圖案100及驅動圖案101可由導電材料形 成,並電性連接至觸控螢幕驅動電路及其他在判斷是否存 在觸摸輸入時所將使用之元件。因此,可根據感測圖案1〇〇 及驅動圖案101之形狀而提供各種觸控螢幕面板。介電層 102可設置於感測圖案100與驅動圖案1〇丨之間。因此, 由導電材料形成之感測圖案100與驅動圖案1〇1可與其間 之介電層102 —起形成電容器。可於感測圖案1〇〇上形成 保護視窗103,以保護該感測圖案1〇〇、驅動圖案1〇1及介 電102。當一觸摸物體處於保護視窗1〇3上或附近時,感 測圖案100與驅動圖案101間之電容可發生變化。 圖3是圖2之觸控螢幕裝置之概念性的配置圖之平面 視圖。 圖3同時繪示感測圖案1〇〇與驅動圖案ι〇1。 201220203 jsjyipif 在觸控螢幕裝置中可形成多個寬的矩 1〇1。當施加電壓至驅動圖案1〇1時,在感測^圖案 動圖案101之間便產生電場。感測圖案1〇〇旦與驅 圖案101為窄之形狀。因此,當施加電壓二較驅動 時,感測圖案100不能完全覆蓋驅動圖案1〇1。 ,1〇1 動圖案101流動至感測圖案100。當出現觸模 2自驅 述電場之至少一部分流動至觸摸物體,換古之别告時,所 摸輸入時,電場會發生變化。因此,在感二圖幸=現觸 動圖案101之間形成之電場會隨觸摸輸入而7。°^與驅 此種變化導致在感測圖案100與驅動圖案1〇1 。電場之 電容發生變化。感測器可感測此電容值以·^形成之 摸輸入。 疋否具有觸 為便於說明及清楚起見,圖3之圖案是 種電極圖案之-實例。應理解,本發 j = 僅限於此。 卿及圍並非 圖4是沿圖3中的線203戴取之剖視圖。 參見圖4,當在保護視窗1〇3上方由電場(即,虛線) 所佔據之區域中進行觸摸輸入時,因經由所述區域進入感 測圖案100之電場路徑之至少一部分發生變化,故在電容 器中積聚之電荷之總量相較於無觸摸輸入時減少。因此, 若感測到驅動圖案1〇1與感測圖案1〇〇間之電容減小’則 可確定已在此點發生觸摸輸入。 至此,已描述了用於判斷是否對觸控螢幕進行觸摸輸 入之原理中的一種。現在,將描述用於量測電容變化的本 12 201220203 JMyipif 發明之某些實施例。 、.圖5是_示根據本發明實施例之驅動電路之示意圖, 所述驅動電路可用於驅動觸控螢幕。 如圖5所示’驅動電路1〇可包括充電/放電電路Μ、 ^貝JaH牛12及電谷器q。因「感測部件」12具有積分功 故其在本說明書中可被稱為「積分部件」。充電/放電 1路11可電性連接至電容器C(;.之兩個端子,以作為用於 ,電容器ce電至電源電壓^以及將電容器c"放電至 ,電壓(ground voltage) 之電路。在下文中,「電容 器ci/·」可被稱為「取樣電容器(samplingcapacit〇r)」。 若使用驅動電路10來驅動一觸控螢幕,則圖5之電容 ,G可對應於上文所述之節點電容器112。換言之,電容 =A可電性連接至驅動信號線%·及感測信號線々,且充 放電電路11可重複進行W次充電/放電操作。 雜訊可經由感測信號線}y而被輸入至圖5之驅動電 路。在此種情形中,感測部件12可對雜訊進行積分,進而 不利地影響感測部件12之輸出。以下,將描述根據本發明 實施例之抗雜訊積分器之配置。 圖6繪示根據本發明實施例之積分器之配置。 參見圖6 ’所述積分器包括第一運算放大器〇A1、第 二運算放大器0A2及電容器(¾。第一運算放大器〇A1與 第一運真放大器〇A2之反相輸入端子分別經由第一開關 S1與苐一開關S2而連接至電容器q·之第一端子)y。電容 器Ci;/之第一端子沿經由第三開關S1’而連接至第一電位 13 201220203In the present disclosure, the technical terms are only used to explain specific example embodiments. It is to be understood that the following is not intended to limit the invention. It is said that the county has a county, and the county with a single type can also include a plurality of types. 1 illustrates a touch screen device, an embodiment of the present invention. The touch screen device is used for application. As shown in FIG. 1 , the touch screen device may include a touch panel, a valley measuring circuit 200 and a touch breaking component 3 . The touch panel 1 may include a plurality of sensing signal lines WD, 、, ., ❼, and a plurality of driving signal line cutters, and, _«, . . . , stone, these sensing signal lines Γ /, Κ 2 Π, ..., and the drive signal lines 尤 /, ; ^ 2, χ 3, , are formed to be insulated from each other. For the sake of convenience, the sensing signal line and the driving signal line are shown as lines in Fig. 1, but may actually be implemented as an electrode pattern. The term "sensing signal line" is used interchangeably with the terms "sensing line" and "sensing electrode", and the term "driving signal line" is used interchangeably with the terms "drive line" and "drive electrode." In Fig. 1, the plurality of sensing signal lines and the driving signal lines are shown insulated from each other and intersected, but the present invention is not limited thereto. Depending on the implementation, these sense signal lines and drive signal lines may not intersect each other. A sensing node 110 for indicating a touch point can be defined as a combination of one sensing signal line and one driving signal line, and each sensing node 110 includes a node capacitor 112. The node capacitor 112 may be formed of a sensing signal line and a driving signal line which are insulated and separated from each other. In Fig. 201220203, the capacitance of the node capacitor 112 formed by the second strip driving signal line and the yth sensing signal line is expressed as q·. The capacitance measuring circuit 200 is electrically connected to the plurality of sensing signal lines 17, D, y, ..., 仏 and the driving signal line edge, meaning 2, ..., to measure the capacitance of the node capacitor 112. . The touch determination component 300 analyzes the capacitance change based on the capacitance of the node capacitor 112 measured by the capacitance measuring circuit 200 to sense the touch point touched by the user. FIG. 2 illustrates an example of the touch screen device of FIG. 1. Figure 2 is a conceptual configuration diagram for describing the operation of a touch screen panel that is directly touched in the entire touch screen device to determine whether an object is touch input. The sensing pattern 100 and the driving pattern 101 may be formed of a conductive material and electrically connected to the touch screen driving circuit and other components that are to be used in determining whether a touch input exists. Therefore, various touch screen panels can be provided according to the shapes of the sensing patterns 1A and the driving patterns 101. The dielectric layer 102 may be disposed between the sensing pattern 100 and the driving pattern 1A. Therefore, the sensing pattern 100 formed of a conductive material and the driving pattern 101 can form a capacitor together with the dielectric layer 102 therebetween. A protection window 103 may be formed on the sensing pattern 1 to protect the sensing pattern 1 驱动, the driving pattern 1 〇 1 and the dielectric 102. When a touch object is on or near the protection window 1〇3, the capacitance between the sensing pattern 100 and the driving pattern 101 may vary. 3 is a plan view of a conceptual configuration diagram of the touch screen device of FIG. 2. FIG. 3 simultaneously shows the sensing pattern 1〇〇 and the driving pattern ι〇1. 201220203 jsjyipif can form multiple wide moments 1〇1 in the touch screen device. When a voltage is applied to the driving pattern 1〇1, an electric field is generated between the sensing patterns 101. The sensing pattern 1 and the driving pattern 101 have a narrow shape. Therefore, when the applied voltage two is driven, the sensing pattern 100 cannot completely cover the driving pattern 1〇1. The 1〇1 moving pattern 101 flows to the sensing pattern 100. When the touch mode 2 appears to drive at least a part of the electric field to the touch object, the electric field changes when the input is touched. Therefore, the electric field formed between the sense map and the current touch pattern 101 will follow the touch input. This change results in the sensing pattern 100 and the driving pattern 1〇1. The capacitance of the electric field changes. The sensor can sense the capacitance value to form a touch input.疋 No touch For the sake of illustration and clarity, the pattern of Figure 3 is an example of an electrode pattern. It should be understood that the present j = is limited to this. And not shown in Fig. 4 is a cross-sectional view taken along line 203 in Fig. 3. Referring to FIG. 4, when a touch input is made in an area occupied by an electric field (ie, a broken line) above the protection window 1〇3, at least a part of the electric field path entering the sensing pattern 100 via the area changes, The total amount of charge accumulated in the capacitor is reduced compared to when there is no touch input. Therefore, if the capacitance reduction between the driving pattern 1〇1 and the sensing pattern 1〇〇 is sensed, it can be determined that the touch input has occurred at this point. So far, one of the principles for judging whether or not to touch input to the touch screen has been described. Some embodiments of the present invention for measuring capacitance changes will now be described. FIG. 5 is a schematic diagram showing a driving circuit according to an embodiment of the present invention, and the driving circuit can be used to drive a touch screen. As shown in Fig. 5, the 'driving circuit 1' may include a charging/discharging circuit Μ, a JaJaH 12 and an electric yoke q. Since the "sensing member" 12 has an integration function, it may be referred to as an "integral member" in this specification. The charging/discharging 1 channel 11 can be electrically connected to the two terminals of the capacitor C (.. as a circuit for discharging the capacitor ce to the power supply voltage ^ and discharging the capacitor c" to the ground voltage. In the text, "capacitor ci/." may be referred to as "sampling capacitor". If the driver circuit 10 is used to drive a touch screen, the capacitance of Figure 5, G may correspond to the node described above. Capacitor 112. In other words, the capacitance=A can be electrically connected to the driving signal line %· and the sensing signal line 々, and the charging and discharging circuit 11 can repeat the charging/discharging operation for W times. The noise can be via the sensing signal line}y And input to the driving circuit of Fig. 5. In this case, the sensing part 12 can integrate the noise, thereby adversely affecting the output of the sensing part 12. Hereinafter, the anti-aliasing according to an embodiment of the present invention will be described. Figure 6 illustrates the configuration of an integrator in accordance with an embodiment of the present invention. Referring to Figure 6 'the integrator includes a first operational amplifier 〇A1, a second operational amplifier OA2, and a capacitor (3⁄4. amplification反相A1 and the inverting input terminal of the first operational amplifier 〇A2 are respectively connected to the first terminal y of the capacitor q· via the first switch S1 and the first switch S2. The first terminal of the capacitor Ci; Three switches S1' are connected to the first potential 13 201220203

Rc,並經由第四開關S2f而連接至第二電位GM)。在下文 中,為方便起見,假定第二電位GWD為零。第一運算放 大器OA1之反相輸入端子及輸出端子可經由第一反饋電 容器ς如而相互連接。第二運算放大器OA2之反相輸入端 子與輸出端子可經由第二反饋電容器 <:开2而相互連接。第 一運算放大器ΟΑ1與第二運算放大器ΟΑ2之非反相輸入 端子可連接至第三電位。第三電位可為地電位GM),儘管 其並非僅限於此。 一個重設開關S3可連接於第一運算放大器ΟΑΐ之反 相輸入端子與輸出端子之間。重設開關S3,可連接於第二 運算放大器ΟΑ2之反相輸入端子與輸出端子之間。當重設 開關S3與S3接通時,被充電於第一反饋電容器匸加與第 二反饋電容器C介2中之電荷全部放電,進而使兩個端子間 之電壓為0。根據本發明之某些實施例,該重設開關S3與 S3可以相同之時序(tjming)來運作。 開關S1及S1’與開關S2及S2’可分別根據圖7(a)中第 ^時脈CLK1與圖7(b)巾第二時脈CLK2之時序而同步進 行開關。然而’本發明並非僅限於此。 圖7(a)至圖7(e)是時序圖,其顯示圖6之積分器之每 一節點狀態隨時間之變化。 圖7⑷顯示開關S1及S1,之通斷(〇n_〇ff)時序。圖 7(b)顯示開關S2及S2,之通斷時序。圖7(物示第二端子 力之電位。® 7(d)繪示第一運算放大胃〇Αι之輸出電壓 〇1圖7(e)續'示第二運算放大器OA2之輸出電壓厂。2。 201220203 圖7(a)及圖7(b),開關si及SI,與開關S2及S2, 非交暨之時間間隔中可交替地處於接通狀態。換言之, =關si及S1,可在時間間_,⑵及[u,,中處於ς通狀 ,,而在時間間隔[t2,tr]中處於斷開狀態。開關幻及幻, 可,時間間隔[t3,t4]及[t3,,t4,]中處於接通狀態,而在時間 間隔[t4, t3’]中處於斷開狀態。可連續地重複開關S1及si, 與開關S2及S2,在時間間隔[tl,tr]中之運作狀態。在圖7⑷ 〜圖7(e)中,時間間隔[t2, t3]及[t4, tl,]不為零,但可被實 質上設定為接近於零。 <在本說明書之下文中,可將緊處於t時刻之前的時刻 稱為「t-」’並將緊處於t時刻之後的時刻稱為「计」。舉例 而言,可將緊處於tl時刻之前的時刻稱為「tl_」,並將緊 處於tl時刻之後的時刻稱為「tl+」。在下文中,將參照圖 8至圖10,所示積分器之運作狀態圖來描述根據本發明實 施例之積分器在圖7(a)〜圖7(e)所示每一時間點之運作。 圖8至圖10是運作狀態圖,其分別繪示所述積分器在 圖7(a)〜圖7(e)之tl+時刻、圖7(a)〜圖7(幻之t2+時刻及 t4+時刻、以及圖7⑻〜圖7(e)之t3+時刻處之運作。此時, 假定電容器(:如、(:片2及c0.皆在tl-時刻處放電,即,所有 電容器中之初始狀態皆為零累計電荷。 參見圖7(a)〜圖7(e)及圖8,在tl+時刻處,開關si 及Slf處於接通狀態,開關S2及S2Aj處於斷開狀態。電 容器(¾之第一端子?>·連接至第一運算放大器0A1之反相 輸入端子。此後’因第一運算放大器OA1之非反相輸入端 201220203 子連接至1電位咖,故第—舒^仙同 二電位。容器•之第二端子&之電位為第一電位 fcc’故電容器q·之兩個端子間之電位差相同於第 Vcc。 、电 因流經電容器Q之電流將流經第—反饋電容器 故第-運算放大器OA1之輸出端子Ql處之電位^如方 程式1所示。 ’ [方程式1] 第一端子?/處之電位保持於第二電位GjvD,且第二 運算放大S GA2之輸㈣孩之電位亦保持於第二電位 GND。 在下文中,假定藉由N次積分來完成一個積分循環 (integration cycle )’則在新積分循環開始之後剛剛完成第 灸-入積分時’ f-運算放大器〇A1之輸出端子〇1處的電 位可表示為。 參見圖7⑻〜圖7(e)及圖9,開關si及S1,是開關S2 及S2在t2+時刻皆處於斷開狀態。電容器乂兩個端子 ^.^差保持成相同於第-電位Fee。此時,儘管第一端 々·與第二端子沿處於浮動狀態(fl〇ating state),為方 便,見’在圖7C及圖7D中仍將第一端子料之電位表 示為第二電位。 201220203 OOJi/iplf 參見圖7⑷〜圖7(e)及圖1〇,在t3+時刻,開關S1及 S1,處於斷開狀態,且開關52及幻,處於接通狀態。第二端 子石處之電位立刻變為第二電位GM),且第一端子&處 =電位立刻變為-4。因第-端子P連接至第二運算放大 器0A2之反相輸人端子’故第—端子&•處之電位迅速升 高至第二電位GM)。因在第—端子位立刻發生 變化之時關隔中’電流自第二運算放大器〇A2之輸 子流出並對第二反網容n W騎充電,故第二運算放 大器0A2之輸出端子〇2處之電位匕"如方程式2所示。 [方程式2]Rc is connected to the second potential GM) via the fourth switch S2f. Hereinafter, for the sake of convenience, it is assumed that the second potential GWD is zero. The inverting input terminal and the output terminal of the first operational amplifier OA1 can be connected to each other via, for example, a first feedback capacitor. The inverting input terminal and the output terminal of the second operational amplifier OA2 are connectable to each other via a second feedback capacitor <: open 2. The non-inverting input terminals of the first operational amplifier ΟΑ1 and the second operational amplifier ΟΑ2 are connectable to a third potential. The third potential can be the ground potential GM), although it is not limited thereto. A reset switch S3 is connectable between the inverting input terminal and the output terminal of the first operational amplifier 。. The reset switch S3 is connectable between the inverting input terminal and the output terminal of the second operational amplifier ΟΑ2. When the reset switches S3 and S3 are turned on, the charges charged in the first feedback capacitor plus the second feedback capacitor C are all discharged, and the voltage between the two terminals is zero. According to some embodiments of the invention, the reset switches S3 and S3 can operate at the same timing (tjming). The switches S1 and S1' and the switches S2 and S2' can be synchronously switched in accordance with the timing of the second clock CLK1 in Fig. 7(a) and the second clock CLK2 in Fig. 7(b), respectively. However, the invention is not limited thereto. Figures 7(a) through 7(e) are timing diagrams showing the state of each node of the integrator of Figure 6 as a function of time. Figure 7 (4) shows the on/off (〇n_〇ff) timing of switches S1 and S1. Figure 7(b) shows the switching sequence of switches S2 and S2. Figure 7 (Material shows the potential of the second terminal force. ® 7 (d) shows the output voltage of the first operational amplification stomach 〇Α 〇 1 Figure 7 (e) continued 'shows the output voltage of the second operational amplifier OA2. 2 201220203 Figure 7 (a) and Figure 7 (b), the switches si and SI, and the switches S2 and S2, can be alternately in the on-time interval. In other words, = off si and S1, can be Inter-time _, (2) and [u,, are in a ς-like state, and are in an open state in the time interval [t2, tr]. Switching illusion and magic, can, time interval [t3, t4] and [t3, , t4,] is in the on state, and is in the off state in the time interval [t4, t3']. The switches S1 and si can be continuously repeated, and the switches S2 and S2 are in the time interval [tl, tr] The operating state. In Figures 7(4) to 7(e), the time intervals [t2, t3] and [t4, tl,] are not zero, but can be substantially set to be close to zero. Hereinafter, the time immediately before the time t is referred to as "t-"', and the time immediately after the time t is referred to as "meter." For example, the time immediately before the time t1 may be referred to as "". Tl_", and will be tight The time after the time t1 is called "tl+". Hereinafter, the integrator according to the embodiment of the present invention will be described with reference to FIGS. 8 to 10, which are shown in FIG. 7(a) to FIG. (e) Operation at each time point shown in Fig. 8 to Fig. 10 are operational state diagrams, respectively showing the integrator at time t1 of Fig. 7(a) to Fig. 7(e), Fig. 7 (a ) ~ Figure 7 (Magic t2+ time and t4+ time, and Figure 7 (8) ~ Figure 7 (e) t3 + time operation. At this time, assume capacitors (: such as, (: slice 2 and c0. are at tl-time) Discharge, that is, the initial state of all capacitors is zero cumulative charge. Referring to Figure 7 (a) ~ Figure 7 (e) and Figure 8, at time t1 +, switches si and Slf are in the on state, switch S2 and S2Aj is in the off state. The capacitor (the first terminal of 3⁄4?) is connected to the inverting input terminal of the first operational amplifier 0A1. Thereafter, the non-inverting input terminal 201220203 of the first operational amplifier OA1 is connected to the 1-potential. Coffee, so the first - Shu ^ Xian with two potential. The second terminal of the container · & the potential is the first potential fcc 'the power between the two terminals of the capacitor q · The difference is the same as the Vcc. The current flowing through the capacitor Q will flow through the first feedback capacitor, so the potential at the output terminal Q1 of the operational amplifier OA1 is as shown in Equation 1. '[Equation 1] First terminal The potential of the / / is maintained at the second potential GjvD, and the potential of the second operational amplification S GA2 (4) is also maintained at the second potential GND. In the following, it is assumed that an integration cycle is completed by N integrations (integration cycle) ) 'The potential at the output terminal 〇1 of the f-OR amplifier 〇A1 can be expressed as just after the start of the new integral cycle. Referring to Figures 7(8) to 7(e) and Figure 9, switches si and S1 are switches S2 and S2 that are in an open state at time t2+. The difference between the two terminals of the capacitor ^ ^.^ is kept the same as the first potential Fee. At this time, although the first terminal 与· and the second terminal are in a floating state, it is convenient to see that the potential of the first terminal material is shown as the second potential in FIGS. 7C and 7D. 201220203 OOJi/iplf Referring to Fig. 7(4) to Fig. 7(e) and Fig. 1〇, at time t3+, switches S1 and S1 are in an off state, and switches 52 and phantom are in an on state. The potential at the second terminal rock immediately becomes the second potential GM), and the potential at the first terminal & = immediately becomes -4. Since the first terminal P is connected to the inverting input terminal of the second operational amplifier 0A2, the potential at the first terminal & • rapidly rises to the second potential GM). When the first terminal bit changes immediately, the current flows from the output of the second operational amplifier 〇A2 and the second reverse network capacity n W rides, so the output terminal 第二2 of the second operational amplifier 0A2 The potential 匕" is shown in Equation 2. [Equation 2]

^3,1 = - ~iL^3,1 = - ~iL

Lfb2 重新參見圖7⑷〜圖7(e)及圖9,在t4+時刻, =與開關S2及S2,皆處於斷開狀態。電容器q之兩個 ^子間之電位差變為零。此時,第—端子V與第 石處於浮動狀態(flGating state),但為方便起見,在^ 中仍將第—端子V處之電位表示為第二電(位) ^將在執棚8至圖1G所述操作時之時__ 疋義為-個循環’則所述循環可盾 :間’因被充電於第一反饋電容器〜與第二=電: 广之電荷未放電,故第一運算放大器〇A1之 ; d之電位匕與第二運算放大器〇A2之輸出端子〇2出= 17 201220203 位分別如圖7(e)及圖7(f)所示升高及降低。當iv次循 環完成時’藉由將電位匕減去電位而獲得之值 可被表示為方程式3。 [方程式3] =+心 |-(為.¾) = +2Wcc.SiLfb2 Referring back to Fig. 7(4) to Fig. 7(e) and Fig. 9, at time t4+, = and switches S2 and S2 are all in the off state. The potential difference between the two sub-substitutes of the capacitor q becomes zero. At this time, the first terminal V and the first stone are in a floating state (flGating state), but for the sake of convenience, the potential at the first terminal V is still expressed as the second electrical (bit) in ^^ will be in the booth 8 When the operation is as shown in FIG. 1G, __ 疋 为 is a cycle, then the cycle can be shielded: between 'because being charged to the first feedback capacitor ~ and the second = electricity: the charge is not discharged, so the first An operational amplifier 〇A1; the potential 匕 of d and the output terminal 第二2 of the second operational amplifier 〇A2 = 17 201220203 bits are raised and lowered as shown in Fig. 7(e) and Fig. 7(f), respectively. The value obtained by subtracting the potential from the potential 当 when iv cycles are completed can be expressed as Equation 3. [Equation 3] = + heart | - (for .3⁄4) = +2Wcc.Si

Cfb 在此種情形中,假定第一反饋電容器c加與第二反饋 電谷器具有相同之值。 參見方程式3,因第一反饋電容器與第二反饋電容器 之值Cyj可具有恆定值,故可以看出,值正比於電容器 Cy之值。 當將圖6之積分器應用於觸控螢幕驅動電路時,由於 在存在觸摸輸入時電容器q·之值發生變化,因而可量測電 容器•之電谷作為對該值」F之量測,並因而可判斷曰否 存在觸摸輸入。 在完成N次積分循環並量測出該值dp後,可將重μ 開關S3及S3'變為接通狀態,以對第一反饋電容器及第一 反饋電容器之所有電荷進行放電。藉此,若將電容器匸 之W次充電/放電所用之時間定義為一個積分循環,^ y 設開關S3及S3’改變成接通狀態之後,可重新開始新的積 201220203 祛\。。此’已參照圖6至圖10描述了根據本發明實施例之 7刀器之操作。然而’如在圖5中所述,雜訊可能會流入 積分器之第一端子}7。 舉例而言’倾述積分H用作觸錢幕驅動電路時, ”訊可餐第—端子}7而流人觸控登幕驅動電路中。換言 =上述感測圖案100可對應於電容器^^之第一端子乃·。 =如手指之類的物體被置於感測圖案^附近以進行觸 模輸入時,雜訊可流入第一端子G中。 根據® 6巾之本發明實施例,财有效地;肖除雜訊輸 =在下文中,將參照圖U⑻〜圖_至圖14⑻〜圖_ 來描述消除的原理。 明音Ξ U⑷〜圖U(f)至圖14⑷〜圖14(f)是繪示根據本發 明實施例來消除積分器之雜訊輸人之原理的圖式。 ,本上,經第-端子Yj輸人之雜訊可被積分後加至第 :運;放大器㈤及第二運算放大器OA2之輸出電壓 ㈣運异放大㈣A1僅於_S1及S1,處於接通狀 siiiir進ΐ積分’而第二運算放大器〇A2貝,j僅於開關 幻及S2處於接通狀態時對雜訊進行積分。 形。圖11⑻〜圖繪示輪入僅具有Dc分量之雜訊的情 間點2圖圓_,在第一時脈CLK1的包括時 !被積分後加至第-運算放大器㈤之輸出電雜 右將在每一接關隔中被積分後加讀出電位&_訊 19 201220203 之大小定義為為,从(W,2 環中被積分後加至第一 … ^在一個積分循 雜訊之大4S °A1,電位匕的 [方程式4] 工 ΙλλγCfb In this case, it is assumed that the first feedback capacitor c is added to have the same value as the second feedback grid. Referring to Equation 3, since the value Cyj of the first feedback capacitor and the second feedback capacitor can have a constant value, it can be seen that the value is proportional to the value of the capacitor Cy. When the integrator of FIG. 6 is applied to the touch screen driving circuit, since the value of the capacitor q· changes when there is a touch input, the electric valley of the capacitor can be measured as the measurement of the value “F”, and Therefore, it can be judged whether or not there is a touch input. After the N integration cycles are completed and the value dp is measured, the heavy μ switches S3 and S3' can be turned on to discharge all the charges of the first feedback capacitor and the first feedback capacitor. Thereby, if the time for charging/discharging the capacitor 匸 is defined as an integration cycle, and the switches S3 and S3' are changed to the ON state, the new product 201220203 祛\ can be restarted. . This has been described with reference to Figs. 6 through 10 for the operation of the 7-blade according to an embodiment of the present invention. However, as described in Figure 5, noise may flow into the first terminal of the integrator}7. For example, when the "pointing point H" is used as the touch screen driving circuit, the "meeting meal-terminal} 7 is used in the touch screen driving circuit. In other words, the above sensing pattern 100 can correspond to the capacitor ^^ The first terminal is ·. = When an object such as a finger is placed near the sensing pattern ^ for touch input, noise may flow into the first terminal G. According to the embodiment of the invention, the financial Effectively; omitting noise transmission = hereinafter, the principle of elimination will be described with reference to Fig. U(8) to Fig. 14 to Fig. 14(8) to Fig. _. 明 Ξ U(4) to U(f) to Fig. 14(4) to Fig. 14(f) are A diagram illustrating the principle of eliminating the noise input of the integrator according to an embodiment of the present invention. In this case, the noise input by the first terminal Yj can be integrated and added to the first: operation; amplifier (5) and The output voltage of the second operational amplifier OA2 (4) is different from the amplification (4) A1 is only in _S1 and S1, and is in the siiiir input integral and the second operational amplifier 〇A2, j is only when the switch is magical and S2 is in the on state. The noise is integrated. Figure 11. (8) ~ Figure shows the round point of the scene with only the Dc component of the noise point 2, in the first time Included in the pulse CLK1! The output is added to the output of the first operational amplifier (5). The output is mixed in each of the junctions and then the read potential &_19 19202020 is defined as W, 2 is added to the first ring and then added to the first... ^ In the case of an integral harmonic signal 4S °A1, the potential 匕 [Equation 4] Ιλλγ

Al ~ Al,nl + AUn2 + Λ1>η3 + ... + Λ h.. r ⑽的包括時間點似㈣,厂 運算放大器QA2“/電^^雜!;被積分後加至第二 中被積分後加至輸κ ^雜:將在每-接通間隔 (^7,,, 二€位匕的雜机之大小定義為心 第m二二)’則在一個積分循環中被積分後加至 _ :運纽大器OA2之輸出電位^的雜訊之 不為方程式5。 [方程式5] 七=42λ1 + i42,„2十Ain3 +…十心必 藉由一同考慮所積分雜訊之影響,方程式3可變成方 ^式6。換言之’藉由在完成財循環後自電位。減去 電位而獲得之值」K可表示為方程式&。 [方程式6] 20 201220203 = +2NVCC + ~αλ cff>Al ~ Al, nl + AUn2 + Λ1 > η3 + ... + Λ h.. r (10) includes the time point (4), the factory operational amplifier QA2 "/ electric ^ ^ miscellaneous!; is integrated and added to the second After the integral is added to the input κ ^ miscellaneous: will be defined in each interval - (^7,,, the two 匕 匕 杂 之 定义 定义 m ) ) ) ) ) ) ) ) ) ) ) ) ) ' ' ' ' ' ' ' ' ' ' ' ' To _ : The noise of the output potential of the OA2 is not Equation 5. [Equation 5] Seven = 42λ1 + i42, „2 ten Ain3 +... Ten hearts must consider the influence of the integrated noise together Equation 3 can be changed to square 6. In other words, by self-potential after completing the financial cycle. The value obtained by subtracting the potential "K" can be expressed as the equation & [Equation 6] 20 201220203 = +2NVCC + ~αλ cff>

^NVCC^NVCC

II

NN

'^1,nfc)'^1,nfc)

^2tnk ^ A Ι,ηΚ 進而,當雜訊僅真有DC分量時,因方程式 實質上得到滿足’故方程式6可表示為方程式7 [方程式7] AV=^2NVcc.^l-hA2-Ai^2tnk ^ A Ι, ηΚ Further, when the noise only has a DC component, the equation is substantially satisfied. Therefore, Equation 6 can be expressed as Equation 7 [Equation 7] AV=^2NVcc.^l-hA2-Ai

LfbLfb

NN

=撕cUd-D fb 2c=l = +2¾. Si= tear cUd-D fb 2c=l = +23⁄4. Si

Lfb 因此,利用根據本發明實施例之積分器,可 有DC分量之雜訊。 秒矛'僅: 圖12(a)〜圖12(f)繪示當提供低頻雜訊輸入 實施例之運作。 町个赞 第:時脈CLK1與第二時脈CLK2之運作 運> 頻,可分別稱為Γ及介哪。圖12⑻〜圖12雜 週』相較於運作週期Γ非常長之情形。在此種开^,) :積2中每一積分循環之積分伽等於二. 母積刀#環中,雜訊僅行進一個循環。 在圖I2(a)〜圖_中,藉由自電位、減去電> 21 201220203 ipif 而得到之值亦可表 〜圖12(f)所示不且有 程式6。當雜訊如圖12(a) 程式足方 之輸出電位^的雜訊之大小“ 算放大iiOAi 至第二運算放大器⑽ 7 /乎抵消在被積分後加 (n^0)。因此n的雜訊之大小七 第-時脈及第二時脈之運作頻於 圖13(a)〜圖不會衫響该值’。 時脈CLK1乃笛-# 在所輸入之雜訊具有與第一 圖=:第;:=之運作頻率相同之頻率時的 數iv等於14,且在中每一積分循環之積分次 次。 母積刀楯環中,雜訊循環亦重複14 r 13(f)中’藉由自電位。減去電位 料表示為絲式6。衫二時脈 放大恶712乂之間隔中被積分後加至第二運算 一Γ^ΓΐΛ電位K°2的雜訊之大小^相同於在第 -,$二匕含時間點似之間隔中被積分後加至第 =算放大器ΟΑ1之輪出電位〜的雜訊之大小‘。然 =積77後加至輪丨電位^的誠之符號與被積分後 至3出電位Fe/的雜訊之符號相反。換言之,形成方程 以r⑷〜_之情形中,方 [方程式8] 22 201220203 &V-+2NV^b+Az~Al =郷 +2NVcc^ + 2aLfb Thus, with the integrator according to an embodiment of the invention, there can be noise of the DC component. Second Spear 'only: Figures 12(a) through 12(f) illustrate the operation of the embodiment when providing low frequency noise input. The town has a praise: the operation of the clock CLK1 and the second clock CLK2, the frequency, can be called Γ and 介. Fig. 12(8) to Fig. 12 are very long compared to the operating cycle. In this open ^,): product 2, the integral gamma of each integral cycle is equal to two. In the parent product knife # ring, the noise only travels one cycle. In Fig. I2(a) to Fig. _, the value obtained by self-potential, minus electric power > 21 201220203 ipif can also be expressed as shown in Fig. 12(f). When the noise is as shown in Fig. 12(a), the size of the noise of the output potential ^ of the program foot "calculates the amplification of iiOAi to the second operational amplifier (10) 7 / cancels the addition of (n^0) after being integrated. Therefore, the miscellaneous of n The size of the message is seven - the clock and the second clock are operated at a frequency of Figure 13 (a) ~ the figure will not ring the value '. Clock CLK1 is the flute - # in the input noise has the same figure =: The frequency of the ::= is the same frequency, the number iv is equal to 14, and the integral of each integral cycle is in the second. In the parent product, the noise cycle is repeated in 14 r 13(f) 'Through the self-potential. Subtracting the potential material is expressed as wire type 6. The size of the noise of the second operation is added to the second operation, and the noise of the potential K°2 is the same. In the period of the -, $2, including the time-point interval, it is added to the size of the noise of the round-throw potential of the first amplifier=1. Then, the product is added to the rim potential ^. The sign is opposite to the sign of the noise that is integrated to the potential of Fe/3. In other words, in the case where the equation is r(4)~_, [Equation 8] 22 201220203 & V-+2NV^b+Az~Al =郷+2NVcc^ + 2a

Lfb 如此一來’圖13(a)〜圖13(f)之雜訊便被移除。 圖14(a)〜圖14(f)是繪示積分器電路中每一積分循環 之積分次數iV等於14、且每一積分循環中雜訊循環被重複 15次之圖式。Lfb is thus removed. The noise of Figure 13(a) to Figure 13(f) is removed. 14(a) to 14(f) are diagrams showing that the integration number iV of each integration cycle in the integrator circuit is equal to 14, and the noise cycle is repeated 15 times in each integration cycle.

ol,N 在,14(a)〜圖14(f)中,藉由自電位減去電位 ,而得到之值亦可表示為方程式6。在圖14(a)〜圖 形中’對於方程式6而言不滿足々,山,但 ^刀後加至第—運算放大器OA1之輸出電位^的雜訊 之】4可&乎抵賴積分後加至第三運算放大器⑽ =2=大“2 (叫一七。)。假 正弦波雜二二Ϊ分次數#為#’則當經端子17而輸入 環中被謝次u為除心::1之循環在母-積分循 本發= 電積分器電路來實質=時’可_ 之輪入被定:響應,財f路區域P2 P2之輸出被定義為藉由自帛二運^之電位、且電路區域 子之電位L減去第—運算放 3㈣之輸出端 匕而獲得之值。圖15給^ 之輸出端子之電位 、,曰不根據本發明實施例在頻域 23 201220203p (frequency domain)中之雜訊移除特性,而圖u(a)〜圖 11(f)至圖14⑻〜圖14(f)繪示在時域(time加腹^)中之 雜訊移除特性。 圖15繪示當一積分循環之積分次數#等於1〇時之實 例。參見圖15 ’可以看出,空響應(null resp〇nse)之頻 率點之數目為10,包括頻率響應曲線中位於峰值頻率 50,000赫茲以下之DC頻率。 如參照圖15所可理解者,當將驅動頻率!·設定為足夠 高時,因圖6所示電路區域P2之雜訊通帶(pass_band) 與在壤j兄中頻繁出現之臨界雜訊頻帶(critical noise band) 相隔大的頻率間隙(frequency gap ),故有利於移除這些雜 訊。具有大於100V之HUM雜訊及其諧波是臨界雜訊之實 例。 對於如上所述滿足方程式6之情形,可根據方程式6 來計算電容器CV之值,如方程式9所表示。 [方程式9] 當電容器(¾之值發生變化時,便可判斷是否已發生觸 摸事件。 在下文中,描述以下情形:根據本發明實施例的圖6 之電路被配置成包括反相積分器電路及非反相積分器電 路。 24 201220203 圖16(a)至圖16(d)繪示可用於本發明實施例之反相積 分器電路的實例。圖16(a)繪示自圖6所示電路移除第二運 算放大器0A2後之電路。可以理解,圖6之電路包括與圖 16(a)所示者實質上相同之反相積分器電路,乃因圖6之開 關S2經由第二運算放大器〇A2之反相輸入端及非反相輸 入端而連接至第二電位GM),而圖16(a)之開關S2則直接 連接至第二電位。 圖16(b)、圖16(c)及圖16(d)繪示當圖16⑷之反相積 分益電路具有根據圖7(a)〜圖7(b)或圖11(a)〜圖11(b)所 示第一時脈CLK1及第二時脈CLK2之開關時序時,分別 在tl+時刻、t2+及t4+時刻、以及t3+時刻之運作狀態。藉 由將圖16(b)、圖16(c)及圖16(d)分別與圖8、圖9及圖10 相比較’亦可以看出,圖6之電路包括與圖i6(a)至圖16(d) 所示者實質上相同之反相積分器電路。 圖16(a)至圖16(d)之電路可被稱為反相開關電容器式 積分器電路(inverting switched capacitor integrator circuit) ° 圖17(a)至圖17(d)繪示可用於本發明實施例之非反相 積分器電路之實例。圖17⑷綠示自圖6之電路移除第一運 算放大器OA1後之電路。可以理解,圖6之電路包含與圖 17(a)至圖17(d)所示者實質上相同之非反相積分器電^, 乃因圖6之開關S1經由第一運算放大器〇A1之反相輸入 端子及非反相輸入端子而連接至第二電而圖17(幻 之開關si則直接連接至第二電位。 25 201220203 JO lpif 圖17(b)、圖17(c)及圖17(d)繪示當圖17⑷之非反相 積分器電路具有根據圖7(a)〜圖7(b)或圖11(a)〜圖11(b) 所示第一時脈CLK1及第二時脈CLK2之開關時序時,分 別在tl+時刻、t2+及t4+時刻、以及t3+時刻之運作狀態。 藉由將圖17(b)、圖17(c)及圖17(d)分別與圖8、圖9及圖 10相比較’亦可以看出,圖6之電路包括與圖17⑷至圖 17(d)所示者實質上相同之非反相積分器電路。 圖17⑷至圖17⑷之電路可被稱作非反相開關電容器 式積分器電路(non-inverting switched capacitor integrator circuit)。 作為對圖6、圖16(a)至圖16(d)及圖17⑷至圖17(d) 之概述,根據本發明實施例之積分器電路是藉由將非反相 積分器電路與反相積分器電路相耦合而獲得,所述非反相 積分器電路與反相積分器電路共用電容器q·以及用於對 電容器CI;/•進行充電/放電之充電/放電電路。 充電/放電電路可對應於圖6之電路區域pi、圖16⑷ 至圖16⑹之電路區域P3以及圖i7(a)至圖17(d)之電路區 域P4。 圖18⑷至圖18(d)繪示根據本發明另一實施例之積分 器電路。 圖18⑻繪示可將圖16⑻至圖16⑹之積分器電路描述 為多個電路模組(例如第一充電/放電電路na與第一積 分部件12-1)之整合。第一充電/放電電路對應於圖 16⑷至圖16⑹之電路區域P3,且第一積分部件12-1對應 26 201220203 於圖16(a)至圖16(d)中第一運算放大器OA1、第—反饋電 容器與第三開關S3之組合。 圖18(b)繪示可將圖16⑷至圖16(d)之積分器電路描述 為多個電路模組(例如第二充電/放電電路11_2與第二積 分部件12-2)之整合。第二充電/放電電路u_2對應於圖 17(a)至圖17(d)之電路區域Ρ4,且第二積分部件12_2對應 於圖17⑻至圖17(d)中第二運算放大器0Α2、第二反饋^ 容器ς阳與第三開關組合。 圖18(c)可藉由將圖18(a)之電路與圖18(b)之電路相整 合而獲得。充電/放電電路11對應於圖6中之電路區域Pl, 第一積分部件12-1對應於圖6中第一運算放大器〇A1、第 一反饋電容器C^7及第三開關S3之組合,且第二積分部件 12-2對應於圖6中第二運异放大器〇A2、第二反饋電容器 及第三開關組合。 圖19繪示根據本發明另一實施例之積分器電路。 圖19所示電路以與圖6相對照之方法方式來實施作為 本發明實施例的圖18(c)之電路。然而,可易於理解者,當 由圖8或圖11(a)〜圖11(b)之第一時脈CLK1及第二時脈 CLK2來驅動開關S1及S1,與開關S2及S2,時,所述電路 執行與圖6所示者相同之操作。 在圖6及圖19中,開關S1設置於所述電路中是用於 在開關S2r處於接通狀態時將第一運算放大器〇A1與電容 器隔離。相比之下,開關S2設置於所述電路中是用於 在開關sr處於接通狀態時將第二運算放大器〇A2與電容 27 201220203 器c&·隔離。 圖16(a)至圖16(d)及圖17⑷至圖17⑷繪示反相放大 器與非反相放大器之實例。儘管在本說明中未揭露,然而 ,理解,具有圖18(a)至圖18(d)所示配置之積分器電路是 藉由使具有不_置之反減鱗反相放大器相搞合 而獲得,此’本發明之精神及朗並非僅限於本文所揭 露之具體電路。 信/ιΛ2, t圖2G_示作為執行模擬之結果而輸出之 值=在所述模擬中,對圖6之電路應用圖u⑷〜圖 :第-時脈CLK1及第二時脈CLK2 加雜訊。在此種具有雜訊 第^子Θ施 之輸出端子。!之電位^ f —運減大器㈤ 運算放大器⑽之輪d,!。’且第二 程式1卜織,可將第— 〜可被表示為方 電容器之值設定為相同值之值與第二反饋 [方程式10] β w = -^cc·^ CfbOl, N In 14(a) to 14(f), the value obtained by subtracting the potential from the potential can also be expressed as Equation 6. In Fig. 14(a) to the figure, 'for Equation 6, it is not satisfied, 山, but ^^ after the knife is added to the output potential of the first operational amplifier OA1 ^ noise] 4 can & To the third operational amplifier (10) = 2 = large "2 (called a seven.). False sine wave hybrid two two-point number of times # is #', then when the input terminal through the terminal 17 is called the second step is the heart:: The cycle of 1 is in the mother-integral cycle = the integrator circuit is essentially = when 'the wheel' is entered: the response, the output of the P2 P2 is defined as the potential of the second pass And the potential of the circuit region sub-minus L is subtracted from the output terminal of the first operational amplifier 3 (four). The potential of the output terminal of Figure 15 is not in accordance with the embodiment of the present invention in the frequency domain 23 201220203p (frequency domain Among the noise removal characteristics, the graphs u(a) to 11(f) to 14(8) to 14(f) show the noise removal characteristics in the time domain (time plus ^). 15 shows an example when the integral number of an integration cycle is equal to 1 。. See Figure 15 ' It can be seen that the number of frequency points of the null response (null resp〇nse) is 10, including the frequency. The DC frequency at a peak frequency of 50,000 Hz or less in the response curve. As can be understood from Fig. 15, when the driving frequency!· is set high enough, the noise passband (pass_band) of the circuit region P2 shown in Fig. 6 It is advantageous to remove these noises because of the large frequency gap between the critical noise bands frequently appearing in the brothers of the soil. The HUM noise with more than 100V and its harmonics are critical. An example of noise. For the case where Equation 6 is satisfied as described above, the value of the capacitor CV can be calculated according to Equation 6, as expressed by Equation 9. [Equation 9] When the value of the capacitor (3⁄4 changes), it can be judged whether or not A touch event has occurred. In the following, a case is described in which the circuit of Fig. 6 according to an embodiment of the invention is configured to include an inverting integrator circuit and a non-inverting integrator circuit. 24 201220203 Figs. 16(a) to 16( d) shows an example of an inverting integrator circuit that can be used in the embodiment of the present invention. Figure 16 (a) shows the circuit after the second operational amplifier 0A2 is removed from the circuit shown in Figure 6. It can be understood that the circuit of Figure 6 The inverter invertor circuit is substantially the same as that shown in FIG. 16(a), because the switch S2 of FIG. 6 is connected to the second via the inverting input terminal and the non-inverting input terminal of the second operational amplifier 〇A2. The potential GM), and the switch S2 of Fig. 16(a) is directly connected to the second potential. Fig. 16(b), Fig. 16(c) and Fig. 16(d) show that the inverted integral gain circuit of Fig. 16(4) has According to the switching timings of the first clock CLK1 and the second clock CLK2 shown in FIG. 7(a) to FIG. 7(b) or FIG. 11(a) to FIG. 11(b), respectively at tl+ time, t2+ and t4+ Time, and the operating status of t3+ time. By comparing FIG. 16(b), FIG. 16(c), and FIG. 16(d) with FIG. 8, FIG. 9, and FIG. 10, respectively, it can also be seen that the circuit of FIG. 6 includes the figure i6(a) to The inverted integrator circuit is substantially the same as shown in Figure 16(d). The circuit of FIGS. 16(a) to 16(d) may be referred to as an inverting switched capacitor integrator circuit. FIG. 17(a) to FIG. 17(d) illustrate that it may be used in the present invention. An example of a non-inverting integrator circuit of an embodiment. Fig. 17 (4) shows the circuit after the first operational amplifier OA1 is removed from the circuit of Fig. 6. It can be understood that the circuit of FIG. 6 includes substantially the same non-inverting integrator circuit as shown in FIGS. 17(a) to 17(d), because the switch S1 of FIG. 6 is via the first operational amplifier 〇A1. The inverting input terminal and the non-inverting input terminal are connected to the second power and Figure 17 (the magic switch si is directly connected to the second potential. 25 201220203 JO lpif Figure 17(b), Figure 17(c) and Figure 17 (d) shows that the non-inverting integrator circuit of FIG. 17 (4) has the first clock CLK1 and the second according to FIG. 7 (a) to FIG. 7 (b) or FIG. 11 (a) to FIG. 11 (b) When the switching timing of the clock CLK2 is at the time of tl+ time, t2+ and t4+ time, and t3+ time, respectively, by referring to FIG. 17(b), FIG. 17(c), and FIG. 17(d), respectively. 9 and FIG. 10, it can also be seen that the circuit of FIG. 6 includes substantially the same non-inverting integrator circuit as shown in FIGS. 17(4) to 17(d). The circuits of FIGS. 17(4) to 17(4) can be It is called a non-inverting switched capacitor integrator circuit. As an overview of FIG. 6, FIG. 16(a) to FIG. 16(d) and FIG. 17(4) to FIG. 17(d), according to Implementation of the invention An integrator circuit is obtained by coupling a non-inverting integrator circuit and an inverting integrator circuit, the non-inverting integrator circuit and the inverting integrator circuit sharing a capacitor q· and for a capacitor CI / / • Charging / discharging circuit for charging / discharging. The charging / discharging circuit can correspond to the circuit area pi of Figure 6, the circuit area P3 of Figure 16 (4) to Figure 16 (6) and the circuit of Figure i7 (a) to Figure 17 (d) Figure 18 (4) to Figure 18 (d) illustrate an integrator circuit in accordance with another embodiment of the present invention. Figure 18 (8) illustrates the integrator circuit of Figures 16 (8) through 16 (6) as a plurality of circuit modules (e.g., A charging/discharging circuit na is integrated with the first integrating component 12-1). The first charging/discharging circuit corresponds to the circuit region P3 of FIGS. 16(4) to 16(6), and the first integrating component 12-1 corresponds to 26 201220203 in FIG. (a) to the combination of the first operational amplifier OA1, the first feedback capacitor and the third switch S3 in Fig. 16(d). Fig. 18(b) shows the integrator circuit description of Figs. 16(4) to 16(d) a plurality of circuit modules (eg, second charging/discharging circuit 11_2 and second integral component) Integration of 12-2) The second charging/discharging circuit u_2 corresponds to the circuit region Ρ4 of Figs. 17(a) to 17(d), and the second integrating component 12_2 corresponds to the first of Figs. 17(8) to 17(d) The second operational amplifier 0Α2, the second feedback^the container is combined with the third switch. Fig. 18(c) can be obtained by integrating the circuit of Fig. 18(a) with the circuit of Fig. 18(b). The charging/discharging circuit 11 corresponds to the circuit region P1 in FIG. 6, and the first integrating component 12-1 corresponds to the combination of the first operational amplifier 〇A1, the first feedback capacitor C^7, and the third switch S3 in FIG. The second integrating component 12-2 corresponds to the second different amplifier 〇A2, the second feedback capacitor, and the third switch combination in FIG. Figure 19 illustrates an integrator circuit in accordance with another embodiment of the present invention. The circuit shown in Fig. 19 is implemented in a manner in contrast to Fig. 6 to implement the circuit of Fig. 18(c) as an embodiment of the present invention. However, it can be easily understood that when the switches S1 and S1 and the switches S2 and S2 are driven by the first clock CLK1 and the second clock CLK2 of FIG. 8 or FIGS. 11(a) to 11(b), The circuit performs the same operations as those shown in FIG. In Figures 6 and 19, a switch S1 is provided in the circuit for isolating the first operational amplifier 〇A1 from the capacitor when the switch S2r is in the on state. In contrast, switch S2 is provided in the circuit for isolating the second operational amplifier 〇A2 from the capacitor 27201220203 c&. when the switch sr is in the on state. 16(a) to 16(d) and Figs. 17(4) to 17(4) show examples of the inverting amplifier and the non-inverting amplifier. Although not disclosed in the present description, it is understood that the integrator circuit having the configuration shown in FIGS. 18(a) to 18(d) is formed by fitting the anti-scaling inverting amplifiers having no anti-scales. It is to be understood that the spirit of the present invention is not limited to the specific circuits disclosed herein.信/ιΛ2, tFig. 2G_ shows the value output as a result of the execution of the simulation = in the simulation, the application of the figure u(4) to the circuit of Fig. 6: the first-clock CLK1 and the second clock CLK2 plus noise . In this type of output terminal with noise. ! The potential ^ f - the power reducer (5) the wheel of the operational amplifier (10) d, !. And the second program 1 can be set to the value of the square capacitor as the value of the same value and the second feedback [Equation 10] β w = -^cc·^ Cfb

[方程式11] 28 201220203 圖20(a)顯示第一運算放大器0A1之輪出端子〇1處之 電位隨時間之變化。圖20(b)顯示第二運算放大器^A2 之輸出端子〇2處之電位PL隨時間之變化。圖2〇(°c)顯示 藉由自電位Fo2減去電位Fw而獲得之值。 在圖20⑷至圖20(c)中,輸入雜訊類似於正弦波,哪 一循環在每一積分循環中重複5次至6次。因此,將在一 個積分循環中之積分的次數N設定成明顯大於5或6之 值。根據本發明實施例之配置’可以看出,可如圖如⑷ 所示獲得已移除雜訊之波形。 當僅使用反相積分器與非反相積分器其中之一積分器 來代替根據本發明的將兩種積分器相耦合之電路配置時°, 可僅獲得方程式10或方程式11之輸出電壓。舉例而言, 當獲得方程式10之輸出電壓時,電容器·之值可表二為 方程式12。 [方程式12] 因此,由於雜訊造成之誤差值,可能無法正確地量測 電容器CV之值。 本發明之電路配置可應用於其他可利用本發明精神之 應用以及觸控螢幕。因此,應理解,本發明之應用並非僅 限於觸控螢幕驅動電路。 29 201220203 在本發明中,運算放大器代表差動放大器(differential amplifier)之一實例。本發明之運算放大器可使用差動放 大器來取代。 根據本發明實施例之電容量測電路是使用包含開關之 開關電容器、反饋電容器(積分電容器)以及運算放大器 配置而成’從而基本上具具有限脈衝響應(finite impulse response,FIR)濾波器之特性。 在附圖之圖6、圖8、圖9、圖1〇、圖16(a)至圖16(d)、 圖17(a)至圖17(d)及圖19中,顯示每一運算放大器之非反 相端子皆連接至同一電位(即,地電壓GM)),所述同一 電位可經由開關S2,而連接至驅動信號線石。然而,可以 理解,即使每一運算放大器之非反相端子連接至不同於地 電壓之另一電壓,亦可獲得本發明上述實施例之效 果。 本發明可提供一種抗雜訊之積分器電路。此外,藉由 對用於感測觸控螢幕輸入之感測器區塊應用所述抗雜訊之 積分器電路,可使因觸摸輸入所產生之雜訊而造成之輸入 感測誤差顯著減小。 以上所揭露之標的物應被視為例示性而非限制性的, 且隨附的申請專利範圍旨在涵蓋仍處於本發明之真正精神 及範圍内之所有此等潤飾、改良或其他實施例。因此,在 法律所容許之最大程度上,本發明之範圍應由後附的申請 專利範圍及其等價範圍之最廣解釋加以確定,而不應被限 制或侷限於上文的詳細說明。 30 201220203 【圖式簡單說明】 :====版心本發明 驅動電路之示意圖’所述 圖6緣示根據本發明實施例之積分器之配置。 之積二|/之)备圖J(e)f時序圖’其綠示根據本發明實施例 之積刀益之母一卽點狀態隨時間之變化。 1〇:會示根據本發明實施例之積分器之配置。 本發日至圖14⑷〜圖刚是用於描述根據 ^發明實施例來抵柯被輸人至積分器之雜訊之原理的圖 式0 頻率^5。料根縣發明料敗射11祕於雜訊之 分16(辦示可用於本發明實施例之反相積 圖η⑻至圖17⑹繪示可用於本發明實施例之非反相 積分器電路之實例。 圖18⑻至圖18⑻及圖19綠示根據本發明另一實 之積分器電路。 圖20⑻至圖20(c)顯示根據本發明實施例之積分器之 運作之模擬結果。 【主要元件符號說明】 1 ·觸控面板 201220203 ίο:驅動電路 11 :充電/放電電路 11-1 :第一充電/放電電路 11- 2 :第二充電/放電電路 12 :感測部件 12- 1 :第一積分部件 12-2 :第二積分部件 100 :感測圖案 101 :驅動圖案 102 :介電層 103 :保護視窗 110 :感測節點 112 :節點電容器 200 :電容量測電路 203 :線 300 :觸摸確定部件 Ciy :電容/電容器 :第一反饋電容器 :第二反饋電容器 CLK1 :第一時脈 CLK2 :第二時脈 π人无3,…,A〇 :時間點 «2,/: (^=7,2,3,…,A〇 :時間點 OA1 :第一運算放大器 32 201220203 W 〆 Λ t OA2 :第二運算放大器 〇1 :第一運算放大器OA1之輸出端子 〇2 :第二運算放大器OA2之輸出端子 P1 :電路區域 P2 :電路區域 P3 :電路區域 P4 :電路區域 51 :第一開關 S1…·第三開關 52 :第二開關 sr :第四開關 53 ··重設開關/第三開關 S3’ :重設開關/第三開關 :電源電壓 :電位 電位 厂。2,# :電位 X7、U、...、:驅動信號線 π:第二端子/驅動信號線 17、Γ2、Γ3、...、:感測信號線 θ :第一端子/感測信號線 33[Equation 11] 28 201220203 Fig. 20(a) shows the change in potential at the wheel terminal 〇1 of the first operational amplifier 0A1 with time. Fig. 20(b) shows the potential PL at the output terminal 〇2 of the second operational amplifier ^A2 as a function of time. Fig. 2 (°c) shows the value obtained by subtracting the potential Fw from the potential Fo2. In Figs. 20(4) to 20(c), the input noise is similar to a sine wave, and which cycle is repeated 5 to 6 times in each integration cycle. Therefore, the number N of integrations in one integration cycle is set to be significantly larger than the value of 5 or 6. It can be seen from the configuration of the embodiment of the present invention that the waveform of the removed noise can be obtained as shown in (4). When only one of the inverting integrator and the non-inverting integrator is used instead of the circuit configuration in which the two integrators are coupled according to the present invention, only the output voltage of Equation 10 or Equation 11 can be obtained. For example, when the output voltage of Equation 10 is obtained, the value of the capacitor can be expressed as Equation 12. [Equation 12] Therefore, the value of the capacitor CV may not be accurately measured due to the error value caused by the noise. The circuit configuration of the present invention can be applied to other applications and touch screens that can utilize the spirit of the present invention. Therefore, it should be understood that the application of the present invention is not limited to the touch screen driving circuit. 29 201220203 In the present invention, an operational amplifier represents an example of a differential amplifier. The operational amplifier of the present invention can be replaced with a differential amplifier. The capacitance measuring circuit according to the embodiment of the present invention is configured by using a switching capacitor including a switch, a feedback capacitor (integrated capacitor), and an operational amplifier to substantially have a characteristic of a finite impulse response (FIR) filter. . In Fig. 6, Fig. 8, Fig. 9, Fig. 1, Fig. 16(a) to Fig. 16(d), Fig. 17(a) to Fig. 17(d) and Fig. 19, each operational amplifier is shown. The non-inverting terminals are all connected to the same potential (ie, ground voltage GM)), and the same potential can be connected to the driving signal line via switch S2. However, it can be understood that the effect of the above-described embodiment of the present invention can be obtained even if the non-inverting terminal of each operational amplifier is connected to another voltage different from the ground voltage. The invention can provide an anti-noise integrator circuit. In addition, by applying the anti-noise integrator circuit to the sensor block for sensing the touch screen input, the input sensing error caused by the noise generated by the touch input can be significantly reduced. . The above-identified subject matter is intended to be illustrative and not limiting, and the scope of the appended claims are intended to cover all such modifications, modifications, and other embodiments. Therefore, to the extent permitted by law, the scope of the invention should be determined by the broadest interpretation of the scope of the appended claims and their equivalents, and should not be limited or limited. 30 201220203 [Simple description of the drawings]: ==== stencil The schematic diagram of the driving circuit of the present invention'. Fig. 6 shows the configuration of an integrator according to an embodiment of the present invention. The product J(e)f timing diagram 'green' shows the change of the state of the mother point of the product according to the embodiment of the present invention over time. 1〇: The configuration of the integrator according to an embodiment of the present invention is shown. The present invention to Fig. 14(4) to Fig. is just a pattern 0 frequency ^5 for describing the principle of the noise transmitted to the integrator according to the embodiment of the invention. The invention is based on the inverse phase product maps η(8) to 17(6) which can be used in the embodiment of the present invention to illustrate an example of a non-inverting integrator circuit that can be used in the embodiment of the present invention. 18(8) to 18(8) and Fig. 19 show another embodiment of the integrator circuit according to the present invention. Fig. 20(8) to Fig. 20(c) show simulation results of the operation of the integrator according to an embodiment of the present invention. 1) Touch panel 201220203 ίο: Drive circuit 11: Charging/discharging circuit 11-1: First charging/discharging circuit 11-2: Second charging/discharging circuit 12: Sensing part 12-1: First integral part 12-2: second integration part 100: sensing pattern 101: driving pattern 102: dielectric layer 103: protection window 110: sensing node 112: node capacitor 200: capacitance measuring circuit 203: line 300: touch determining part Ciy Capacitor/capacitor: first feedback capacitor: second feedback capacitor CLK1: first clock CLK2: second clock π person no 3, ..., A〇: time point «2, /: (^=7, 2, 3,...,A〇: time point OA1: first operational amplifier 32 201220203 W 〆Λ t OA2 : Operational amplifier 〇1: Output terminal 〇2 of the first operational amplifier OA1: Output terminal P1 of the second operational amplifier OA2: Circuit area P2: Circuit area P3: Circuit area P4: Circuit area 51: First switch S1...·Third Switch 52: second switch sr: fourth switch 53 · reset switch / third switch S3': reset switch / third switch: power supply voltage: potential potential factory. 2, #: potential X7, U, .. .: drive signal line π: second terminal/drive signal line 17, Γ2, Γ3, ...,: sensing signal line θ: first terminal/sensing signal line 33

Claims (1)

201220203 七、申請專利範圍: i 一種積分器電路,包括: 第-運算放大器;第二運算放大器立 中所述第一運算放大器與所述第- 及電谷4 ” 端子被配置成分別經由第一丄器之反相, 電容器之第-端子, 、第―_而連接至所述 所述電容器之第二端子被配置成 第四開關而連接至第-電位與第二電位,·”帛二開關與 所述第-運算放大器之所述反相 被配置成經由第-反饋電容器而相互連接端子 放=之所述反相輸入端子與輸出端子則被配置= 二反饋電容器而相互連接,以及 战a由第 所述第-運算放大器與所述第二運算放大 輸入端子被配置成連接至第三電位。 非反相 2. 如中請專利範圍第w所述之積分器電路, 述第-開關與所述第三開關是由第—時脈驅動ς令所 二開關與所述第四開關是由第二時脈驅動。 斤述第 3. 如申請專利範m第2項所述之積分器電路 =:時脈與所述第二時脈之接通_是交替地 4. 如申請專職圍第丨項所狀積分^ 述電容器是由形成於電容式觸控螢幕中之感 2所 圖案形成。 阅茶及驅動 5. 如申請專利範圍第4項所述之積分器電路,其中所 34 201220203 器的兩個端子其中之—個對應於所述感測圖案,所 _L固端子的所述其中之一個連接至所述第一運算放大器 及所述第二運算放大器。 外側 6.如申請專利範圍第5項所述之積分器電路,其中相 ,於所述驅動圖案,所述感測圖案設置於所賴控螢幕之 丫 ^如申請專利範圍第1項所述之積分器電路,其中所 ,電谷f之兩個端子中連接至所述第一運算放大器及所述 第二運算放大器的一個端子是藉由纜線或無線而輸入之雜 5孔之流入路徑。 …8.如申請專利範圍第1項所述之積分器電路,其中所 述第二電位相同於所述第三電位。 、9. 一種電容式觸控螢幕之輸入感測電路,在所述電容 式觸控螢幕中形成有感測圖案及驅動圖案,所述輸入感測 電路包括: 第一運算放大器;以及 第二運算放大器, 其中所述感測圖案被配置成分別經由第一開關而連接 至所述第一運算放大器之反相輸入端子、以及經由第二開 關而連接至所述第二運算放大器之反相輸入端子, 所述驅動圖案被配置成分別經由第三開關與第四開關 而連接至第一電位與第二電位, 所述第一運算放大器之所述反相輸入端子與輸出端子 被配置成經由第一反饋電容器而相互連接,且所述第二運 35 201220203i 算放大器之所述反相輸入端子 容器而相互連接,以及 、,‘子、.坐由第二反饋電 所述第-運算放大器與所述第 輸入端子連接至第三電位。 彡异放大15之非反相 10.如申請專利範圍第9 中:述第-開關與所述第三開關=輸路’其 11·如申请專利範圍第 中所述第二電位相同於所述^電=輸人感測電路,其 12. -種Μ電容n式齡器魏包括: 反相開關電容器式積分器電路;以及 非反相開關電容器式積分 玫 、、 關電容H式積的電路,° ’連接頌述反相開 :所f反相開關電谷器式積分器電路之取 被所述非反相關電容H式積分器電路共用。 - 哭番利㈣第12項所述之開關電容器式積分 所述取樣電容器中之電荷進行時間積分,以輸出負;ί 且 所述非反=關電容器式積分器電路對充電 樣電容器中之電荷進行時間積分,以輸出正電壓。 Μ.如^月專利範圍第12項所述之開關電容器式積分 器電路,其情姐相開關餘ϋ式積分料路之積分時 間間隔之至少—部分衫叠於所述非反相_電容器式積 36 it 201220203 分器電路之積分時間間隔。 。口 15.⑹申請專利範圍帛12項所述之開關電容器式積分 =電路,其中所述取樣電容器是由形成於電容式觸控螢幕 中之感測圖案與驅動圖案形成。 16.如申請專利範圍第12項所述之開關電容器式積分 器電路其中所述取樣電容器之兩個端子中連接至所述反 =關電容H式積分H電路與所述非反相開關電容器式積 刀器電路的一個端子是藉由纜線或無線而輸入之雜訊之流 入路徑。 〇〇 17.如申請專利範圍第12項所述之開關電容器式積分 器電路,其中第二電位相同於第三電位。 18. —種積分器電路,包括: 電容器; 充電/放電電路,連接至所述電容器,以對所述電容器 進行充電/放電; 反相積分器電路,連接至所述充電/放電電路;以及 非反相積分器電路’連接至所述充電/放電電路。 19. 如申請專利範圍第18項所述之積分器電路,其中 所述反相積分器電路對充電於所述電容器中之電荷進行時 間積分,以輸出負電壓,且 、_所述非反相積分器電路對充電於所述電容器中之電荷 進行時間積分,以輸出正電壓。 20. 如申請專利範圍第18項所述之積分器電路,其中 所述電容器是由形成於電容式觸控螢幕巾之感顧案與驅 37 20122020} 動圖案形成。 々申叫專利範圍第18項所 ==兩個端子中連接至所述反相積分= 述=目,器電路的—個端子是藉峨或無線而輸入斤 之雜sfl之流入路捏。 22.如申叫專利範圍第18項所述之積分器電路,豆中 所述反相積分器電路之積分時間間隔之至少 ^ 於所述非反相積分器電路之積分時間間隔。 够t t申°月專利範圍第18項所述之積分器電路’其中 第二電位相同於第三電位。 T 24. —種積分器電路,包括: 第一運算放大器;第二運算放大器;以及電容器4 中所述第—運算放大器與所述第二運算放大器之反相輸I 端子被配置成分職接至所述電容ϋ之第-端子, 、“:ff:運算放大器之所述反相輸入端子與輸出端子 被=成經由串聯連接之第一反饋電容器與第一開關而相 互連接,且所述第二運算放大器之所述反相輸入端子與輸 出端子則經由串聯連接之第二反饋電容器與第二開關而相 互連接, =電容器之第二端子被配置成分別經由第三開關與 第四開關而連接至第一電位與第二電位,且 所述第-運算放大器與所述第二運算放大器之非反相 輸入端子連接至第三電位。 25·如申凊專利範圍第24項所述之積分器電路,其中 所述第二電位相同於所述第三電位。 38201220203 VII. Patent application scope: i An integrator circuit comprising: a first operational amplifier; a second operational amplifier; the first operational amplifier and the first-and-electric valley 4" terminal are configured to be respectively through the first The inverting of the buffer, the first terminal of the capacitor, the first terminal connected to the capacitor is configured as a fourth switch connected to the first potential and the second potential, and the second switch And the inverting of the first operational amplifier is configured to be connected to each other via a first feedback capacitor; the inverting input terminal and the output terminal are configured to be connected to each other by a feedback capacitor, and a The first operational amplifier and the second operational amplification input terminal are configured to be connected to a third potential. Non-inverted 2. In the integrator circuit of the patent scope, the first switch and the third switch are driven by the first clock and the fourth switch is Two clock drive.千述第3. The integrator circuit as described in the second paragraph of the application patent m =: the connection between the clock and the second clock _ is alternately 4. If applying for the full-time 丨 所 item points ^ The capacitor is formed by a pattern of sensations 2 formed in a capacitive touch screen. Reading tea and driving 5. The integrator circuit of claim 4, wherein one of the two terminals of the 34 201220203 corresponds to the sensing pattern, wherein the One of the two is connected to the first operational amplifier and the second operational amplifier. The integrator circuit of claim 5, wherein, in the driving pattern, the sensing pattern is disposed on the control screen, as described in claim 1 The integrator circuit, wherein one of the two terminals of the electric valley f connected to the first operational amplifier and the second operational amplifier is an inflow path of the impurity 5 holes input by a cable or wireless. The integrator circuit of claim 1, wherein the second potential is the same as the third potential. 9. An input sensing circuit for a capacitive touch screen, wherein a sensing pattern and a driving pattern are formed in the capacitive touch screen, the input sensing circuit comprising: a first operational amplifier; and a second operation An amplifier, wherein the sensing pattern is configured to be coupled to an inverting input terminal of the first operational amplifier via a first switch, and to an inverting input terminal of the second operational amplifier via a second switch The driving pattern is configured to be connected to the first potential and the second potential via the third switch and the fourth switch, respectively, wherein the inverting input terminal and the output terminal of the first operational amplifier are configured to be via the first The feedback capacitors are connected to each other, and the inverting input terminal of the second amplifier 35 201220203i is connected to each other, and the 'sub, the second feedback power is the first operational amplifier and the The first input terminal is connected to the third potential. The non-inverting of the different amplification 15 is as described in the ninth application: the first switch and the third switch = the transmission path, wherein the second potential is the same as described in the patent application scope ^Electric=input sensing circuit, 12. The kind of tantalum capacitor n-type device includes: reverse-phase switched capacitor integrator circuit; and non-inverting switched capacitor-type integrated rose, closed capacitance H-type product circuit , ° 'Connection Description Inverting On: The f-inverting switch is controlled by the non-reverse-correlation capacitance H-type integrator circuit. - crying Fanli (4) Switched capacitor type in item 12, integrating the charge in the sampling capacitor for time integration to output negative; ί and the non-reverse-off capacitor integrator circuit for the charge in the charging capacitor Time integration is performed to output a positive voltage.开关. The switching capacitor type integrator circuit according to item 12 of the patent scope of the present invention, wherein at least part of the integration time interval of the singular phase switching integrated circuit of the sister phase switch is stacked on the non-inverting _capacitor type The integration time interval of the product 36 it 201220203 divider circuit. . Port 15. (6) The switched capacitor type integral = circuit described in claim 12, wherein the sampling capacitor is formed by a sensing pattern and a driving pattern formed in the capacitive touch screen. 16. The switched capacitor integrator circuit of claim 12, wherein the two terminals of the sampling capacitor are connected to the reverse-off capacitance H-type integral H circuit and the non-inverting switched capacitor type One terminal of the knife-cutter circuit is an inflow path of noise input through a cable or wireless. The switched capacitor type integrator circuit of claim 12, wherein the second potential is the same as the third potential. 18. An integrator circuit comprising: a capacitor; a charge/discharge circuit coupled to the capacitor to charge/discharge the capacitor; an inverting integrator circuit coupled to the charge/discharge circuit; An inverting integrator circuit ' is connected to the charge/discharge circuit. 19. The integrator circuit of claim 18, wherein the inverting integrator circuit time integrates a charge charged in the capacitor to output a negative voltage, and the non-inverting The integrator circuit time integrates the charge charged in the capacitor to output a positive voltage. 20. The integrator circuit of claim 18, wherein the capacitor is formed by a sensory pattern formed on a capacitive touch screen towel. 々 々 专利 专利 专利 专利 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 22. The integrator circuit of claim 18, wherein the integration time interval of the inverting integrator circuit in the bean is at least ^ the integration time interval of the non-inverting integrator circuit. The integrator circuit 'described in item 18 of the patent scope is the same as the third potential. T 24. An integrator circuit comprising: a first operational amplifier; a second operational amplifier; and the first operational amplifier of the capacitor 4 and the inverting input terminal of the second operational amplifier are configured to be configured to a first terminal of the capacitor ,, ": ff: the inverting input terminal and the output terminal of the operational amplifier are connected to each other via a first feedback capacitor connected in series with the first switch, and the second The inverting input terminal and the output terminal of the operational amplifier are connected to each other via a second feedback capacitor connected in series with the second switch, and the second terminal of the = capacitor is configured to be connected to the fourth switch and the fourth switch, respectively. a first potential and a second potential, and the non-inverting input terminal of the first operational amplifier and the second operational amplifier is connected to a third potential. 25. The integrator circuit of claim 24 Wherein the second potential is the same as the third potential.
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