TW201212646A - Solid-state imaging device and camera system - Google Patents

Abstract

A solid-state imaging device includes: a pixel section in which pixels performing photoelectric conversion are arranged in a matrix shape; and a pixel signal reading section that has an AD conversion section which reads pixel signals through pixel units from the pixel section and performs analog digital (AD) conversion. The pixel signal reading section includes comparators each of which compares a reference signal, which is a ramp wave, with read analog signal potentials of pixels in a corresponding column, counter latches each of which is disposed to correspond to each of the comparators, is able to count a comparison time of the corresponding comparator, stops the count when an output of the corresponding comparator is inverted, and retains a corresponding count value, and an adjustment section that performs offset adjustment on the reference signal for each row on which the AD conversion is performed.

Description

201212646 VI. Description of the Invention: [Technical Field] The present invention relates to a solid-state imaging device which is exemplified by a CMOS image sensor and a photographing system. [Prior Art] A CMOS image sensor can be manufactured by using the same manufacturing procedure as that of a typical CMOS integrated circuit, and the CMOS image sensor can be driven by a single power source. Therefore, by using a CMOS program, it is possible to provide analog circuits and logic circuits together in the same wafer. Therefore, there are a number of powerful advantages, such as a reduction in the number of peripheral 1Cs. The output circuit of the mainstream CCD is a single channel (ch) output type that uses an FD amplifier with a floating diffusion (FD) layer. In contrast, since the CMOS image sensor has an FD amplifier for each pixel, its output circuit is a line parallel output type in mainstream use, in which a single column in the pixel array is selected and the entire column is read simultaneously in the row direction. It is difficult for the FD amplifier in the pixel to exhibit sufficient driving energy to be placed in each force, and thus it is necessary to reduce the data rate. This is a parallel processing that is advantageous. There are various proposals for the proposed signal read (output) circuit of the parallel output type CMOS image sensor.

An analog-to-digital converter that reads a pixel signal read line (in the lower (output) circuit has a pixel for each 155125.doc 201212646 abbreviated as ADC) to capture the pixel signal into a digital signal Circuit. For example, 'this is disclosed in jP_a_2〇〇5_278135 or the non-patent document "Integrated 800x600 CMOS Image System" (W. Yang et al., ISSCC Digest of Technical Papers (pages 304 to 305) (February 1999)). A CMOS image sensor equipped with a row parallel ADC. 1 is a block diagram showing an exemplary configuration of a solid-state imaging device (CM〇s$ image sensor) equipped with a line parallel ADC. The solid-state imaging device 1 includes a pixel area 2, a vertical scanning circuit 3, a horizontal transfer scanning circuit 4, and a line processing circuit group 5 formed by an ADC group as shown in FIG. The solid-state imaging device 1 further includes a digital-to-analog converter (hereinafter abbreviated as DAC) 6 and an amplifier circuit (s/a) 7. The pixel area 2 is configured such that, for example, the unit pixels 21 are arranged in a matrix shape (column and row shape), each of which includes a photodiode (photoelectric conversion device) and an in-pixel amplifier. In the row processing circuit group 5, a plurality of rows of the row processing circuit 51 are arranged, each of the row processing circuits forming each row processing circuit (ADC) 51 in each row including a comparator 51_丨, The comparator compares the reference signal RAMP (Vslop) with the analog signal Vs1 having a RAMP waveform obtained by changing the reference signal generated by the DAC 6 in a stepwise manner, the analog signal being passed through the vertical signal line 8 The pixels of each column line are obtained. 155125.doc 201212646 Each row of processing circuit (ADC) 51 further includes a counting latch (memory) 5 1 -2, which counts the comparison time of the comparator 5 丨 丨 and retains the counting result 》 row processing circuit The 5 1 has an n-bit digital signal conversion function and is disposed for each of the vertical signal lines (row lines) 8-1 to 8-n, thereby constituting a row parallel ADC block. The output of each count latch (memory) 51-2 is connected to a horizontal transfer line 9 having, for example, a k-bit width. Further, k amplifier circuits 7 corresponding to the horizontal transfer line 9 are disposed. FIG. 2 is a diagram illustrating a timing chart of the circuit of FIG. 1. FIG. In each row of processing circuit (ADC) 51, the comparator 5 1 -1 disposed for each row reads the analog signal (potential vsl) to the vertical signal line 8 and the reference signal RAMP which is changed in a stepwise manner. (Vslop) comparison. At this time, the counting latch 51-2 performs counting until the level of the analog potential Vs1 and the level of the reference signal RAMP (Vslop) cross each other and the output of the comparator 51_1 is inverted, and then the vertical signal line 8 The potential (analog signal) Vsl is converted into a digital signal (ad-converted). The AD conversion is performed twice by one read. In the first conversion, the reset level (p phase) of the unit pixel 21 is read to the vertical signal line 8 (8-1 to 8-n), and AD conversion is performed. The phase of the reset level includes the change between pixels. In the second conversion, the signals photoelectrically converted by the respective unit pixels 21 are read to the vertical signal lines 8 (8-1 to 8-n) (D phase), and AD conversion is performed. The D phase also includes variations between pixels, and thus performs the calculation of (1) phase level _ 155125.doc 201212646 P phase level ' thereby achieving correlated double sampling (CDS). The signal converted into a digital signal is recorded in the counter latch 5, and is sequentially read to the amplifier circuit 7' via the horizontal transfer line 9 by the water transfer scanning circuit 4 and finally output. In this way, row parallel output processing is performed. Further, the counting processing of the counting latch 51·2 under the p phase is referred to as main sampling, and the counting processing of the counting lock #51_2 under the D phase is referred to as secondary sampling. SUMMARY OF THE INVENTION The above CDS is performed even when the effect of the dark current and the characteristics of the photodiode (pD) are ignored, so that the change of the threshold value of the read amplifier transistor is eliminated from reading to the vertical signal line 8. The change in signal potential Vsl. In the CDS, the difference between the reset level and the signal level is obtained (reset level + net signal level), and therefore ideally if the net signal is 〇, the difference is 0 ° here, in some cases Then, even in the absence of incident light, the difference may not be zero. For these cases, multiple reasons may be considered. One of these reasons is to add the offset value to the primary and secondary samples based not only on the effects of the noise but also on the effects of the ramp-reset characteristics and the reset characteristics of the comparator. Any of them. Even when an offset value is added between samples, there is no difference in the way of the rounding in the AD conversion. In this case, the image quality is not affected. However, in the presence of differences in the way of truncation (ie, in the case of 155125.doc 201212646 quantization error), it is difficult for CDS to eliminate the change. In addition, since a comparator is provided for each row, there is a high correlation in each row, and under certain conditions, there is a line where quantization error is more likely to occur and a row in which quantization error is less likely to occur. For this reason, in the case where the resolution is high, the range of discrete values can be increased. In contrast, in the case where the resolution is low, fixed vertical stripes appear in the image. Therefore, it is necessary to provide a solid-state imaging device and a photographic system capable of suppressing the occurrence of quantized vertical stripes caused by quantization errors in AD conversion. 'This improves image quality. A solid-state imaging device according to an embodiment of the present invention includes: a pixel region, wherein a plurality of pixels performing photoelectric conversion are arranged in a matrix shape; and a pixel signal reading region having an AD conversion region, The AD conversion region reads pixel signals from the pixel region via a plurality of pixel units, and performs analog-to-digital (AD) conversion. The pixel signal read area includes: a plurality of comparators, each of the comparators being a reference of one of the ramps and a reference analog signal potential of the pixels in a corresponding row; a plurality of counts a latch, each of the counting latches being arranged to correspond to each of the plurality of comparators capable of counting the comparison time of the corresponding comparator, when 5 hai corresponds to one of the outputs of the comparator The count is stopped when inversion, and a corresponding count value is maintained; and an adjustment area that performs offset adjustment on the reference signal for each column in which AD conversion is performed. A photographing system according to another embodiment of the present invention includes: a solid-state imaging device; and an optical system. The optical system forms an object image on the solid-state imaging device 155125.doc 201212646. The solid-state imaging device includes: a pixel region in which a plurality of pixels performing photoelectric conversion are arranged in a matrix shape; and a pixel signal reading circuit having an AD conversion region from the pixel The region reads the pixel signals via a plurality of pixel units and performs analog-to-digital (AD) conversion. The pixel signal reading circuit includes a plurality of comparators, each of the comparators comparing a reference signal of a ramp wave with a read analog signal potential of a pixel in a corresponding row; a plurality of count locks a register, each of the counting latches being disposed to correspond to each of the plurality of comparators, capable of counting one of the corresponding comparators for comparing time 'When one of the corresponding comparators outputs an inverse The counting is stopped at the time of turning, and a corresponding count value is maintained; and an adjustment area that performs offset adjustment on the reference signal for each column in which the AD conversion is performed. According to the embodiments of the present invention, it is possible to suppress the occurrence of quantized vertical fringes caused by quantization errors in AD conversion, and thereby it is also possible to improve image quality. [Embodiment] Hereinafter, reference will be made to the accompanying drawings. Embodiments of the invention are described. In addition, the description will be given in the order of the following items. 1. Exemplary total configuration of solid-state imaging device 2. Exemplary configuration of row ADC 3 • Example of reference signal formation using DAC 4 • Exemplary configuration of photographic system

3 is a block diagram showing an exemplary configuration of a solid-state imaging device (CMOS image sensor) equipped with a line parallel adC 155125.doc 201212646, in accordance with an embodiment of the present invention. 4 is a block diagram showing more specifically the ADC group in the solid-state imaging device (CMOS image sensor) equipped with the line parallel ADC of FIG. 3. <1. Exemplary total configuration of the solid-state imaging device> The solid-state imaging device 100 includes a pixel region 110 as an imaging region, a vertical scanning circuit 120, a horizontal transfer scanning circuit 13A, and a timing control circuit 140, as shown in FIGS. 3 and 4. The solid-state imaging device 100 further includes a row processing circuit group 150 which is an ADC group as a pixel signal reading region; and a DAC bias circuit 160' which includes a DAC (digital bit - Analog converter) 161. The adjustment zone is configured to have respective functions of a timing control circuit 丨4, a row processing circuit group (ADC group) 150, and a DAC bias circuit 160. The solid-state imaging device 100 includes an amplifier circuit (S/A) 170, a signal processing circuit 180, and a line memory 190. In the above components, the pixel region 11A, the vertical scanning circuit 12A, the horizontal transfer scanning circuit 130, the row processing circuit group (adc group) 150, the DAC bias circuit 160, and the amplifier circuit (S/A) 17 It is configured by an analog circuit. The timing control circuit 140, the signal processing circuit ι8〇, and the line memory 19 are configured by a digital circuit. The solid-state imaging device 100 according to the embodiment further includes a determination area 2 that determines the brightness of the object based on the output of the amplifier circuit 170. As will be described later, the determination result of the determination area 200 is used in the 155125.doc 201212646 switching regarding whether or not the offset adjustment of the clamp DAC is performed. In the pixel region 110, a plurality of unit pixels 11A are arranged to have a two-dimensional shape (matrix shape) of a claw column and n rows, each of the unit pixels having a photodiode (photoelectric conversion device) ) and the in-pixel amplifier. [Exemplary Configuration of Unit Pixel] FIG. 5 is a diagram illustrating an exemplary pixel of a cm〇s$ image sensor composed of four transistors according to an embodiment. For example, &, the unit pixel 11 8 includes a photo-electric body 111 as a photoelectric conversion device. The unit pixel 110A further includes the following four transistors as an active device of each photodiode U1: a transfer transistor U2' as a transfer device as a reset device, a reset transistor 113, an amplifier transistor 114' and selection The transistor is 丨丨5. The photodiode 111 photoelectrically converts incident light into electric charges (here, electrons), and the amount of electric charge corresponds to the amount of light. The transfer transistor 112 is connected between the photodiode lu and the floating diffusion FD as an output node. When the gate (transfer gate) of the transfer transistor 112 receives the drive signal TG via the transfer control line LTx, the transfer transistor 112 transfers the electrons photoelectrically converted by the photodiode as a photoelectric conversion device to the floating diffusion reset lamp. The crystal 113 is connected to the power supply line LVDD and the floating diffusion FDi δ. The gate of the reset transistor 113 is reset via the reset control line. [The lamp receives the reset L number RST and the battery 6 resets the potential of the floating diffusion to 155125. .doc 201212646 Power Line LVDD Potential" The floating diffusion FD is connected to the gate of the amplifier transistor 114. The amplifier transistor 114 is connected to the vertical signal line ι6 via the selection transistor 115. The amplifier transistor 114 and a constant current source outside the pixel region form a source follower. Further, via the selection control line LSEL, a control signal (address signal or selection signal) SEL can be applied to the gate of the selection transistor 115, and thereby the selection transistor 115 is turned on. When the selection transistor 115 is turned on, the amplifier transistor 114 amplifies the potential of the floating diffusion FD, and outputs the voltage Vs1 corresponding to the potential to the vertical signal line 116. The voltage output from each pixel is output to the line processing circuit group 15 as a pixel signal reading area via the vertical signal line 116. For example, the respective gates of the transfer transistor 112, the reset transistor ι, and the selection transistor 115 are connected column by column. Therefore, this operation is simultaneously performed in parallel for each pixel corresponding to a single column. The reset control line LRST, the transfer control line LTx, and the selection control line 1SEL are disposed in the pixel region 110 as one set for each column in the pixel configuration. The reset control line LRST, the transfer control line LTx, and the selection control line LSEL are driven by the vertical scanning circuit 12A as the pixel driving area. In the solid-state imaging device 100, 'the timing control circuit 14' is configured to generate an internal clock as a control circuit for sequentially reading signals from the pixel region 110; the vertical scanning circuit 120, the vertical scanning The circuit control column address and column scan; and the horizontal transfer scan circuit 13A, the water 155125.doc -12-201212646 flat transfer scan circuit 130 controls the row address and the line scan. The timing control circuit 140 generates signal processing in the pixel region 110, the vertical scanning circuit 120, the horizontal transfer scanning circuit 130, the row processing circuit group 15A, the DAC bias circuit 160, the signal processing circuit 180, and the line memory 19A. The necessary timing signals. The timing control circuit 140 includes a DAC control region 141 that controls the generation of the reference signal RAMP (Vslop) of the DAC 161 in the DAC bias circuit 160. The DAC control region 141 performs control to adjust the offset of the reference signal RAMP for each column of the AD conversion of the row processing circuit (ADC) 151 of the row processing circuit group 150 being executed. The DAC control region 141 is capable of performing control at the CDS (Correlated Double Sampling) in the row processing circuit group 15A to adjust the respective reference signals ramp of the main sampling (p phase time) and the secondary sampling (D phase time). Offset. At this time, the DAC control area 141 adds a random offset signal (less than ±0.5 LSB) for each column to the reference signal RAMp at p phase time, at D phase time, or at both p phase time and D phase time. In this case, the noise overlaps and thus changes its true value. In addition, the DAC control area 141 also applies an offset signal to each of the p-phase and the D-phase only when the initialization process (auto-zero (AZ)) (which determines the operation point of each line at the start of the column operation) The method of inputting the comparator is used as a method of not changing the true value.

The pixel region 110 photoelectrically converts the video image and the screen image of each pixel column by photon accumulation and release using the line shutter, thereby outputting the analog signal VSL 155125.doc -13 - 201212646 to each row of the row processing circuit group 150. Circuit 151. In the ADC group 150, each ADC block (each row region) uses the reference signal (ramp signal) ramp from the DAC 161 to subject the analog output of the pixel region 110 to the APGA adaptive integrated ADC and digital CDS, and outputs several Digital Signal of Bits <2. Exemplary Configuration of Row ADC> In the row processing circuit group 150 according to the embodiment, a row processing circuit (ADC) 1 5 1 as an ADC block is arranged in a plurality of rows . The specific row processing circuit group 15 has a k-bit digital signal conversion function. A line processing circuit (ADC) 151 is disposed in the respective vertical signal lines (line lines) 116-1 to 116-n, thereby constituting a row parallel adc block. Each ADC 151 has a comparator 151-1' which compares a reference signal RAMP (Vslop) with an analog signal Vs1 having a slope obtained when the reference signal generated by the DAC 161 is changed in a stepwise manner. Waveform, the analog signal is obtained from the pixels of each column line via a vertical signal line. Each ADC 151 further includes a count latch 151_2 that counts the comparison time and maintains the count result. The output of each count latch 1 5 1 - 2 is connected to a horizontal transfer line LTRF having, for example, a k-bit width. Further, k amplifier circuits 170 and signal processing circuits 18 corresponding to the horizontal transfer line LTRF are disposed. In the ADC group 150, each comparator 151-1 placed for each row will read the analog signal potential Vsi to the vertical signal line 116 and the reference signal 155125.doc 8 • 14· 201212646

Vslop (slope signal RAMP with a linearly varying slope waveform with a specific slope) is compared. At this time, similar to the comparator 151_丨, the count latch 151-2 placed for each row is operating. The reference signal RAMp (potential Vsi 〇 p) having a ramp waveform and the count value '? when the pair is corresponding to each other - the ADC 151 converts the potential (analog signal) Vsl of the vertical signal line 116 into a digital signal. C 15 1 converts the change in the voltage of the reference 彳5 RAMP (potential Vslop) into a time change' and converts the time into a digital value by counting the time at a specific period (clock). When the analog signal Vs1 and the reference signal RAMp (Vsi〇p) cross each other, the output of the comparator 151-1 is inverted, and the input clock of the counting latch ΐ5ι·2 is stopped, or the clock input of the input is stopped. Up to the count latch 丨5, 2, thereby completing the AD conversion. After the end of the above AD conversion period, the horizontal transfer scanning circuit 13 转移 transfers the data held in the count latch 151_2 to the horizontal transfer line LTRF, and inputs the data to the signal processing circuit 180 via the amplifier η 借此Signal processing produces two-dimensional images. The horizontal transfer scanning circuit 130 performs multi-channel simultaneous parallel transfer to ensure the transfer rate. The luxury timing control circuit 140 generates the timing necessary for signal processing in the blocks of the pixel region 11, the row processing circuit group 150, and the like. In a subsequent stage, the signal processing circuit 180 performs a vertical line defect or point detection based on the signal stored in the line memory 19〇 (p〇int cardiacized to the young school 155125.doc _ 201212646 positive, performed for the signals Clamp ^. w, and perform digital signal processing, and intermittent blocking such as parallel-series conversion, how difficult, coding, adding, averaging operation. The digital signal transmitted for each pixel column is expected to be cut in line memory. According to the embodiment of the present invention, the digital output of the signal processing circuit 180 is transmitted as an input to the ISP or the baseband LSI. Here, the configuration of each comparator i5i according to the embodiment will be described. And the function 'This comparator performs initialization processing (auto-zero processing) in the ADC group (pixel signal reading circuit group) 15 在 In the following, the comparator is denoted by reference numeral 3 。. An exemplary configuration circuit of a comparator according to an embodiment is shown in Fig. 6. In the comparator 3A, the first amplifier and the second amplifier are connected in series. The first amplifier 310 performs a low speed signal ratio. The operation is to narrow the operating bandwidth of the first stage, and the second amplifier 32 increases the gain of the output of the first amplifier 3 10. The first amplifier 310 includes p-channel MOS (PMOS) transistors PT311 to PT314, and n-channel MOS. (NMOS) transistors NT311 to NT313. The first amplifier 310 includes a first capacitor C311 and a second capacitor C312 as AZ level sampling capacitors. The sources of the PMOS transistors PT311 and PT312 are connected to the power supply potential VDD. PMOS transistor PT3 11 The drain is connected to the 155125.doc -16 · 201212646 NMOS of the NMOS transistor NT3 11, and the connection point therebetween constitutes the node ND311. In addition, the drain and the gate of the PMOS transistor PT3 11 are connected, and the connection point therebetween Connected to the gate of the PMOS transistor PT312. The drain of the PMOS transistor PT312 is connected to the drain of the NMOS transistor NT312, and the connection point therebetween constitutes the output node ND312 of the first amplifier 3 10. NMOS transistors NT311 and NT312 The emitters are connected to each other, and the connection point therebetween is connected to the drain of the NMOS transistor NT313. The source of the NMOS transistor NT313 is connected to the ground potential GND. The gate of the NMOS transistor NT311 is connected to the electricity. The first electrode of the container C311, and the connection point therebetween constitutes the node ND3 13. Further, the second electrode of the capacitor C3 11 is connected to the input terminal TRAMP for the ramp signal RAMP. The gate of the NMOS transistor NT3 12 is connected to the capacitor C3 The first electrode of 12, and the connection point therebetween constitutes node ND314. Further, the second electrode of the capacitor C312 is connected to the input terminal TVSL for the analog signal VSL. Further, the gate of the NMOS transistor NT313 is connected to the input terminal TBIAS for the bias signal BIAS. The source of the PMOS transistor PT3 13 is connected to the node ND3 11, and its drain is connected to the node ND313. The source of the PMOS transistor PT314 is connected to the node ND312, and its drain is connected to the node ND314. Further, the gates of the PMOS transistors PT313 and PT314 are commonly connected to the input terminal TCPL of the first control pulse CPL, which is active at a low level. 155125.doc •17· 201212646 In the first amplifier 310 having the above configuration, the PMOS transistors PT311 and PT312 constitute a current mirror circuit. In addition, the NMOS transistors NT311 and NT312 use the NMOS transistor NT3 13 as a current source to form a difference. In addition, the gate of the NMOS transistor NT3 11 constitutes a first signal input terminal, and the gate of the NMOS transistor NT312 constitutes a second signal input terminal. In addition, PMOS transistors PT313 and PT314 act as AZ switches, and capacitors C311 and C312 act as AZ level quasi-sampling capacitors. Further, the output signal lstcomp of the first amplifier 310 is output from the output node ND312 to the second amplifier 320. The second amplifier 320 has a PMOS transistor PT321, NMOS transistors NT321 and NT322, and an AZ level sampling capacitor C321. The source of the PMOS transistor PT321 is connected to the power supply potential VDD, and its gate is connected to the output node ND3 12 of the first amplifier 310. The drain of the PMOS transistor PT321 is connected to the ? 〇 ! 5 transistor price 321 of the pole ’ and the connection point therebetween constitutes the output node ND3 21 . The source of the NMOS transistor NT3 21 is connected to the ground potential GND, and its gate is connected to the first electrode of the capacitor C321, and the connection point therebetween constitutes the node ND3 22. The second electrode of the capacitor C3 21 is connected to the ground potential GND. The drain of the NMOS transistor NT322 is connected to the node ν 321 and the source is connected to the node ND 322. In addition, the gates of the NMOS transistor NT322 are commonly connected to the input terminal TXCPL of the second pulse 155125.doc -18-8 201212646 pulse XCPL, which is active at a high level. The second control pulse XCPL takes a level complementary to the first control pulse signal CPL supplied to the first amplifier 310. In the second amplifier 320 having the above configuration, the PMOS transistor PT32 1 constitutes an input circuit and a current source circuit. In addition, the NMOS transistor NT322 acts as an AZ switch, and the capacitor C321 acts as an AZ level quasi-sampling capacitor. Further, the output node ND321 of the second amplifier 320 is connected to the output terminal TOUT of the comparator 300. Next, the operation of the comparator 300 according to the embodiment will be described. In the comparator 300, during the calibration period (AZ period), in order to determine the operation point for each row at the start of the column operation, the first control pulse signal CPL is supplied at a low level, and the second is supplied at a high level. Control pulse XCPL. Thereby, the PMOS transistors PT313 and PT314 which are AZ switches of the first amplifier 310 are turned on. Similarly, the NMOS transistor NT322 which is the AZ switch of the second amplifier 320 is turned on. As described above, in the ADC group 150, by using the comparator 300, the DAC offset level, the pixel reset level, and the AZ level of each row are first sampled, and the capacitor is sampled at the AZ level. Charges are accumulated in the capacitors C311, C312, and C321. In the control pulse CPL, which is supplied, for example, during the calibration period, the amplitude of the control pulse is given such that it is necessary to switch on the 155125.doc -19-201212646 AZ switching transistor for initialization (calibration). The electric house Vgss is finally set to the minimum required voltage. In this way, in an embodiment, the resulting offset is minimized. Therefore, the fluctuation range of the offset is also suppressed. Next, a P phase operation is performed. In response to the reset signal RST of the receiving pixel, the analog signal VSL is changed and compared with the ramp signal RAMP from the DAC 161' thereby performing an ad conversion for each row. When the coupled signal of the analog signal VSL intersects with the ramp signal ramp of the nodes ND313 and ND314 to be supplied to the first amplifier 3 1 , the output of the comparator 300 changes, and the first amplifier is at the comparator 3 It has become high impedance (HiZ) after the operation. The AD conversion is performed by the counting operation based on the output of the comparator 3〇〇 controlling the subsequent stage. For example, s ' immediately after the start of the P phase period, the output signal compout of the comparator 3 暂时 temporarily changes to the low level, and then changes to the high level when the ramp wave crosses the analog signal VSL. Next, the D phase operation is performed. Perform AD conversion in the same path as p phase. However, compared to the p-phase operation, the amount of signal for photoelectric conversion in the pixel in the D-phase operation is large, and thus the dynamic range of the AD conversion is generally expanded. Therefore, when AD conversion is performed at the same gradation as the P phase RAMP wave, the D phase period becomes longer than the p phase period. In this case, the output of the comparator 300 also changes when the coupled signal of the analog signal VSL is crossed with the ramp signal RAMP to be supplied to the first point ND3 13 and the ND3 14 of the first amplifier 3 10 , the first amplifier is The comparator 155125.doc .20- 8 201212646 300 has become a high impedance (HiZ) after AZ operation. Similarly to the case of the p phase, AD conversion is performed by controlling the counting operation of the subsequent stage based on the output of the comparator 300. In this case, immediately after the completion of the P phase period, the output signal compout of the comparator 3 再次 is changed to the low level again, and then the RAMP wave is changed to the high level when the RAMP wave and the analog signal VSL are crossed again during the 〇 phase period. Level. As described above, since the AZ operation, the P phase operation, and the d phase operation are repeatedly performed for each line in the same path in each column operation, the inherent variation or kTC noise of the respective lines is removed via the analog CDS. In addition, as a method of reading a pixel signal for a CMOS image sensor, there is a temporary sampling by a MOS switch disposed in the vicinity of the photoelectric conversion device in a capacitor in front of the photoelectric conversion device to be used as a photoelectric conversion device ( A method of reading a signal charge of an optical signal generated by a photodiode such as a photodiode. In the sampling circuit, the overlap typically has a noise value that is inversely related to the value of the sampling capacitor. In the pixel, when the signal charge is transferred to the sampling capacitor, the signal charge is completely transferred by using the potential gradient. Therefore, the noise will not appear during the sampling process, but the noise values overlap when the voltage level of the capacitor in the previous stage of sampling is reset to a specific reference value. In order to remove noise, CDS is usually used. As described above, 'in the CDS' reads and stores the signal charge immediately, the state of the sample (reset level), then reads the signal level after sampling, and the level of the self-storing charge Subtract the read signal level, borrow 155125.doc 201212646 to eliminate noise. Under the control of the DAC control region 141, the DAC 161 generates a reference signal (ramp signal) having a slope waveform that linearly changes and has a specific slope, and supplies the reference signal RAMP to the row processing circuit group 150 » in the DAC control region 141 Under control, the DAC 161 generates a reference signal RAMP that is subjected to an offset adjustment for each column of AD conversions of each row of processing circuits (ADCs) 151 that are executed by the row processing circuit group 15A. Under control of the DAC control region 141, the DAC 161 generates a reference signal RAMP during the CDS in the row processing circuit group 150, which is subjected to an offset during the sampling process in each of the primary and secondary samples. Adjustment. Under the control of DAC control region 141, DAC 161 will have a random offset signal (less than ±0.5 LSB) for each phase at P phase time (primary sampling), at D phase time (minor sampling), or at p phase time. Both the D phase time and the D phase time are added to the reference signal RAMP. In this case, the noise overlaps and thus changes its true value. Further, under the control of the DAC control area 141, the DAC 161 applies an offset signal which is applied not at the p-phase and the D-phase but only at the auto-zero (AZ) so as not to change the true value. As shown in FIG. 4, DAC 161 is configured to include a ramp DAC (slope DAC) 162, a clamp DAC 163, and an adder region 164. <3. Example of Reference Signal Formation Using DAC> Fig. 7 is a diagram illustrating a basic exemplary set of 155125.doc • 22-8 201212646 of a current control DAC according to an embodiment. The current control DAC 161 is configured as a power reference type DAC with power supply VDD as a reference. The current control DAC 161 can also be configured as a ground reference type daC having a ground GND as a reference. Specifically, one end of the reference resistor R1 is connected to the power supply Vdd, and the other end of the reference resistor R1 is connected to the output of the ramp DAC 162 and the output of the clamp DAC 163. The ramp output node ND 161 is formed by the connection point of the output. The reference resistor R1 and the output node ND 161 constitute an adder region 164. The ramp DAC 162 includes X current sources and switches 8 hips 1_1 to SW1 -X. The terminals a of the switches SW1-1 to SW1-X are connected to current sources Ι]μι to 11-x, respectively, which are connected to the ground GnD. The terminals b of the switches swi-i to swi-x are commonly connected to the output node ND 161. The switches SW1-1 to swi-χ are selectively turned on and off in accordance with the control signal CTL1 generated by the DAC control area 141. The clamp DAC 163 includes y current sources 丫 to ^ 丫 and switches 8 贾 2_1 to SW2-y. • Terminals a of switches SW2-i to SW2-y are connected to current sources 12_丨 to 12-y' respectively. These current sources are connected to ground gND. The terminals b of the switches S W2- i to SW2_y are commonly connected to the output node 161 ° according to the control signal generated by the DAC control region 141 (: 1 ^ 2 to selectively 155125.doc • 23 - 201212646 turn the switch on and off SW2-1 to SW2-y » In the home position DAC 163, the sticking ceremony is not only included in the current value corresponding to the fixed value of the control signal CTL2 but also including the offset value. As shown in Fig. 7, the reference signal RAMp (oblique wave) in the integrated ADC is generated by summing the output signal S162 of the ramp DAC 162 and the output signal S163 of the clamp DAC 163 for DC level control. Control in the prior art In the method, when the ad conversion is performed for each column, the reference signal is generated when the output signal of the home DAC 163 is set to a fixed value. Therefore, there is a rounding in the AD conversion in the main sampling and the secondary sampling between the lines. In the difference of the modes, the vertical stripes caused by the quantization error are concerned. In the embodiment, when the AD conversion is performed for each column, the output signal S163 of the clamp DAc 163 is not fixed (that is, the control signal is not set to a fixed value). And Using a pseudo random number based control signal CTL2. In an embodiment, in the first method, at p phase time (primary sampling), at D phase time (minor sampling), or at p phase time and D phase time ( Two samples) perform control based on pseudo random numbers. In other words, in the first method, the manner of picking up (quantizing) in the AD conversion is changed by changing the true value. In an embodiment, in the second method , the offset signal is not applied when P phase (primary sampling) and D phase (secondary sampling), and the offset signal is applied only when auto-zeroing (AZ), so as not to change the true value. Specific examples of DAC control of numbers 155125.doc • 24-201212646 Figure 8 shows a diagram illustrating a specific example of PN control based on pseudo-random number according to an embodiment. Part (A) of Figure 8 shows no offset adjustment applied The case of the portion (B) in Fig. 8 shows the case where the offset adjustment is applied. In Fig. 8, the portion (X) indicates the analog value before the AD conversion, and the portion (Y) indicates the digit value after the AD conversion, And part (z) indicates in CDS The value in the following. In this example, in the P phase, the digital conversion analogy values in the "a" column and the "A" row are "〇9", "b" column and The analog conversion analogy in the "A" line is "ο"", and the analog conversion analogy in the "c" and "A" lines is "〇9". The digits in the "a" and "B" lines The conversion analog value is "〇4", the digital conversion analogy value in the "b" column and the "B" row is "〇5", and the digital conversion analogy value in the "c" column and the "B" row is "〇3". "." The digital conversion analogy values in the "a" and "c" rows are "16", and the digital conversion analog values in the "b" and "C" rows are "15", and the "." and "c" lines The digital conversion analog value in the middle is "1 4". For example, as shown in FIG. 8, the offset value is set such that the set value in the "a" column is set equal to +0.3 LSB (the control is initially analogous, but for easier understanding, the value is digitally converted) The set value in the next "b" column is set equal to +〇2 τ叩, π υ·2 LSB and the set value in the next "ε" column is set equal to 0.1 LSB. In the "A" column, the "a" column and the factory value are changed from "0.9" to "丨2", "b" 155125.doc - 25- 201212646 The analogy value changed from "〇·7" to "0.9", and the digital conversion analogy value in "c" column and "AJ line changed from "0.9" to "1". The digital conversion analogy values in the "a" and "B" rows have been changed from "〇4" to 0.7", and the digital conversion analog values in the "b" and "B" rows have been changed from "0.5" to "0.7", i"C The digital conversion analog value in the column and the "B" row has been changed from "0.3" to "〇4". The analog conversion analogy values in the "," and "C" rows have changed from "..." to "1.9" and the "c" row has changed from M" to "1.7" and "." And the conversion analog value in the "c" line is changed from "1.4" to "15". In the D phase, in the case of no offset adjustment, the digital conversion analogy values in the "a" column and the "A" row are "1.2", and the digital conversion analogy values in the "b" column and the factory Aj row are " 1"", the digital conversion analog value in the "e" column and the "A" row is "1.3". The digital conversion analogy values in the a and "B" rows are "〇8", and the digital conversion analog values in the "b" and "" lines are "〇8", and the "cj column and "B" rows are The digital conversion analog value is "〇6". The digital conversion analogy values in the "3" and "C" rows are "1.9", and the digital conversion analog values in the "b" and "c" rows are "丨6", and the "c" and "C" lines The digital conversion analog value is "1.7". For example, as shown in Figure 8, the offset value is set so that the set value in the "a" column is equal to +Q1 LSB (the control is initially analog control, but To make it easier to understand, the value is digitally converted. The set value in the 'down-,' column is set equal to +0.0 LSB, and the set value in the next rc, c" is set equal to 155125.doc 201212646. .〇l§b. Therefore, in the D phase, the "a" column ratio is changed from "1.2" to "13", the conversion analog value is maintained at "M", and the conversion analog value is maintained in the "1.3" and "A" lines. The number of digits in the "b" and "A" rows in the "A" row and the digits in the "A" row are changed from "〇.8" to f 0.9", The digital conversion analog values in the b and "B" rows are maintained at 〇.8"' and the digital conversion analog values in the "c" and "B" rows remain at "0.6". The digital conversion analog values in the a and "C" rows are changed from "i 9" to 2. 〇j, and the digital conversion analog values in the "b" and "c" rows remain at 1 _6", and "c The digital conversion analog value in the "column and rc" rows remains at "1.7". The digital value after AD conversion is as described below without applying offset adjustment. In the P phase, the digital conversion analog value "0.9" in the "a" column and the "A" row is changed to the digit value "〇", and the digital conversion analog value "0.7" in the "b" column and the "A" row is changed. The digit value "〇" is changed, and the digit conversion analog value "0.9" in the "c" column and the "A" line is changed to the digit value "〇". The digit conversion value "0.4" in the "a" column and the "B" line is changed to the digit value "0". The digit conversion analog value "0.5" in the "b" column and the "B" row is changed to the digit value "0". The digit conversion analog value "0.3" in the "c" column and the "B" row is changed to the digit value "0". The digital conversion analog value "1.6" in the "a" column and the "C" line is changed to 155125.doc •27· 201212646 The numeric value "1", the "b" column and the "c" row are converted to the analog value "1.5". Change to the digit value "1", and the digit conversion analog value "1_4" in the "c" column and the "C" row is changed to the digit value "1". In the D phase, the digit conversion analog value "1.2" in the 'a" column and the "A" row is changed to the digit value "i", and the digit conversion analog value "1.1" in the "b" column and the "A" row is changed. The digit value r 1" is changed, and the digit conversion analog value "1.3" in the rc" column and the "A" line is changed to the digit value "1". The digit conversion analog value "〇8" in the "a" column and the "B" line is changed to the digit value "0". The "bit" conversion value "0.8" in the "b" column and the "b" line is changed to a digit value. 〇", and the digital conversion analog value "0.6" in the rc" column and the "b" line is changed to the digit value "〇". The digital conversion analog value "1.9" in the "a" column and the "C" line is changed to the digit value "1", and the digital conversion analog value "1.6" in the "b" column and the "C" line is changed to "1". The digit conversion value "1.7" in the rc" column and the "c" line is changed to the digit value "丨". In addition, the digital values after the CDS are as described below. The digit values in the "a" and "A" rows are changed to "i", the digit values in the "b" and "A" rows are changed to "丨", and the "c" and "a" rows are The digit value is changed to "1". The digit values in the "a" and "B" rows are changed to "〇", the digit values in the "b" and "B" rows are changed to "〇", and the digit values in the rc" column and ΓΒ" rows are changed. Become "〇". The digit values in the "a" and "C" lines are changed to "〇", the digit values in the "b" and "C" lines are changed to "〇", and the "c" and "c" lines are 155125. .doc 8 •28· 201212646 The digit value is changed to “ο”. In this case, in the "A" line, since the correlation between the columns is high, it is possible that the quantization error appears as a fixed vertical stripe. In the case where an offset adjustment is applied, the digital value after the AD conversion is as described below. In the P phase, the digit conversion analog value "1.2" in the "a" column and the "A" row is changed to the digit value "i", and the digit conversion analog value "0.9" in the "b" column and the "A" row is changed. The digit value "〇" is changed, and the digit conversion analog value "1_〇" in the rc" column and the "A" line is changed to the digit value "1". The digit conversion analog value r 〇.7" in the "a" column and the "B" row is changed to the digit value "0", and the digit conversion analog value "0.7" in the "b" column and the "B" row is changed to the digit value. The digital conversion analog value "0.4" in the "〇" and "rc" columns and the "B" row is changed to the digit value "〇". The digit conversion value "1.9" in the "a" column and the "C" line is changed to the digit value "1". The "bit" conversion value "1.7" in the "b" column and the "c" line is changed to the digit value "1". The digital conversion analog value "1.5" in the rc" column and the "c" line is changed to the digit value "1". In the D phase, the digit conversion analog value in the 'a' column and the 'a' line is changed to the digit value "1", and the digit conversion analog value "1.1" in the rb" column and the ra" line is changed to the digit value ri. And the digit conversion analog value "1.3" in the "re" and "A" rows is changed to a digit value Γ ι"β The digit conversion analog value "〇.9" in the "a" column and the "B" row is changed to The digit value "0", the digit conversion conversion value "0.8" in the "b" column and the "B" row is changed to the digit value "〇", and the "c" column and the "Bj line number 155125.doc -29· The 201212646 bit conversion analog value "0.6" is changed to the digit value "〇". The digital conversion analog value "2.0" in the "a" column and the "C" line is changed to the digit value "2". The "bit" conversion value "1.6" in the "b" column and the "C" line is changed to the digit value "1". The digit conversion value "1.7" in the "c" column and the "c" row is changed to the digit value "丨". Further, the digit values after the CDS are as described below. The digit values in the "a" and "A" rows are changed to r 〇", the digit values in the "b" and "A" rows are changed to "丨", and the digit values in the rc" column and ΓΑ" rows Change to "0". The digit values in the "a" and "B" rows are changed to "〇", the digit values in the "b" and "B" rows are changed to "〇", and the "c" and "B" rows are The digit value changes to "0". The digit values in the "a" and "C" lines are changed to "丨", the digit values in the "b" and "C" lines are changed to "〇", and the "c" and "c" lines are The digit value is changed to "〇". In this case, in each row, the correlation between the columns is not high, and thus the occurrence of fixed vertical stripes is not concerned. As described in the embodiment, when the offset adjustment is performed on the output of the clamp 163, the output of the clamp DAC 163 changes. When the output of the home DAC 163 changes, the entire reference signal RAMP

The level is shifted for each sample. Therefore, the time advance or delay until the output of the comparator 15M is inverted is reversed and the output value of the counter is increased or decreased. In this case, 'the clamp DAC is installed, which makes it possible to suppress the occurrence of quantized vertical stripes after I55125.doc 201212646 of (10), which will increase the width of the output value of the latch 丨5 h 2 Or reduce the width to less than 1 lsb (enough to change the adjustment of the rounding mode during AD conversion: 士ο.) The effect of the offset adjustment is equal to the effect of the jitter processing. However, it is possible without subsequent processing. The offset adjustment in the analog processing is realized by designing the existing circuit. Here, the time until the ADC measurement is measured until the output of the comparator is inverted is taken as the signal value. Further, the output value of each of the count latches 151_2 is The output value after the CDS. As described above, the solid-state imaging device 1 according to the embodiment includes the determination area 200' which determines the brightness of the object based on the output of the amplifier circuit m. As will be described later, the determination area 200 The result of the determination is used to switch whether to perform the offset adjustment of the clamp DAC. For example, if the brightness is higher than a certain threshold and the reference signal RAMP output from the DAC ΐ6 is set to a high gain, then The fixed area 2 (10) turns off the switches, and controls the output of the clamp DAC 163 to be set to a fixed value. In contrast, if the brightness is below a certain threshold and the reference signal RAMP output from the 曰 UAL 161 is set to a low gain, then The decision is that the sword 疋 200 turns on the switch SW3, and controls the output of the clamp DAC 163 to undergo the bias and local shift adjustment instead of setting the cause

Value. U When adjusting the gain (amplifying the output signal), change the slope of the RAMP as the ramp, and adjust until the output of the inverting comparator is: (4) I55125.doc 201212646. However, the change in the slope of the reference signal RAMP means a change in resolution. In general, as the resolution becomes lower, the quantized vertical fringes appear more in the image. Therefore, this situation is effective if the control for causing the offset adjustment function to function is performed in use at low gain, because the image quality is not destroyed when quantization error does not occur. In addition, since the vertical stripes are conspicuous in the dark time, the control for causing the offset adjustment function to function when the amount of light is small is also effective. Fig. 9 is a view for explaining an operation waveform in the case where the offset adjustment function is selectively applied to each column. In the example shown in Fig. 9, the offset adjustment function is not applied to the third column, and the offset adjustment function is applied to the (n+1)th column. The operation based on the configuration described above is described below.

In the following description of the example, the offset adjustment of the clamped daC output is performed in the Ρ phase and the D phase. This is only an example. Therefore, it is also possible to perform pseudo-random number-based offset adjustment control in primary sampling, secondary sampling, or both sampling. It is also possible to selectively perform offset adjustment control for each column. At the Ρ phase time, the DAC 161 sums the output signal S163 of the clamp DAC 163 for DC level control and the output signal S162 of the ramp dac 162 subjected to the offset adjustment, and generates a reference signal RAMP (Vslop). In each row of processing circuit (ADC) 151, the comparator 15 1 -1 disposed for each row compares the analog signal potential v s j read to the vertical signal line 丨丨 6 with the reference signal RAMP. 155125.doc 32 8 201212646 The count latch 151_2 performs counting until the level of the analog potential Vs1 and the level of the reference signal RAMp cross each other and the output of the comparator 151.1 is inverted. The counting latch 151-2 performs the counting operation in synchronization with, for example, the clock CLK, and stops the counting operation when the output level of the benefit 151-1 is reversed and holds the current value. The P phase of the reset level includes a change between pixels. In the second conversion, the signals photoelectrically converted by the respective unit pixels U0A are read to the vertical signal lines 116(1)6] to U6_n) (D phase), and the AD conversion is performed. At the D phase time, the DAC 161 also sums the output signal S163 of the home position DAC 163 for the sink level control and the output signal S162 of the slope 182 subjected to the offset adjustment, and generates the reference signal RAMp (Vsi 〇p). . In each row of processing circuit (ADC) 151, the analog signal 151 read to the vertical signal line 116 is compared with the reference signal RAMP via a comparator 151 arranged for each row. The count latch 151_2 performs counting until the level of the analog potential Vs1 and the level of the reference signal RAMp cross each other and the output of the comparator 151.1 is inverted. The juice number latch 151-2 performs a counting operation in synchronization with, for example, the clock CLK, and stops the counting operation when the output level of the comparator is inverted, and holds the current value. In addition to the results of the P phase and D phase conversion, the calculation of the _bit level-P phase level is performed, thereby implementing the correlated double sampling elevation S). 155125. doc •33· 201212646 The signal converted into a digital signal is sequentially read by the horizontal (row) transfer scanning circuit 丨3〇 from the horizontal transfer line LTRF to the amplifier circuit 17〇, and finally output. In this way, row parallel output processing is performed. The above description of an exemplary case of performing offset adjustment of the clamp DAC output in the P phase and the D phase has been given. Specifically, in the first method according to the embodiment shown in FIG. 9, at p phase time (primary sampling), at D phase time (secondary sampling), or at p phase time and D phase time (two kinds) Sampling) Performs control based on pseudo-random numbers. In other words, in the first method, the manner of rounding (quantization) in the gossip conversion is changed by changing the true value. In the embodiment, 'in the second method, the control can be performed as follows: the offset signal is not applied at the p phase (primary sampling) and the D phase (secondary sampling), and the bias is applied only at the automatic zeroing (AZ) Shift the signal so that it does not change the true value. Fig. 10 is a diagram for explaining an operation waveform in a case where the offset adjustment is not performed during any of the P phase time and the D phase time and the offset adjustment is performed during the auto zero period. As shown in Figure 10, the offset adjustment period is limited to the auto zero period (AZ period). In this case, similar to the first method of Fig. 8, the quantized vertical fringes caused by the quantization error become insignificant. In addition, the control to apply the signal when the offset signal is not applied in the P phase (primary sampling) and the D phase (secondary sampling) and only the automatic resetting (AZ) is equivalent to the offset value of the P phase time. The offset value from the D phase time is equal to each other 155125.doc -34-8 201212646. 11 shows a diagram illustrating a specific example of pseudo-random number based dac control according to an embodiment, which makes the offset values of the P phase time offset value and the D phase time equal to each other" (part of FIG. 11) ) shows the case where no offset adjustment is applied. Part (B) of Figure i i shows the case where an offset adjustment is applied. In Fig. 11, the portion (X) indicates the analog value before the AD conversion, the portion (Y) indicates the digit value after the AD conversion, and the portion indicates the value after the CDS2. In this example ten, in the P phase, the digital conversion analogy values in the "a" column and the "A" row are "〇9", "b" column and "A" row without applying offset adjustment. The digital conversion analog value is "〇7", and the digital conversion analog value in the "c" column and the "A" line is "〇9". The analog conversion analogy values in the "a" and "B" rows are "〇4", and the digital conversion analog values in the "b" and "B" rows are "〇5", and the "c" and "B" The digital conversion analog value in the line is "〇3". The analog conversion values in the "a" and "C" lines are "16". The analog conversion values in the "b" and "C" lines are "丨5", and the "c" and "C" The digital conversion analog value in the line is "j 4". * A n\ small example -...α" The set values in the yy, "b" and "c" columns are set equal to +02lsb (the control is initially analog control, but for easier understanding, the value is digitally converted) . Therefore, in the P phase, the analog conversion analog values in the "a" column and the "A" row are changed from "... to...", "b" column and "A" row are two 155125.doc -35· 201212646 The analog value changed from "0.7" to Γ〇9", and the "c" column and the "digital conversion analog value in the line changed from "0.9" to Γ11". The analog conversion analogy values in the "a" and "B" lines have been changed from "〇4" to 0.6", and the digital conversion analog values in the "b" and "b" lines have been changed from "0.5" to "〇.7". The digital conversion analog value in the rc column and the "B" row is changed from "0.3" to "〇5". The analog conversion analogy values in the "a" and "c" lines have changed from "i 6" to i, 8", and the "b" and "Cj line digit conversion analog values have changed from "1.5" to "1.7". 'And the conversion value of the Li position in the "c" and "c" lines has changed from "1.4" to "16". In the D phase, in the case of no offset adjustment, the digital conversion analogy values in the "a" column and the "A" row are r 1.2", and the "b" column and the "digital conversion analog value in the Aj line" are " M", and the digital conversion analog value in the rc" column and the "Α" line is "1.3". The digital conversion analogy values in the aj column and the "B" row are "〇8", and the digital conversion analog values in the "b" column and the "B" row are "〇8", and the "^" column and the "B" row. The digital conversion analog value in the middle is "〇.6". The analog conversion analogy values in the "a" and "C" lines are "i 9", and the digital conversion analog values in the "rb" and "c" rows are "16", and the "c" and "C" lines The digital conversion analog value in the middle is "I.?". For example, as shown in Figure ,, similar to the p-phase time, the offset value is negotiated so that the set values in the "a" column, the "b" column, and the "c" column are set equal to +0.2 LSB. (The control is initially analog control, but for easier understanding, the value is digitally converted) β 155J25.doc -36· 201212646 Therefore, in the D phase, the digital conversion analog values in the "a" column and the Γ A" row are "1.2" changed to "i.4", the digit conversion analog value in the "rb" column and the "A" line was changed from "1.1" to "13", and the digit conversion analogy in the "c" column and the "A" row The value changes from "13" to "1.5". The analog conversion analogy values in the "a" and "B" lines are changed from r 〇.8 j to 'h0' and the digit conversion analog values in the "b" and "B" lines are changed from "0.8" to " 1. The numerical conversion analogy value in "c" and "b" rows has been changed from "0.6" to "〇.8". The analog conversion analogy values in the "a" and "C" lines have changed from "1.9" to "2·1", and the digital conversion analog values in the "b" and "C" lines have changed from "1.6" to "1.8". The analog conversion analog value in the "c" column and the rc" line has been changed from "1.7" to "1.9". The digital value after AD conversion is as described below without applying offset adjustment. In the P phase, the digit conversion analog value "〇·9" in the "a" column and the "A" row is changed to the digit value "0", the "b" column and the digit conversion analog value "0.7" in the "A" row. Change to the digit value "〇", and the digit conversion analog value "0.9" in the rc" column and the "eight" line is changed to the digit value "〇". • The digital conversion analog value “0.4” in the “a” and “B” lines is changed to the digit value “0”. The digit conversion analog value “〇.5” in the “b” and “B” lines is changed to a digit. The value is "0", and the digital conversion analog value "0.3" in the "c" column and the r B" row is changed to the digit value "〇". The digital conversion analog value "1.6" in the "a" column and the "C" line is changed to the digit value "1", the "b" column and the "C" line in the digit conversion analog value 155125.doc -37- 201212646 1.5" Change to the digit value "1", and the digit conversion analog value "1.4" in the "Cj column and "c" row is changed to the digit value "1". In the D phase, the digital conversion analog value "1.2" in the "a" column and the "A" row is changed to the digit value "l", and the digital conversion analog value "1.1" in the "b" column and the "A" row is changed. The digit value "i" is changed, and the digit conversion analog value "1.3" in the rc" column and the r Aj line is changed to the digit value "1". The digit conversion analog value "〇8" in the "a" column and the "B" row is changed to the digit value "0". The digit conversion analog value "0.8" in the "b" column and the "B" row is changed to a digit value. 〇", and the digital conversion analog value "0.6" in the "c" column and the "B" row is changed to the digit value "〇". The digital conversion analog value r 1.9 in the "a" column and the "C" line is changed to the digit value "1". The "b" and "c" lines are converted to "1". The digit conversion analog value "1.7" in the "c" column and the "◦" row is changed to the digit value r 1". Further, the digit values after the CDS are as described below. The digit values in the "a" and "A" rows are changed to "丨", the digit values in the "b" and "A" rows are changed to "1", and the "c" and "a" rows are The digit value is changed to "1". The digit values in the "a" and "B" rows are changed to "〇", the digit values in the "b" and "B" rows are changed to "〇", and the "c" and "B" rows are The digit value is changed to "〇". The digit values in the "a" and "c" rows are changed to "〇", the digit values in the "b" and "C" rows are changed to "〇", and the digit values in the rc" and rC" rows are changed. Change to "〇". 155125.doc -38· 8 201212646 In this case, in the "A" line, since the correlation between the columns is high, it is possible that the quantization error appears as a fixed vertical stripe. In the case where an offset adjustment is applied, the digital value after the AD conversion is as described below. In the P phase, the digital conversion analog value "1.1" in the "a" column and the "A" row is changed to the digit value "1", the "b" column and the digit conversion analog value "0.9" in the "A" row are changed. The digit value is "〇", and the "^" column and the digit conversion analog value "1.1" in the "a line" are changed to the digit value "1". The digit conversion analog value "〇.6" in the "a" column and the "B" row is changed to the digit value "0", and the digit conversion analog value "0.7" in the "b" column and the "B" row is changed to the digit value. "〇", and the digital conversion analog value "0.5" in the rc" column and the "B" line is changed to the digit value "〇". The digital conversion analog value "18" in the "a" column and the "C" line is changed to the digit value "1", and the number of digit conversion analog values in the "b | column and "r ^ ^ ^" uL" 「 Change to the digit value "i", and the rc" column and the "c" line median conversion analog value "1.6" are changed to the digit value "1 in the D phase" in the "a" column and the "A" row. The analogy value "to" is changed to the digit value "i", the digit conversion conversion value "1.4" in the column and the "A" line is changed to the digit value "丨", and the "c" column and "a is changed to the digit value" The digital conversion analog value in the line "The digit conversion conversion value "1()" in the "a" column and the "B" line is changed to the digit value 1" - the digit conversion analog value in the "b" column and the "B" row. "1·." changes to the digit value ^", and the digit conversion conversion value "0.8" in the "." column and the "B" row is changed to a digit value "〇155125.doc •39- 201212646 "a" column and " The digit conversion analog value "21" in the C line is changed to the digit value "2". The digit conversion analog value "1.8" in the "b" column and the "C" line is changed to a digit value. ", And" c "columns and" c "in the row of the class-digital conversion ratio" 1.9 "is changed to a digital value" i. " In addition, the digital values after the CDS are as described below. The digit values in the "a" and "A" rows are changed to "〇", the digit values in the "b" and "A" rows are changed to "丨", and the digits in the "c" column and the "Aj line" The value changes to "0". The digit values in the "a" and "B" rows are changed to "丨", and the digit values in the "b" and "Bj rows are changed to "丨", and the digits in the "c" and rB" rows The value changes to "〇". The digit values in the "a" and "C" rows are changed to "丨", the digit values in the "rb" and "C" rows are changed to "〇", and the digits in the "c" and "c" rows The value changes to "0". In this case, the correlation between the columns is not high in each row, and therefore this method is less inefficient than the first method, but does not pay attention to the occurrence of fixed vertical stripes. As described above, according to the solid-state imaging device of the embodiment, it is possible to obtain the following effects. According to the embodiment, it is possible to control the sampling value with high accuracy only by adjusting the offset value. The adjustment is performed for each column, thereby implementing the dither processing in an analog format. The occurrence of quantized vertical stripes can be suppressed, whereby it is possible to prevent image quality degradation of an object. 155125.doc .4〇. 8 201212646 These functions can be implemented by adding only new control functions to existing circuits. The size of the circuit does not increase. A solid-state imaging device having such effects can be applied as an imaging device of a digital camera or a video camera. <4. Illustrative Configuration of Photographic System> Fig. 12 is a diagram for explaining an exemplary configuration of a photographing system using a solid-state imaging device according to an embodiment of the present invention. As shown in Fig. 12, the photographing system 400 includes an image forming apparatus 41, to which the solid-state imaging device 1 according to the embodiment can be applied. The photographic system 400 further includes an optical system that directs incident light (which forms an object image on a pixel region of the imaging device 410) to a pixel region of the imaging device 410 (eg, an image of incident light (image light)) A lens 420) formed on the imaging surface. The photographing system 400 further includes a drive circuit (drv) 430 that drives the imaging device 410, and a signal processing circuit (pr〇 440 that processes the output signal of the imaging device 41. The drive circuit 430 includes a timing generator (not shown), the timing generator generates various timing signals 'the timing signals include start pulse and pulse pulses for driving the circuits in the imaging device 410. The drive circuit 43 drives the imaging device by using predetermined timing signals. 410. Further, the 'signal processing circuit 440 performs predetermined signal processing on the output signal of the imaging device 410. The image signal processed by the signal processing circuit 440 is recorded on a recording medium (such as a suffix). By using a printer or The analog image is formed as a copy (hard c〇py) on the recording medium recorded on the 155125.doc •41-201212646. In addition, the image signal processed by the chemical processing circuit 440 is also displayed as a liquid crystal display. a video image on a monitor formed by or the like. As described above, in a shadow such as a digital still camera In the capture device, by incorporating the above-described solid-state imaging device 1 as the imaging device 41, it is possible to achieve a high-precision imaging system. The present invention is contained in July 27, 2, and 2, respectively. The subject matter disclosed in the priority patent application No. JP 2009-174367 and JP 2010-167543, the entire contents of which are hereby incorporated herein by reference. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur insofar as the modifications, combinations, sub-combinations and BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an exemplary configuration of a solid-state imaging device (CM〇s image sensor) equipped with a line parallel ADC; FIG. 2 is a view of FIG. FIG. 3 is a block diagram showing a schematic configuration of a solid-state imaging device (CMOS image sensor) equipped with a line parallel according to an embodiment of the present invention, and FIG. 4 is a further Specifically FIG. 3 is a block diagram of an ADC group in a solid-state imaging device (CMOS image sensor) equipped with a row parallel ADc; FIG. 5 is a diagram illustrating a cM〇s shadow 155125 composed of four transistors according to an embodiment. Doc 8 • 42· 201212646 A diagram of an exemplary pixel of a sensor; FIG. 6 is a circuit diagram illustrating an exemplary configuration of a comparator according to an embodiment, FIG. 7 is a diagram illustrating a current control DAC according to an embodiment Figure of a basic exemplary configuration; Figure 8 shows a diagram illustrating a specific example of a pseudo-random number based dac control according to an embodiment; Figure 9 is a diagram illustrating the case where an offset adjustment function is selectively applied to each column FIG. 10 is a diagram illustrating an operation waveform in a case where the offset adjustment is performed during any one of the p phase time and the D phase time and the offset adjustment is performed during the auto reset cycle; 11 shows a diagram illustrating a specific example of pseudo-random number based DAC control according to an embodiment where the offset values of the p-phase time offset value and the D-phase time are equal to each other; and FIG. 12 illustrates the use According to this Example of the solid-state imaging device imaging system of Ming exemplary configuration of the embodiment shown in FIG. [Main component symbol description] 1 Solid-state imaging device 2 Pixel region 3 Vertical scanning circuit 4 Horizontal transfer scanning circuit 5 Row processing circuit group 6 Digital-to-analog converter 155125.doc . ^ 201212646 7 Amplifier circuit 8-1 Vertical signal line 8 -2 Vertical signal line 8-3 Vertical signal line 8-n Vertical signal line 9 Horizontal transfer line 21 Unit pixel 51 Line processing circuit 51-2 Counting latch 51-1 Comparator 100 Solid-state imaging device 110 Pixel area 110A Unit pixel 111 Photodiode 112 Transfer transistor 113 Reset transistor 114 Amplify β transistor 115 Select transistor 116 Vertical signal line 116-1 Vertical signal line (row line) 116-2 Vertical signal line (line line) 116-3 Vertical signal line (row line) 116-n vertical signal line (row line) 120 vertical scanning circuit 155125.doc -44- 8 201212646 130 140 141 150 151 151-1 151-2 160 161 162 163 164 170 180 190 200 300 310 320 400 410 420 430 440 Horizontal Transfer Scan Circuit Timing Control Circuit DAC Control Area Line Processing Circuit Group Line Processing Circuit (ADC) Comparator Count Latch DAC Bias Road DAC (digital - analog converter)

Ramp DAC

Clamp DAC Adder Area Amplifier Circuit Signal Processing Circuit Line Memory Decision Area Comparator First Amplifier Second Amplifier Photographic Imaging Device Lens Drive Circuit (DRV) Signal Processing Circuit (PRC) 155125.doc -45- 201212646 a Terminal ADC analog-to-digital converter b terminal C311 first capacitor C312 second capacitor C321 capacitor 11-1 current source 11-2 current source Il-x current source 12-1 current source 12-2 current source I2-y current source LRST heavy Set control line LSEL Select control line LTRF Horizontal transfer line LTx Transfer control line LVDD Power line ND161 Node ND311 Node ND312 Node ND313 Node ND314 Node ND321 Node ND322 Node 155125.doc • 46 8 201212646 NT311 NMOS transistor NT312 NMOS transistor NT313 NMOS Crystal NT321 NMOS transistor NT322 NMOS transistor PT3 11 PMOS transistor PT312 PMOS transistor PT313 PMOS transistor PT314 PMOS transistor PT321 PMOS transistor R1 reference resistor SW1-1 switch SW1-2 switch SWl-x switch SW2-1 switch SW2-2 switch SW2-y switch TBIAS input terminal TCPL Input terminal TOUT input terminal TRAMP input terminal TVSL input terminal TXCPL input terminal • 47 155125.doc

Claims (1)

201212646 VII. Patent application scope: 1. A solid-state imaging device, comprising: a pixel area, wherein a plurality of pixels performing photoelectric conversion are arranged in a matrix shape; and a pixel signal reading area, the pixel signal reading area has a An AD conversion region that reads a pixel signal from the pixel region via a plurality of pixel units and performs analog-to-digital (AD) conversion, wherein the pixel signal read region includes a plurality of comparators, each of the comparators One compares a reference signal with a read analog signal potential of a pixel in the corresponding row, the reference 彳§ is a ramp, and the plurality of count latches each of the count latches And corresponding to the plurality of comparators, each of which can count the comparison time of the corresponding comparator, stop the counting when the output of one of the corresponding comparators is reversed, and maintain a corresponding count value, and An adjustment area that performs offset adjustment on the reference signal for each column in which the AD conversion is performed. 2. The solid-state imaging device of claim 1, wherein the pixel #-number read region is capable of performing a correlated double sampling process by performing primary and secondary sampling on a counting operation performed by the counting latches, and Wherein the adjustment zone is capable of performing the offset adjustment on the reference signal for at least one of the primary sample and the secondary sample. 3. The solid-state imaging device of claim 2, 155125.doc 201212646 wherein the adjustment region applies different offset values to the offset adjustments for the reference signals of the primary sample and the secondary sample, and performs the offset Shift adjustment. 4. The solid-state imaging device of claim 2, wherein the adjustment region applies the same offset value to the offset adjustment of the reference signals for the primary sample and the secondary sample, and performs the offset adjustment. 5. The solid-state imaging device of claim 2, wherein the pixel 读取 § reading area is capable of performing an initialization process on an input portion of the comparators when starting a column operation, the initialization process determining an operation for each row a point, and wherein the adjustment zone performs the offset adjustment not during the primary sampling and the secondary sampling, and the offset adjustment is performed during an initialization processing cycle. 6. The solid-state imaging device of claim 1, wherein the adjustment region performs a clamping process on the reference signal based on setting a set value in response to a control signal. 7. The solid-state imaging device of claim 6, wherein the set value is set for each read column. 8. The solid-state imaging device of claim 6, wherein the sway value is set such that a change amount of one of the count latches of each of the count latches is within a range of 5 LSB. 9. The solid-state imaging device of claim 1, wherein a darkness at which the brightness level of the signal is below a predetermined level is 155125.doc 201212646 ίο. 11. The adjustment zone performs the offset adjustment on the reference signal. The solid-state imaging device of claim 1, further comprising: a determination area, the determination area receiving the output signal of the pixel (four) reading area, and determining whether the brightness level of the corresponding signal is lower than - the preset position Precisely, :, Zhongtian "Haijue District" determines that the brightness level of the signal is lower than the preset level, and the adjustment area performs the offset adjustment on the reference signal. a photographic system comprising: a solid-state imaging device; and an optical system that forms an object image on the solid-state imaging device, wherein the solid-state imaging device includes a pixel region in which a plurality of pixel configurations for performing photoelectric conversion are performed Forming a matrix shape, and a pixel signal reading circuit having a dead D conversion region. The AD conversion region extracts pixel signals from the pixel region via a plurality of pixel units and performs analog digital (AD) conversion The pixel signal reading circuit includes a plurality of comparators, each of the comparators comparing a reference number with a read analog signal potential of a pixel in a corresponding row, the reference signal being a skew Wave, a plurality of counting latches, each of the counting latches being disposed to correspond to each of the plurality of comparators, capable of counting one of the corresponding comparators for comparison time, when the corresponding Comparator - stop the count when the output is reversed, and maintain a corresponding count value, and 155125.doc 201212646 an adjustment zone, the adjustment The region performs offset adjustment on the reference signal for each column in which the AD conversion is performed. 155125.doc •4