201210405 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種控制模組，特別是指一種發光元 件的控制模組。 【先前技術】 個人電腦、筆記型電腦、飼服器、儲存器及嵌入系統 等電子裝置通常利帛一個控制模組來控制多4固發光二極體 (LED)’以顯示多個硬碟的狀態。例如：每一個硬碟對應 三個發光二極體，這三個發光二極體分別指示該硬碟的活 動（activity)、確定（locate)及錯誤（err〇r)資訊。 參閱圖1，一種習知的控制模組包含一個起始端（ initiator) 11及一個目標端（target) 12，這兩端^、η之 間的通訊符合小外型規格委員會_8485 (SFF_8485 )規格書 對串列式通用輸入/輸出（serial general purp()se input/〇u_ ，SGPIO)匯流排的規範。 起始端11產生一個時鐘信號scl〇ck、一個載入信號 SLoad，及一個帶有硬碟狀態資訊的資料輸出信號加 。目標端Π包括一個目標晶片121。目標晶片121電連接 到起始端1丨及多個發光二極體21，並接收時鐘信號sci〇ck 、載入信號SLoad及資料輸出信號SData〇ut，且根據時鐘 信號SClock及載入信號SLoad對資料輸出信號81)咖〇加 進行串列至並列轉換，以產生多個控制信號來分別控制發 光二極體21是否發光，並產生一個傳送到起始端u的資料 輸入信號SDataln。 201210405 根據SFF-8485規格書的規範，載入信號sLoad及資料 輸出信號SDataOut在時鐘信號SCi〇ck的上升緣轉變。輸出 信號SDataOut載有多個位元的資料，載入信號sLoad在輪 出信號SDataOut的最後一個位元的資料傳送時由低電位轉 變成高電位來指示目前一筆資料的傳送將結束及下一筆資 料的傳送即將開始。目標晶片121根據時鐘信號SCi〇ck的 下降緣對載入信號SLoad及資料輸出信號SDataOut.進行取 木κ，且根據取樣到的載入信號SL〇ad對取樣到的資料輪出 #號SDataOut進行串列至並列轉換。 然而’上述的控制模組有下以缺點： (1) 市面上銷售的符合SFF_8485規格書規範的目標晶片 121相當地昂貴，導致控制模組的成本較高。 (2) 目標晶片121能控制的發光二極體21的數目有上限 。參閱圖2，當設計者想要控制更多發光二極體21時，除 了必須使目標端12包括更多個目標晶"21之外，還必須 使起始端u產生更多個時鐘信號scl〇ck、載入信號SL〇ad I資料輸出信E SData〇ut ’且接收更多個資料輸入信號 SDataln’導致起始端u可能需要以更多個晶片來實現，且ϋ 控制模組需要湘較多條導線來在起始端U及目標端12之 間傳遞信號。 【發明内容】 电。因此，本發明之目的即在提供—種成本較低的控制模 於疋，本發明控制模組適用於控制一個包括多個發光 201210405 兀件的發光單7G，且包含一個起始端及一個目標端。該起 始端用以根據部分異於小外型規格_8485規格書的規範產 生一個時脈信號、一個在該時脈信號的下降緣轉變之鎖存 信號，及一個在該時脈信號的下降緣轉變之串列資料信號 。該目標端包括一個目標晶片。該目標晶片電連接到該起 始端，及適用於電連到該發光單元，用以接收該時脈信號 、該鎖存信號及該串列資料信號，並根據該時脈信號及該 鎖存信號對該串列資料信號進行串列至並列轉換，以產生 多個控制信號來分別控制該發光單元的發光元件是否發光 Ο 本發明之功效在於：藉由使該起始端根據部分異於小 外型規格-8485規格書的規範來產生該時脈信號、該鎖存信 號及該串列資料信號，該目標晶片可以採用市面上銷售的 較便宜的晶片，因此可以降低成本。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚地呈現。 參閱圖3與圖4，本發明控制模組之較佳實施例適用於 控制二個發光單元4 ’這二個發光單元4分別是一個包括多 個發光兀件41的第一發光單元4-1，及一個包括多個發光 =件41的帛二發光單元4_2。這些發光元件4ι可以是例如 發光二極體。本實施例控制模組包含-個起始端31及-個 目標端32。目標端32包括二個目標晶片321，這二個目標 201210405 晶片321分別是一個第一目標晶片321-1及一個第二目標晶 片 321-2。 起始端31用以根據部分異於小外型規格_8485規格書 的規範’產生一個時脈信號Clock、一個在時脈信號ciock 的下降緣轉變之鎖存信號Latch，及一個在時脈信號ci〇ck 的下降緣轉變之弟一串列資料信號SerialDatal。在本實施 例中，時脈信號Clock符合SFF-8485規格書對一個時鐘信 號（SClock)的規範，鎖存信號Latch與SFF_8485規格查 所規範的一個載入信號（SLoad )相似，不同之處包括鎖存 t 5虎Latch在時脈仏5虎Clock的下降緣轉變，第一串列資料 信號SerialDatal與SFF-8485規格書所規範的一個資料輸出 信號（SDataOut)相似，不同之處包括第一串列資料信號 SerialDatal在時脈信號Clock的下降緣轉變。 第一目標晶片321-1電連接到起始端31，及適用於電 連到第一發光單兀4-1，用以接收時脈信號cl〇ck、鎖存信 號Latch及第一串列資料信號SerialDatal ’並根據時脈信號 Clock及鎖存信號Latch對第一串列資料信號SeHalDatai進 订串列至並列轉換，以產生多個第一控制信號來分別控制 第一發光單元4-1的發光元件41是否發光，且將第一串列 資料k唬SerialData 1延遲一段預設時間，以產生一個第二 串列資料信號SerialData2。 第一目標晶片321-2電連接到起始端31與第一目標晶 片321-1，及適用於電連到第二發光單元4_2，用以接收時 脈信號Clock、鎖存信號Latch及第二串列資料信號 201210405201210405 VI. Description of the Invention: [Technical Field] The present invention relates to a control module, and more particularly to a control module for a light-emitting element. [Prior Art] Electronic devices such as personal computers, notebook computers, feeding devices, storage devices, and embedded systems generally benefit from a control module to control multiple 4 solid-state LEDs (LEDs) to display multiple hard disks. status. For example, each hard disk corresponds to three light-emitting diodes, and the three light-emitting diodes respectively indicate activity, locate, and error (err〇r) information of the hard disk. Referring to FIG. 1, a conventional control module includes an initiator 11 and a target 12, and the communication between the two ends η and η conforms to the specification of the small form specification committee _8485 (SFF_8485). The book specifies the specification of the serial general-purpose input/output (serial general purp()se input/〇u_, SGPIO) bus. The start terminal 11 generates a clock signal scl〇ck, a load signal SLoad, and a data output signal with hard disk status information plus. The target end Π includes a target wafer 121. The target chip 121 is electrically connected to the start end 1丨 and the plurality of light emitting diodes 21, and receives the clock signal sci〇ck, the load signal SLoad and the data output signal SData〇ut, and according to the clock signal SClock and the load signal SLoad The data output signal 81) is serially coupled to the parallel conversion to generate a plurality of control signals for controlling whether the light-emitting diode 21 emits light, respectively, and generates a data input signal SDataln transmitted to the start terminal u. 201210405 According to the specification of the SFF-8485 specification, the load signal sLoad and the data output signal SDataOut transition at the rising edge of the clock signal SCi〇ck. The output signal SDataOut carries data of a plurality of bits, and the load signal sLoad transitions from a low potential to a high potential when the data of the last bit of the round-out signal SDataOut is transmitted to indicate that the transmission of the current data is ended and the next data is The transfer is about to begin. The target wafer 121 performs a fetching of the load signal SLoad and the data output signal SDataOut. according to the falling edge of the clock signal SCi〇ck, and performs the sampling of the data wheel #SOutout according to the sampled load signal SL〇ad. Tandem to parallel conversion. However, the above control module has disadvantages as follows: (1) The target wafer 121 sold in the market conforming to the SFF_8485 specification is quite expensive, resulting in a high cost of the control module. (2) The number of the light-emitting diodes 21 that the target wafer 121 can control has an upper limit. Referring to FIG. 2, when the designer wants to control more of the light-emitting diodes 21, in addition to having to include more target crystals in the target end 12, it is necessary to cause the starting end u to generate more clock signals scl. 〇ck, load signal SL〇ad I data output letter E SData〇ut 'and receive more data input signal SDataln' causes the starting end u may need to be implemented with more chips, and the control module needs to compare A plurality of wires are used to transfer signals between the start end U and the target end 12. SUMMARY OF THE INVENTION Electric. Therefore, the object of the present invention is to provide a lower cost control mode. The control module of the present invention is suitable for controlling a light-emitting single 7G including a plurality of illumination 201210405 components, and includes a start end and a target end. . The start end is configured to generate a clock signal, a latch signal that changes at a falling edge of the clock signal, and a falling edge of the clock signal according to a specification different from the small outline specification _8485. Transform the serial data signal. The target end includes a target wafer. The target chip is electrically connected to the start end, and is adapted to be electrically connected to the light emitting unit, for receiving the clock signal, the latch signal and the serial data signal, and according to the clock signal and the latch signal Performing serial-to-parallel conversion on the serial data signal to generate a plurality of control signals to respectively control whether the light-emitting elements of the light-emitting unit emit light. The effect of the present invention is that the starting end is different from the small shape according to the part. The specification of the specification -8485 specification generates the clock signal, the latch signal and the serial data signal, and the target wafer can use a cheaper wafer that is commercially available, thereby reducing the cost. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Referring to FIG. 3 and FIG. 4, a preferred embodiment of the control module of the present invention is suitable for controlling two light-emitting units 4'. The two light-emitting units 4 are respectively a first light-emitting unit 4-1 including a plurality of light-emitting elements 41. And a second light emitting unit 4_2 including a plurality of light emitting elements 41. These light-emitting elements 4ι may be, for example, light-emitting diodes. The control module of this embodiment includes a start end 31 and a target end 32. The target end 32 includes two target wafers 321 which are a first target wafer 321-1 and a second target wafer 321-2, respectively. The start end 31 is configured to generate a clock signal Clock, a latch signal Latch that changes at the falling edge of the clock signal ciock, and a clock signal ci according to a specification different from the small outline specification _8485 specification. The descending edge of 〇ck is the serial data signal SerialDatal. In this embodiment, the clock signal Clock conforms to the specification of a clock signal (SClock) in the SFF-8485 specification, and the latch signal Latch is similar to a load signal (SLoad) specified by the SFF_8485 specification, and the difference includes Latch t 5 Tiger Latch in the falling edge of the clock 仏 5 Tiger Clock, the first serial data signal SerialDatal is similar to a data output signal (SDataOut) specified in the SFF-8485 specification, the difference includes the first string The column data signal SerialData1 transitions at the falling edge of the clock signal Clock. The first target wafer 321-1 is electrically connected to the start end 31, and is adapted to be electrically connected to the first illumination unit 4-1 for receiving the clock signal cl〇ck, the latch signal Latch and the first serial data signal. SerialData1' and serially-commuting the first serial data signal SeHalDatai to the parallel conversion according to the clock signal Clock and the latch signal Latch to generate a plurality of first control signals to respectively control the light-emitting elements of the first light-emitting unit 4-1 41 is illuminated, and the first serial data k唬SerialData 1 is delayed for a preset time to generate a second serial data signal SerialData2. The first target wafer 321-2 is electrically connected to the start end 31 and the first target wafer 321-1, and is adapted to be electrically connected to the second light emitting unit 4_2 for receiving the clock signal Clock, the latch signal Latch and the second string. Column information signal 201210405
Seria1Data2，並根據時脈信號a〇ck及鎖存信號對第 二串列資料信號Se—進行争列至並列轉換，以產生 多個第二控制信號來分別控制第二發光單以_2的發光元件 41是否發光’且將第二串列資料信號延遲一段 預設時間，以產生-個第三串列資料信號⑽仙㈣。 參閱圖3與圖5,在本實施例中，目標晶片32i皆採用 SN74LV595A曰曰曰片（其價格比市面上銷售的符合sff侧5 規格書規範的，片便宜），因此，每一目標“ 32ι且 有下列接腳：症、R^LK、兩、SRClk、驗ϋ 及Qh，，其中，接腳δέ被拉到低位準，接腳RCLK接收鎖 存信號Latch’接腳函反友被拉到高位準，接腳讥“尺接 收時脈信號Cloek，接腳SER接收相對應的第—或第二串列 貧料信號SedalDatal、SerialData2，接腳Qa〜Qh輸出相對 應的第-或第二控制信號，接腳Qh，輸出相對應的第二或第 三串列資料信號SerialData2、SerialData3。第—發光單元 Μ包括八個發光元件41。第二發光單S 4_2包括八個發: 凡件41。第-目標晶片32Μ分別根據時脈信號⑸ck的 上升緣及鎖存信號Lateh的上升緣對第_串列資料信號 SeriaiDatai進行移位及鎖存的操作，以產生八個第一^制 信號來分別控制第—發光單元的人個發光料Μ ^否 發光。第二目標晶片321_2分別根據時脈信號Cl0ck的：升 緣及鎖存信號Lateh的上升緣對第m料μ Sena版a2進行移位及鎖存的操作，以產生人個第： 信號來分別控制第：發光單元心2的人個發光元件41 :否 201210405 發光。第一串列資料信號SerialDatal載有十六個位元的資 料。由於目標晶片321是根據鎖存信號Latch的上升緣進行 鎖存操作，鎖存信號Latch與SFF_8485規格書所規範的載 入信號（SLoad)不同之處必須更包括鎖存信號Latch在第 串歹/資料SerialData 1的最後一個位元的資料傳送完畢後 才指示進行鎖存，因此，目標晶片321在根據時脈信號Seria1Data2, and contiguously parallel-converts the second serial data signal Se_ according to the clock signal a〇ck and the latch signal to generate a plurality of second control signals to respectively control the illumination of the second illumination sheet to _2 Whether the component 41 emits light and delays the second serial data signal for a predetermined time to generate a third serial data signal (10). Referring to FIG. 3 and FIG. 5, in the embodiment, the target wafer 32i adopts the SN74LV595A cymbal (the price is lower than that of the commercially available sff side 5 specification, and the film is cheap), therefore, each target " 32ι has the following pins: syndrome, R^LK, two, SRClk, verification and Qh, where the pin δέ is pulled to the low level, the pin RCLK receives the latch signal Latch' pin and the friend is pulled To the high level, the pin 讥 "receives the clock signal Cloek, the pin SER receives the corresponding first - or the second serial poor signal SedalDatal, SerialData2, the pin Qa ~ Qh output corresponding to the first or second The control signal, the pin Qh, outputs a corresponding second or third serial data signal SerialData2, SerialData3. The first light-emitting unit Μ includes eight light-emitting elements 41. The second illumination sheet S 4_2 includes eight hairs: a piece 41. The first target chip 32 移位 shifts and latches the _ series data signal SeriaiDatai according to the rising edge of the clock signal (5) ck and the rising edge of the latch signal Lateh to generate eight first signals respectively. The person who controls the first light-emitting unit illuminates Μ ^ no light. The second target wafer 321_2 respectively shifts and latches the mth material μ Sena plate a2 according to the rising edge of the clock signal Cl0ck and the rising edge of the latch signal Lateh to generate a first: signal to respectively control The first light-emitting element 41 of the light-emitting unit core 2: No 201210405 Lights up. The first serial data signal SerialDatal carries sixteen bits of information. Since the target wafer 321 is latched according to the rising edge of the latch signal Latch, the latch signal Latch must be different from the load signal (SLoad) specified in the SFF_8485 specification to include the latch signal Latch in the first string/ After the data of the last bit of the data SerialData 1 is transferred, the latch is instructed to be latched. Therefore, the target wafer 321 is in accordance with the clock signal.
Clock的上升緣進行十六次移位操作後，才根據鎖存信號The rising edge of the clock is subjected to sixteen shift operations before it is based on the latch signal.
Latch的上升緣進行—次鎖存操作，來更新十六個發光元件 41的狀態。 ¥然，目標晶片32!也可以採用進行準位觸發式鎖存 的，它型號的“ ’在這種情況τ，鎖存信號可以是 在第_列貧料SerialDatal的最後一個位元的資料傳送完 ★畢後才指示進行鎖存，但也可以是像SFF_m5規格書所規 鞄的载入#號（SLoad )那樣，是在第一串列資料 SenalDatai的最後—個位元的資料傳送時指示進行鎖 參閱圖3，值得注意的是，在本银 可以是包括其它數目的目標曰片321貝/ 1 ，目標端32 件“的總數目及每一二片321 ^所要控制的發光元 而定。例二 數 最夕此控制的發光元件41的 數目為十六時，目標端32只需 第一目標晶片32W)就足以㈣+ 仏晶片321(即 …所要發光元件41。又例 田所要控制的發光元件41的總數目為二 標晶…多能控制的發光元件41的數目為八時母:標 201210405 端32需要包括三個目標晶y π ,〇 一 仏曰片321才足以控制二十個發光元 件41。ΐι二個目標晶片3 21八Βι丨s结 月为別疋弟一目標晶片321-1' 二目標晶片321-2，及串接太楚— Ψ接在弟一目標晶片321-2之後且基 於時脈信號Clock及鎖存作缺T + u _^ 久領件彳4 Lateh進行操作的另—個 晶片（圖未示）。 細上所述’與習知的控击丨禮& 士 W衩制杈組相比，本實施例藉由使 起始端3ΐ所產生的部分信號的時序不同於sff摘$規格 書的規範，可以採用市面上銷售的較便宜的晶片來作為目 標晶片32卜322,因此成本較低，確實能達成本發明之目 的。另外’本實施例藉由使目標晶片321產生串列資料# 號（例如：SerialData2、SerialData3 )，在需要串接更多個 目標晶片321以控制更多個發光元件41時，起始端η仍 只需要產生二個信號ClGek、Lateh、㈣仰如，因此起始 端11不需要以更多個晶片來實現，且控制模、组只需要利用 三條導線來在起始端31及目標端32之間傳遞信號。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍’即大凡依本發明申請專利 範圍及發明說明内容所作之簡單.的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一個方塊圖，說明習知的控制模組； 圖2是一個方塊圖，說明習知的控制模組用以控制更 多個發光二極體的狀況； 圖3是一個方塊圖，說明本發明控制模組之較佳實施 201210405 例； 圖4是一個時序圖，說明較佳實施例所產生的一個時 脈信號、一個鎖存信號及一個第一串列資料信號的時序； 及 圖5是一個電路圖，說明較佳實施例的目標晶片的一 種實施態樣。The rising edge of Latch performs a sub-latch operation to update the state of the sixteen light-emitting elements 41. However, the target chip 32! can also be used for the level-triggered latching, its model "' in this case τ, the latch signal can be the data transfer in the last bit of the first column of the poor material SerialDatal The latch is instructed after the completion of the completion of the message, but it can also be indicated by the load ## (SLoad) as specified in the SFF_m5 specification, when the data of the last bit of the first serial data SenalDatai is transmitted. Refer to Figure 3 for the lock. It is worth noting that the silver may include other numbers of target slabs 321 lb / 1 , the total number of target 32 pieces and the number of luminaries to be controlled for each two 321 ^ . In the case of the second embodiment, the number of the light-emitting elements 41 controlled by this time is sixteen, and the target end 32 only needs the first target wafer 32W) to be enough (four) + 仏 wafer 321 (ie, the light-emitting element 41 to be controlled. The total number of the light-emitting elements 41 is two-numbered crystals... The number of multi-energy-controllable light-emitting elements 41 is eight-time mother: the standard 201210405 end 32 needs to include three target crystals y π, and the one-chip 321 is sufficient to control twenty Light-emitting element 41. ΐι two target wafers 3 21 Β 丨 丨 结 结 为 为 为 一 一 一 目标 目标 目标 目标 目标 目标 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 After 2 and based on the clock signal Clock and latching the missing T + u _ ^ long collar 彳 4 Lateh operation of another wafer (not shown). Detailing the 'speak with the conventional control Compared with the 衩 衩 , , , , , , 本 本 本 本 本 本 本 本 本 本 本 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分The wafer 32 is 322, so the cost is lower, and the object of the present invention can be achieved. By causing the target wafer 321 to generate the serial data # (for example: SerialData2, SerialData3), when it is necessary to serially connect more target wafers 321 to control more of the light-emitting elements 41, the starting end η still only needs to generate two The signals ClGek, Lateh, and (4) are reversed, so the starting end 11 does not need to be implemented by more chips, and the control modes and groups only need to use three wires to transmit signals between the starting end 31 and the target end 32. The present invention is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, i.e., the equivalent changes and modifications made by the present invention in the scope of the invention and the description of the invention. It is still within the scope of the present invention. [Simplified Schematic] FIG. 1 is a block diagram showing a conventional control module; FIG. 2 is a block diagram showing a conventional control module for controlling more Figure 3 is a block diagram showing a preferred embodiment of the control module of the present invention 201210405; Figure 4 is a timing diagram illustrating a time produced by the preferred embodiment The timing of the pulse signal, a latch signal, and a first serial data signal; and Figure 5 is a circuit diagram illustrating an embodiment of the target wafer of the preferred embodiment.
10 201210405 【主要元件符號說明】 11 ····. 起始 32 •…目標端 12·.·.· ….目標端 321… 目才示BB片 121… 目才示B曰片 4 ...... •…發光單元 21 ••… …·發光二極體 41 ··..· •…發光元件 31 ··.·· •…起始端10 201210405 [Explanation of main component symbols] 11 ····. Start 32 •...Target end 12·.·.· .... Target end 321... The BB piece 121 is displayed... The B ... ... •...Lighting unit 21 ••...··Lighting diode 41 ··..·•...Lighting element 31 ······...Starting end