TW201216041A - CPU power supply circuit and operating method thereof - Google Patents

Abstract

A central processing unit (CPU) power supply circuit and an operating method thereof are provided. The CPU power supply circuit includes a power circuit, a sample unit, a switching unit and a comparator. The power circuit is connected with the power supply and the CPU. The power circuit includes an inductance having an output end which is connected with the CPU. The sample unit is connected with an input end of the inductance to sample an input signal for converting the input signal and providing a sample voltage. The switch unit is connected with a control end of the power circuit. The comparator is connected with the sample unit and the switch unit for comparing with the sample voltage and a reference voltage. When the sample voltage is smaller than the reference voltage, the comparator controls the switch unit to make the power circuit entering a continuous conduction mode.

Description

〇344twf.doc/n 201216041 VI. Description of the Invention: [Technical Field] The present invention relates to a power supply circuit, and more particularly to a central processing unit power supply circuit and a method of operating the same. [Prior Art] A general personal computer such as a notebook (n〇teb0〇k, nb) computer often uses a multilayer ceramic capacitor in the capacitance (for example, input capacitance) of a central processing unit (CPU) power supply circuit. (Multi-Layer Ceramic Capacitor, MLCC) 'To reduce costs and reduce component ©. However, when the operating frequency of the power supply circuit of the towel processing unit falls within the audio range that can be perceived by the human ear, components such as multi-layer ceramic capacitors emit audible noise due to the piezoelectric effect*. The traditional way to solve the problem of audio noise is to make the capacitors without piezoelectric effect, such as P〇lymerized 〇rgadc Seimconductor Capacitors (P0SCAP) or other electrolytic capacitors to reduce the audio caused by the change of πυ load. noise. However, p〇scAp has disadvantages such as high cost and large component area. [Summary of the Invention] The bribe supply-radio-based single-source source for Lin Lu and its operation method can effectively suppress the audio noise actively. The embodiment proposes a central processing which is connected between the power supply and the central processing unit. The above power supply 33344twf.doc/n 201216041 circuit includes a voltage conversion circuit, a sampling unit, a setting unit, and a comparator. The voltage conversion circuit includes an input capacitor and an inductor, and the input capacitor is connected to the power supply. The output of the inductor is connected to the central processing unit.

A sampling unit is coupled to the input of the inductor to sample an input signal at the input of the inductor. The sampling unit converts the input signal to provide a sampling voltage. a further unit is connected to one of the operating mode control terminals of the voltage conversion circuit. The comparator connects the sampling unit to the setting unit. The comparator compares the sampled voltage with a reference voltage. When the sampling voltage is less than the reference voltage, the comparator controls the setting unit such that the voltage conversion circuit enters a continuous conduction mode (CCM). In an embodiment of the invention, the voltage conversion circuit further includes The food device, the first power switch, the second power switch and the output capacitor. The regulator ^ has the above operation mode control terminal. The first power switch is respectively connected to the power source; the controller, the regulator, the input end of the inductor, and the sampling unit. The second power is connected to the first power switch, and the regulator and the inductor are respectively connected to the sampling unit. The output capacitor is connected to the output of the inductor and the central processing unit

In the implementation of the present invention, the light-difficult circuit is a town-level ceramic capacitor, and the input capacitors are respectively connected to the power supply and the first power supply s. In the embodiment of the invention, the regulator has - no connection & (DCM) and continuous conduction mode (CCM), when the central processing unit: load state 'regulator is in discontinuous conduction mode, and take ^ h reference *1 pressure 'adjustment H according to the operation mode of the setting unit enter _ _ formula. + Continuation of the guide in the present invention - the age of the towel, the sampling unit has a time delay effect 201216041 „344 twf.doc/n in one embodiment of the invention. In one embodiment of the invention, it becomes an analog signal. The input nickname is a pulse width modulation signal, and the sampling unit Μ converts the input signal in a frequency embodiment. The size and input signal of the input signal are provided. The embodiment of the present invention provides an operation method of the power supply circuit for controlling the connection to the surface supply H. The above-mentioned surface (four) circuit includes money, and the bet (four) is connected to the central processing unit 70. The above-mentioned method of the f-secret circuit includes: inputting the input signal of the input end of the inductor; converting the input money For sampling voltage; comparing the sampling voltage with the - reference voltage; if the sampling power is less than the reference, the voltage conversion circuit enters a continuous conduction mode (CCM). In the embodiment of the invention, the input signal is pulse width modulation Signal 0 In the embodiment of the present invention, wherein the step of converting the input signal to the sampling voltage, the magnitude of the sampling voltage is proportional to the frequency of the input money. The above embodiment of the present invention detects, by the sampling unit and the comparator, whether the voltage conversion electric power is tilted on the human ear to detect the audio range. When the voltage conversion circuit operates in the non-audio range, regardless of the voltage conversion circuit at the time In which operation mode, the comparator and the setting unit do not change the operation mode of the voltage conversion circuit. When the comparator detects that the voltage conversion circuit operates in the audio range, the comparator control setting unit 33344twf.doc/n 201216041 = The operation frequency of the L voltage conversion circuit is separated from the audio target. Therefore, the central processing source supply circuit disclosed in the embodiment of the present invention can effectively suppress the audio noise actively. In addition, the unit is a sampled electric recorder. The money at the end, so it can be electrically driven to drive the circuit.

The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] FIG. 1 is a schematic diagram showing the function modules of a central processing unit power supply circuit 1GG according to an embodiment of the present invention. The central processing unit power supply circuit 1 is connected to the power supply 102 and the central processing unit 1〇3. In the towel of this embodiment, the electric hybrid should be 1G2, and the electric sigh can be corrected (four) Qing). The power supply 102 can convert the commercial power 101 (AC voltage source) into an input voltage Vin, and then supply the input voltage Vin to the computer system. In the embodiment of the invention, the electric wire (10) further comprises (4) a conversion circuit for converting a plurality of sets of direct current voltages, which can convert a higher voltage vin (usually 19V) into a voltage required for each device, for example: 3.3 γ· In the present embodiment, the conversion circuit is a DC-DC power type conversion. In other implementations, the input Vin can also be supplied by the electric _, which is not limited by the present invention. In the computer system, the power supply circuit 1 converts the input voltage vin to the voltage level required by the central processing unit 1G3, and weaves the output voltage 201216041]-

Vout is output to the central processing unit 103 for supplying power to the central processing unit 103. In the present embodiment, the power supply circuit 1 includes a voltage conversion circuit 110, a sampling unit 120, a comparator 130, and a setting unit 14A. The voltage conversion circuit 110 is connected to the power supply 102 and the central processing unit 103' to convert the input voltage Vin into an output voltage v〇ut. The voltage conversion circuit 110 is operable in a discontinuous conduction mode (DCM) and a continuous conduction mode (CCM). When the central processing unit 1〇3 is in a low load state, the voltage conversion circuit 110 is in the discontinuous conduction mode (Dcm), and the sampling voltage Vsp is smaller than the reference voltage Vref, the voltage conversion circuit no is discontinuously turned on according to the operation of the setting unit 140. Mode (DCM) forces into continuous conduction mode (CCM). In this embodiment, the voltage conversion circuit further includes an inductor regulator 111, a first power switch Mu, a second power switch MD, an input capacitor cin, and an output capacitor Cout. The regulator 111 has an operation mode control terminal CCM#, and the regulator in has a discontinuous conduction mode (DCM) and a continuous conduction mode (CCM), which can control the voltage conversion circuit 110 according to the signal of the operation mode control terminal CCM#. Continuous conduction mode or continuous conduction mode. Generally, the signal connection of the operation mode control terminal CCM# is received from the chipset (for example, a south bridge chip or a platform controller hub (PCH), not shown) or the central processing unit 101 to receive a control signal. Switch to CCM. For example, in the present embodiment, 'the central processing unit 103', 'transfers the operation mode setting signal Vopm from the chip group to the regulator 111, 201216041 33344twf.doc/n or directly transfers the operation mode by the central processing unit 103. Setting signal

Vopm is given to regulator 111. In the present embodiment, the operation mode control terminal CCM# is also connected to the setting unit 14A, and a detailed description thereof will be described later. The regulator 111 is connected to the first power switch Mu, the second power switch MD and the setting unit 14 respectively. The first power switch 连接 is respectively connected to the power supply 102, the regulator in, the input of the inductor l, the sampling unit 120 and the input. Capacitor Cin. The second power switch MD is connected in series with the first power switch MU' and the second power switch MD is connected to the regulator m, the input of the inductor L and the sampling unit 12A, respectively. The input capacitor Cin is connected to the first power switch MU and the power supply 102, respectively. The input terminals of the inductors are connected to the first power switch MU, the second power switch MD, and the sampling unit 120, respectively. The output of the inductor L is connected to the central processing unit 1〇3 to supply the output voltage Vout. The output capacitor Cout is connected to the output of the inductor L and the central processing unit 103. In this embodiment, the input capacitor Cin is a multilayer ceramic capacitor (MLCC), and the output capacitor c〇ut is a polymer organic semiconductor solid electrolytic capacitor (P0SCAP). The sampling unit 120 is connected to the input end of the inductor L, the first power switch MU, and the second power switch MD to sample the input signal of the input end of the inductor L. The sampling unit 120 converts the input signal VL at the input of the inductor L to provide the sampling voltage Vsp to the comparator 13A. The comparator 13A is connected to the sampling unit 120 and the setting unit 140, respectively. The setting unit 14 is connected to the operation mode control terminal CCM# of the comparator 130 and the regulator m, respectively. 〇 344twf.doc/n 201216041 Setting unit HO connected to the electric house turn CCM# ’ 调 g g ηι > π ^ π琛 mode control mode (4) @之#作料(四)端CC:M#. The operation mode of the voltage conversion circuit (10) can be operated. When the operation mode control terminal CCM# is the first logic level: the operation mode of the heartbeat ST n〇 is the discontinuous conduction mode (DCM). When the operation mode control terminal CC is at the second logic level, the operation mode of the voltage conversion circuit 11G is the continuous conduction mode (CCM). For example, when the operation mode control terminal is at the first logic level, the operation mode of the voltage conversion circuit UG is a pulse ftequenCy modulation (PFM) mode, and when the operation mode control terminal is the second logic standard The operation side of the bit-time voltage conversion circuit 11G is a pulse width modulation (PWM) mode. For another example, when the operation mode control terminal is at the first logic level, the operation mode of the voltage conversion circuit u〇 is “auto mode” (for example, dynamically selecting the operation in the pFM mode or the PWM mode according to the load), and When the operation mode control terminal is at a high logic level, the operation mode of the voltage conversion circuit 110 is limited to the PWM mode. The sampling unit 120 samples the input signal VL at the input of the inductor L to provide the sampling voltage Vsp. In the present embodiment, the input signal VL is a pulse width modulation (PWM) signal of a digital type. The sampling unit 120 can convert the input digital type signal into an analog signal. In this embodiment, the sampling unit 120 can include a scale delay circuit (resistive capacitance delay circuit) to have a time delay effect to avoid sampling signals. The operation mode of the voltage conversion circuit 110 is switched too frequently. 33344twf.doc/n 201216041 The level of the sampling current Vsp is the pulse frequency corresponding to the signal VL, that is, corresponding to the operating frequency of the voltage conversion circuit 110, that is, the magnitude of the sampling voltage Vsp is proportional to the frequency of the input signal VL. When the voltage conversion circuit operates in discontinuous conduction mode (DCM), the operating frequency is proportional to the magnitude of the load current. The constant load current is reduced from high to high, which causes the operating frequency to decrease from high to high, so the sampling voltage Vsp will also decrease from high. Therefore, in the discontinuous conduction mode (DCM), the power conversion circuit 110 causes the operating frequency to enter the audio range (2〇!^ to 2〇KHz) due to the change of the load, and the sampling voltage Vsp falls correspondingly to a certain voltage. Range (hereinafter referred to as the first voltage range); similarly, when the voltage conversion circuit 11 is operated in the audio range (eg, several hundred KHz), the county voltage Vsp will fall correspondingly into another voltage range (hereinafter referred to as Second voltage range). Therefore, a reference voltage level can be selected between the aforementioned first voltage range and the second voltage range, and the reference voltage Vref can be set with reference to the voltage level. In other embodiments, the sampling unit 12G can count the number of digits and the number of digits. For example, the input end of the connector L is used to output the number of pulses of the 4th VL in unit time, and then the result is output to the digital analog conversion analog-to-digital converter to convert the count output from the counter into an analog sample. The voltage Vsp, 轮, outputs the sampled voltage v to the comparator 130. The comparator 130 receives the sampled ink % and controls the setting unit MO. When the sampling voltage Vsp is smaller than the reference voltage μ, the comparator 13 344 344 twf.doc/n 201216041 controls the operation of the setting unit 14G, forcing the f-voltage switching ramp m to enter the continuous conduction mode (CCM). Generally speaking, if the input capacitor Cin 丨 multi-layer ceramic capacitor (MLCQ 'the voltage conversion circuit (4) operates in discontinuous conduction mode (DCM) there will be noise problems, but the power conversion efficiency is higher. If the voltage conversion circuit no operates The continuous conduction mode (CCM) has no noise problem, but the power conversion efficiency is low. Therefore, when the comparator 130 detects that the voltage conversion circuit 11 is operating in the non-audio range, the comparator 130 controls the operation of the setting unit 14A to The operation mode of the voltage conversion circuit 110 is made as DCM as possible. When the comparator 130 detects that the voltage conversion circuit 11 is operating in the audio range, the comparator 130 controls the operation of the setting unit 140 to cause the setting unit 14 to change the voltage conversion circuit 110. The operation mode is CCM until the operating frequency of the voltage conversion circuit 11A is away from the audio range. Therefore, the present embodiment can operate the voltage conversion circuit 110 in the DCM while using a lower cost multilayer ceramic capacitor (MLCC) as the input capacitance. Cin. That is to say, the present embodiment can reduce the audio noise without sacrificing the power conversion efficiency. Because the voltage conversion circuit 11 〇 POSCAP and electrolytic capacitors may not be used, and the present embodiment can enjoy the cost and space benefits brought by the MLCC. In another embodiment, when the comparator 130 detects that the voltage conversion circuit 110 4 is in the non-audio range, 'Compare The operation of the voltage control circuit 110 is "automatic mode" for the operation of the control unit 14A. The automatic mode causes the voltage conversion circuit 110 to automatically select the operation according to the load 33344twf.doc/n 201216041 Frequency modulation CPFM) mode or pulse width modulation (pw In general, the operating frequency of the PWM mode is much higher than this ^ when comparing, please detect the power operation in the audio clock, than (4) 13G_ setting unit (10) = fixed unit 14 〇 Changing the operation mode of the voltage conversion circuit 11〇 to p, ^M mode 'until the operation of the electric (four) switching circuit 11G leaves the regulator m at least has the first-operation mode and the second operation mode ^. Han Hao early το 14G can be based on Sampling the voltage Vsp and changing the logic level of the mode control terminal CXM#, and entering the (4)_u 2 mode as the first operation mode or the second operation ^: The first operation mode may be a pulse width change, The conduction mode 'and the second operation mode can be = _ in a; f real patch, voltage conversion circuit (10) (four) for mode control mode control terminal CCM #) also via the setting unit = in another compact 2: 1 〇 S receive operating mode Set the signal V, connect the chip _ (four) bridge s object by the setting unit (10) so that the center l control the single coffee), not green), the signal vj ^ group transmission mode setting] 1 frequency conversion in the frequency range The circuit 11 决定 can determine the operation mode according to the operation mode signal ν_:: 201216041^, oc/n state output by the chip group. When the voltage conversion circuit 110 operates in the audio range, the setting unit 140 forcibly changes the operation mode of the voltage conversion circuit 11() to CCM (or PWM mode) until the operating frequency of the voltage conversion circuit 11() leaves the audio range. 2 is a circuit diagram showing the central processing unit power supply circuit 100 shown in FIG. The sampling unit 12A includes a first resistor R1 and a sampling capacitor CSp. The first end of the first resistor ri is connected to the input end of the inductor L, and the second end of the first resistor R1 is connected to the comparator 13A to provide the sampling voltage Vsp. The first end of the sampling capacitor Csp is connected to the second end of the first resistor R1, and the second end of the sampling capacitor Csp is grounded. In the embodiment shown in FIG. 2, comparator 130 includes an operational amplifier OP. The first input terminal (e.g., the inverting input terminal) of the amplifier op is coupled to the output terminal of the sampling unit 12G (the second end of the first resistor R1) to receive the sample and press Vsp. A second input of the operational amplifier 〇p (e.g., a non-inverting input) is coupled to the reference voltage Vref. The output terminal of the operational amplifier 〇p is connected to the setting unit 140. In the embodiment shown in FIG. 2, the setting unit 14A includes a second resistor R2 and a pull switch SW. The first end of the second resistor R2 is connected to the first voltage, and the second end of the resistor R2 is connected to the operating terminal of the voltage converting circuit 110 (the mode control terminal CCM# of the adjusting 11 111). The mode switch sw: the mountain-end is connected to the second resistor R2 (four) two ends. The jth of the mode switch SW is connected to the second f voltage. The control terminal of the mode switch sw is connected to two of the comparators 13 (the output of the operation is amplified by 11 0P). In the embodiment shown in FIG. 2, the voltages of the first voltage and the voltage are respectively the line voltages vcc and the ground voltages of 201216,041,344,344,400. In other embodiments, the first voltage can be a ground voltage and the second voltage can be a system voltage vcc. In the embodiment shown in Fig. 2, the front stage component (e.g., the towel center unit 1G3 or the crystal plate) can supply the operation mode setting signal Vopm in an open draine manner. Figure 3 is a timing diagram showing the timing of the circuit of Figure 2 in accordance with an embodiment of the present invention. Referring to Fig. 2 and Fig. 3, the voltage conversion circuit 11() can dynamically determine the operation mode by the operation mode setting signal output from the central processing unit 1G3 or the chipset. t The central processing unit 103 is heavily loaded, and the voltage conversion circuit 110 is operated in the PWM mode. At this time, the voltage is switched to two, and the frequency is fixed at a certain rate (higher than the tone 31 operation ' 曰 3 is light load' The voltage conversion circuit 110 is in the "mode" mode, which is the dynamic rate according to the load state. Therefore, in the W mode, the electrical miscellaneous power may operate in the sound state according to the load state (four). For reference to the cake, so the mode closes the SW to stop the nj series of low-precision V, the op amp test voltage level, so the die-off switch sw is the lead-off logic for the two voltages of the voltage conversion circuit 110 & a, 'set The lowering of the potential of the unit control terminal _) == (the operation mode bit of the mode converter circuit m of the regulator 1U) is changed to the PWM mode by the strong return. Therefore, the present invention 201216041 ^344twf.doc/n The central processing unit power supply circuit 100 disclosed in the embodiment can effectively suppress the audio noise actively. For another example, when the central processing unit 103 is in a low load state, the regulator 111 is in the discontinuous conduction mode (DCM) ' and the sampling voltage Vsp is smaller than the reference. Regulator 111 when voltage Vref According to the operation of the setting unit 14〇, the continuous conduction mode (CCM) is entered by the discontinuous conduction mode (DCM). Therefore, the power supply circuit 1 disclosed in the embodiment of the present invention can effectively suppress the audio noise actively. FIG. 4 is in accordance with FIG. Another embodiment of the present invention is a circuit diagram of the central processing unit power supply circuit 100 shown in Fig. 1. For details of Fig. 4, reference may be made to the related description of Fig. 1 and Fig. 2. Fig. 4 is different from Fig. 2 in the figure. An embodiment of the setting unit 140 of 4. It is assumed here that the pre-stage element (for example, the central processing unit 103 or the chip set) supplies the operation mode setting signal Vopm in a push-pull manner (push_puU). To avoid the operation of the setting unit 140 The operation mode setting signal supplied by the preamplifier element conflicts, so the first end of the second resistor R2 receives the operation mode setting signal Vopm' as shown in FIG. 4. When the voltage conversion circuit 11 is operated in the ^: frequency range' The control voltage outputted by the operational amplifier 〇p is at a logic high level and the mode is turned off to be in an on state, so the setting unit 14 将^ operates the mode of the voltage conversion circuit 110 The potential of the terminal (modulation control terminal CCM#) of the terminal (t4) is pulled down to the logic scale & to force the change of the operation mode of the voltage conversion circuit m to CCM (or the operating frequency of the pwM mode to the voltage conversion circuit 110 to leave the audio range. 16 201216041 33344twf.doc/n In the above embodiment, the hysteresis effect can be added to the comparator 13 or the Rc delay effect can be added to the setting unit 14 to adjust the sensitivity of the action, while taking into account the energy saving effect of the DCM and the human ear. Feeling. For example, FIG. 5 is a circuit diagram showing a central processing unit power supply circuit 1A shown in the drawing in accordance with still another embodiment of the present invention. The details of Fig. 5 can be referred to the related description of Figs. i, 2 and 4. Fig. 5 is different from Fig. 4 in the embodiment of the setting unit 14A of Fig. 5. The setting unit 14A shown in FIG. 5 includes a second resistor R2, a mode switch sw, a second resistor R3, a diode D1, and a delay capacitor cd. The first terminal of the second resistor R2 receives the operation mode setting signal Vopm, and the second terminal of the second resistor R2 is connected to the operation mode control terminal of the voltage conversion circuit 110 (the mode control terminal CCM# of the regulator ln). The first end of the mode switch SW is connected to the second end of the second resistor R2, and the second end of the mode switch sw is connected to a second voltage (for example, a ground voltage. The first end of the third resistor R3 is connected to the output end of the comparator 13? Receiving a control voltage VC. The second end of the third resistor scale 3 is connected to the control end of the mode switch. The anode of the diode D1 is connected to the first end of the third resistor Rg, and the cathode of the diode m is connected to the third resistor R3. The second end, the delay capacitor Cd is connected to the second end of the third resistor R3. The third resistor R3, the diode D1 and the delay capacitor Cd are added to the setting unit 14〇j, so that the mode switch sw is turned on quickly. And the delay cutoff (tum〇ff), so as to prevent the voltage conversion circuit 110 from switching back and forth between the PWM mode and the PFM mode. Fig. 6 is a flow chart showing the operation method of the above power supply circuit 1 according to an embodiment of the present invention. This method of operation can control the voltage conversion circuit 110 connected between the power source 17 201216041; 344 twf.doc/n provider 102 and the central processing unit 1 〇 3. First, the sampling unit 120 proceeds to step S610 to sample the voltage conversion circuit 110. The input signal VL of the input terminal of the central processing unit 1〇3 is connected. Next, the sampling unit 12〇 performs step s62〇 to convert the input signal VL to the sampling voltage Vsj^, and then the comparator 13 performs step S630' To compare the sampling voltage Vsp with the reference voltage Vref. If the sampling voltage Vsp is less than the reference voltage Vref, the comparison $(10) controls the electric house conversion 11〇 through the setting unit 140, so that the electric conversion circuit 110 enters the continuous conduction mode (step S64G). The wire sample money % is greater than the test voltage vref, and the comparator 13 〇 controls the voltage conversion circuit 110 ′ through the setting unit 14 使得 to make the voltage conversion circuit n mode (step S650 ). The mussels are equal to the central portion disclosed in the second embodiment. The processing unit power supply circuit _ 疋 轻 轻 电路 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷==Frequency, as a feature of identifying whether there is noise, the operation mode of the ΐ voltage-converting circuit 110, although , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The field towel has the usual knowledge. Within 18 33344 twf.d〇〇/n 201216041, when some changes and refinements can be made, the scope of this application is subject to the definition of the patent application scope. BRIEF DESCRIPTION OF THE DRAWINGS (cpuUi is a schematic diagram of a functional module of a central processing unit supply circuit according to an embodiment of the present invention. Fig. 2 is a diagram showing a central processing power supply 1_(4) shown in Fig. 。 according to an embodiment of the present invention. The embodiment of the invention illustrates a schematic diagram of the circuit sequence shown in FIG. 4 is a diagram illustrating the power supply of the central processing unit of FIG. 1 in accordance with another embodiment of the present invention. FIG. 5 is a schematic diagram showing the power supply circuit of the central processing unit of FIG. 1 according to still another embodiment of the present invention. FIG. 6 is a flow chart showing an operation method of a power supply circuit according to an embodiment of the present invention. [Description of main component symbols] 100: power supply circuit 101 = mains supply 1〇2: power supply 103: central processing unit 110: voltage conversion circuit ui: regulator MU: first power switch MD: second power switch ΟΡ: operation Amplifier R1: first resistor R2: second resistor R3: third resistor 201216041 ^344twf.doc/n 201216041 ^344twf.doc/n 120: sampling unit 130: comparator 140: setting unit Cd: delay capacitor Cin: input capacitor Cout : Output capacitor Csp : Sampling capacitor D1 : Diode L : Inductance S610 ~ S650 : Step SW : Mode switch VC : Control voltage

Vin : input voltage VL : signal at the input of the inductor

Vopm: operation mode setting signal

Vout: output voltage

Vref: reference voltage

Vsp: sampling voltage

20

Claims (1)

33344twf.doc/n 201216041 VII. Patent application scope: 1. A central processing unit power supply circuit, connected to a power supply and a central processing unit, comprising: a voltage conversion circuit comprising an input capacitor and an inductor The input capacitor is connected to the power supply, an output end of the inductor is connected to the central processing unit; a sampling unit is connected to an input end of the inductor to sample the inductor An input signal of the input terminal, and converting the input signal to provide a sampling voltage; a setting unit connected to an operation mode control end of the voltage conversion circuit; and a comparator connecting the sampling unit and the setting unit, The comparator compares the sampling voltage with a reference voltage, and when the sampling voltage is less than the reference voltage, the comparator controls the setting unit such that the voltage transitions into a continuous conduction mode. 2. The power supply circuit as described in claim 1 of the patent scope, the voltage conversion circuit in JL further includes: ', six different line mode control terminal; (4) rate switch, which is connected to the power supply, The regulator is connected to the sampling terminal of the inductor and the sampling unit; and is connected in series to connect the first power switch, and the input terminal of the inductor and the sampling unit; - an output capacitor 'connecting the output of the inductor to the central processing, 21 201216041" axis oc / n 3. The power supply circuit as described in claim 2, the middle layer of ceramic capacitors, and the input capacitors respectively Connect the power supply to read the first rate switch. The power supply circuit of claim 2, wherein the continuous conduction mode and the continuous conduction mode, when the state is in a low load state, the regulator is in the discontinuous edge 12, the sampling voltage is less than the reference voltage The regulator operates as early as 70 and enters the continuous by the discontinuous conduction mode Conduction mode. 5. The power supply circuit of claim 1, wherein the sampling unit has a time delay effect. 6. The power supply circuit of claim 1, wherein the input signal is a pulse width modulation signal. 7. The power supply circuit of claim 1, wherein the sampling unit converts the input signal into an analog signal. 8. The power supply circuit of claim 2, wherein the magnitude of the sampled voltage is proportional to a frequency of the input signal. 9. A method of operating a power supply circuit for controlling a voltage conversion circuit coupled between a power supply and a central processing unit, the voltage conversion circuit including an "inductance" a processing unit, the method comprising: sampling an input signal at an input end of the inductor; converting the input signal to a sampling voltage; comparing the sampling voltage with a reference voltage; and 22 201216041 33344twf.doc/n if the sampling voltage is less than The reference voltage causes the voltage conversion circuit to enter a continuous conduction mode. 10. The method of operation of claim 9, wherein the input signal is a pulse width modulation signal. 11. The method of operation of claim 9, wherein in the step of converting the input signal to the sampled voltage, the magnitude of the sampled voltage is proportional to the frequency of the input signal. twenty three