201214574 六、發明說明： 【發明所屬之技術領域】 本 = 月係關於-種電晶體結構及其製作方法，特別是關於一種可 收尚閘極通道應力值的電晶體結構及其製作方法。 【先前技術】 隨著積體電路變得更小且更快，現今採用應變石夕 ㈣1ned蠢0n)」技術’來增加載子的移動率，以提升電晶體速度。 為了增加載子移動率’已知可形成—個應力的㈣道，應力能增加 電子團和電_的移動率’使得電晶體能透過應力通道來增強效 能，此技術可在_長度不變的情況下來改進電晶體速度效能，而 不須增加電路製造或設計的複雜度。 一般來說，應力的料道可以藉由町兩種方式賴：第一種 方式是利㈣成在電Μ關的應力_，例如沈積在多晶石夕間極 上的應力膜或者在魏金屬層形成後才沈積的接觸刻停止層， 此方式又被稱做「製程誘發應變(pr〇cess—in—㈣」；另一種 方式則是直接應變料_行元件的製作。後者之應變石夕晶圓 的作法係在晶格常數較矽大的半導體基材上成長出應變矽層。 然而’於65 nm或更小尺寸之技術中，需要更高速度的電晶體， 因此需要更進一步提升矽通道的應力值。 201214574 【發明内容】 有鑑於此，本發日繼—種電晶體的製作方法可提祕通道的應201214574 VI. Description of the invention: [Technical field to which the invention pertains] This is a structure of a transistor and a method for fabricating the same, and particularly relates to a transistor structure capable of receiving a stress value of a gate channel and a method of fabricating the same. [Prior Art] As integrated circuits become smaller and faster, strain strains are used today to increase the mobility of carriers to increase the speed of the transistors. In order to increase the carrier mobility rate, it is known that a stress can be formed (four), and the stress can increase the mobility of the electron group and the electricity _ so that the transistor can pass through the stress channel to enhance the performance. This technique can be used in the _ length. The situation improves transistor speed performance without increasing the complexity of circuit fabrication or design. In general, the stress channel can be relied on by the two methods: the first way is to make the stress in the electric _, such as the stress film deposited on the polycrystalline slab or in the Wei metal layer. The contact stop layer deposited after formation, this method is also called "process induced strain (pr〇cess-in-(4)"; the other method is the production of direct strain material_row element. The round method is to grow a strained germanium layer on a semiconductor substrate with a relatively large lattice constant. However, in a technology of 65 nm or less, a higher speed transistor is required, so that the germanium channel needs to be further improved. The stress value. 201214574 [Summary of the Invention] In view of this, the method of making a transistor can be used to improve the channel.
本發明提供-種電晶體的製作方法，料提供—基底其上具有一 閑嫩十繼谢⑽較關，接著分卿成 -淺冰卿_ly d_ drain，_區於閘極之二側之基底中， 再形H儀子包含—含侧壁子和—犧牲嫩子於第一側壁 子上’其中含碳側壁子接觸第一側壁子之表面，且犠牲側壁子位於 含碳側壁子之表面，之後形成一源㈣及極摻雜區於閘極之二側之基 斜，移_牲舰子，㈣分之含碳趣子，使含補壁子形成 L型’最後’形成-金屬石夕化物層位於源極/沒極換雜區上，其中 金屬梦化物層較源極/沒極摻雜區接近閘極。 本發明提供-種電晶體結構，包含：—基底，—電晶體設於基底 上其中電晶體包含：一閘極設於基底上，一複合側壁子至少位於 間極之兩側’其中複合側壁子之最外層表面具有—L型輪廓，一源 極/沒極摻雜區位於閘極之二側的基底中以及—金屬魏物層位於 源極/;及極摻雜區上，其巾金屬石夕化物層較源極/沒極摻雜區接近閘 極。 本發明利用不同側壁子中的含碳濃度不同，在濕式蝕刻時，使得 含碳漢度高的側壁子被保留，而含碳濃度低的側壁子被移除，因此 在餘留在閘極上的側壁子之寬度變小，使得後續在電晶體上形成應 力膜時’可以提供閘極通道較大的應力值。 201214574 【實施方式】 第1圖至第5圖為根據本發明之一較佳實施例所繪示的一種電晶 體的製作^法之示意^第6晴示的是—_式場效電晶體之側視 不意圖。如第1圖所示，首先提供-基底10其上定義有-第-電晶 體區1000和-第二電晶體區2〇〇〇 , 一淺溝渠絶緣12電性絶緣第一 電晶體區1000和第二電晶體區2〇〇〇，一第一閘極14和一第二問極 16分別設於基底1〇之第一電晶體區1〇〇〇和第二電晶體區誦之 上表面’於第-閘極14和基底1〇之間設有一第一問極介電層18， 於第一閘極16和基底1G之間财-第二閘極介電層2G。隨後於第 一閉極16兩側分別形成一凹槽22,再利用▲晶製程於凹槽22中形 成石夕化錯或切之為層24。接著形成—第―㈣子材料層％ 順應的覆蓋第-閘極14、第二閘極16、基底1〇表面和蟲晶層％ 表面’位於第-閘極14和第二閘極16週圍的第一側壁子材料層％ 定義為第—側壁子28，然後利用第—側壁子28、第-閘極14和第 二閘極16為遮罩，形成一淺摻雜沒極(_y doped drain，LDD)區 30、32於分別於第一閘極14和第二間極16二側的基底财。 如第2圖所示，形成一第二側壁子材料層％順應的覆蓋第一側 壁子材料層26，其中第二側壁子材料層34可以由多層材料構成， 例如為-含碳側壁子材料層36和一犠牲側壁子材料層％，以使得 最後所形成的第二麵子為多層側壁子，第二側壁子之結構請參閱 後續步驟之崎含·壁子材㈣36可以_驗_法或離子 植入法形成，詳細來說，原位捧雜法其施行方式可以在化學氣相沉 積時同時通人碳離子，以形成含碳的側壁子材料層％，舉例而言: 201214574 將含碳氣體以100至1500 sccm流量通入反應室，較佳的流量為丨2⑻ seem，以形成含碳的側壁子材料層36，而離子植入法其施行方式係 為先形成-側壁子材制紐翻_子植人法植人碳，以形成含 碳側壁子材料層36 ’舉例而言’離子植人法可在側壁子材料層中植 入10E21至lGE22atm/em3的碳，以形成含碳㈣子材料層％，然 後經過後續的蝕刻形成含碳側壁子。含碳側壁子材料層36較佳為含 碳的氮化矽，其具有一第一碳濃度，較佳介於1〇E21至l〇E22 atm/cm3 之間。 另外，犠牲側壁子材料層38的形成方式可以是在含碳側壁子材 料層36完成之後，在同一個反應室(圖未示)中接續形成犧牲側壁子 材料層38。犠牲側壁子材料層38可以選擇性地含碳或不含碳，只 義牲側壁子材料層38中的第二碳濃度比含碳的側壁子材料層％ 之第碳/辰度低即可’在不含碳的情況下，犠牲側壁子材料層％ 之第二碳濃度為零。同樣地，犠牲側壁子材料層38的形成方式可以 為化學氣她積法，而使其含碳方式可以絲位摻雜法或離子植入 法’並且犠牲側壁子材料層38較佳為氮化矽。舉例而言，將含碳氣 體以0至1500 sccm流量通入反應室，較佳的流量為〇_，以形 成犠牲側壁子材料層38。如第3圖所示，利用乾式侧，侧犧牲 側壁子材料層38以及含碳側壁子材料層36，以形成一含碳側壁子 40和-犠牲側壁子42’由於含碳側壁？ 4〇和犠牲側壁子42係由蝕 刻犠牲側壁子材料層38以及含碳側壁子材料層36而來，因此含碳 側壁子40亦含有與含碳讎子材觸36 _的第—賴度，而犧 牲側壁子42亦含有與犠牲侧壁子材料層38相同的第二碳濃度，如 201214574 刖所述’第-碳献大於第二碳濃度，而第二碳濃度可以選擇性地 為零’於本發明之触實施例巾，第二碳濃度較佳為零，也就是說 儀牲側壁子42中不含碳。值得注意的是：根據產品設計不同，第一 石反濃度也可隨之調整。另外，第一碳濃度之分佈可以為一固定值， 也就是說在含碳的側壁子4〇的各個部分，都具有相同碳濃度；當 然’第-碳漢度之分佈可以為一變化值，例如較靠近閘極14 ' 16 的含石反側壁子40之部分具有較高的碳濃度，而較遠離閘極14、16 的部分具有較低的碳濃度。同樣地第二碳濃度之分佈也可以為一固 定值或是其分佈亦可以為一變化值，若是第二碳濃度之分佈為一變 化值’則較靠近閘極14、16的犠牲側壁子42之部分具有較高的碳 濃度，而較遠離閘極14、16的部分具有較低的碳濃度。 在含碳側壁子40和犠牲側壁子42完成之後，利用第一間極14、 第二閘極16、第一側壁子28和含碳側壁子4〇和犠牲侧壁子42為 遮罩’於第—閘極14和第二閘極16的兩側之基底⑴中分別形成一 源極/汲極摻雜區44、46。 如第4圖所心利用濕式侧，例如利用熱鱗酸移除犧牲側壁子 42，和部分的含碳側壁子4〇，侧壁子令的含碳濃度高低會影響到熱 碟酸侧側壁子的速率，因此，熱伽會對含碳濃度不相同的含碳 側壁子4〇和罐子，含韻度較高的 側壁子較不容易被熱鱗酸去除，因此在濕式韻刻步驟之後，大部分 的含碳側壁子4G會訂，並且形成-L型，而難側壁子42 = 全被去除。當然’在不同的實施例中，調控犧牲側壁子％内的含碳 濃度後，亦可以使熱磷酸只移除部分的犧牲側壁子幻。 3火 201214574 如第5圖所示’進行一金屬石夕化製程，於LDD區30、32和源極 /汲極摻雜區44、46上方拟屮人 、 肜成一金屬矽化物層50,金屬矽化物層50 車父源極Λ及極推雜區44靠折笛一 pa, 迎第一閘極14 ’金屬矽化物層50較源極/ 及極摻_6 #近第二閘極16。至此本發敗電晶魏構％業已 完成。隨後可以在後續的製財於電晶體結構上形成-應力膜，以 在第-閘極Μ和第二閘極16下方的基底ι〇内形成應力的料道。 根據本發明之另-較佳實施例，本發明提供—種電晶體結構，其 中具有相同魏的元件將_同的標號表示，如第5麟示，一第 電曰日體54包3基底1〇，一第一開極14設於基底川上，一第 閘極”電層18 δ又於第一閘極14和基底1〇之間，一複合側壁子 58至夕位於第-閘極14之兩側，其中複合側壁子％之最外層表面 具有一 L型輪廓，二源極/汲極摻雜區6〇、62分別位於第一閘極14 之二側的基底10中，以及一金屬矽化物層5〇位於源極/汲極摻雜區 60、62上。其中複合側壁子58包含一第一側壁子28和一含碳側壁 子40，第一側壁子28接觸第一閘極14，含碳側壁子4〇接觸第一側 壁子28，含碳側壁子40的外層表面即是複合側壁子58之最外層表 面。另外’含碳側壁子40中的碳濃度較佳介於ι〇Ε2ΐ至10Ε22 atm/cm3之間，含碳側壁子40較佳為含碳的氮化矽。 再者’第一電晶體54的源極/沒極摻雜區60、62分別包含一 LDD 區30和一源極/汲極摻雜區44，LDD區30具有一第一底部64和一 第一前鋒(front)66，而源極/汲極摻雜區44具有一第二底部68和一 第一則鋒70。而LDD區30較淺，源極/;及極捧雜區44較深，換句 話說’第一底部64與基底10表面之間的距離較第二底部68與基底 201214574 10表面之間的距離小，而LDD區30和源極/汲極摻雜區44之重疊 部分形成-重叠區72。此外，第一前鋒66與第一閘極14之間的距 離較第二前鋒7G與第-閘極14之間的距離小。 值得注意的是’金屬石夕化物層5〇覆蓋第二前鋒7〇，詳細來說金 屬石夕化物層50覆蓋重疊區72和沒有與源極/沒極換雜區44重疊的 部分LDD區30，此外金屬矽化物層5〇較源極/汲極摻雜區44靠近 第一閘極14。 此外，本發明的電晶體結構中的源極/汲極換雜區可以另包含有 蠢晶層’如第5圖所示’ -第二電晶體56包含一第二閘極16設於_ 基底10上’一第二閘極介電層2〇設於第二閘極16和基底1〇之間， 一複合側壁子58至少位於第二閘極16之兩側，其中複合側壁子58 之最外層表面具有一 L型輪廓，二源極/汲極摻雜區wo、162分別 位於第二閘極16之二側的基底1〇中，以及一金屬矽化物層5〇位於 源極/汲極摻雜區160、162上。其中複合側壁子58包含一第一側壁 子28和一含碳側壁子40，第一側壁子28接觸第二閘極16，含碳側 壁子40接觸第一側壁子28 ,含碳側壁子40的表面即是複合側壁子鲁 58之最外層表面。另外，含碳側壁子40中的碳濃度較佳介於1〇E21 至10E22 atm/cm3之間’含碳側壁子40較佳為含碳的氮化矽。 再者，電晶體結構56的源極/汲極搀雜區160、162分別包含一 LDD區32和一源極/沒極摻雜區46，LDD區32具有一第一底部164 和一第一前鋒(front)166，而源極/;及極摻雜區46具有一第二底部168 和一第二前鋒170。而LDD區32較淺，源極/没極摻雜區46較深， 而LDD區32和源極/汲極摻雜區46之重疊部分形成一重疊區172。 10 201214574 此外’第一則鋒166與第二閘極16之間的距離較第二前鋒17〇與第 二閘極16之間的距離小。金屬石夕化物層5〇覆蓋第二前鋒17〇。金 屬矽化物層50覆蓋重疊區172和沒有與源極/汲極摻雜區恥重疊的 部分LDD區32，而金屬矽化物層％較源極/汲極摻雜區牝靠近第 二閘極16。 另外複合侧壁子58可以僅位於第一閘極14之兩側和第二閘極 16之兩側，也可以是環繞第一閘極14和第二閘極16。 • 此外，本發明之方法可以利用於各式電晶體，例如埋入式通道元 件(buried channel device)、金屬-絕緣體-半導體場效電晶體(misfet) 或是非平面型電晶體，例如縛式場效電晶體(FinFET)或三間極場效 電晶體(Tri-gate)。舉例而言，如第6圖所示，一鰭式場效電晶體2〇〇 具有-閘極結構202 ’ -箱狀結構2〇4，源極/汲極捧雜區260、262 位於閘極結構202兩側，源極/汲極摻雜區26〇、262分別包含一 LDD 區230和一源極/汲極摻雜區244，一複合側壁子258設於閘極結構 202上，複合側壁子258如同第5圖中的複合侧壁子％ 一樣包含一 •含石厌側壁子24〇和一第一側壁子228，其製作方式已在第i圖至第4 圖敘述，在此不再贅述。另外於源極/汲極摻雜區26〇、262上另設 有一金屬矽化物層250，金屬矽化物層25〇較源極/汲極摻雜區244 接近閘極結構202。 於本發明中特意將部分在閘極上的側壁子在源極/汲極摻雜區完 成之後去除’由於側壁子變薄’使得後續沉積的應力膜可使應力的 矽通道產生更向的應力，以提升電晶體的速度。另外，由於熱填酸 對不同含碳濃度的侧壁子有不同的選擇比，因此可以藉由側壁子的 201214574 含碳激度來控制側壁子需要被移除的部分，並且保留足夠的側壁子 寬度在閘極上。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範園 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第5圖為根據本發明之一較佳實施例所繪示的一種電晶 體的製作方法之示意圖。 第6圖繪示的是一鰭式場效電晶體之側視示意圖。 【主要元件符號說明】 10 基底 12 淺溝渠絶緣 14 第一閘極 16 第二閘極 18 第一閘極介電層 20 第二閘極介電層 22 凹槽 24 蠢晶層 26 第一側壁子材料層 28、 228 第一側壁子 30、32、LDD 區 34 第二側壁子材料層 230 36 含碳側壁子材料層 38 犠牲側壁子材料層 40、240 含碳側壁子 42 犠牲側壁子 50、 金屬矽化物層 12 201214574 250 52 電晶體結構 54 56 第二電晶體 58 ' 258 44、46、 源極/汲極摻雜區 64、 60、62、 164 第一電晶體 複合側壁子 第一底部 160、 162、 ® 230、 244、 260 、 262 66、166 第一前鋒 68、 168 70、170 第二前鋒 72 > 172 200 縛式場效電晶體 202 204 鯧狀結構 1000 2000 第二電晶體區 第二底部 重疊區 閘極結構 第一電晶體區 13The invention provides a method for fabricating a kind of transistor, which is provided with a substrate having a leisurely tenth step (10), and then divided into a shallow ice _ly d_drain, and the _ area is on the two sides of the gate. In the substrate, the reshaped H-meter includes - containing a sidewall and a sacrificial tender on the first sidewall, wherein the carbon-containing sidewall contacts the surface of the first sidewall, and the sidewall is located on the surface of the carbon-containing sidewall Then, a source (four) and a highly doped region are formed on the two sides of the gate, and the base is inclined, and the carrier is submerged, and (4) is divided into carbon-containing fungs to form an L-shaped 'final' formation-metal stone. The Xiyang layer is located on the source/drain-changing region, wherein the metal dream layer is closer to the gate than the source/dope-doped region. The invention provides a transistor structure comprising: a substrate, wherein the transistor is disposed on the substrate, wherein the transistor comprises: a gate is disposed on the substrate, and a composite sidewall is located at least on both sides of the interlayer; wherein the composite sidewall The outermost surface has an -L-shaped profile, a source/dot-doped region is located in the substrate on both sides of the gate, and a metal-wet layer is located at the source/; and the highly doped region, the metallization of the metal The cation layer is closer to the gate than the source/dot doped region. The present invention utilizes different carbon concentration in different sidewalls, so that in the wet etching, the sidewalls with high carbon content are retained, and the sidewalls with low carbon concentration are removed, so that they remain on the gate. The width of the sidewalls becomes smaller, so that when a stress film is formed on the transistor, a larger stress value of the gate channel can be provided. 201214574 [Embodiment] Figs. 1 to 5 are diagrams showing the fabrication of a transistor according to a preferred embodiment of the present invention. The sixth embodiment shows the side of the -type field effect transistor. Do not intend. As shown in FIG. 1, firstly, a substrate 10 is defined with a -first transistor region 1000 and a second transistor region 2, a shallow trench insulation 12 electrically insulating the first transistor region 1000 and The second transistor region 2〇〇〇, a first gate 14 and a second gate 16 are respectively disposed on the first transistor region 1〇〇〇 of the substrate 1 and the upper surface of the second transistor region ' A first interposer dielectric layer 18 is disposed between the first gate electrode 14 and the substrate 1A, and a second-gate dielectric layer 2G is disposed between the first gate electrode 16 and the substrate 1G. A recess 22 is then formed on each side of the first closed pole 16 and then formed into a layer 24 by the ▲ crystal process in the recess 22. Then, the - (four)th material layer % compliant coverage of the first gate 14 , the second gate 16 , the substrate 1 和 surface and the worm layer % surface 'is located around the first gate 14 and the second gate 16 The first side wall material layer % is defined as the first side wall 28, and then the first side wall 28, the first gate 14 and the second gate 16 are used as a mask to form a shallow doped drain (_y doped drain, The LDD) regions 30, 32 are on the two sides of the first gate 14 and the second interpole 16 respectively. As shown in FIG. 2, a second sidewall sub-material layer is formed to conform to the first sidewall sub-material layer 26, wherein the second sidewall sub-material layer 34 may be composed of a plurality of layers, for example, a carbon-containing sidewall material layer. 36 and a layer of the material layer of the sidewall material, so that the second surface formed is a multi-layered side wall. For the structure of the second side wall, please refer to the subsequent steps of the wall-containing material (four) 36 can be _ test _ method or ion implant In the formation of the method, in detail, the in-situ method can be carried out in the chemical vapor deposition at the same time to pass carbon ions to form a carbon-containing sidewall material layer %, for example: 201214574 to carbon-containing gas A flow rate of 100 to 1500 sccm is introduced into the reaction chamber, preferably at a flow rate of 丨2 (8) seem, to form a carbon-containing sidewall material layer 36, and the ion implantation method is performed first by forming a side wall material. The implanted human carbon is used to form the carbon-containing sidewall material layer 36'. For example, the ion implantation method can implant 10E21 to lGE22atm/em3 carbon in the sidewall material layer to form a carbon-containing (tetra) sub-material. Layer %, then subjected to subsequent etching Into sub carbonaceous sidewalls. The carbon-containing sidewall material layer 36 is preferably a carbon-containing tantalum nitride having a first carbon concentration, preferably between 1 〇 E21 and 1 〇 E22 atm/cm 3 . Alternatively, the sacrificial sidewall material layer 38 can be formed by successively forming a sacrificial sidewall sub-material layer 38 in the same reaction chamber (not shown) after completion of the carbon-containing sidewall sub-material layer 36. The sacrificial sidewall material layer 38 may be selectively carbon-free or carbon-free, and the second carbon concentration in the sidewall material layer 38 may be lower than the carbon/thinth of the carbon-containing sidewall material layer. In the absence of carbon, the second carbon concentration of the material layer of the sidewall material is zero. Similarly, the layer of the sidewall material layer 38 may be formed by a chemical gas deposition method, and the carbon-containing method may be a silk-doping method or an ion implantation method, and the sidewall material layer 38 is preferably nitrided. Hey. For example, the carbonaceous gas is passed into the reaction chamber at a flow rate of 0 to 1500 sccm, preferably at a flow rate of 〇, to form a layer 38 of the sidewall material. As shown in Fig. 3, with the dry side, the side sacrificial sidewall material layer 38 and the carbonaceous sidewall material layer 36 are formed to form a carbon containing sidewall 40 and a sidewall portion 42' due to the carbon containing sidewalls. The 〇 and 犠 sidewalls 42 are etched from the sidewall material layer 38 and the carbon-containing sidewall material layer 36, so the carbon-containing sidewall 40 also contains the first lag with the carbon-containing raft material. The sacrificial sidewall 42 also contains the same second carbon concentration as the sidewall material layer 38, as described in 201214574 ' 'the first carbon contribution is greater than the second carbon concentration, and the second carbon concentration can be selectively zero. In the embodiment of the present invention, the second carbon concentration is preferably zero, that is, the instrument side wall 42 contains no carbon. It is worth noting that depending on the product design, the first stone counter concentration can also be adjusted accordingly. In addition, the distribution of the first carbon concentration may be a fixed value, that is, the carbon concentration of each side of the carbonaceous side wall 4 〇 has the same carbon concentration; of course, the distribution of the first carbon-carbonity may be a change value. For example, the portion of the stone-containing anti-wall 40 that is closer to the gate 14' 16 has a higher carbon concentration, while the portion that is farther from the gates 14, 16 has a lower carbon concentration. Similarly, the distribution of the second carbon concentration may also be a fixed value or its distribution may also be a change value. If the distribution of the second carbon concentration is a change value, then the sidewalls 42 of the gates 14 and 16 are closer to each other. Portions have a higher carbon concentration, while portions farther from the gates 14, 16 have a lower carbon concentration. After the carbonaceous sidewalls 40 and the sidewalls 42 are completed, the first interpole 14, the second gate 16, the first sidewall 28, and the carbonaceous sidewalls 4 and the sidewalls 42 are used as a mask. A source/drain doping region 44, 46 is formed in the substrate (1) on both sides of the first gate 14 and the second gate 16, respectively. As shown in Fig. 4, the wet side is utilized, for example, by using hot squaring acid to remove the sacrificial sidewalls 42 and a portion of the carbonaceous sidewalls 4, the carbon concentration of the sidewalls of the sidewalls affects the side wall of the hot acid acid side. The rate of the child, therefore, the heat gamma will be different for carbon-containing sidewalls and tanks with different carbon concentrations, and the side walls with higher rhythm are less likely to be removed by the hot sulphuric acid, so after the wet rhyme step Most of the carbon-containing sidewalls 4G will be ordered and form a -L type, while the difficult side wall 42 = is completely removed. Of course, in various embodiments, after adjusting the carbon concentration in the sacrificial sidewalls, it is also possible to remove only a portion of the sacrificial sidewalls of the hot phosphoric acid. 3Fire 201214574 As shown in Figure 5, a metallization process is performed to form a metal telluride layer 50 over the LDD regions 30, 32 and the source/drain doping regions 44, 46. The telluride layer 50 has a source Λ and a pole tweezer 44 on the whistle-pa, and the first gate 14' metal bismuth layer 50 is closer to the source/pole and _6 #near the second gate 16. At this point, the failure of the power crystal has been completed. A stress film can then be formed on the subsequent fabrication of the transistor structure to form a stressed channel in the substrate ι 下方 below the first gate Μ and the second gate 16 . According to another preferred embodiment of the present invention, the present invention provides a transistor structure in which elements having the same Wei are denoted by the same reference numerals, as shown in the fifth column, a first electron cell 54 package 3 substrate 1 〇, a first open pole 14 is disposed on the basement, a first gate "electric layer 18 δ is between the first gate 14 and the substrate 1", and a composite sidewall 58 is located at the first gate 14 On both sides, wherein the outermost surface of the composite sidewall portion has an L-shaped profile, the two source/drain doping regions 6〇, 62 are respectively located in the substrate 10 on both sides of the first gate 14, and a metal deuteration The layer 5 is located on the source/drain doping regions 60, 62. The composite sidewall 58 includes a first sidewall 28 and a carbon-containing sidewall 40, the first sidewall 28 contacting the first gate 14, The carbonaceous sidewall 4〇 contacts the first sidewall 28, and the outer surface of the carbonaceous sidewall 40 is the outermost surface of the composite sidewall 58. Further, the carbon concentration in the carbonaceous sidewall 40 is preferably between ι〇Ε2ΐ Between 10 Ε 22 atm/cm 3 , the carbon-containing sidewall 40 is preferably a carbon-containing tantalum nitride. Further, the source/polarization of the first transistor 54 The inter-cells 60, 62 include an LDD region 30 and a source/drain doping region 44, respectively. The LDD region 30 has a first bottom portion 64 and a first front portion 66, and the source/drain electrodes are doped. The region 44 has a second bottom portion 68 and a first front edge 70. The LDD region 30 is shallower, the source/; and the pole holding region 44 is deeper, in other words, between the first bottom portion 64 and the surface of the substrate 10. The distance is smaller than the distance between the second bottom portion 68 and the surface of the substrate 201214574 10, and the overlapping portion of the LDD region 30 and the source/drain doping region 44 forms an overlap region 72. Further, the first front 66 and the first The distance between the gates 14 is smaller than the distance between the second front 7G and the first gate 14. It is worth noting that the 'metal lithium layer 5 〇 covers the second front 7 〇, in detail the metal lithium The layer 50 covers the overlap region 72 and a portion of the LDD region 30 that does not overlap the source/depolarization swap region 44, and further the metal telluride layer 5 is closer to the first gate 14 than the source/drain doping region 44. The source/drain-changing region in the transistor structure of the present invention may further comprise a stray layer 'as shown in FIG. 5' - the second transistor 56 includes a second gate 16 A second gate dielectric layer 2 is disposed between the second gate 16 and the substrate 1 , on the substrate 10, and a composite sidewall 58 is located at least on both sides of the second gate 16, wherein the composite sidewall The outermost surface of 58 has an L-shaped profile, the two source/drain doped regions wo, 162 are respectively located in the substrate 1〇 on both sides of the second gate 16, and a metal telluride layer 5 is located at the source The composite sidewalls 58 include a first sidewall 28 and a carbon-containing sidewall 40, the first sidewall 28 contacts the second gate 16, and the carbon-containing sidewall 40 contacts A side wall 28, the surface of the carbonaceous sidewall 40 is the outermost surface of the composite sidewall. Further, the carbon concentration in the carbon-containing sidewall 40 is preferably between 1 〇 E21 and 10 E22 atm/cm 3 . The carbon-containing sidewall 40 is preferably carbon-containing lanthanum nitride. Furthermore, the source/drain doping regions 160, 162 of the transistor structure 56 include an LDD region 32 and a source/dot-doped region 46, respectively. The LDD region 32 has a first bottom 164 and a first A front 166, and a source/; and a highly doped region 46 has a second bottom 168 and a second front 170. The LDD region 32 is shallower, the source/dot doped region 46 is deeper, and the overlap between the LDD region 32 and the source/drain doped region 46 forms an overlap region 172. 10 201214574 Furthermore, the distance between the first front 166 and the second gate 16 is smaller than the distance between the second forward 17 〇 and the second gate 16. The metal lithium layer 5 〇 covers the second front 17 〇. The metal telluride layer 50 covers the overlap region 172 and a portion of the LDD region 32 that does not overlap with the source/drain doping region, while the metal telluride layer % is closer to the second gate 16 than the source/drain doping region . In addition, the composite sidewalls 58 may be located only on both sides of the first gate 14 and on both sides of the second gate 16, or may surround the first gate 14 and the second gate 16. • In addition, the method of the present invention can be utilized in various types of transistors, such as buried channel devices, metal-insulator-semiconductor field-effect transistors (misfets), or non-planar transistors, such as bound field effects. A transistor (FinFET) or three pole-effect transistors (Tri-gate). For example, as shown in FIG. 6, a fin field effect transistor 2A has a gate structure 202'-box structure 2〇4, and a source/drain region 260, 262 is located in the gate structure. On both sides of the 202, the source/drain doping regions 26A and 262 respectively comprise an LDD region 230 and a source/drain doping region 244, and a composite sidewall spacer 258 is disposed on the gate structure 202. 258, like the composite sidewall % in FIG. 5, includes a stone-containing sidewall spacer 24 and a first sidewall spacer 228, which are described in the first to fourth figures, and are not described herein again. . Further, a metal germanide layer 250 is further disposed on the source/drain doping regions 26A, 262, and the metal germanide layer 25 is closer to the gate structure 202 than the source/drain doping region 244. In the present invention, the sidewalls partially on the gate are deliberately removed after the source/drain doping region is completed. "Because of the thinning of the sidewalls", the subsequently deposited stress film can cause more stress to the stressed germanium channel. To increase the speed of the transistor. In addition, since the hot acid has different selection ratios for the sidewalls with different carbon concentrations, the carbon dioxide intensity of the sidewalls can be used to control the portion of the sidewall that needs to be removed, and sufficient sidewalls are retained. The width is on the gate. The above is only the preferred embodiment of the present invention, and all changes and modifications made by the application of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 5 are schematic views showing a method of fabricating an electric crystal according to a preferred embodiment of the present invention. Figure 6 is a side elevational view of a fin field effect transistor. [Main component symbol description] 10 substrate 12 shallow trench insulation 14 first gate 16 second gate 18 first gate dielectric layer 20 second gate dielectric layer 22 recess 24 stray layer 26 first sidewall Material layer 28, 228 First sidewall sub- 30, 32, LDD region 34 Second sidewall sub-material layer 230 36 Carbon-containing sidewall sub-material layer 38 Emerged sidewall sub-material layer 40, 240 Carbon-containing sidewall 42 Reinforced sidewall 50, metal Telluride layer 12 201214574 250 52 transistor structure 54 56 second transistor 58 ' 258 44, 46, source/drain doping region 64, 60, 62, 164 first transistor composite sidewall sub-first bottom 160, 162, ® 230, 244, 260, 262 66, 166 first forward 68, 168 70, 170 second forward 72 > 172 200 closed field effect transistor 202 204 braided structure 1000 2000 second transistor area second bottom Overlap region gate structure first transistor region 13