TW201203515A - Thin-BOX metal backgate extremely thin SOI device - Google Patents

Abstract

Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm think are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure further includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings. The present structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, and especially during STI and contact formation.

Description

201203515, invention: [Technical Field] The present invention relates generally to semiconductor devices, and more particularly to CMOS thin buried oxide back-thin silicon-on-insulator (ETSOI) devices To reduce the short channel effect caused by the use of metal back polarity control. [Prior Art] The size of various integrated circuit components is reduced, and transistors (e.g., field effect transistors (FETs)) have undergone significant improvements in power consumption of performance spots. These improvements can be used to reduce the size of the components used in most of them, which is so large that the capacitance resistance _ low 'and increase the output current of the transistor'. However, the performance of the device is reduced in size. Improvement, recently ΐί, will be challenged. ^^Electricity (4)^County^(4) Increased flow denaturation and (MOSFETs) are particularly large-scale semiconductor field effect transistors, and the size of FETS and other devices is reduced == domain, channel region, and gate size are also . The necessity of a shallow source/drain junction with smaller and shorter channel lengths. Desire: The body causes the pole (d〇_) to diffuse laterally into the human channel, and the shallow junction is H = the type of diffusion has a negative impact on leakage current and collapse performance. Factory: :30 nm to 丨00 nm shallow source Pole / " = It is necessary to have acceptable performance. 4 201203515 (siliCon-on-insuiator, S0I) technology allows the formation of high-speed, shallow junction devices. In addition, the insulation layer on the cover device The performance of the parasitic junction capacitance is improved by reducing the parasitic junction capacitance. In the insulating substrate, a buried oxide ' BOX film formed by tantalum oxide is formed on the single crystal stone. And forming a single crystal germanium film thereon. There are various methods for fabricating the overlying germanium on the insulating layer, one of which is separation-by-implanted oxygen (SIMOX), in which oxygen It is an ion implanted in a single crystal germanium substrate to form a buried oxide film. Another method of forming a negative layer on an insulating layer is wafer bonding, in which germanium oxide is present. The second semiconductor substrate of the surface layer is bonded to the surface of the tantalum oxide A buried oxide layer is formed between the two semiconductor substrates. The shallow junction transistor uses a shallow trench isolation (STI) technique to isolate the device and the circuit. The shallow trench isolation technology is greatly increased. Manufacturing cost, because this shallow trench isolation process requires a large number of process steps and equipment 'such as thermal oxidation, chemical vapor disposition (CVD), wet nitride wet etching, reactive ion exchange (reactive ion) Etch, RIE), high-density electrical destruction (hdp) 矽 oxide deposition, wet cleaning, chemical-mechanical polishing (CMP), and photolithography. wafer consistency and yield It is also one of the considerations, because the shallow trench isolation process requires additional processing steps. Miniaturizing CMOS components pushes the negligible parameter numbers to become important factors in circuit design. Important component parameters include short 201203515 channel control And extremeiy thin silicon-on-insulator (ETSOI) 'both are designed for this purpose The new grade of transistor "The ultra-thin insulating layer overlying tantalum is a completely depleted charge carrier transistor element (ie, at 3 〇〇K, the charge carrier concentration in the channel is on the order of 1 〇 3 atoms / cubic centimeter) Or lower), which uses an ultra-thin stone channel, where most of the carriers are fully depleted 'FD' in operation. The challenge for this class of transistors is their Vt variation and high external resistance (Rext). The FDSOI transistor threshold voltage vt is a function of the first order of magnitude of the channel dopant and changes accordingly, which also varies with the thickness of the atomic channel, rather than a conventional PDS device. Magnitude. This is due to a compensation factor in a partially depleted (pD) field effect transistor that captures the change in the depth of the doped depletion and does not exist in a fully depleted element. Therefore, Vt changes more drastically as the doping changes, such as a random doping fluctuation. In addition, there is another brand new factor (ie, variation in body thickness) that needs to be tested1. Since the 矽 element on the extremely thin insulating layer is completely depleted, the thickness of the body changes, which leads to the change of the charge contained in the financial position. According to the Gauss's law, the change of the channel electromotive force changes the criticality. Voltage. 5 noon want to improve the short-channel effect (SCE), the order of the crystal structure, including the bungee bias bias to reduce the heart - post low g, mBL) and sub-threshold swing (sub thresh 〇id s:ng). As the transistor becomes smaller, the short channel effect becomes a major factor. Therefore, as the ultra-thin insulating layer is covered with 矽 (5) tra thm si丨ic〇n 〇n 201203515 insulator ' UTSOI), the ultra-thin insulating layer is covered with a back gate and a double gate, and a very thin stone channel is applied. It is completely depleted during operation. The main carrier' provides excellent control of the short channel effect. The back gate component is expected to provide a solution for random doping fluctuations because Vt can be set by the back gate electromotive force, reducing the dependence on channel doping. As the size of the transistor is further reduced, the short channel effect reduces the ability to shorten the gate length of conventional MOSFETs (complementary MOSFETs). Single Gate Fully Depleted Insulator Semiconductor (Single Gate Fully Depleted

Semiconductor-on-insulator (Single Gate FDSOI) technology has been proven to be one of the solutions to reduce short-channel effects and reduce non-ideal parasitic capacitance. However, this single-gate FDSOI technique may require strict thickness requirements and uniform control of the Shishi film on the insulating layer to achieve complete depletion. In addition, the above-described drain induced virtual substrate biasing (DIVSB) effect is another challenge for single-gate FDSOI technology. In contrast, the dual-gate FDSOI technique may have less stringent requirements on the thickness of a semiconductor on the insulating layer, which may reduce the bias induced virtual substrate bias effect and may maintain better short channel effect control and high transduction ( Trans-conductance). By way of illustration and reference to FIG. 1, there is a prior art ultra-thin insulating layer overlying germanium comprising a buried oxide layer 110 over a substrate 100, including a very thin insulating layer over the buried oxide layer. The layer is covered with a layer of germanium 20' and includes a gate stack over the layer of germanium on the very thin insulating layer. The gate stack includes a dielectric constant oxide layer 丨y over the overlying insulating layer on the very thin insulating layer, followed by a high dielectric constant metal gate 201203515 layer 132, which is covered by high dielectric constant oxidation. Above the object layer. The core, 'genus region 133 is located above the high dielectric constant metal gate layer. Each /f ^ d 130 (raised source/drain regions » RSD ) is placed over the overlying layer of the very thin insulating layer and contacts the spacer. (4) Ϊ—第—in the face-to-center, the present invention describes a novel warrior gate tungsten and oceanic source/drain region (RSD) 13〇 placed on the ultra-thin insulating layer over the 矽 layer The spacer 15 is in contact with each other. The (4) component on the very thin insulating layer of S has a thick buried oxide (BOX) 105'. It has been experimentally shown that the short channel effect (SCE) can only be improved by about 20 to 40%. As the HKMG gate stack size is further reduced, better short channel effect control is required. The thickness of the overlying germanium layer 105 on the very thin insulating layer is between 6 nm and 2 nm. Due to the ultra-thin insulating layer overlying the germanium layer 1〇5, the experience of active source drain and extended regions has made it difficult to implant and activate the annealing. Although implantation is still possible, only a portion of the dopant is activated due to the lack of re-crystallization. The sheet resistance from the two active regions is greatly k幵', which is seriously deteriorated due to its electrostatic properties. The use of a floating source/drain region (RSD) 130 can be used to partially improve this problem, but the expansion resistor is a major factor in performance degradation. The in-situ doped floating layer source/drain is another technique for overlying the germanium element on the very thin insulating layer, and a rapid thermal annealing (RTA) temperature system is integrated therein to reduce the resistance and The dopant is driven under the HKMG stack. Since halogen implants are not suitable for good Vt control, high Vt and punch-through are caused. 201203515 According to the above considerations, it is necessary to have and have separate 呰, two: on the edge layer "pieces" 丄 = = = 2::::: 得, (10) one [invention] In the first aspect, the present invention It is disclosed that a novel allowable touch can be used to select the present invention - an embodiment disclosed - an extremely thin insulating layer, a thin layer of insulating material, which comprises a thin oxide and a disordered insulator. This embodiment describes that a very thin insulating layer overlying a 70-layer of a semiconductor layer on a film or a gate electrode, including a compound and an oxynitride insulator, is considered to have a high temperature. In the case of 600: (and oxygen may form oxidization!!, the use of the system has a special correlation. The basic structure of the present invention includes and protects the tungsten film while avoiding the formation of the above tungsten oxide. An embodiment of the present invention provides a very thin insulating layer overlying a stone-like "electrical" hanging metal inter-electrode (MGHK) completely depleted insulating layer overlying germanium element (FDSOI), wherein the tungsten back gate is a low resistance Thin film nitride coated to avoid fabrication The formation of a metal oxide. The ultra-thin buried oxide on the ultra-thin insulating layer provides a semiconductor structure with excellent short-channel control and greatly improves the buckling-induced bias reduction (dram induced bias 丨owering, D1BL). And a sub-threshold swing. The semiconductor structure includes an off-nFET and a PFET having a back gate metal 201203515, which is biased by a '' and can be independently biased. Shallow trench isolation structure (STI) In another aspect, an embodiment of the present invention provides a method for forming a thin buried oxide metal back gate very thin insulating layer overlying germanium element, comprising: providing a thin insulating layer The substrate is covered, and the thickness of the layer on the layer is between 6 and 8 nm, preferably in the range of 10 nm, and the thin layer of nitride is preferably between 5 and 10. Between the nanometers, followed by a layer of heavier between 1 〇 and nanometers' followed by a thin layer of nitrides deposited in a thick burial oxide at a thickness of 5 i 1 () nanometers. Preferably, it is composed of cerium oxide There is a deep production of 13 〇 nanometers to 2 〇〇 nanometers on the ruthenium substrate. A shallow trench isolation structure (sti) provides an isolation barrier between the pFET and the nFET element. Reactive ion remnant ( Reactive i〇n etching, R positive) is used to open the trench to the buried oxide layer and isolate it with the bulk material. This is then filled with oxide. The PFET of the very thin insulating layer is The pedestal is made by the source and the pole (RSD) of the floating layer in the active area. The reactive ions resemble the opening of the trench to contact the back gate metal. Then a _ wall is formed. ) to provide isolation between the source of the floating layer and the drain and back gate metal. 2 The vaporized metal fills up as a back-closed junction. In another aspect, an embodiment of the present invention provides an extremely thin insulating layer overlying stone (ETSOI) device including a -first buried oxide (germanium) layer over the wire plate and - The metal layer is surrounded by the top and bottom thin nitride layers; a thin second β〇χ is located on the thin layer of the mouse layer and the thin insulating layer is overlaid on the thin layer. Above the BOX, wherein the second layer, the upper thin nitride layer, 10 201203515, and the thin insulating layer overlying the germanium layer are in contact with a spacer; and a field effect transistor having a gate The stack is disposed on the thin insulating layer over the germanium layer, the gate stack includes a footprint of the dielectric stack on the gate stack, the dielectric layer having the thin insulating layer overlying the germanium layer as a pass The other objects, features, and advantages of the present invention will become more apparent from the following detailed description. It should be noted that the detailed description The preferred embodiments of the present invention are for illustrative purposes only. The various changes of the present invention can be naturally achieved without departing from the scope of the present invention. [Embodiment] The following detailed description of the present invention will be made in the following discussion of the present invention. The drawings are to be regarded as illustrative only, and are not intended to However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other respects, conventional structures or process steps are not described in detail to avoid obscuring the invention. It can be understood that when a component such as a layer, region or substrate is "on" or "above" another element, it can be a direct bit, a component above or other intervening component. Existence. When the component is referred to as "directly on another component" or "directly on top of another component", there is no intervening element. It is also understood that at the same time, 201203515, when the element is referred to as "connected to" or "faced to" another 70 pieces, it may be directly connected or coupled to another element, or there may be intermediate elements present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there is no intermediate element. Figures 2 through 9 depict steps in various processes in accordance with an embodiment of the present invention, not semiconductor Structure, these steps are preferably used to form a semiconductor component having a thin buried oxide metal back gate very thin insulating layer overlying germanium element. The following describes an extremely thin insulator overlying germanium component having a very thin insulating The layer is coated with a selective epitaxial length and has a metal back gate (BG), preferably consisting of tungsten because tungsten is characterized by low resistance, wherein the back gate is protected by an extremely thin, far-dyed layer. In this embodiment of the invention, other embodiments reduce the short channel effect (SCE) by applying a voltage to the metal back gate to regulate the front gate threshold voltage vt'. Threshold voltage

The control of the change in Vt is thus provided by the thickness of the overlying thin layer of the insulating layer and the dopant. Figure 2 depicts an initial structure that can be used in an embodiment of the invention. The initial structure may include a very thin insulating layer overlying 矽(s〇I) layer 1〇〇, hereinafter referred to as an ultra-thin insulating layer overlying germanium channel or ETS〇I, which is located in a very thin n buried oxide (BOX) ) Above layer 1〇1. Under the buried oxide 1〇1, a very thin tantalum nitride 1〇2 is used to protect a metal back gate (BG) 103 from delaminate. With a second very thin buried dielectric, a tantalum nitride 104 is deposited to coat the metal back gate 3 and is isolated from a thick buried oxide (BOX) 1〇5, the thickness of which is preferably between丨 4 〇 nanometer to the order of 200 nanometers. Finally, a substrate 丨〇6 was added to process the substrate as 201203515. The material of the Z tif board (10) can be composed of any semiconductor material, including but not limited to, broken, wrong, dreamy, 1 carbon, carbon supplement, stellite gallium, gallium nitride, indium sulphide, indium phosphide A group or a group of compound semiconductors. The semiconductor substrate 1 6 may also include an organic semiconductor or a layered semiconductor such as tantalum/mash. The thickness of the channel is about 3 nm to nanometer and k is above the phase 1 oxide 1, preferably between 8 nm and nanometer. A metal back gate f (BG) layer 104 having a thickness of preferably between 1 G nm and 2 G nm is coated on a thin layer of thin silicon nitride layer 1 〇 2 and a thin layer of thin silicon nitride layer 104 The thickness of each layer is preferably between 5 nm and 10 nm, and the back gate layer is not layered. Referring to FIG. 3, the initial structure includes a first recess formed in the ETSOI channel 1〇〇 and recessed to the thick buried oxide i〇s and the isolated substrate of the Xixi vaporization 108, the isolated metal back gate 1 〇4 and ets〇i channel layer 100. The oxide 107 i is recessed to form a shallow trench isolation structure (STI). Still referring to FIG. 3, the two-layer ultra-thin tantalum nitride layers 102 and 1 4 having a thickness of 7 nm or less are preferably used. Each set is set on the metal back gate (BG) 1〇4

Above and below. In the present invention-embodiment, a thin insulator tantalum nitride substrate 108 isolates the back gate 1〇4 from the shallow trench insulator (STI) oxide fill 丨07, where ST] acts as a subsequent pFET and An isolation barrier between nFET components (not shown). 201203515 Referring to Figure 4, there is shown a side cross-sectional view of a metal oxide complementary semiconductor field effect transistor (MOSFET) semiconductor device. The initial element is provided with a gate stack including a high dielectric f-number oxide layer 131 over the upper surface of the recessed ETSOI channel, and then a further over the high dielectric constant oxide layer咼 Dielectric constant metal gate (MGHK). This preferred metal region consisting of tungsten 133 (because of the low resistance of tungsten) is located above the MGHK layer. The gate dielectric of the gate stack may comprise an oxide, a nitride, an oxynitride, or a multilayer stack as described above. The dielectric dielectric materials include, but are not limited to, oxidized (Hf 〇 2), zirconia (Zr 〇 2), lanthanum oxide (La 2 〇 3), alumina (Al 2 〇 3), titanium oxide (Ti 〇 2), barium titanate (srTi〇3), barium aluminate (LaA1〇3), barium oxide (Υ2〇3), barium oxynitride (Hf^)xNy), strontium oxynitride (Zr〇xNy), oxynitridation镧(La2OxNy), gas oxidation (eight 〇12〇), titanium oxynitride (Ti〇), TiO3锶, LaA1〇xNy, Y2〇xNy Any of the above-mentioned salts, and any of the above alloys. The complementary MOS field effect transistor (MOSFET) further includes a source region and a drain region (not shown) located within the ETS 〇I channel at a location occupied by the gate stack. This gate stack can be formed by depositing a plurality of material layers, photolithography, and etching. Alternatively, an alternate gate process can be utilized to form the gate stack. The channel region located in the ETSOI layer is directly below the gate stack and between the source and drain regions of the MOSFET. ^ > The spacer tether is then attached to the sidewall of the gate stack. In an active source-drain (SD) region, a floating source and drain (RSD) 丨 30 is applied and contacts the spacer. 14, 201203515 ^ Figure 5 is a schematic diagram depicting the formation of a back gate layer (BG). Preferably, a trench is etched by reactive ion etching (RIE) and stopped on the back gate layer 104. A thick spacer 110' of about 1 〇 to 15 nm thick is then formed to isolate the ETS0I field effect transistor component and the active floating source source-drain region 130. A reactive ion etching process is then continued to tunnel a trench down to the buried oxide layer with germanium nitride as a spacer layer. This trench is then filled with an oxide deposit. The ultra-thin insulating layer-on-chip (ETS〇I) elements are preferably fabricated in this manner and include a floating source drain (RSD) 130 〇' in the source/drain active region. It is a schematic diagram depicting the filling of a metal-filled 12 从 from the back gate trenches. The other is equivalent to the metal, and is formed by evaporation. Figure 7 is a side view of the ETS0I component, depicting the floating source and floating layer drain (RSD) 130 of the ί 月 gate (BG) in the source _ immersed region, and is extremely thin The layer is tilted to avoid stratification. The contact trench is then opened with a reactive ion to pick up the t-metal. The contact trench is preferably filled with a vapor-deposited metal as a back gate contact. ET: This: After Γ, you can use the known process to form including this

兀 = the remainder of the integrated circuit. The thin spacers allow ETS0I σ between “electrical dielectric and metal gate stacking and epitaxial floating 1=/汲. The constructed structure provides _ ETS0 high dielectric constant gold by two pMG called full-empty S01 S parts, in which the metal back interrogation system, argon low resistance is coated to prevent metal emulsification and ETSO during the manufacturing process. The thin buried oxide provides the new channel control of the semiconductor structure excellent 201203515 1 , which greatly improves the buckling induced bias reduction and the sub-threshold swing. A semiconductor structure in accordance with an embodiment of the present invention includes nFET and pFET back gate elements and can be independently biased. Figure 8 shows the use of very thin tantalum nitrides 1〇2 and 1〇4 to isolate the back gate metal tungsten 103 from oxidation, wherein the metal tungsten layer 1〇3 is de-layered due to the volume expansion of the tungsten oxide. . Here, a nuclear reactive analysis (NRA) was used to confirm the nitrogen concentration of the two different films deposited on tungsten. No nitrogen concentration was observed for both cerium oxide and cerium on the tungsten surface. Very thin tantalum nitride 9A provides 0el5 [N] as sufficient protection and no oxidation. Figure 9 depicts an Auger analysis to confirm the presence of a very thin tantalum nitride film to protect the metal tungsten back gate. A sample is constructed of a tantalum nitride film 9A over a tungsten layer on the surface of a germanium dioxide. A metallic cobalt coating was deposited over the surface of the nitride to perform thickness analysis. This Auger analysis showed a significant nitrogen peak between the metallic cobalt coating and the tungsten surface and no oxygen was detected. In contrast, the junction between the town and the dioxin is not lateral to the nitrogen, and the thinner diarrhea is specifically ignored here. The results of this analysis concluded that the deposition of very thin tantalum nitride 9A over the surface of the surface completely prevented oxidation and no oxidation. All in all, the structure constructed by this method minimizes the short channel effect. Therefore, it is very important that the thickness of the overlying channel on the insulating layer is extremely thin. When the thickness of the overlying germanium layer is combined with the back gate layer, the combination of the two effectively controls the short channel effect and the dopant therein. In addition, ETSO] high dielectric constant metal back gates are completely vacant components, and the combination of buried oxides' provides not only excellent short-channel control, but also significantly reduces the buckling-induced bias and sub-threshold swing β at 201203515. The present invention may be embodied in other specific forms without departing from the spirit and scope of the invention. The aspects of the specific embodiments are to be considered as illustrative and not restrictive. Therefore, the scope of the present invention is shown as the scope of the accompanying application patent and is not as shown in the foregoing description. All changes that fall within the meaning and scope of the patent application are deemed to fall within the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS In order to immediately understand the advantages of the present invention, reference is made to the specific embodiments illustrated in the accompanying drawings, The invention will be described with additional clarity and detail with reference to the accompanying drawings in which: FIG. 1 is a prior art ultra-thin insulating layer overlying crucible (ETSOI). A side cross-sectional view of an electric raft; 2, according to the present invention - a side view of a substrate covered with an insulating layer; a pole/seeking 3 is a - the first process step and a corresponding slot isolation structure (STI ; 眞 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = The step of metal filling to contact the back gate; Figure 7 is a side cross-section of the final structure 17 201203515 in accordance with the present invention, illustrating the contact of the element with the associated via hole; Figure 8 is a nuclear reaction Analysis result graph, this analysis system The addition to the very thin nitride layer and the back gate tungsten layer interface; and Figure 9 is an Auger profile of the structure of the present invention and the analysis of the tungsten and cobalt overlayer interface shows no oxidation. [Main component symbol description] 100 substrate 101 buried oxide layer 102 extremely thin silicon nitride 103 metal back gate 104 second very thin buried dielectric 105 buried oxide 106 dream substrate 108 thin insulator tantalum nitride substrate 110 Buried oxide layer 120 very thin insulating layer overlying germanium layer 130 floating layer source/drain region (rSd) 131 oxide layer 132 two dielectric constant metal gate 133 metal region 150 spacer

Claims (1)

201203515 VII. Patent application scope: L-type semiconductor device comprises: a first buried oxide (BOX) layer is located on a stone substrate and a back gate metal layer is thinned above and below the top of the BOX Surrounded by a nitride layer; a first BOX is located on the upper thin nitride layer, and a thin insulating layer overlying silicon layer (silic〇n-〇n-insulation 'SOI) is stacked on the thin second BOX Upper, wherein the second BOX layer, the upper thin nitride layer, and the thin insulating layer are in contact with a spacer; and a field effect transistor (FET) having a gate stack is disposed on the thin insulating layer over the germanium layer, the gate stack includes a dielectric layer on a footprint of the gate stack, the dielectric layer having the thin insulating layer The cover layer acts as a recessed channd of the field effect transistor. The semiconductor device of claim 1, wherein the gate stack further comprises a germanium dielectric constant oxide layer disposed on the upper surface of the ultra-thin insulating layer over the germanium layer, a high dielectric layer A high-k metal gate (MGHK) is placed over the germanium dielectric constant oxide layer, and a metal region is over the MGHK layer. 3. The semiconductor device according to claim 2, wherein the high dielectric constant oxide layer is composed of a material including an oxide, a nitride, an oxynitride, or The above-described composition is a multilayer stack, or wherein the metal region is composed of tungsten. 4. The semiconductor device of claim 5, further comprising at least -19 201203515 spacers applied to the vertical sidewalls of the gate stack; and further comprising on the ultra-thin insulating layer a floating source and drain (RSD) extending from the sidewall spacer sidewall of the gate stack to isolate the upper thin nitride layer, the thin second buried oxide layer and the thin a spacer layer overlying the insulating layer; and wherein the isolation spacer provides isolation between the source of the floating layer and the drain and the back gate metal. 5. The semiconductor device according to claim 1 a voltage system is known to be applied to the old gate layer to reduce the short channel effect (this (10) Channei, SCE) or a control in which the threshold voltage (eg, V〇itage, vt) changes from the thin insulating layer 6. The semiconductor device of claim 1, wherein the contact trench is filled with the evaporation metal of the back gate layer. The semiconductor device described in the first item of the patent scope Has a high number of dielectric (four), which includes oxygen ^ (Zr02), yttrium oxide (La2 〇 3), alumina (Al2 〇 3), titanium oxide (Ti 〇 2), titanic acid (, rTi03), sau 〇(LaAl〇3), oxidized (γ2〇3), nitrous oxide (Hf〇xNy), , yttrium (Zr〇xNy), lanthanum oxynitride (La2〇xNy), aluminum oxynitride (Al2〇xNy) ), titanium oxynitride (TiOxNy), titanium oxynitride (SrTi〇), aluminum arsenide lanthanum (LaA10xNy), nitrous oxide (Y2〇xNy), any of the above-mentioned oxalates, and any of the above alloys 8. The semiconductor device of claim 5, further comprising at least one pair of nFETs and pFETs including a covered back gate layer, and a shallow trench 20 201203515 trench isolation structure (shallow 9. The semiconductor device of claim 1, wherein the thickness of the overlying layer of the ultra-thin insulating layer overlying a buried oxide layer is between 6 Between nanometer and 8 nm, the buried oxide layer is covered by surrounding isolation spacers. 10. A method for forming a semiconductor device, comprising: a) Providing a lithium substrate having a first buried oxide (BOX) layer and a back gate metal layer surrounded by one of the top of the buried oxide layer and a lower thin nitride; b) thin nitrogen on the upper Forming a thin second buried oxide layer thereon and forming a thin insulating layer overlying germanium layer thereon, wherein the second buried oxide layer, the upper thin nitride layer, and the thin insulating layer The slab layer contacts a spacer; and uc) forms a field effect having a gate stack over the thin layer of the thin insulating layer, the gate stack including a dielectric layer at the footprint of the gate stack The electrical layer 'the dielectric layer has a recessed channel on the edge layer as a recessed channel of the field effect transistor. 11. The method of claim 1, wherein the method further comprises forming a floating layer source and a floating layer on the thin thin insulating layer, which is from the sidewall stack of the idle electrode stack. The wall extends to isolate the spacer layer from the upper thin nitride layer, the thin second buried oxide layer, and the thin insulating layer. 12. The method of claim 2, wherein the step of forming a 5 Hz field effect transistor over the thin layer of the insulating layer 201203515 comprises forming a gate stack having a high dielectric constant An oxide layer is disposed on the ultra-thin insulating layer over the germanium layer, followed by forming a high dielectric constant metal gate (MGHK) over the high dielectric constant oxide layer, and a metal region is located in the high dielectric layer Above the electrical constant metal gate layer, and forming a shallow trench isolation structure (STI) to provide an isolation barrier between one of the PFET and NFET devices constructed over the germanium layer overlying the thin insulating layer. I3. The method of claim 1, wherein the reactive ion is engraved to open the trench downward to the buried oxide layer and the nitride layer used as the isolation layer. Filled with yttrium oxide or more to form a pair of very thin = edge layer overlying 7PFET xiao nFETs with - floating layer and floating layer immersion (RSD) are each located in a source and drain active region. The method of claim 10, further comprising performing a reverse bank = sub-side process to form a contact trench to contact the back gate metal, and then Ί _ as the source of the floating layer is extremely (4) The compartment between the pole metals. X and filling the contact groove with a metal evaporating from the gate metal contact: the method described in the item, wherein the thin insulating layer has a thickness of nanometer 1 to 2 nm And forming a thickness of ι〇度: 5 to 2: ^ and forming the extremely thin nitride layer, which is thicker than 10 to 20 is too Μ 2 to form the back gate metal layer and the thickness of the dielectric oxide Then, the thickness of the thick buried portion formed by the dioxotomy and the thickness of the substrate having a thickness of 5 to (1) nanometers is on the order of 45 atomic weight. twenty two