201203478 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體封裝件及其製造方法， 且特別是有關於一種具有内埋式線路的半導體封裝件及 其製造方法。 < 【先前技術】 傳統的半導體封裝件包括基板、晶片、介電保護層 及，案化導電層。其中，晶片設於基板上，介電保護層曰 覆蓋晶片，圖案化導電層形成於介電保護層上。一般而 言，塗佈-層導電材料於介電保護層上後，應用敍^ (etching)技術圖案化導電材料以形成圖案化導電層。 更進一步提升。 然而’圖案化導電層與介電賴層之，接觸面積 有限’使圖案化導電層與介電保護層之間的結合度無法 【發明内容】 本發明係有關於一種半導體封裝件及其製造方法， 半導體封裝件之圖案化線路層係⑽式線路，X或’201203478 VI. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having a buried wiring and a method of fabricating the same. <Prior Art A conventional semiconductor package includes a substrate, a wafer, a dielectric protective layer, and a patterned conductive layer. Wherein, the wafer is disposed on the substrate, the dielectric protective layer 覆盖 covers the wafer, and the patterned conductive layer is formed on the dielectric protective layer. Generally, after the coating-layer conductive material is applied over the dielectric protective layer, the conductive material is patterned using an etching technique to form a patterned conductive layer. Further improvement. However, the combination of the patterned conductive layer and the dielectric layer has a limited contact area, so that the degree of bonding between the patterned conductive layer and the dielectric protective layer cannot be achieved. SUMMARY OF THE INVENTION The present invention relates to a semiconductor package and a method of fabricating the same , patterned circuit layer of semiconductor package (10) type line, X or '
圖案化線路（trace)層。基板具有一 ic layer)及 一第一基板表 201203478 1 ' 里 VVUU7‘|V\ :此=元件設於第一基板表面並具有-主動表面。 覆蓋主動:1=動表面上。第一雷射活化介電材料 ::主動表面並具有一第一圖案化溝 槽並露出該此導雷如墙„^ 岽μ姚案化線路層埋設於第-圖 案化溝槽内並電性連接於該些導電柱。 =本：明之另一方面’提出一種半導體封裝件之 :有：Γ ^方法包括以下步驟。提供-基板，基板 板表面，·設置數個半導體元件於基板之第 一板表面上，每個半導體元件包括數個導電柱並且有 一主動表面’該些導電柱形成於主動表面上；形成1第 活化介電㈣覆蓋每個半導體元件之主動表面，· 二：：第：雷射活化介電材料上形成—第一圖案化溝 槽以形成一第一圖案化雷射活化 露出該此導雷飪.相士略 口系化溝槽並 m 第一圖案化線路層於第一圖案 ’ θ内’第m線路層並電性連接於該些導電 *體:：板及第-雷射活化介電材料’以形成數個半 為二本發明：上述内容能更明顯易懂，下文特舉較 佳只靶例，並配合所附圖式，作詳細說明如下： 【實施方式】 第一實施例 導體^1圖’其繪示依照本發明較佳實施例之半 ==裝件的剖視圖。半導體封料刚包括基板102、 導體凡件104、線路結構174、介電保護層136、數個 201203478 t -·· 電柱（conductive pi 1 lar) 112 及數個銲球 122。其 中，線路結構174包括第一雷射活化介電材料 (laser-activated dielectric material)154、第一圖 案化雷射活化層106及第一圖案化線路（什狀幻層1〇8。 其中’第一雷射活化介電材料154係為可使用雷射光照 射來進行移除動作以形成一溝槽且同時進行活化動作以 在该溝槽之表面形成一具導電性的雷射活化層。 基板102係金屬板，其厚度約為5〇〇微米（μπ])，然 其並非用以限制本發明，基板1〇2之厚度亦可為其它數 值範圍。 基板102的材質例如是銅（Cu)或其它金屬。金屬 製成的基板102其強度甚佳，可增加半導體封裝件1〇〇 的整體結構強度。並且，基板1〇2中大部分的外表面裸 路出來，加上金屬製成的基板1 〇2其散熱性佳，因此可 快速散逸半導體封裝件1 〇 〇内部的產熱。 雖然本實施例中基板1〇2的材質係以金屬為例作說 明，然此非用以限制本發明。於其它實施態樣中，基板 102的材質亦可為pp(p〇iypropylene)基板或陶瓷基板。 較佳但非限定地，基板102的熱膨脹係數 (Coefficient of Thermal Expansion, CTE)與第一雷 射活化介電材料154的熱膨脹係數大致上相同。例如， 基板102及第一雷射活化介電材料154的熱膨脹係數皆 介於17(10 6/°C)至23之間。由於基板1〇2及第—雷射 活化介電材料154的熱膨脹係相近，使半導體封農件1 〇〇 因受熱所發生的翹曲量較小。 201203478 » ί * τ» W^A.» Λ\ 半導體元件104例如是晶片，較佳但非限定地，半 導體元件1G4係薄型晶片，其厚度約為5一。半導體元 件1〇4的數量為單個，其位置大致上位於基板1〇2的中 間位置，可使半導體封裝件1〇〇在製作過程中所發生的 輕曲量較均勻且較小。 半導體元件104具有側面118及相對之背面12〇與 主動表面114’導電柱112形成於主動表面114上。半導 體元件104之背面120透過黏著層116固設於基板1〇2 之第一基板表面110上。 第雷射/舌化介電材料154覆蓋半導體元件104之 2動表面114、側面118及基板1〇2之第一基板表面11〇。 Γ雷射活化介電材料154並具有第一圖案化溝槽m， 其露出導電柱112。第-圖案化溝槽124之槽側壁132形 成有第—圖案化雷射活化層106。 第-圖案化線路層108之至少一部分形成於第一圖 雷槽124 Θ。在本實施例中’第一圖案化線路層⑽ /連接於導電柱112,且全部之第-圖案化線路層1()8 里5又於第—圖案化溝槽124内。進—步地說，第一圖案 層108接觸到第一圖案化溝槽124中全部的槽側 ^ ，可增加第一圖案化線路層108與第一圖荦化雷射 ^之間的接觸面積，以提升結合強度^ ^^其它實施態樣中’第一圖案化線路層1〇8之一部 於圖案化溝槽124内’而其之另一部分可突 出於第—圖案化溝槽124。 此外，第一圖案化線路層108的材質與導電柱112 201203478 的材質係相同。例如’第一圖案化線路層1〇8的材質為 銅’而導電柱112係銅柱，相同材質之第__圖案化線路 層108與導電柱1丨2間的結合度係較佳。 第一圖案化溝槽丨24於第一雷射活化介電材料154 之上表面126露出開口 128，第一圖案化線路層1〇8之上 表面130與第一雷射活化介電材料154之上表面126大 ，上齊平，然此非用以限制本發明。於其它實施態樣中， 第-圖案化線路層1〇8之上表面13〇可低於或高於第一 雷射活化介電材料154之上表面126。 如第1圖所示，第一圖案化線路層1〇8可往半導體 封裝件10+0的外侧面的方向延伸，使得至少部分之銲球 122可沿著第—圖案化線路層⑽的延伸方向移至半導體 元件104與半導體封裝们〇〇之外侧面之間的位置，而 使半導體封裝件1〇〇成為扇出型（Fan_〇ut)半導體封裝 結構。 、 介電保護層136具有數個開孔138，該些銲球122 對應地形成於該㈣孔138並電性連接於第—圖案化線 路層108。較佳但非限定地’半導體封料⑽更包括表 面處理層140 ’其形成於第—®案化線路層108上，鮮球 122形成於表面處理層刚上。其中，表面處理層14〇的 材質利如是鎳（Ni)，（Pa)與金（Au)中至少一者， 其可應用例如是電鍍技術形成。表面處理層14〇除了可 保護第-圖案化線路層⑽外，亦可提昇銲球與第 圖案化線路層10 8間的結合性。 此外基板1〇2的外侧壁148、第一雷射活化介電 201203478 • 1 ννυυ^^Γ/Λ 材料154的外側壁150及介電保護層136的外側壁152 大致上切齊，即，外側壁148、外側壁150及外側壁152 大致上係共平面。 雖然本實施例之半導體封裝件100的第一圖案化線 路層108的層數係以單層為例作說明，然於其它實施態 樣中，請參照第2圖，其繪示依照本發明一實施例之半 導體封裝件的剖視圖。第2圖中半導體封裝件2〇〇之線 路結構274包括數層圖案化線路層。詳細地說，相較於 魯第1圖之半導體封裝件1〇〇,半導體封裝件200包括數層 雷射活化介電材料及數層圖案化線路層，其中相鄰的圖 案化線路層係彼此電性連接其中—層雷射活化介電材 料係設於相鄰之圖案化線路層之間。以下係以其中一第 二雷射活化介電材料258及其中—第二圖案化線路層⑽ 為例說明。Pattern the trace layer. The substrate has an ic layer and a first substrate table 201203478 1 'VVUU7'|V\: This = component is disposed on the surface of the first substrate and has an active surface. Cover active: 1 = on the moving surface. a first laser-activated dielectric material: an active surface and having a first patterned trench and exposing the lead-lead layer such as a wall „μ 姚μ姚化化线路层 embedded in the first-patterned trench and electrically Connected to the conductive pillars. = Ben: On the other hand, a semiconductor package is proposed: there is: Γ ^ method includes the following steps: providing - substrate, substrate board surface, · setting a plurality of semiconductor components on the substrate first On the surface of the board, each of the semiconductor elements includes a plurality of conductive pillars and has an active surface formed on the active surface; forming a first active dielectric (4) covering the active surface of each of the semiconductor elements, · 2:: Forming a first patterned trench on the laser-activated dielectric material to form a first patterned laser to expose the conductive tracer; the phase-triggered trench and the first patterned circuit layer a pattern 'θ in the 'mth circuit layer and electrically connected to the conductive body:: plate and the first-laser-activated dielectric material' to form a plurality of half of the invention: the above content can be more clearly understood , the following is a better target only, and DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention is a cross-sectional view of a half == assembly according to a preferred embodiment of the present invention. The semiconductor package just includes the substrate 102. a conductor member 104, a wiring structure 174, a dielectric protective layer 136, a plurality of 201203478 t -··electric pillars 112 and a plurality of solder balls 122. The wiring structure 174 includes a first laser activation medium. a laser-activated dielectric material 154, a first patterned laser activating layer 106, and a first patterned line (a sinusoidal layer 〇8. wherein 'the first laser-activated dielectric material 154 is usable The laser light is irradiated to perform a removal operation to form a trench and simultaneously perform an activation operation to form a conductive laser activating layer on the surface of the trench. The substrate 102 is a metal plate having a thickness of about 5 μm. (μπ]), but it is not intended to limit the present invention, and the thickness of the substrate 1〇2 may be other numerical ranges. The material of the substrate 102 is, for example, copper (Cu) or other metal. The substrate 102 made of metal is very strong. Good, can increase semiconductor The overall structural strength of the package is 1 并且. Moreover, most of the outer surface of the substrate 1 裸 2 is bare, and the substrate 1 〇 2 made of metal has good heat dissipation, so that the semiconductor package 1 can be quickly dissipated. Although the material of the substrate 1〇2 in the present embodiment is exemplified by a metal, it is not intended to limit the present invention. In other embodiments, the material of the substrate 102 may also be pp ( Preferably, but not limited to, the coefficient of thermal expansion (CTE) of the substrate 102 is substantially the same as the coefficient of thermal expansion of the first laser-activated dielectric material 154. For example, the substrate 102 and the first laser-activated dielectric material 154 each have a coefficient of thermal expansion between 17 (10 6 / ° C) and 23. Since the thermal expansion coefficients of the substrate 1〇2 and the first-laser-activated dielectric material 154 are similar, the amount of warpage of the semiconductor sealing member 1 due to heat is small. 201203478 » ί * τ» W^A.» Λ\ The semiconductor component 104 is, for example, a wafer. Preferably, but not limited to, the semiconductor component 1G4 is a thin wafer having a thickness of about 5 Å. The number of semiconductor elements 1 〇 4 is a single, and its position is substantially at the intermediate position of the substrate 1 〇 2, so that the amount of light curvature which occurs in the manufacturing process of the semiconductor package 1 较 is relatively uniform and small. The semiconductor component 104 has a side surface 118 and an opposite back surface 12A and an active surface 114' conductive pillar 112 formed on the active surface 114. The back surface 120 of the semiconductor device 104 is fixed to the first substrate surface 110 of the substrate 1A through the adhesive layer 116. The first laser/tongue dielectric material 154 covers the movable surface 114 of the semiconductor device 104, the side surface 118, and the first substrate surface 11A of the substrate 1〇2. The Γ laser activates the dielectric material 154 and has a first patterned trench m that exposes the conductive pillars 112. The trench sidewalls 132 of the first patterned trench 124 are formed with a first patterned laser active layer 106. At least a portion of the first patterned circuit layer 108 is formed in the first torpographic channel 124. In the present embodiment, the first patterned wiring layer (10) is connected to the conductive pillars 112, and all of the first-patterned wiring layers 1 (8) are in the first patterned trenches 124. In other words, the first pattern layer 108 contacts all of the groove sides of the first patterned trench 124, and the contact area between the first patterned circuit layer 108 and the first patterned germanium can be increased. In order to improve the bonding strength, in another embodiment, 'one of the first patterned circuit layers 1 〇 8 is in the patterned trench 124 ' and another portion thereof may protrude from the first patterned trench 124 . In addition, the material of the first patterned circuit layer 108 is the same as that of the conductive pillar 112 201203478. For example, the material of the first patterned wiring layer 1〇8 is copper and the conductive pillars 112 are copper pillars, and the degree of bonding between the first patterned wiring layer 108 and the conductive pillars 1丨2 of the same material is preferable. The first patterned trench 丨 24 exposes the opening 128 on the upper surface 126 of the first laser-activated dielectric material 154, and the first patterned upper layer 〇8 upper surface 130 and the first laser-activated dielectric material 154 The upper surface 126 is large and flush on the top, which is not intended to limit the invention. In other embodiments, the upper surface 13 of the first patterned circuit layer 1A may be lower or higher than the upper surface 126 of the first laser-activated dielectric material 154. As shown in FIG. 1, the first patterned wiring layer 1〇8 may extend in the direction of the outer side surface of the semiconductor package 10+0 such that at least a portion of the solder balls 122 may extend along the first patterned circuit layer (10). The direction is moved to a position between the semiconductor element 104 and the outer side of the semiconductor package, and the semiconductor package 1 is made into a fan-out type semiconductor package structure. The dielectric protection layer 136 has a plurality of openings 138. The solder balls 122 are correspondingly formed in the (four) holes 138 and electrically connected to the first patterned circuit layer 108. Preferably, but not limited to, the semiconductor encapsulant (10) further includes a surface treatment layer 140' formed on the first substrate layer 108, and a fresh ball 122 is formed on the surface treatment layer. The material of the surface treatment layer 14 is, for example, at least one of nickel (Ni), (Pa) and gold (Au), which can be formed by, for example, electroplating. The surface treatment layer 14 can also improve the bond between the solder ball and the first patterned circuit layer 108 in addition to protecting the first patterned circuit layer (10). In addition, the outer sidewall 148 of the substrate 1〇2, the first laser-activated dielectric 201203478 • 1 ννυυ^^Γ/Λ the outer sidewall 150 of the material 154 and the outer sidewall 152 of the dielectric protective layer 136 are substantially aligned, ie, the outer side Wall 148, outer sidewall 150, and outer sidewall 152 are generally coplanar. Although the number of layers of the first patterned circuit layer 108 of the semiconductor package 100 of the present embodiment is exemplified by a single layer, in other embodiments, please refer to FIG. 2, which illustrates a method according to the present invention. A cross-sectional view of a semiconductor package of an embodiment. The wiring structure 274 of the semiconductor package 2 in Fig. 2 includes a plurality of patterned wiring layers. In detail, the semiconductor package 200 includes a plurality of layers of laser-activated dielectric material and a plurality of patterned circuit layers, wherein adjacent patterned circuit layers are in contact with each other, compared to the semiconductor package 1 of FIG. Electrically connected to the layer of laser activated dielectric material is disposed between adjacent patterned circuit layers. The following is an example of a second laser-activated dielectric material 258 and its medium-second patterned circuit layer (10).
凊繼績參照第2圖’第二雷射活化介電材料258覆 蓋第-圖案化線路層1()8並具有第二圖案化溝槽桃。第 二圖案化溝槽246之槽側壁形成有第二圖案化雷射活化 層206。第二圖案化溝槽⑽露出第一圖案化線路層⑽ 之-部分，第二圖案化線路層244埋設於第二圖案化溝 =246内並透過第二圖案化溝槽⑽電性連接於第一圖 ^匕線路層刚。此外，介電保護層挪覆蓋最外層之圖 案化線路層272，以保護圖案化線路層272。 雖然本實施例之半導體封裝件⑽的半導體元件 104的數量係以單個為例作說 -la…国甘a 然於其它實施態樣中， 明一第3圖’其㈣依照本發明—實施例之半導體封 201203478 第3圖之半導體封裝件_的半導體元 例如是二個。該些半導體元請 ==上對稱於半導體封裝件300的基請的中 且/體封裝件_在製作過程中所發生的趣 小。詳細地說，半導體封裝件300的基 板102的趣曲量大致上對稱於基板⑽的中間位置c，因 此不致使基板102之單側的翹曲量過大。 此外’於其它實施態樣巾，請參照第4圖，其緣示 依照本發明另—實施例之半導體封裝件的剖視圖:相曰較 =第1圖之半導體封裝件刚，第4圖之半導體封裝件 4〇〇更包括設於半導體封裝件4〇〇外部的半 4〇4。半導體元件4〇4例如是覆晶⑴ip响），盆之鲜 球434透過介電保護層436之數個開孔復電性連接於 半導體元件104。半導體元件4〇4並位於半導體封裝件 400之二銲球422之間。 又 以下係以第5圖並搭配第6A至6F圖說明第j圖之 半導體封裝件100之製造方法。第5圖纟會示依照本發明 第一實施例之半導體封裝件的製造方法流程圖，第6八至 6F圖繪示第i圖之半導體封裝件的製造示意圖。 於步驟S102中，提供如第6A圖所示之基板1〇2， 基板102具有第一基板表面u〇。 於步驟S1041中，如第6A圖所示，藉由黏著層116 將半導體元件104固設於基板102之第一基板表面11〇 上0 该些半導體元件104可另外於晶圓上製作電路完成 201203478 > i ννουν/m 並切割分離後，重新分佈於基板1〇2上。 然後，於步驟S1042中，如第6β_示，㈣合或 盍基板102的第-.基板表自11〇、半導體元件⑽之主動 表面114及側面118。為不使圖式過於複雜，第诎圖僅 繪不出單個半導體元件104。 本步驟S1042之第-雷射活化介電材料154係以重 佈後之该些+導體元件104的整體作為封裝對象，因此， 本實施例之製程係重佈晶片之封膠體級封裝 (Chip-red.str.bution Encapsulant Level Package), e使裝作出的半導體封裝件列屬晶片尺寸財（㈤p Scale Package，CSP)或晶圓級封裝（Wafer；L晴丨The second embodiment of the second laser-activated dielectric material 258 covers the first-patterned wiring layer 1 () 8 and has a second patterned trench peach. A sidewall of the trench of the second patterned trench 246 is formed with a second patterned laser activating layer 206. The second patterned trench (10) exposes a portion of the first patterned wiring layer (10), and the second patterned wiring layer 244 is embedded in the second patterned trench 246 and electrically connected to the second patterned trench (10). A picture ^ 匕 line layer just. In addition, the dielectric cap layer covers the outermost patterned circuit layer 272 to protect the patterned circuit layer 272. Although the number of the semiconductor elements 104 of the semiconductor package (10) of the present embodiment is exemplified by a single example, a third embodiment of the semiconductor package (10) is shown in FIG. 3, which is in accordance with the present invention. The semiconductor package of the semiconductor package 201203478 of FIG. 3 is, for example, two semiconductor elements. The semiconductor elements are == symmetrical on the base of the semiconductor package 300 and the / package is _ in the production process. In detail, the amount of the substrate 102 of the semiconductor package 300 is substantially symmetrical with respect to the intermediate position c of the substrate (10), so that the amount of warpage on one side of the substrate 102 is not excessively large. In addition, in other embodiments, please refer to FIG. 4, which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention: a semiconductor package of FIG. 1 and a semiconductor of FIG. The package 4 further includes a half 4 4 disposed outside the semiconductor package 4 . The semiconductor element 4〇4 is, for example, flip chip (1) ip ring), and the fresh bulb 434 of the pot is electrically connected to the semiconductor element 104 through a plurality of openings of the dielectric protective layer 436. The semiconductor component 4〇4 is located between the solder balls 422 of the semiconductor package 400. Further, a method of manufacturing the semiconductor package 100 of the jth diagram will be described with reference to Fig. 5 and Figs. 6A to 6F. 5 is a flow chart showing a method of fabricating a semiconductor package according to a first embodiment of the present invention, and FIGS. 6-8 to 6F are views showing a manufacturing process of the semiconductor package of FIG. In step S102, a substrate 1〇2 as shown in FIG. 6A is provided, and the substrate 102 has a first substrate surface u〇. In step S1041, as shown in FIG. 6A, the semiconductor device 104 is fixed on the first substrate surface 11 of the substrate 102 by the adhesive layer 116. The semiconductor device 104 can be fabricated on the wafer. 201203478 > i ννουν/m and after cutting and separating, redistributed on the substrate 1〇2. Then, in step S1042, as shown in the sixth step, the first substrate of the substrate 102 is formed from 11 Å, the active surface 114 of the semiconductor element (10), and the side surface 118. In order not to overly complicate the drawing, the first drawing only shows a single semiconductor component 104. The first-laser-activated dielectric material 154 of the step S1042 is packaged by the whole of the +-conductor elements 104 after the redistribution. Therefore, the process of the embodiment is a package-level package of the re-wafer wafer (Chip- Red.str.bution Encapsulant Level Package), e makes the semiconductor package made by the chip size ((5) p Scale Package, CSP) or wafer level package (Wafer; L Qingyi
Package，WLP)等級，然此非用以限制本發明。 然後，於步驟S1043中，如第6C圖所示，以雷射於 第雷射活化電材才斗154上形成第一圖案化溝槽 ^第-圖案化雷射活化層⑽’第—圖案化溝槽124並露 =些導電柱112。如第6C圖之粗線所示，由雷射形成 的4 一圖案化溝槽124中，其槽側壁132係被活化而形 成具導電性的第一圖案化雷射活化層106。此外，雷射照 射的過程可選擇性地使用光罩。 然後，於步驟幻044中，如第6D圖所示，以無電鍍 Electroless)技術形成第一圖案化線路層1肿於第一 圖案化溝槽丨24内，並使第一圖案化線路層108電性連 接於該些導電柱112。 由於第一圖案化雷射活化層1 具導電性因此第 201203478 -圖案化線路層1G8可透過電財式形成於第—圖案化 雷射活化層H)6h使第-圖案化線路層1〇8埋設於第 一圖案化溝槽124内。 此外，第一圖案化線路層1〇8的形成厚度係依據無 f鍍製程的時間而定。例如’藉由時間的控制，第 案化線路層108之上表面130與第一圖案化雷射活化層 106之上表面126大致上齊平，如第6D圖所^然此非 用以限制本發明。 此外，由於第一圖案化線路層108的形成過程可不 使用光罩，因此不會發生因鮮定位不準所產生的偏位 問題。如此，半導體封裝件⑽的線路（trace)尺寸精 度係較佳，其線_寬度及線路之_間距皆可小於ι〇 μι再者，由於第-圖案化溝槽124及第—圖案化線路 層1〇8的尺寸精度較佳，故，即使在形成多層圖案化線 ^層（如第2圖之半導體封裝件2〇〇)的情況下，仍可使 多層圖案化線路層之間精確地接觸，以維持較佳 品質。 另外，由於可在不需應用蝕刻製程的情況下形成第 一圖案化線路層108’因此第一圖案化線路層1〇8不會發 生蝕刻製私通常會發生的過切（underc的）不良問題， 可避免因過切問題所導致的結構強度下降。進一步地 j，相較於傳統應用蝕刻技術形成之圖案化線路層，本 實鈀例之第一圖案化線路層108的結構強度係較佳。 ▲然後，於步驟S1045中，形成如第6E圖所示之介電 保蔓層136覆蓋第一圖案化線路層及第一雷射活化 201203478 * 1 1 wou^zm 介電材料154之上表面156。介電保護層136並具有數個 開孔138，以露出第一圖案化線路層1〇8之一部分178。 然後，於步驟S1046中，形成如第6E圖所示之表面 處理層140於第一圖案化線路層1 之該部分1 π上。 然後，於步驟S106中，如第6F圖所示，對應半導 體元件104的位置，切割第一雷射活化介電材料154、介 電保護層136及基板1〇2。 於切割步驟S106中，切割路徑p通過基板1〇2、第 一雷射活化介電材料154及介電保護層136，使基板ι〇2 的外側壁148、第一雷射活化介電材料154的外側壁150 及介電保護層136的外侧壁152大致上切齊。 然後，於步驟S108中，形成數個如第i圖所示之銲 球122於第-圖案化線路層⑽之開孔138内的表面處 理層140上，以電性連接於第—圖案化線路層1〇8。至此， 形成如第1圖所示之半導體封裝件1〇〇。 ^然步驟S108係於切割步驟灿6之後完成，然於 其它實施態樣中’步驟81〇8亦可於㈣步驟s⑽之 完成。 以下係以第5圖之流程圖說明第2圖之半導體封裝 件200之製造方法。半導體㈣件細的製造方法中， 步驟S1G2、S1G41至S1G44相似於第i圖之半導體封裝 件100的製造方法’於此不再重複贅述，以下係從步驟 S1044之後開始說明。於步驟Sl〇44之後，形成第二雷射 材料258覆蓋第—圖案化線路層⑽（第一圖 化線路層⑽繪示於第2圖），其中第二雷射活化介電材 13 201203478 , · 料258相似於第一雷射活化介電材料154，在此不重複贅 述。然後，以雷射於該第二雷射活化介電材料258上形 成如第2圖所示之第二圖案化溝槽246及第二圖案化雷 射活化層206’第二圖案化溝槽246並露出第一圖案化線 路層108之-部分。然後，以電鍍方式形成如第2圖所 之第二圖案化線路層244於露出之第—圖案化線路層 108之該部分上及第二圖案化雷射活化層2〇6上内，第二 圖案化線路層244並電性連接於第一圖案化線路層1〇8。 第2圖之半導體封裝件中其它雷射活化介電材料層 及其它圖案化線路層的形成方法分別相似於第二雷射活 化介電材料258及第二圖案化線路層244的形成方法， 在此不再重複贅述。 第一貫施例Package, WLP) level, which is not intended to limit the invention. Then, in step S1043, as shown in FIG. 6C, a first patterned trench is formed on the laser-activated electrical material hopper 154, and the first patterned trench activation layer (10) is patterned. The slot 124 is exposed to some of the conductive posts 112. As shown by the thick line in Fig. 6C, in the four patterned trenches 124 formed by the laser, the trench sidewalls 132 are activated to form the first patterned laser activated layer 106 having conductivity. In addition, the process of laser irradiation can selectively use a reticle. Then, in step 044, as shown in FIG. 6D, the first patterned wiring layer 1 is formed in the first patterned trench 24 by electroless plating (Electroless) technology, and the first patterned wiring layer 108 is formed. Electrically connected to the conductive pillars 112. Since the first patterned laser activating layer 1 is electrically conductive, the 201203478 - patterned circuit layer 1G8 can be formed on the first patterned laser activating layer H) 6h by means of electricity to make the first patterned circuit layer 1 〇 8 Embedded in the first patterned trench 124. Further, the thickness of the first patterned wiring layer 1 〇 8 is determined depending on the time of the f-free plating process. For example, by time control, the upper surface 130 of the first circuit layer 108 is substantially flush with the upper surface 126 of the first patterned laser activating layer 106, as shown in FIG. 6D. invention. In addition, since the photomask is not formed in the formation process of the first patterned wiring layer 108, the problem of the offset caused by the inaccurate positioning is not caused. Thus, the dimensional accuracy of the trace of the semiconductor package (10) is better, and the line_width and the pitch of the line can be less than ι〇μι, because the first-patterned trench 124 and the first patterned layer The dimensional accuracy of 1〇8 is better, so that even in the case of forming a multilayer patterned wiring layer (such as the semiconductor package 2〇〇 of FIG. 2), precise contact between the multilayer patterned wiring layers can be achieved. To maintain better quality. In addition, since the first patterned wiring layer 108' can be formed without applying an etching process, the first patterned wiring layer 1〇8 does not suffer from an undercut problem that usually occurs in etching. , to avoid structural strength degradation caused by overcutting problems. Further, the structural strength of the first patterned wiring layer 108 of the present palladium example is better than that of the patterned wiring layer formed by the conventional etching technique. ▲ Then, in step S1045, the dielectric protective layer 136 as shown in FIG. 6E is formed to cover the first patterned circuit layer and the first laser activation 201203478 * 1 1 wou ^ zm dielectric material 154 upper surface 156 . The dielectric cap layer 136 has a plurality of openings 138 to expose a portion 178 of the first patterned circuit layer 1〇8. Then, in step S1046, the surface treatment layer 140 as shown in Fig. 6E is formed on the portion 1π of the first patterned wiring layer 1. Then, in step S106, as shown in Fig. 6F, the first laser-activated dielectric material 154, the dielectric protective layer 136, and the substrate 1〇2 are cut corresponding to the position of the semiconductor element 104. In the cutting step S106, the cutting path p passes through the substrate 1〇2, the first laser-activated dielectric material 154, and the dielectric protective layer 136, so that the outer sidewall 148 of the substrate ι2, the first laser-activated dielectric material 154 The outer sidewall 150 and the outer sidewall 152 of the dielectric cap layer 136 are substantially aligned. Then, in step S108, a plurality of solder balls 122 as shown in the figure i are formed on the surface treatment layer 140 in the opening 138 of the first patterned circuit layer (10) to be electrically connected to the first patterned line. Layer 1〇8. Thus far, the semiconductor package 1A as shown in Fig. 1 is formed. ^Step S108 is completed after the cutting step 灿6, but in other embodiments, 'Step 81 〇8 can also be completed in (4) step s(10). Hereinafter, a method of manufacturing the semiconductor package 200 of Fig. 2 will be described with reference to a flowchart of Fig. 5. In the semiconductor (four) thin manufacturing method, the steps S1G2, S1G41 to S1G44 are similar to the manufacturing method of the semiconductor package 100 of the first embodiment, and the description thereof will not be repeated here, and the following description will be made after the step S1044. After step S104, a second laser material 258 is formed to cover the first patterned circuit layer (10) (the first patterned circuit layer (10) is shown in FIG. 2), wherein the second laser-activated dielectric material 13 201203478, Material 258 is similar to first laser activated dielectric material 154 and will not be described again herein. Then, a second patterned trench 246 and a second patterned laser active layer 206' second patterned trench 246 as shown in FIG. 2 are formed on the second laser-activated dielectric material 258. And exposing a portion of the first patterned circuit layer 108. Then, a second patterned wiring layer 244 as shown in FIG. 2 is formed by electroplating on the portion of the exposed first patterned circuit layer 108 and the second patterned laser activating layer 2〇6, and second The patterned wiring layer 244 is electrically connected to the first patterned wiring layer 1〇8. The other laser-activated dielectric material layers and other patterned circuit layers in the semiconductor package of FIG. 2 are formed similarly to the second laser-activated dielectric material 258 and the second patterned circuit layer 244, respectively. This is not repeated here. First consistent example
=參，第7圖及第8八至仙圖，帛7圖緣示依照 X貫施例之半導體封裝件的製造方法流程圖， 主^ 8β圖繪不應用第二實施例之製造方法製造第1圖 體封裝件的製造示意圖。第二實施例中與第一實; 1同之處沿用相同標號，在此不再贅述。第二實施] 件件的製造方法與第一實施例之半導體封』 ㈣ ^同之處在於，第二實施例之製造方法1 ^件；載板中相對二面上分別形成二組相似的半導體_ 、千’使產能加倍。 載板=rrS2G2中，提供如第8A圖所示之載板56〇< 載板560具有相對之第—載板表面562與第二載板^ 14 201203478 564。 於步驟S204中，如第8a圖所示，以黏貼方式分別 設置二個如第1圖所示之基板1〇2於載板560之第一載 板表面562上及弟一载板表面564上。 接下來的製程步驟中，可同時於載板560中相對二 側上分別形成一組相似的半導體封裝件，使產能加倍。 以下僅以形成於第一载板表面562上之基板102的半導 體封裝件為例作說明。 • 步驟S2061至S2066相似於第5圖之步驟S1041至 S1046，在此不再重複贅述，以下從步驟S208開始說明。 於步驟S208中’如第8B圖所示，以撕除方式將半 導體封裝件自載板560上分離。 接下來的步驟S210至S212相似於第5圖之步驟 S106至S108，在此不再重複贅述。 第三實施例 • 請參照第9圖，其繪示依照本發明第三實施例之半 導體封裝件的剖視圖。第三實施例中與第一實施例相同 之處沿用相同標號，在此不再贅述。第三實施例之半導 體封裝件與第一實施例之半導體封裝件不同之處在於， 第三實施例之半導體封裝件600的基板602中相對二面 形成有二組相似的線路結構674及676。 半導體封裝件600之基板602係具有數個導電貫孔 (conductive via) 670 的石夕基板（Si substrate)或玻 璃基板（glass substrate)。 15 201203478 電 · TSV)技術^^ 67G係由碎穿孔（Through Si 1 icon Via, 態樣中，^成。然此非用職制本發明，於其它實施 其它種類的其f封#件咖之基板6(32亦可塑膠基板或 銅而形成。 ^導電貝孔可於機械穿孔後於孔内鍍 基板⑽（線路姓 線路'、。構674相似於第2圖中 介電材料654 /j 不同之處在於，第一雷射活化 的導電貫孔β7η案化溝槽624更露出基板_中部分 案化溝槽接Λ案Γ路層608可透過第一圖 :籌。676以相似於線路結構㈣的方式電性連接於基 位於基才反602之相對二面上的線路結構676及 W4可透過基板6〇2電性連接。 圖之半導體封裝件600的 以下係以第5圖說明第9 製造方法。 於步驟S102中，提供如第9圖所示的基板6〇2，基 板602具有相對之第-基板表面61〇與第二基板表面 680。接下來的製程步驟中’可同時於基板中相對之 第-基板表面610與第二基板表面咖上分別設置數個 半導體7L件，然、後形成相似的線路結構674及676。線路 結構674及676的形成方法相似於第2圖之基板1〇2上 方的線路結構274的形成方法，在此不再贅述。 本發明上述實施例所揭露之半導體封裝件及其製造 方法’具有夕項特徵’列舉部份特徵說明如下： (1).半導體封裝件之圖案化線路層係内埋式線路。 201203478 f * t wr f x 内埋式線路中至少一八 案化溝槽内，使内埋二：：：雷射活化介電材料之圖 介電材L翻^ 導體封裝件之雷射活化 ’接觸面積較大’結合強度較強。 相，斤μ於基板及雷射活化介電材料的熱膨脹係數 ❹料切_量較小: 多層心的層數可以是 ^).由於圖案化線路層的形成過程可不使用光 可提由於光罩定位不準的偏位問題，如此 線路件的線路尺寸精度’其線路的寬度及 綠路之間的間距皆可小於10帅。 (5).由於在不需要應用韻刻製程的情況下亦可形 j第一圖案化線路層’因此圖案化線路層不會發生敍刻 衣程會發生的過切不良問題， x 致的結構強度下降。 了避免因為過切問題所導 ⑻.圖案化線路層接觸_#化溝槽之槽側壁，辦 =圖案化線路層與㈣化雷射活化層之間曰 提升結合強度。 (7) .雷射活化介電材料被雷射照射過的部 活化而形成具導電性的雷射活化層，有助 贫 驟中鍍層的產生。 、錢v (8) .基板係係金屬板’其強度甚佳，可增 封裝件的整體結構強度。 (9) .基板之側面及底面係裸露出來，可快 導體封裝件内部的產熱。 201203478 2所述，雖然本發明已以較佳實施 如， =非用以限定本發明。本發明所屬技術領域 各種之更動賴。因此二=圍内’當可作 之申請專利翻所界定者^ 關當視後附 【圖式簡單說明】 的剖視第^繪线财發賴料麵丨之料體封裝件 剖視圖第。2圖繪示依照本發明-實施例之半導體封裝件的 剖視圖第。3圖繪示依照本發明—實施例之半導體封裝件的 的剖視第Γ㈣依财㈣另—實_之半導體封裝件 的製㈣本糾第—實施狀何體封裝件 第6Ai 6F圖繪示第！圖之半導體封裝件的製造示 忍圆〇 的照本㈣f狀料體封裝件 第8A至8B圖繪TF應用第二實施例之製造方法製造 圖之半導體封裝件的製造示意圓。 的剖示依照本發明第三實施例之半導體封裝件 201203478 ， 1 j wouy/m 【主要元件符號說明】 半導體封裝件 100 、 200 、 300 、 400 、 600 : 102、602 :基板= reference, Fig. 7 and Fig. 8 to Fig. 7, Fig. 7 is a flow chart showing the manufacturing method of the semiconductor package according to the X embodiment, and the main manufacturing method is not applied to the manufacturing method of the second embodiment. 1 schematic diagram of the manufacture of the picture package. In the second embodiment, the same reference numerals are used in the same reference numerals as in the first embodiment, and details are not described herein again. Second Embodiment] The manufacturing method of the component is the same as the semiconductor package of the first embodiment. (4) is the same as the manufacturing method of the second embodiment; two sets of similar semiconductors are formed on opposite sides of the carrier. _, thousand 'doubled the production capacity. In the carrier plate = rrS2G2, the carrier plate 56 as shown in Fig. 8A is provided. The carrier plate 560 has the opposite first carrier surface 562 and the second carrier plate 14 201203478 564. In step S204, as shown in FIG. 8a, two substrates 1〇2 as shown in FIG. 1 are respectively disposed on the first carrier surface 562 of the carrier 560 and on the carrier surface 564. . In the subsequent process steps, a similar set of semiconductor packages can be formed on opposite sides of the carrier 560 at the same time to double the throughput. Hereinafter, only the semiconductor package of the substrate 102 formed on the first carrier surface 562 will be described as an example. • Steps S2061 to S2066 are similar to steps S1041 to S1046 of FIG. 5, and the description thereof will not be repeated here, and the following description will be made from step S208. In step S208, as shown in Fig. 8B, the semiconductor package is separated from the carrier 560 in a tear-off manner. Subsequent steps S210 to S212 are similar to steps S106 to S108 of Fig. 5, and the detailed description thereof will not be repeated here. THIRD EMBODIMENT • Referring to Fig. 9, there is shown a cross-sectional view of a semiconductor package in accordance with a third embodiment of the present invention. In the third embodiment, the same reference numerals are used in the same portions as the first embodiment, and details are not described herein again. The semiconductor package of the third embodiment is different from the semiconductor package of the first embodiment in that two sets of similar line structures 674 and 676 are formed on the opposite sides of the substrate 602 of the semiconductor package 600 of the third embodiment. The substrate 602 of the semiconductor package 600 is a Si substrate or a glass substrate having a plurality of conductive vias 670. 15 201203478 Electric · TSV) Technology ^^ 67G is made of broken perforation (Through Si 1 icon Via, in the form, ^. This is not the use of the present invention, in other implementations of other types of its f-block 6 (32 can also be formed by plastic substrate or copper. ^ Conductive shell hole can be plated in the hole after mechanical perforation (10) (line name line ', structure 674 is similar to the second picture dielectric material 654 / j difference The first laser-activated conductive through-hole β7η cased trench 624 is more exposed to the substrate. The middle-segmented trench interface layer 608 can be transmitted through the first figure: 676 is similar to the line structure (4). The circuit structures 676 and W4 electrically connected to the opposite sides of the base 602 can be electrically connected through the substrate 6〇2. The semiconductor package 600 of the figure is described below with reference to FIG. In step S102, a substrate 6〇2 as shown in FIG. 9 is provided, and the substrate 602 has a first substrate surface 61〇 and a second substrate surface 680. The next process step can be simultaneously in the substrate. The first substrate surface 610 and the second substrate surface are respectively provided with a plurality of half The body 7L is formed into a similar circuit structure 674 and 676. The formation of the line structures 674 and 676 is similar to the method of forming the line structure 274 above the substrate 1〇2 of FIG. 2, and will not be described herein. The semiconductor package disclosed in the above embodiments and the method of manufacturing the same have been described as follows: (1) The patterned circuit layer of the semiconductor package is embedded in the circuit. 201203478 f * t wr At least one of the eight buried trenches in the fx buried circuit, so that the buried dielectric::: laser activated dielectric material, the dielectric material L is turned over; the laser package of the conductor package is 'large contact area' The strength is strong. The phase, the mass expansion coefficient of the substrate and the laser-activated dielectric material is less than the amount: the number of layers of the multilayer core can be ^). Since the formation of the patterned circuit layer can not use light Due to the misalignment problem of the reticle positioning, the line size accuracy of such a line piece can be less than 10 handsomely between the width of the line and the green line. (5). Since it is not necessary to apply the rhyme process In the case, it can also be shaped first. The circuit layer is 'so that the patterned circuit layer does not suffer from over-cutting problems that occur during the coating process, and the structural strength of x is reduced. Avoiding the problem of over-cutting (8). Patterned circuit layer contact _# The groove side wall of the groove, the patterning circuit layer and the (four) laser activation layer between the 曰 lift bonding strength. (7) The laser-activated dielectric material is activated by the laser-irradiated portion to form a conductive The laser activation layer helps to produce the coating in the lean phase., money v (8). The substrate is a metal plate that has a very good strength and can increase the overall structural strength of the package. (9) The side and bottom of the substrate are exposed to heat the inside of the conductor package. As described in 201203478 2, although the present invention has been preferably implemented, for example, = is not intended to limit the present invention. The technical field to which the present invention pertains is more versatile. Therefore, if the application is patented, it can be defined as the patent application. ^After the view, the cross-section of the drawing is a cross-sectional view of the material package. 2 is a cross-sectional view showing a semiconductor package in accordance with an embodiment of the present invention. 3 is a cross-sectional view of a semiconductor package in accordance with the present invention. FIG. 4 is a fourth embodiment of a semiconductor package according to the fourth aspect of the invention. The first! The manufacture of the semiconductor package of the figure shows the photo of the semiconductor package (4) f-shaped material package. Figs. 8A to 8B illustrate the manufacturing method of the TF application of the second embodiment. A semiconductor package according to a third embodiment of the present invention 201203478, 1 j wouy/m [Description of main component symbols] Semiconductor package 100, 200, 300, 400, 600: 102, 602: substrate
104、304、404 :半導體元件 106 :第一圖案化雷射活化層 108、· 608:第一圖案化線路層 110、610:第一基板表面 112 :導電柱 114 :主動表面 116 :黏著層 118 :側面 120 :背面 122、422、434 :銲球 124、624 :第一圖案化溝槽 126、130 :上表面 128 :開口 13 2 :槽側壁 136 ' 236、436 :介電保護層 138、438 :開孔 140 :表面處理層 148 ' 150、152 :外側壁 154、654 .第一雷射活化介電材料 174、274、674、676 :線路結構 178* 一部分 19 201203478 206 :第二圖案化雷射活化層 244 :第二圖案化線路層 246 :第二圖案化溝槽 258 :第二雷射活化介電材料 272 :圖案化線路層 560 :載板 562 :第一載板表面 564:第二載板表面 670 :導電貫孔 680 :第二基板表面 C:中間位置 P:切割路徑104, 304, 404: semiconductor element 106: first patterned laser activating layer 108, · 608: first patterned circuit layer 110, 610: first substrate surface 112: conductive pillar 114: active surface 116: adhesive layer 118 Side 120: Backside 122, 422, 434: Solder balls 124, 624: First patterned trenches 126, 130: Upper surface 128: Opening 13 2: Slot sidewalls 136' 236, 436: Dielectric protective layers 138, 438 : Opening 140: surface treatment layer 148' 150, 152: outer sidewalls 154, 654. First laser activated dielectric material 174, 274, 674, 676: line structure 178* portion 19 201203478 206: second patterned thunder The active layer 244: the second patterned wiring layer 246: the second patterned trench 258: the second laser activated dielectric material 272: the patterned wiring layer 560: the carrier 562: the first carrier surface 564: the second Carrier surface 670: conductive via 680: second substrate surface C: intermediate position P: cutting path