201203417 六、發明說明： 【發明所屬之技術領域】 本發明涉及一種用於檢測半導體晶片的電氣特性的探針 板’尤其涉及探針卡基板。 【先前技術】 通常，半導體元件通過在晶片（wafer)上形成圖案.的處 理（Fabrication )工序和對形成圖案的晶片用各元件進行裝 配的裝配（Assembly )工序來製造。 完成處理工序的半導體元件在經過裝配工序之前會進行 用於對形成於各晶片的各元件檢測電氣特性的晶片電氣特 性棟選（Electrical Die Sorting :以下稱為「eds」）工序。 在此，EDS工序是為了在形成於晶片的元件中判別出不 良元件而進行的工序。在EDS工序中主要使用對晶片上的元 件施加電氣信號’ ϋ通過對元件回應的電氧信號#分析來判 定元件的不良與否的探針台。 判定元件的不良與否的探針台為了向元件的焊盤傳遞電 氣信號而安装使用探針板（PrGbeeard)。探針板具有探針卡 基板和-㈣上的針（Needle^將該針接觸到連接於半導 體晶>1上的兀件的焊盤’從而半導體元件檢測設備通過連接 於探針卡基板的探針板的針，與元件的焊盤㈣Μ㈣， 由此判_元件的不良與否。 在韓國A開專利第1G_2__議2497號（以下稱為「現 201203417 有技術1」）中，探針卡基板對應於形成在晶片的半導體元 件的排列而由多個區塊（Block)構成，因此能夠減少對晶片 的EDS測試時間。但是’隨著探針卡基板從印刷電路板替換 為具有優異的熱膨脹係數、高頻特性的多層陶.竞 (MulU-Layer Ceramic，MLC )基板，且由於半導體晶片的 面積變大而要求更寬面積的探針基板，以多層陶瓷（MLC ) 基板構成探針基板時，存在所需成本高的問題。 圖la是示出為了解決上述問題而提出的探針板基板1〇 的平面圖。在現有的用於探針基板的pCB基板以彩虹 (Rainbow )形狀排列並安裝多層陶瓷材料的區塊。該多層 陶瓷區塊11視為一個待測裝置（]0〜1£^11110以1^〇1)1^)。 在此，所謂待測裝置（DUT)是指，在進行某種測試時，將 接受其測試的被測元件。 這種技術相比於現有技術丨具有能夠減少所使用的探針 卡的製造成本的效果。 但是’如上述及之技術中還發現了如下的問題。 探針卡基板由上部焊盤、過孔（via)、下部焊盤構成。 在進行EDS測試時，電氣信號從上部焊盤經過充填有導電趲 的過孔傳遞到下部焊盤，從而傳遞到半導體元件的焊盤。 圖lb至圖lc疋用於說明上述的探針卡基板的電氣信 路徑的圖。根據這些圖.，探針板的練1G由多個多層陶 區A 11構成’且從測試探針13連接至多層陶 區塊U上的待測裝置12的傳送電路分別連接於各個區塊 因此’在進行Eps測試時，電氣信號從測試探針13分支 201203417 各待測裝置1 2而進行傳遞。這會引起信號的分支偏差，且 &成阻抗失配..（Impedance Mismatching)。因此’具有不適 於作為逐漸向高頻（High Frequency )、高速（High Speed ) 特性發展的半導體元件的檢測設備的問題。 【發明内容】 本發明是為了解決上述問題而‘提出的，其目的在於提供 一種能夠消除因探針板基板的區塊之間的分支而引起的信 號偏差的方法。 為了實現上述目的，根據本發明的一方面的探針卡基板 包括：用於與外部的印刷電路板進行電氣連接的連接部；與 所述連接部電氣連接，且從所述連接部接收電氣信號而形成 測試的多個被測元件被設定為一個區塊的多個多層陶曼區 瑰。並且，從所述連接部傳遞到所述多個多層陶瓷區塊中的 某一個多層陶瓷區塊的電氣信、號均等地分支並傳遞到每個 戶斤述多個被測元件。 並且，從所述連接部傳遞到所述多個多層陶瓷區塊中的 某/個多層陶瓷區塊的電氣信號通過兩次分支傳遞到所述 多個被測元件中的某一個被測元件。 另外，所述多個多層冑竟區塊中的某一個多層陶竞區塊 由四個被測元件設置。 另外，所述連接部與所述多個多相£區塊中的某一個 多層陶瓷區塊的電氣連接通過一個連接線連接。 201203417 並且’從所述連接部傳遞到所述多個多層陶竟區塊中的 某一個多層陶瓷區堍的電氣信號在所述多層陶瓷區塊内進 行分支’以均等地傳遞到每個所述多個被測元件。 根據本發明的探針卡基板設計為由四個待測裝置 (Device Under Test ’ DUT)構成一個多層陶瓷區塊，因此 能夠減少因分支而造成的信號偏差。其結果，具有能夠在沒 有引起分支偏差的情況下接收在檢測時從半導體元件傳遞 的k號，且能夠降低阻抗失配的效果。 因此，可適合作為具有高速、高頻特性的半導體檢測設 備。 【實施方式】 以下，為了咸夠更加具體地理解本發明，通過參照附圖 的優選實施例來進行說明。 ，圖3a、圖3b201203417 VI. Description of the Invention: [Technical Field] The present invention relates to a probe card ′ for detecting electrical characteristics of a semiconductor wafer, and more particularly to a probe card substrate. [Prior Art] Generally, a semiconductor element is manufactured by a process of forming a pattern on a wafer and an assembly process of assembling each element of the patterned wafer. The semiconductor element that has completed the processing step is subjected to a process of electrically electrifying (Electrical Die Sorting) (hereinafter referred to as "eds") for detecting electrical characteristics of each element formed on each wafer before the assembly process. Here, the EDS process is a process performed to identify a defective component in an element formed on a wafer. In the EDS process, an application of an electrical signal to a component on a wafer is generally used to determine the defect of the component by analyzing the electrical oxygen signal # response to the component. The probe station that determines the failure of the element is mounted with a probe card (PrGbeeard) for transmitting an electrical signal to the pad of the element. The probe card has a probe card substrate and a pin on the (four) (Needle^ contacts the pin to a pad attached to the die on the semiconductor crystal > 1) so that the semiconductor component detecting device is connected to the probe card substrate The needle of the probe card and the pad (4) of the component (4) are used to determine whether the component is defective or not. In the Korean Patent No. 1G_2__2497 (hereinafter referred to as "201203417 Technology 1"), the probe The card substrate is composed of a plurality of blocks corresponding to the arrangement of the semiconductor elements formed on the wafer, so that the EDS test time for the wafer can be reduced. However, 'the probe card substrate is replaced with an excellent one from the printed circuit board. MulU-Layer Ceramic (MLC) substrate with thermal expansion coefficient and high-frequency characteristics, and a wider area of the probe substrate is required due to the larger area of the semiconductor wafer, and the probe substrate is composed of a multilayer ceramic (MLC) substrate. At the time, there is a problem that the required cost is high. Fig. 1a is a plan view showing the probe card substrate 1A proposed to solve the above problem. The conventional pCB substrate for the probe substrate is arranged in a rainbow shape. And mounting the multilayer ceramic tile. The multilayer ceramic block 11 as a device under test (] 0~1 £ ^ 11110 ^ 〇1 1) ^ 1). Here, the device under test (DUT) refers to a device under test that will be tested when a certain test is performed. This technique has an effect of reducing the manufacturing cost of the probe card used compared to the prior art. However, the following problems have been found in the above-described techniques. The probe card substrate is composed of an upper pad, a via, and a lower pad. During the EDS test, an electrical signal is transmitted from the upper pad through the via filled with the conductive turns to the lower pad, thereby being transferred to the pads of the semiconductor device. Figs. 1b to 1c are diagrams for explaining the electrical signal path of the above probe card substrate. According to these figures, the transfer 1G of the probe card is composed of a plurality of multi-layered ceramic regions A 11 and the transfer circuits connected from the test probe 13 to the device under test 12 on the multi-layer ceramic block U are respectively connected to the respective blocks. 'When performing the Eps test, the electrical signal is transmitted from the test probe 13 to the 201203417 device to be tested 12 for transmission. This causes branch deviations in the signal and & impedance mismatch.. (Impedance Mismatching). Therefore, there is a problem that it is unsuitable for a detecting device which is a semiconductor element which is gradually developed to high frequency and high speed. SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and an object thereof is to provide a method capable of eliminating signal deviation caused by a branch between blocks of a probe card substrate. In order to achieve the above object, a probe card substrate according to an aspect of the present invention includes: a connection portion for electrically connecting to an external printed circuit board; is electrically connected to the connection portion, and receives an electrical signal from the connection portion The plurality of measured elements forming the test are set as a plurality of multi-layered Tauman areas of one block. Further, an electric signal, which is transmitted from the connecting portion to one of the plurality of multilayer ceramic blocks, is equally branched and transmitted to each of the plurality of elements to be tested. And, an electrical signal transmitted from the connecting portion to the one or more multilayer ceramic blocks of the plurality of multilayer ceramic blocks is transferred to one of the plurality of devices under test through two branches. In addition, one of the plurality of multi-layered tiles is provided by four elements to be tested. Further, the electrical connection of the connecting portion to one of the plurality of multi-phase blocks is connected by a connecting wire. 201203417 and 'electrical signals transmitted from the connection portion to one of the plurality of multilayer ceramic blocks are branched in the multilayer ceramic block' to be equally transferred to each of the Multiple tested components. The probe card substrate according to the present invention is designed to constitute a multilayer ceramic block by four Device Under Test 'DUTs, thereby reducing signal deviation due to branching. As a result, it is possible to receive the k number transmitted from the semiconductor element at the time of detection without causing branch deviation, and it is possible to reduce the impedance mismatch. Therefore, it can be suitably used as a semiconductor detecting device having high speed and high frequency characteristics. [Embodiment] Hereinafter, the present invention will be more specifically understood by reference to the preferred embodiments of the accompanying drawings. , Figure 3a, Figure 3b
圖2為用於說明本發明的探針卡的側視圖 為根據本發明實施例的探針卡基板的平面圖，丨 發明實施例的探針卡基板的放大圖，圖仆為 本發明實施例的探針卡的電氣信號的路徑的桐 201203417 過探針卡基板⑽傳遞到探測針13G，傳遞到探測針㈣的 電氣信號將會傳遞到設置於半導體晶片的焊盤。 在此，印刷電路板21〇是將各種類型的多個部件密集地 搭載到用紛㈣脂和環氧樹脂製成的平板上，而且將連接各 部件之間的電路密集地縮小到樹脂平板的表面並進行固定 的電路板。 測試探針120連接於設置在印刷電路板21〇的焊盤，以 電氣連接到形成於印刷電路板21〇的電路圖案.，從而起到將 從印刷電路板210傳遞的電氣信號傳遞到探針卡基板ι〇〇的 作用即，測試探針120為電氣連接印刷電路板21〇和探針 卡基板100的連接部、 探針卡基板100的下側表面設置有探測針13〇，且連接 成使探測針130能夠接收通過測試探針12〇傳遞的電氣俨 號。 ’ 。 探針卡基板100由上部焊盤、過孔、下部焊盤構成。上 p焊盤通岑與測s式探針i 2 〇連接而接收從印刷電冷板21 〇傳 遞的電氣信號。該電氣信號經過被稱為過孔的通路而傳遞到 下部焊盤，由此使連接於下部焊盤的探測針1 30能夠進行半 導體元件的測試.。 在此’上部焊盤為多層陶瓷區塊110,其通過過孔與安 裝於下部焊盤的探測針130電氣連接。 在此’過孔構成探針卡基板1〇〇,並充填有導電材料。 導電材料採用電氣特性優異的Ag、Cu等。所充填的導電材 料起到使多個排線與圖案通電的作用。 201203417 過孔的用途包括：用於電氣連接各個層之間的過孔、方 便熱擴散的導熱（thermal)孔、在堆疊步驟中用於將各個層 對準到正確的位置的定位（t〇〇ling)孔、還有當印製圖案時 作為基準點的對位（registrati〇n )孔等。 待測裝置1 40根據本發明實施例，在探針卡基板丨〇〇的 上u卩焊盤女裝為多個。在此，所謂待測裝置是指，在進 行某種測試時，將接受其測試的被測元件。 圖3a為根據本發明實施例的探針卡基板ι〇〇。如圖所 丁夕層陶瓷區塊以彩虹（Rainbow)形狀排列在探針 卡基板100上。圖4a為構成基板的多層陶瓷區塊的放大 圖。根據該圖，一個多層陶瓷區塊11〇由四個待測裝置14〇 構成。 在此，多層陶瓷區塊110電氣連接於探針卡基板，以使 探測針13〇與印刷電路板21G的電路圖案之間形成通電。多 層陶竞區塊110通過測試探針12G接收從印刷電路板21〇傳 遞的電氣信號。 圖仆為用於說明當利用本發明的探針卡基板⑽對半 體元件進行測試時從測試探針12〇傳遞的電氣信號的路徑 圖。.從印刷電路板210接收信號的測試探針12〇將信號傳 到安裝於探針卡隸_的多層㈣區& U0的待測裝 二)。由於四個待測裝置14〇在一個基板構成，因此從測 針120至多層陶竞區塊110由一個連接線連接，電氣 待測裝[刚之前需要經過兩次分支。即，電氣信號: 疋兴測試探針120分支到每個待㈣置⑷而傳遞，而是 201203417 多層陶瓷區塊110内均等地傳遞到每個待測裝置14〇，因此 可降低有可能發生的信號偏差。這種方式由於能夠消除信號 的分支偏差，因此在檢測高頻元件時能夠降低阻抗失配。 並且’對於在多層陶瓷區塊110安裝有四個待測裝置 的本發明的探針卡基板丨⑼而言，並不僅僅限定於多層陶究 區塊110的形狀為長方形的情況（如圖4a所示），多層陶竟區 塊U0可U除了長方形之外的各種_和形狀構成探料 基板 100(如圖 圖b所不）。即，當將四個待測裝置i4〇安裝 =多層陶曼區塊U0時，可以將探針卡基板1〇〇使用於料 。而且可以將各種形狀的多層陶莞區塊u 的探針卡基板100。 x月 7上所述，雖然對本發明的具體說明是通過參照附圖的 4來細的，但是上述實施例僅對本發明的優選例進行 了說明，本發明不能理絰幺 權利ho 解為局限於上述的實施例，本發明的 __應當理解㈣請專利範圍及其等同的Μ來理解。 【圖式簡單說明】 ' 圖1a為現有的探針卡基板的平面圖； -圖113.至圖1(；.為用於^?0日3：日士1^ 號路經的圖；為用於說明現有的探針板的基板的電氣信 =為示W於說明本發明的探針卡的結構的示意圖。 a至圖外為示出根據本發明的探針卡基板的圖； 4a至圖4b為用於說明根據本發明的探針卡的電氣信 201203417 號路徑的圖。 【主要元件符號說明】 1 0 0探針卡基板 110多層陶瓷區塊 120測試探針 1 3 0為探測針 140待測裝置 200探針卡 2 1 0印刷電路板2 is a plan view showing a probe card of the present invention as a plan view of a probe card substrate according to an embodiment of the present invention, and an enlarged view of a probe card substrate according to an embodiment of the present invention. The path of the electrical signal of the probe card, Tong 201203417, is transmitted to the probe pin 13G through the probe card substrate (10), and the electrical signal transmitted to the probe pin (4) is transmitted to the pad provided on the semiconductor wafer. Here, the printed circuit board 21 is intensively mounted on a flat plate made of various greases and epoxy resins, and the circuit between the connected components is densely reduced to the resin flat plate. The surface is fixed and the board is fixed. The test probe 120 is connected to a pad provided on the printed circuit board 21 to electrically connect to a circuit pattern formed on the printed circuit board 21, thereby transmitting an electrical signal transmitted from the printed circuit board 210 to the probe. The function of the card substrate ι is that the test probe 120 is a connection portion electrically connecting the printed circuit board 21 and the probe card substrate 100, and the probe card substrate 100 is provided with a probe pin 13 〇 on the lower surface of the probe card substrate 100, and is connected The probe pin 130 is enabled to receive an electrical nickname that is transmitted through the test probe 12A. ’ The probe card substrate 100 is composed of an upper pad, a via, and a lower pad. The upper p-pad is connected to the s-type probe i 2 而 to receive an electrical signal transmitted from the printed electric cold plate 21 . The electrical signal is transmitted to the lower pad via a via called a via, thereby enabling the probe 1 30 connected to the lower pad to be tested for the semiconductor component. Here, the upper pad is a multilayer ceramic block 110 which is electrically connected to the probe pin 130 mounted on the lower pad through a via. Here, the via hole constitutes the probe card substrate 1 and is filled with a conductive material. The conductive material is made of Ag, Cu, or the like having excellent electrical properties. The filled conductive material acts to energize the plurality of wires and patterns. 201203417 The use of vias includes: electrical vias for electrically connecting vias between layers, thermal holes for thermal diffusion, and positioning for aligning the layers to the correct position during the stacking step (t〇〇 Ling), and a registrati〇n hole or the like as a reference point when printing a pattern. The device under test 1 40 has a plurality of women's clothing on the probe card substrate 根据 according to an embodiment of the present invention. Here, the device to be tested refers to a device under test that will be tested when a certain test is performed. Figure 3a is a probe card substrate ι according to an embodiment of the present invention. As shown in the figure, the ceramic blocks are arranged in a rainbow shape on the probe card substrate 100. Fig. 4a is an enlarged view of a multilayer ceramic block constituting a substrate. According to the figure, a multilayer ceramic block 11 is composed of four devices 14 to be tested. Here, the multilayer ceramic block 110 is electrically connected to the probe card substrate to form a current between the probe pin 13A and the circuit pattern of the printed circuit board 21G. The multi-layer Taojing block 110 receives electrical signals transmitted from the printed circuit board 21 through the test probe 12G. The figure is a path diagram for explaining an electrical signal transmitted from the test probe 12A when the semiconductor element is tested using the probe card substrate (10) of the present invention. The test probe 12, which receives the signal from the printed circuit board 210, transmits the signal to the device to be tested (2) mounted in the multi-layer (4) area & U0 of the probe card. Since the four devices to be tested 14 are formed on one substrate, the strobe 120 to the multi-layer Taojing block 110 are connected by a connecting wire, and the electrical device is to be tested [just before the branch is required twice). That is, the electrical signal: the Zhaoxing test probe 120 branches to each of the (four) sets (4) for transmission, but the 201203417 multilayer ceramic block 110 is equally transferred to each of the devices 14 to be tested, thereby reducing the possibility of occurrence. Signal deviation. In this way, since the branch deviation of the signal can be eliminated, the impedance mismatch can be reduced when detecting the high frequency component. And 'for the probe card substrate 丨 (9) of the present invention in which the plurality of ceramic devices 110 are mounted with the device to be tested, it is not limited to the case where the shape of the multilayer ceramic block 110 is rectangular (see FIG. 4a). As shown in the figure, the multi-layer ceramic block U0 can form a probe substrate 100 in various shapes and shapes other than a rectangle (as shown in FIG. b). That is, when four devices to be tested i4 are mounted = multi-layered Tauman block U0, the probe card substrate 1 can be used for the material. Moreover, the probe card substrate 100 of the multilayer ceramic block u of various shapes can be used. The above description of the present invention is only a mere description of the preferred embodiment of the present invention, and the present invention cannot be construed as being limited to the scope of the present invention. The above-described embodiments, the __ of the present invention should be understood (4) to understand the scope of the patent and its equivalent. [Simple diagram of the drawing] 'Fig. 1a is a plan view of a conventional probe card substrate; - Fig. 113. to Fig. 1 (;. is a diagram for the path of the 0:3: Japanese 1^; for use The electrical signal of the substrate of the conventional probe card is shown as a schematic diagram for explaining the structure of the probe card of the present invention. A to the outside is a view showing the probe card substrate according to the present invention; 4a to 4b It is a diagram for explaining the path of the electric letter 201203417 of the probe card according to the present invention. [Main element symbol description] 1 0 0 probe card substrate 110 multilayer ceramic block 120 test probe 1 3 0 is the probe pin 140 Measuring device 200 probe card 2 1 0 printed circuit board