201203281 六、發明說明： 【發明所屬之技術領域】 本發明係關於定址一陣列中之一特定裝置的方法，尤其 是定址一電子資料儲存裝置或記憶體之方法。本發明亦關 於電子記憶體結構。 【先前技術】 雖然數位記憶體之概念相當簡單’即可處於兩種資料狀 態〇、1之一者中的一單元陣列使得可個別定址此等狀態以 璜取（及寫入）資料’但是非常大規模的記憶體之實際的實 施方案並不簡單。 半導體技術已引起此等記憶體裝置之若干實施方案，其 中藉由各種物理屬性實現〇、丨狀態。例如，動態隨機存取 記憶體（DRAM)中之一電容器上之電荷；靜態隨機存取記 憶體（SRAM)中之一數位正反器的狀態；經遮罩唯讀記憶 體（ROM)之低電阻及高電阻；紫外光可擦除可程式化唯讀 記憶體（EPROM)、電可擦除且可程式化唯讀記憶體 (EEPROM)及快閃EEPR0M之浮動閘電晶體陣列。在此等 情況下，通常在藉由將數位資料確證至矩陣之列及行上而 定址的二維矩陣中而製作記憶體。藉由監測一臨限電流或 電壓以決定是否將先前被寫入之已儲存的元素解譯為一資 料位元〇或1而讀取資料。當裝置可在電源被移除時保持其 之寫入狀態時’肖記憶體為非揮發性，舉例而言如 EPROM、EEPROM、R〇m及快閃記憶體之情況。 在印刷電子器件領域中’存在許多新興且有競爭性的非 I53752.doc 201203281 揮發性記憶體候選者 且在其之最 一维矩陣係由列及行定址， 最韌早形式中，各列及各 經由-外部互遠““ 仃而要電曰曰體。必須 半導體或-矽半導俨沙 ^曰體拎供為-印刷有機 連，在 體。然而，此-定址方案需要大量互 1000χ]ΟΟΛ 冑m(Mb)的非揮發性記憶體單元中， 矩陣通常需要2〇〇〇個驅動互連。 【發明内容】 定址可藉由超過一 特定裝置的方法， 根據本發明之-第-態樣，提供-種 臨限之-信號定址之—裝置陣列中之一 該方法包括下列步驟： 提供一信號導體 體， 該陣列之該等裝置鏈接至該信號導 輸入一第一信號至該導體上之一第一部位， 然後在一所選的時間延遲之後輸入一第二信號至該導體 上之一第二部位，使得該第一信號與該第二信號在對應於 該特定裝置之該導體上的一部位處干涉，藉此產生定址在 該部位處鏈接至該導體之該特定裝置的超過一臨限的一信 號0 可能僅藉由兩個信號輸入定址附接至該導體之許多（可 能數千或數百萬個）裝置的任一者。此將與需要各裝置之 兩個導體之相交的上文提及的習知記憶體結構相對照。 定址方案依賴於在多個點處被驅動之傳輸線中固有的電 磁信號的延遲及在該傳輸線内之一既定位置（位址;)處超過 一臨限之此等信號的疊加。有利的是，可藉由適當地考慮 153752.doc 201203281 傳輸線損耗及播散而改良定址之精度及因此改良解析度及 記憶體大小。一個—維（1_D)傳輸線導體可擴展至二維（2_ D) ’從而消除對微條狀導體圖案化之需要。 本發明之此第一態樣亦提供設備，該設備包括： 可由超過一臨限之一信號定址且被一信號導體鏈接的一 裝置陣列；及 一信號產生器，其經組態以輸入一第一信號至該導體上 之一第一部位，且在一時間延遲之後，輸入一第二信號至 該導體上之一第二部位，使得該第一信號與該第二信號在 對應於一預定裝置之該導體上之一部位處干涉， 藉此產生定址在該部位處鏈接至該導體的該預定裝置之 超過一臨限的一信號。 憑藉至該信號產生器之輸入資料來預定該預定裝置。此 種輸入資料可來自該設備外部或可由該信號產生器自身產 生。 該設備可包括兩個信號導體，該裝置陣列連接在該兩個 信號導體之間，藉此以2的指數增加可定址的部位數目。 該等裝置可為記憶體單元或發光裝置。 根據本發明之一第二態樣，提供： 資料儲存設備，該資料儲存設備包括： 可定址的發光裝置之一第一陣列， 一光感測器，其回應於自該等發光裝置之任意者發射之 光而產生一信號，及 一第二區域陣列，其位於該第一陣列與該光感測器之間 153752.doc • 6 · 201203281 的光路徑中且對準該第一陣列之該等發光裝置，該等區域 之透明度對應於待儲存的資料。 一區域之透明度將判定在定址一發光裝置時該所發射之 光是否被光感測裝置拾取。此提供用於讀取儲存在該區域 中之資料（通常為二進位或「〇」.）的一機制。—區域 之透明度（或透明度之缺乏）容易受印刷方法影響，例如藉 由將油墨平版石印（offset丨ith〇 printing)至一透明基板上以 建立一非透明區域及非油墨印刷以建立一透明區域。因 此本發明之此第二態樣提供儲存資料之一廉價方式。 在較佳實施例中，亦可使用印刷（亦即，以流體形式沈 積電子活性材料)製造可定址的發光裝置之該第一陣列及 該光感測裝置。如此-來，可大體上平行於該第二區域陣 列配置其箏以建立一積層柘。 板或者，一平面型波導可饋送 光至位於該設備之一側的一感測器。 陣歹二明之一第三態樣提供一種將資料可擷取地儲存在-陣列中之方法，兮 τ π 电D亥方法包括下列步驟： 在對應於待儲存之眘 料，哕Μ / ’ 車列中的若干點處沈積材 於出之性錢得當H點被電激發時，自該點 賴於該材料是否存在於該點處，·及’· 該點發出的一電信‘測§㈣列中之任意點被電激發時自 此一方法採用沈積作為 實施或實施較廉價，尤1ί:錄機制。此方法可為易於 其他(例如，裝飾)目的之、二中其，藉由印刷之沈積已用於 153752.doc 201203281 β.該所沈積材料之屬性可為電阻，在此情況下，當被一電 β·電激發時’通過該材料之呈—電流形式的—電信號將由 該電阻判定。 體 或者，該材料可為—臨限裝s，諸如一電晶體或二& u方法可彳木用具有不同屬性的兩種或兩種以上類型材 料。當被激發時，一材料可具有相對高的電流且另一材料 可具有相對低的電流。 本發明之第二態樣及第三（f料儲存器）態樣係使用該第 一態樣之該方法有利地予以^址。在此—方案中，印刷電 子記憶體陣列與驅動及感測電路之矽之間的互連自1 Mb習 知上所需之2000個最小化至約4個互連。互連需要量及複 雜性之此一減小使此可印刷的非揮發性記憶體裝置成本非 常低且服從大規模製程。 因此，在根據該第二態樣之一裝置中^該等發光裝置可 經組態以僅在遭受超過一臨限之一輸入信號時發光。該輸 入信號可為一電壓信號》 該裝置可包括該等發光裝置連接至的—信號導體，及一 k號產生器，s亥彳§號產生器係經組態以輸入一第一信號至 該導體上之一第一部位，且在相對於該第一信號之一時間 延遲之後輸入一第一k號至該導體上之一第二部位，使得 該第一信號與該第二信號在對應於期望致動之一裝置之該 導體上之一部位處干涉。 根據（例如）上文之S亥第二非光學態樣製造之設備包括： 153752.doc 201203281 可由超過一臨限之一信號定址且被一信號導體鏈接之一 裝置陣列；及 一信號產生器，其係經組態以輸入一第一信號至該導體 上之一第一部位，且在一時間延遲之後輸入一第二信號至 該導體上之一第二部位，使得該第一信號與該第二信號在 對應於一預定裝置之該導體上之一部位處干涉， 藉此產生定址在該部位處鏈接至該導體之該預定裝置的 一信號； 其中一裝置在被定址時影響自該裝置發出的一電信號； 該設備進一步包括至少一感測器以量測該電信號。 s玄裝置可具有一電阻，使得當被一電麼定址時，呈一電 流形式之一電信號流過該裝置以被該感測器拾取，該感測 器自身可具有一臨限。 或者，該裝置可為一臨限裝置，諸如一電晶體或二極體。 可藉由使用具有可切換屬性之一裝置獲得可重寫的設 備。可藉由對該裝置施加具有大於通常用於定址該裝置之 幅度的一電信號（但是，仍然可使用如上所述之第一信號 與第二經時間延遲信號之干涉施加該電信號）達成切換。 一適當的裝置可包括硫族化物玻璃，可藉由一加熱脈衝之 轭加而使硫族化物玻璃在具有不同電阻率之兩種狀態（結 晶與非結晶）之間變化。 本發明之該第一態樣亦可應用於習知的記憶體結構，例 如界定記憶體單元之列-行架構。代替具有二極體或電晶 體，各記憶體單元自身可包括具有（例如）上文所述之種類 153752.doc 201203281 且可由超過一臨限之一信號定址並且被至少一信號導體鏈 接之記憶體裴置的一陣列，及一信號產生器，其經組態以 輸入一第一信號至一導體上之一第一部位，且在一時間延 遲之後，輸入一第二信號至一導體上之一第二部位，使得 δ亥第一 k唬與該第二信號在對應於一預定記憶體裝置之該 導體上之一部位處干涉，藉此產生定址在該部位處鏈接至 該導體的該預定裝置之超過一臨限的一信號。 【實施方式】 現在參考附圖以實例方式描述本發明之一實施例β 為了展示傳輸線可如何用於定址記憶體，首先有用地將 一傳輸線考慮為由大量（在極限上為無限）呈如圖丨上所示之 梯子形式之相同的互連電感器及電容器組成的一常數k梯 形結構。 此一結構用作為一延遲線，該結構之總延遲Td近似為.201203281 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of addressing a particular device in an array, and more particularly to a method of addressing an electronic data storage device or memory. The invention is also related to electronic memory structures. [Prior Art] Although the concept of digital memory is quite simple 'a two-array array in one of two data states, one can make these states individually addressable (and write) data' but very The actual implementation of large-scale memory is not simple. Semiconductor technology has led to several implementations of such memory devices in which the 〇 and 丨 states are achieved by various physical properties. For example, the charge on one of the capacitors in a dynamic random access memory (DRAM); the state of a digital flip-flop in a static random access memory (SRAM); the low of the masked read-only memory (ROM) Resistor and high resistance; UV erasable programmable read only memory (EPROM), electrically erasable and programmable read only memory (EEPROM) and flash EEPR0M floating gate transistor array. In such cases, the memory is typically created in a two-dimensional matrix that is addressed by confirming the digital data to the columns and rows of the matrix. The data is read by monitoring a threshold current or voltage to determine whether the previously stored stored element is interpreted as a data bit 〇 or 1. When the device can maintain its write state when the power source is removed, the read memory is non-volatile, such as in the case of EPROM, EEPROM, R〇m, and flash memory. In the field of printed electronics, there are many emerging and competitive non-I53752.doc 201203281 volatile memory candidates and in their most dimensional matrix are addressed by columns and rows, in the most tough form, columns and Each via the external - external "" 仃 仃 。 。 。 。 。 。 。. It must be semiconductor or - semi-conductive semi-conducting sand. However, in this non-volatile memory cell where the addressing scheme requires a large number of mutually χm(Mb), the matrix typically requires 2 drive interconnects. SUMMARY OF THE INVENTION Addressing can be provided by a method that exceeds a particular device, in accordance with the first aspect of the present invention, providing a threshold-signal addressing-device array comprising the steps of: providing a signal a conductor body, the devices of the array being linked to the signal to input a first signal to a first portion of the conductor, and then inputting a second signal to the conductor after a selected time delay a second portion such that the first signal and the second signal interfere at a location on the conductor corresponding to the particular device, thereby generating more than one threshold of the particular device addressed to the conductor at the location A signal 0 may be addressed to any of a number (possibly thousands or millions) of devices of the conductor by only two signal inputs. This will be in contrast to the above-mentioned conventional memory structure that requires the intersection of the two conductors of each device. The addressing scheme relies on the delay of the electromagnetic signal inherent in the transmission line driven at a plurality of points and the superposition of such signals beyond a threshold at a given location (address;) within the transmission line. Advantageously, the accuracy of the addressing and thus the resolution and memory size can be improved by properly considering the transmission line loss and dissemination of 153752.doc 201203281. A one-dimensional (1_D) transmission line conductor can be extended to two-dimensional (2_D)' to eliminate the need for patterning of microstrip conductors. This first aspect of the invention also provides an apparatus comprising: an array of devices addressable by one of more than one threshold and linked by a signal conductor; and a signal generator configured to input a Transmitting a signal to a first portion of the conductor and, after a time delay, inputting a second signal to a second portion of the conductor such that the first signal and the second signal correspond to a predetermined device Interference at a location on the conductor thereby generating a signal that is more than a threshold of the predetermined device addressed to the conductor at the location. The predetermined device is predetermined by the input data to the signal generator. Such input data may come from outside the device or may be generated by the signal generator itself. The apparatus can include two signal conductors, the array of devices being coupled between the two signal conductors, thereby increasing the number of addressable locations by an exponent of two. These devices can be memory cells or light emitting devices. According to a second aspect of the present invention, there is provided a data storage device comprising: a first array of addressable illumination devices, a light sensor responsive to any of the illumination devices Generating a signal to generate a signal, and a second array of regions located in the optical path between the first array and the photosensor 153752.doc • 6 · 201203281 and aligned with the first array The illumination device, the transparency of the regions corresponds to the data to be stored. The transparency of an area will determine whether the emitted light is picked up by the light sensing device when the illumination device is addressed. This provides a mechanism for reading the data stored in the area (usually binary or "〇".). - Transparency (or lack of transparency) of the area is susceptible to printing methods, such as by offset lithography onto a transparent substrate to create a non-transparent area and non-ink printing to create a transparent area. . Thus this second aspect of the invention provides an inexpensive means of storing data. In a preferred embodiment, the first array of addressable illumination devices and the photo sensing device can also be fabricated using printing (i.e., depositing an electronically active material in a fluid form). As such, the kite can be configured substantially parallel to the second array of regions to create a layer of stacks. A plate or a planar waveguide can feed light to a sensor located on one side of the device. A third aspect of the array of 歹二明 provides a method for storing data in an array. The 兮τ π electric D Hai method includes the following steps: In response to the caution to be stored, 哕Μ / 'car At some points in the column, when the deposited material is electrically excited, the point H depends on whether the material exists at the point, and '· a telecommunications issued by the point § (four) column When any point in the system is electrically excited, deposition from this method is cheaper to implement or implement, especially the recording mechanism. This method can be used for other (eg, decorative) purposes, and the deposition by printing has been used for 153752.doc 201203281. The properties of the deposited material can be resistance, in this case, when When the electric β is electrically excited, the electric signal passing through the current-current form of the material will be determined by the electric resistance. Alternatively, the material may be a singular s, such as a transistor or a two & u method for eucalyptus using two or more types of materials having different properties. When excited, one material can have a relatively high current and another material can have a relatively low current. The second aspect of the invention and the third (f-storage) aspect are advantageously addressed using the method of the first aspect. In this arrangement, the interconnection between the printed electronic memory array and the drive and sense circuits is minimized from the 2,000 required to 1 Mb to about 4 interconnects. This reduction in interconnect requirements and complexity makes this printable non-volatile memory device very low cost and subject to large scale processes. Thus, in a device according to the second aspect, the illumination devices can be configured to illuminate only when subjected to an input signal that exceeds one threshold. The input signal can be a voltage signal. The device can include a signal conductor to which the illumination device is coupled, and a k-factor generator configured to input a first signal to the a first portion of the conductor and inputting a first k number to a second portion of the conductor after a time delay relative to one of the first signals such that the first signal and the second signal correspond to It is desirable to actuate at one of the conductors of one of the devices to interfere. Apparatuses fabricated according to, for example, the second non-optical aspect of the above-described S-Hai include: 153752.doc 201203281 An array of devices that can be addressed by one of more than one threshold and linked by a signal conductor; and a signal generator, Is configured to input a first signal to a first portion of the conductor, and after a time delay, input a second signal to a second portion of the conductor such that the first signal and the first The second signal interferes at a location on the conductor corresponding to a predetermined device, thereby generating a signal addressed to the predetermined device at the location that is linked to the conductor; wherein a device is affected from the device when it is addressed An electrical signal; the device further comprising at least one sensor to measure the electrical signal. The s-device may have a resistor such that when it is addressed by an electrical device, an electrical signal in the form of a current flows through the device for picking up by the sensor, and the sensor itself may have a threshold. Alternatively, the device can be a threshold device such as a transistor or a diode. A rewritable device can be obtained by using a device having one of the switchable properties. Switching can be achieved by applying an electrical signal to the device having an amplitude greater than that typically used to address the device (although the electrical signal can still be applied using interference of the first signal and the second time delayed signal as described above) . A suitable apparatus can include chalcogenide glass which can be varied between two states (crystalline and amorphous) having different resistivities by the addition of a heat yoke. This first aspect of the invention can also be applied to conventional memory structures, such as a column-row architecture that defines memory cells. Instead of having a diode or a transistor, each memory cell itself may comprise a memory having, for example, the type 153752.doc 201203281 described above and which may be addressed by one of the more than one threshold and linked by at least one signal conductor An array of devices, and a signal generator configured to input a first signal to a first portion of a conductor and, after a time delay, input a second signal to one of the conductors a second portion such that the first signal and the second signal interfere at a portion of the conductor corresponding to a predetermined memory device, thereby generating the predetermined device addressed to the conductor at the portion A signal that exceeds a threshold. [Embodiment] An embodiment of the present invention will now be described by way of example with reference to the accompanying drawings. In order to illustrate how a transmission line can be used for addressing memory, it is first useful to consider a transmission line as being represented by a large number (infinite on the limit). A constant k-ladder structure consisting of the same interconnected inductor and capacitor in the form of a ladder as shown. This structure is used as a delay line, and the total delay Td of the structure is approximately .
Td=n*SQRT(L*C) 其中η為LC區段之數目。每一區段之延遲tn由下式給出. tn=SQRT(L*C) 可使用影像阻抗技術展示的是，該傳輸線之阻抗係由下式 給出： Z(cd)=SQRT(L/C)*SQRT(1-L*C*(〇2 /4) =Z0*SQRT(l-(L*C*co2 /4)) 其中Z〇=SQRT(L/C)係該線之特性阻抗。對於高於由下气终 出之一臨界頻率之頻率，該阻抗變為虛數： coc=2/SQRT(L*C) 153752.doc -10- 201203281 fc=l/(n*SQRT(L*C) 圖2中展示梯形結構元件之振幅及相位特性。當一傳輸 線與等於其之特性阻抗Z〇的一被動電阻器終接時，則該等 終接處不存在反射。 根據本發明，可參考圖3瞭解在沿著該傳輸線之一既定 點處之電壓疊加以超過一臨限，圖3為由32個梯形區段組 成之一阻尼傳輸線的一示意圖。驅動器VG1及VG2將經定 時的電壓脈衝注入該等傳輸線之相對末端，且在節點〇1至 16處使用各自的電壓計▽]^〇1至¥]^16監測結果。該電路之 特性阻抗為1 00 Ω。 圖4繪示節點16處之隨時間的輸出，該輸出在該線之邊 緣處為最壞的情況。圖5展示節點16及其他節點〇6至15之 隨時間的輸出。 圖6中進一步繪示此内容，圖6展示在一理想傳輸線之相 對末端處同時引入的兩個脈衝隨時間的進展。圖6八之實跡 線及虛跡線分別展示在t=〇及t=2時之該兩個脈衝。圖昍之 實跡線及虛跡線展示在t=3及t=4時之該兩個脈衝。圖^之 貫跡線展示在t=5時該兩個脈衝如何在沿著該線之可定義 部位（該所示實例中之中間點）處相長干涉，以建立具有明 顯大於該等個別脈衝之振幅（〇 5)的振幅（ι 〇)之一可定義尖 ♦。圖6C之虛跡線及圖犯之實跡線及虛跡線分別展示該 等脈衝在t=6、t=7及t=8時之隨後分離。 圖7再次展示脈衝進展，此時為在一有損傳輸線（藉由一 低通滤波器模型化）之情況下。在t=5時（圖7C之實線）’該 153752.doc 201203281 兩個脈衝再次在該相同中間點處相長干涉，雖然具備且有 一較低振幅（約0.8)及較寬且不太精確的一尖峰。儘管如 此’該模擬繪示當恰當地終接一傳輸線時，可在兩個埠處 驅動該傳輸線以建立一經充分良好地定義之疊加的臨限脈 衝’即使在該線被電感器之内部電阻阻尼之時。在圖7之 該實例中’一適當的臨限可為介於〇.8與〇 5之間的中間 值，比如0.65。 由此可見，本發明適用於通常具有高於習知的銅之電阻 率的印刷電子器件中之實施方案。與具有近似為25_1〇〇 ιηΩ平方之一表面電阻率之印刷導體（例如，聚合物導體， 諸如PEDOT)相比，條狀線及微條狀線之印刷電路板（peg) 上之典型的6 οζ銅跡線具有近似為】.〇 平方之一表面電 阻。 然而，為確保臨限偵測可靠，該傳輸線之總跡線阻尼電 阻較佳地應小於該特性阻抗。 该傳輸線之所要的解析度決定發射至該傳輸線中之脈衝 之間的必要的最小延遲。該所要的解析度亦有效地將類比 傳輸線量化為該等模擬之該常數1^梯形結構。該所要的解 析度進步影響發射至該傳輸線中之脈衝的寬度，以確保 僅疋址。亥線上之一部位，該臨限脈衝之經重新建構的寬度 在時域中較佳地應小於經最小解析之梯形區段的延遲。 在6玄傳輸線中之電容的介電質部分為半導體（如在下文 榀述之印刷圮憶體裝置中）的情況下，此將為有損耗且將 導致較㈣率下之正常播散。該導體跡線中之集膚效應亦 I53752.doc -12· 201203281 將導致梯形網路之内_*β φ jα μ # HP電感部分的播散。此等播散效 表示較高的頻率遭受較短 〜 _ J、慫乙蒽心。如圖8令所管 7對於具有播散之一無損線(藉由一全通濾波器模型 化），此在t=5時（圖㈣之實線）引㈣據兩個正常時間單 位之-寬脈衝，從而引起較差的時間及部位精度。 在實際應用中，可藉由網路分析及傅立葉方法分析且校 正此等效應。網路分析允許識別實際的傳輸線值，而傅立 葉分析將給出對處理資料之最佳方式的洞L，藉由 濾波及預強調方式以在具有處於臨限至底限或雜訊位準之 經改良的信號的臨限位址處獲得時域中之非常尖銳的脈衝 波形有限7〇素方法亦.可用於分析且校正延遲及播散。圖 9展示具有中等播散及某損耗之一實際線中之經模型化的 脈衝進展’但疋其中在藉由一分步預強調展示之情況下， 已藉由在驅動該線之前預等化該等脈衝而達成時間及脈衝 形狀之良好的精度。此措施使時間精度與脈衝振幅兩者基 本上回到圖6之該理想條件。 圖10係本發明之一第 維實施例的一示意繪示。驅動 器175、180在兩個末端處對傳輸線17〇供應信號。如上文 所說明，該等各自信號之間的延遲係經選取使得該等信號 在/σ著6亥線之一特定點處相遇（例如，圖1 〇中之點P)且相 長干涉。所得的信號超過一臨限，藉此致動重合部位處之 裝置，例如致動該線170與一接地線190之間的一記憶體單 元185。為了提供一個1 Mb記憶體定址方案，如在上文之 该等不意模擬中評估之此一傳輪線需解析一百萬個部位。 153752.doc •13- 201203281 圖11係利用在深度（Z)方向上互相隔開之水平（X)傳輸線 200及垂直（Y)傳輸線210之兩個陣列的另一實施例的—示 意繪示。驅動器220、225自任一末端共同驅動該等水平傳 輸線200，而驅動器230、235自任一末端共同驅動該等垂 直傳輸線210。施加至該等X線之信號具有與施加至該等γ 線之信號相反的符號’使得在該等X線中之信號疊加與該 專Y線中之信號疊加重合的情況下，所得之電位差超過一 預定臨限且致動該重合部位處的裝置（例如，致動一記憶 體單元）。 對於一既定的tx及ty驅動延遲之定址沿著具有由一區段 之延遲tn分離的一連串事件的一對角線發生。可藉由閘控 感測放大器或將該整串事件儲存在石夕控制器ic上之一移位 暫存器中而讀取一特定的部位。 圖12之裝置具有優點：無需導體層之條狀線圖案化，該 裝置替代地具有一矩形（在此情況下為正方形）傳輸層或面 板250❶二維電位（更恰當的電磁）「波」係經由墊％^「發 射」至該層250中。該層亦在全部四側255上與其之特性阻 抗終接以最小化邊緣反射。 可藉由通常使用電磁信號之傅立葉及有限元素方法的計 算來實現臨限電壓在該時域中之最佳的波疊加而最佳化該 等信號輸入墊260之形狀及位置。 在上文引言中論述之該等記憶體裝置之許多者中，可將 該等記憶體元件考慮為小信號二極體。具有下列典型的局 部值及電感值的圖13之電路可在時域中模擬一小信號二極 I53752.doc • 14. 201203281 體之短時間脈衝回應： Z〇=SQRT(L/C)=50 Ω L=10 nH C=L/Z(^2=4 pF tn=SQRT(L*C)=200 ps fc=l/pi*tn)=1.59 Ghz 圖14中展示該電路之對應的時序圖。將見到的是，臨限 電流回應（AM1)比電壓（VM1)更尖銳，從而建議臨限電流 感測係對一局部電壓刺激之最合適的量測。 此等電流感測機制將在發光二極體、有機發光材料及有 機半導體中找到，且圖15展示根據本發明之一第二態樣且 採用此一材料之一記憶體結構的一實施例。 一基板3 00(例如PET或經塗佈之板）具有一第一陰極層 3 10(例如，具有一金屬導電材料，諸如銦錫氧化物 (ιτο))、發光材料（例如，有機（〇LED)材料，諸如小分子 或聚合物）之一第二層320及一第三透明的陽極層33〇(例如 一孔注入材料，諸如聚伸乙基二氧噻吩（pED〇T))。 層310、320、330界定一發光裝置36〇 ,可藉由使用上文 概述之該機制使該發光裝置360之任意區域或像素遭受大 於某一臨限之一電壓而使該發光裝置36〇之任意區域或像 素受激發以發射光。圖16中展示對應的雙重埠傳輸線定址 示意圖，該陽極層330係連接至信號驅動器34〇、35〇，且 該陰極層3 10係連接至接地。 上文中，該發光裝置360位於一光感測裝置4〇〇處該光 153752.doc -15- 201203281 感測裝置400係由失在導電透明聚合物（例如，pED〇T)之 一下層420與一上金屬導電層43〇之間的一光伏聚合物層 41 0組成。 分別具有不透明區域或像素38〇、382及透明區域或像素 390、392之另一資料層37〇位於該發射裝置36〇與該感測裝 置400之間。可藉由油墨印刷提供該等區域。 當該發射裝置360之一特定區域38〇,、382,、39〇f、392, 受激發以發射光時’該資料層之該等對應的區域38〇、 3 82、390、392的不透明/透明狀態判定感測層4〇〇是否接 收該光。此提供用於讀取該資料層之任意特定區域之狀態 的一機制。由此可見’可藉由將不透明區域之一圖案印刷 至另一透明層上而將二進位資料可擷取地儲存在層37〇 中〇 一微複製拓樸325可有利地併入該pLED/OLED層320與 透明陽極層330之作用介面中以增加局部電場以增強光子 發射。該微複製之尺度一般小於記憶體單元之尺度，且因 此不需要對齊。 圖17展示圖15之該裝置的一替代實施例，其中該光感測 層由將透過該資料層370之任意光引導至在450處示意指示 之一％端石夕光债測器的一光學光導440代替。圖18之該示 意圖中所繪示之該定址機制仍然與先前實施例中之定址機 制相同。 上文關於圖15及圖17論述之該光學記憶體構造的一優點 在於一光感測機制有效地隔離該傳輸線定址方案中之脈衝 153752.doc -16- 201203281 電流產生的電雜訊。 該光學結構之另一優點在於其有助於擴展該方法以建立 具有及不具有記憶體之可變的電子顯示器，該記憶體具備 通常具有與纪憶體單元相同的像素數目之一基本上不變的 實體結構。 圖19繪不不具有記憶體之一顯示器結構，與圖15及圖17 之該等實施例共同的元件係由共同的參考數字指定。省略 上文提及之實施例的該等光㈣器層及電路，且在該記憶 體層370上印刷一規則的圖案5〇〇以定義像素51〇〇再次使 用如圖2G巾所％示之該傳輸線定址方案定址該顯示器。藉 由以高於人類閃爍偵測之一速率（通常為5〇 Ηζΐ7〇 Ηζ)持 續地刷新該像素資料使該顯示器保持工作。 此一系統比現代平板顯示器更接近一陰極射線管（crt) 系統，此係在一既定時間定址一單一部位之故，如同一 CRT之電子束。藉由改變在一特定像素部位處之定址停留 時間而獲得灰階。該所示實施例係、單色，但是可藉由劃分 紅、綠及藍像素而容易地將該結構轉換為彩色。百萬像素 灰階顯示器之顯示結構可能需要大規模的位址刷新。 可在-早-結構上同B夺容易地容納淺資訊内容顯示器與 記憶體。在此一實施例中’頂層波導係經組態以允許檢視 與光收集兩者之一雙重目的、降低的效率模式起作用。 然而’圖2U會示—替代的非光學記憶體單元結構，圖22 展丁對應的疋址不意圖β與先前實施例共同之特徵係由共 同的參考數字指示。 153752.doc •17· 201203281 在此實施例中，OLED臨限機構係由具有有機半導體電 晶體或二極體元件610之一層600代替。例如，McCuU〇ch 等人之Nature Materials第5卷第328至333頁（2〇〇6年4月）及 Berggren 等人之 Nature Materials 第 6 卷第 3 至 5 頁（2〇〇7 年 1 月）中論述此等元件。如由不同的陰影612、614指示，對 應於二進位「0」及「丨」之不同類型的元件係用於在該層 600中記錄資料。此等非光學方法依賴於流過臨限裝置（諸 如電晶體及二極體或可將電阻製成可變之材料）之電流的 相對量。 在一實施例中，一主動二極體或電晶體（如已知具有在 被定址時引起一相對高的電流之一低電阻）可提供一類型 兀件（例如，對應於「1」）。另一類型元件（例如，對應於 「〇」）可具有在被定址時引起一相對低的電流之一較高的 臨限或根本無法被圖案化。 -玄疋址方案可用於改變該層中之一特定的部位處之材料 的相（phase)。一種適當的材料係硫族化物玻璃，其在被施 加熱之後在具有不同電阻率之兩種狀態（晶體及非晶體）之 間變化。一較大的電壓脈衝可用於局部加熱基板上之一特 疋的。卩位且改變其之狀態，一較低位準的電壓脈衝用於讀 取4。卩位。此一配置允許該記憶體成為可重寫。一類似方 案可用於上文論述之該等光學配置中，—相變化引起不同 光學屬性，例如接近透明至接近不透明，而非相對高的電 阻至相對低的電阻。 該感測機制使用圖20之差動方案，其中一已致動的臨限 153752.doc 201203281 機構610使一差動傳輸線中之電流失衡《此失衡將依賴於 已沈積在被定址之該部位處的元件類型而不同。一差動放 大器650用於偵測以便使共模電雜訊最小。 在操作中’該印刷記憶體裝置（諸如聚合物二極體及電 晶體）可能過於緩慢以至於不能在高記憶體解析度之窄脈 衝寬度下做出回應。以短脈衝重複地激勵一已定址的部位 將具有擴展慢速裝置所察覺之脈衝寬度的效果，從而在該 臨限部位處有效地建立一準駐波。 雖然該定址方案在本質上為類比，但是可藉由以小於該 時域中之典型的脈衝寬度的一規模圖案化該等記憶體單元 而提供數位域之某一精度。此將確保在該臨限裝置之整個 寬度上經受完全加強的電壓脈衝（由該兩個信號之干涉引 起）’從而確保最大輸出。感測設備可經設定以僅對此最 大輸出做出回應，藉此降低對該系統中之任意其他的雜訊 之靈敏度。 使用二維傳輸線定址方案之光學記憶體結構亦具有一完 王同質之PLED或OLED結構的優點，完全同質之pled或 OLED結構具有藉由使用習知的油墨及印刷技術對應於〇及 1印刷不透明及透明的圖案所完成之非揮發性資料記憶體 圖案化。此光學方法有助於捲軸式薄膜之低成本高速的製 造’稍後可將其等轉換至可印刷的紙卡或PET基板上。此 將與係屬圖19及圖20中所揭示之該種類的非光學記憶體結 構相對照，其中需要藉由選擇性地印刷有機半導體而在顯 微鏡下將該有機半導體圖案化至非揮發性資料陣列記憶體 153752.doc •19· 201203281 中。此需要以電方式寫該記憶體之一方案，從而導致需要 進一步的顯微鏡下圖案化之進一步的複雜性。 圖ίο之二維結構亦有助於藉由薄膜捲轴式製造技術進行 製造。當以圖13及圖15之該等光學記憶體結構實施時，可 將製造分解為三個模組程序： 程序1:結構之汞齊層的捲軸式薄膜製造 步驟a.聚合物（pled)或其他的有機（OLED)發光作用層 320位於該金屬化或導電的微複製聚合物膜31.〇上。 步驟b.該光伏層41〇或波導層44〇位於該金屬化或導電 聚合物膜330上。 程序2:捲軸式轉換至撓性傳輸面板 步驟a.自程序1的步驟a剪切積層板以形成一面板250， 且將其接合至一基板300 ,例如一可印刷的基板，諸如 紙、板或PET。 步驟b，對於各面板25〇，確保恰當地終接該傳輸線，例 如藉由在其之邊緣255處印刷特性終接阻抗Zq。亦可印刷 用於積體電路之連接的經最佳化之驅動終端260及墊。 步驟e.拾取積體電路且將其置於該等連接墊上。 程序3:捲軸式之最後裝置製造 步驟a.印刷資料層370或像素圖案500、51〇。此非揮發 吐5己1體圖案可包含誤差校正、冗餘及對齊資料位元。可 使用‘準的印刷裝備，包含印刷機、專業的墨噴式印表 機田射印表機及個人桌上型電腦喷墨印表機。然而，習 知的印刷機可提供最高速度的製造。墨喷式印刷雖然較 153752.doc 201203281 慢 但是會產生較精細的解析度及因 度 此較高的記憶體密 二.然後將來自先前步驟之臨限層及偵測器層㈣ 至貧料層以製成非揮發性記憶體裝置。因為無需對齊，故 可在普通的印刷設備中高效地執行該程序。 " 以上方法允許以高生產率A量製造適用於錯存可處理的 工業及消費性電子產品之高資訊内容的低成本裝置。 可藉由包含卡基板上之薄電池及音訊電路及致動器而建 立一完整的視聽裝置。若將射頻通信包含於石夕冗中，則該 裝置可作為一 1%資訊内容儲存裝置。 在上文所述之料實施财，對臨限事件之定址及感測 方便地在可㈣♦積體電路中之45奈米至9G奈米尺度下實 施。對照來看，藉由在具有約10微米至50微米之可印刷的 線寬度的1G平方毫米至⑽平方毫米的典型區域上沈積（用 通俗語為「印刷」）電子活性流體而方便地製造該等傳輸 線及相關的記憶體結構。 然而，本發明之定址方案同樣可應用於(例如，在石夕上 的）亞微米實施方案。在此一尺度下’時序將為較緊且解 析度因此較低’例如各二維的Χ、γ面板中之1〇至1〇〇部位 提供處於⑽位元至1〇〇〇〇位元之範圍中的記憶體解析度。 微米尺度石夕亦可能存在’非晶石夕係沈積在換性基板（諸 如PET或不錄鋼)上以製造主動f子器件材料。 該定址方案亦可與每一記憶體單元採用二極體或電晶體 之習知的X-Y(列-行）架構組合使L，習知的圖案化 153752.doc -21 · 201203281 可用於將該記憶體粗粒化至處於百萬及十億字級下的單元 中，且本發明之定址方案可用於將該等單元進一步細粒化 至每字千位元級。 在一實施例中，χ_γ矩陣圖案化提供經粗粒化的二維單 兀，然後在XY平面中進一步解析該等單元而無需進一步 圓案化。例如，在】00奈米線寬節點處，以局部驅動及感 測電晶體（例如，如同一 TFT LCD)圖案化i微米χ㈣米之單 疋，然後使用本發明之定址方案將此等丨微米“微米單元 之各者向下解析至約100至1〇〇〇個記憶體部位，且因此無 需進一步圖案化。 … 或者，該定址方案可應用於垂直於習知架構之χ γ矩陣 的—第三Ζ維度中。一對應的讀寫程序可採用兩個臨限位 準作為每一CD的讀/寫。 【圖式簡單說明】 圖1A及圖1B係一傳輸線之圖解視圖； 圓2係繪示圖以及圖1B之該傳輸線之振幅及相位特性的 一圖表； 圖3係另一傳輸線之一示意圖； 圖4係繪示圖3之節點16之輸出隨時間變動的一圖表； 圖5緣示郎點6至16處之輸出隨時間的變動； 圖6繪示脈衝沿著一理想傳輸線之進展； 圖7繪示脈衝沿著一有損傳輸線之進展； 圖8繪示脈衝沿著具有播散之一無損耗線的進展； 圖9繪示脈衝沿著具有某—播散但是具有脈衝預等化之 153752.doc -22· 201203281 一線路的進展； 圖ίο係本發明之—第一實施例的一示意繪示； 圖11係本發明之—第二實施例的一示意圖； 圖12係本發明之一第三實施例的一示意圖； 圖13係繪示—小信號二極體之回應的一電路圖 圖14展示圖13之該電路之電流及時間的變動； 圖15係本發明之一第四實施例的一截面圖’ 圖16係同等於圖15之傳輸線的一示意圖； 圖17係本發明之一第五實施例的一截面圖； 圖1 8係同等於圖17之傳輸線的一示意圖’ 圖19係本發明之一第六實施例的一截面圖； 圖20係同等於圖19之傳輸線的一示意圖； 圖21係本發明之一第七實施例的一截面圖； 【主要元件符號說明】 圖22係同等於圖21之傳輸線的一示意圖。 170 傳輸線 175 驅動器 180 驅動器 185 記憶體單元 190 接地線 200 水平（X)傳輪線 210 垂直傳輸線 220 驅動器 225 驅動器 153752.doc 201203281 230 驅動器 235 驅動器 250 傳輸層或面板 255 四側 260 墊 300 基板 310 第一陰極層 320 第二層 325 微複製拓樸 330 第三透明的陽極層 340 信號驅動器 350 信號驅動器 360 發光裝置 370 另一資料層 380 不透明區域或像素 380' 不透明區域或像素 382 不透明區域或像素 382' 不透明區域或像素 390 透明區域或像素 390' 透明區域或像素 392 透明區域或像素 392' 透明區域或像素 400 光感測裝置 410 光伏聚合物層 153752.doc -24- 201203281 420 下層 430 上金屬導電層 440 光學光導 450 遠端矽光偵測器 500 規則的圖案 510 像素 600 層 610 有機半導體電晶體或二極體元件 650 差動放大器 153752.doc -25-Td = n * SQRT (L * C) where η is the number of LC segments. The delay tn of each segment is given by: tn=SQRT(L*C) The image impedance technique can be used to show that the impedance of the transmission line is given by: Z(cd)=SQRT(L/ C)*SQRT(1-L*C*(〇2 /4) =Z0*SQRT(l-(L*C*co2 /4)) where Z〇=SQRT(L/C) is the characteristic impedance of the line For frequencies above one critical frequency from the end of the air, the impedance becomes an imaginary number: coc=2/SQRT(L*C) 153752.doc -10- 201203281 fc=l/(n*SQRT(L* C) The amplitude and phase characteristics of the ladder structure elements are shown in Figure 2. When a transmission line is terminated with a passive resistor equal to its characteristic impedance Z, there is no reflection at the terminations. Referring to Figure 3, it is understood that the voltage superimposed at a predetermined point along one of the transmission lines exceeds a threshold, and Figure 3 is a schematic diagram of one of the 32 trapezoidal sections damped transmission lines. The drivers VG1 and VG2 will be timed. Pulses are injected into the opposite ends of the transmission lines, and the results are monitored at nodes 至1 to 16 using respective voltmeters 〇1 to ]1. The characteristic impedance of the circuit is 100 Ω. 16 places to lose over time The output is the worst case at the edge of the line. Figure 5 shows the output of node 16 and other nodes 〇6 to 15 over time. This is further illustrated in Figure 6, which shows an ideal transmission line. The two pulses simultaneously introduced at the opposite end progress with time. The real trace and the imaginary trace of Fig. 6 show the two pulses at t=〇 and t=2, respectively. The traces show the two pulses at t=3 and t=4. The traces of Figure 2 show how the two pulses are at a definable location along the line at t=5 (in the example shown) At the midpoint of the constructive interference, one of the amplitudes (ι 〇) that is significantly larger than the amplitude of the individual pulses (〇5) can define the tip ♦. The virtual trace of Figure 6C and the real trace of the graph And the imaginary traces respectively show the subsequent separation of the pulses at t=6, t=7 and t=8. Figure 7 again shows the pulse progression, at this time a lossy transmission line (by a low-pass filter model) In the case of t=5 (solid line in Fig. 7C) 'The 153752.doc 201203281 two pulses again at the same intermediate point Although it has and has a lower amplitude (about 0.8) and a wider and less accurate spike. However, the simulation shows that when a transmission line is properly terminated, the transmission line can be driven at two turns to establish Once fully defined, the superimposed threshold pulse 'even when the line is damped by the internal resistance of the inductor. In the example of Figure 7, 'a suitable threshold can be between 〇.8 and 〇5 The intermediate value between, such as 0.65. Thus, it can be seen that the present invention is applicable to embodiments in printed electronic devices that typically have higher resistivities than conventional copper. A typical printed circuit board (peg) of strip lines and microstrip lines compared to a printed conductor having a surface resistivity of approximately 25_1 〇〇ιηΩ square (for example, a polymer conductor such as PEDOT) The οζ copper trace has a surface resistance of approximately 〇. square. However, to ensure reliable detection of the threshold, the total trace damping resistance of the transmission line should preferably be less than the characteristic impedance. The desired resolution of the transmission line determines the minimum delay necessary between the pulses transmitted into the transmission line. The desired resolution also effectively quantizes the analog transmission line to the constant 1^ ladder structure of the simulations. The desired degree of resolution affects the width of the pulses transmitted into the transmission line to ensure only the address. At one location on the line, the reconstructed width of the threshold pulse should preferably be less than the delay of the least resolved trapezoidal segment in the time domain. In the case where the dielectric portion of the capacitor in the 6 myn transmission line is a semiconductor (as in the printed memory device described below), this will be lossy and will result in normal dissemination at a higher (four) rate. The skin effect in this conductor trace is also caused by the spread of the _*β φ jα μ # HP inductive part of the ladder network. These broadcast effects indicate that the higher frequencies suffer from shorter ~ _ J, 怂 蒽 蒽. As shown in Fig. 8, the tube 7 has a lossless line with a spread (modeled by an all-pass filter), which is at t=5 (solid line of the figure (4)) (4) according to the two normal time units - wide Pulses, resulting in poor time and location accuracy. In practical applications, these effects can be analyzed and corrected by network analysis and Fourier methods. Network analysis allows the identification of actual transmission line values, while Fourier analysis will give the hole L the best way to process the data, by filtering and pre-emphasizing the way to have a threshold to the threshold or noise level. A very sharp pulse waveform in the time domain is obtained at the threshold address of the improved signal. The 〇7 〇 method can also be used to analyze and correct delay and spread. Figure 9 shows the modeled pulse progression in an actual line with moderate spread and loss, but where it has been pre-equisized before driving the line, with a step-by-step pre-emphasis display These pulses achieve good accuracy in time and pulse shape. This measure essentially returns both the time accuracy and the pulse amplitude back to the ideal condition of Figure 6. Figure 10 is a schematic illustration of a first dimensional embodiment of the present invention. The drivers 175, 180 supply signals to the transmission line 17A at both ends. As explained above, the delay between the respective signals is chosen such that the signals meet at a particular point of / σ at 6 ray (e.g., point P in Figure 1) and constructively interfere. The resulting signal exceeds a threshold to actuate the means at the coincident portion, such as a memory unit 185 between the line 170 and a ground line 190. In order to provide a 1 Mb memory addressing scheme, one of the transmission lines as assessed in the above-mentioned unintended simulations needs to resolve one million locations. 153752.doc • 13- 201203281 FIG. 11 is a schematic illustration of another embodiment of two arrays of horizontal (X) transmission lines 200 and vertical (Y) transmission lines 210 separated from each other in the depth (Z) direction. The drivers 220, 225 drive the horizontal transmission lines 200 together from either end, and the drivers 230, 235 collectively drive the vertical transmission lines 210 from either end. The signals applied to the X lines have a sign 'opposite to the signal applied to the gamma lines' such that when the signal superpositions in the X lines overlap with the signals in the dedicated Y line, the resulting potential difference exceeds A predetermined threshold and actuating the device at the coincident site (eg, actuating a memory unit). Addressing for a given tx and ty drive delay occurs along a pair of angular lines having a series of events separated by a segment of delay tn. A particular location can be read by gating the sense amplifier or storing the entire sequence of events in a shift register on the Shishi controller ic. The device of Figure 12 has the advantage of not requiring stripline patterning of the conductor layer, which device instead has a rectangular (square in this case) transport layer or panel 250" two-dimensional potential (more appropriate electromagnetic) "wave" system It is "emitted" into the layer 250 via the pad %^. This layer is also terminated on all four sides 255 with its characteristic impedance to minimize edge reflection. The shape and position of the signal input pads 260 can be optimized by calculating the Fourier and finite element methods of the electromagnetic signals to achieve optimal wave superposition of the threshold voltages in the time domain. In many of the memory devices discussed in the introduction above, the memory elements can be considered small signal diodes. The circuit of Figure 13 with the following typical local and inductance values can simulate a small signal dipole in the time domain. I53752.doc • 14. 201203281 Short-term impulse response of the body: Z〇=SQRT(L/C)=50 Ω L = 10 nH C = L / Z (^2 = 4 pF tn = SQRT (L * C) = 200 ps fc = l / pi * tn) = 1.59 Ghz The corresponding timing diagram of the circuit is shown in FIG. It will be seen that the threshold current response (AM1) is sharper than the voltage (VM1), suggesting that the threshold current sensing is the most appropriate measurement for a local voltage stimulus. Such current sensing mechanisms will be found in light emitting diodes, organic light emitting materials, and organic semiconductors, and Figure 15 shows an embodiment of a memory structure in accordance with a second aspect of the present invention and employing such a material. A substrate 300 (eg, PET or coated board) has a first cathode layer 3 10 (eg, having a metallic conductive material, such as indium tin oxide (ιτο)), a luminescent material (eg, organic (〇LED) a second layer 320 of a material, such as a small molecule or a polymer, and a third transparent anode layer 33 (eg, a hole injecting material such as polyethylidene dioxythiophene (pED〇T)). The layers 310, 320, 330 define a illuminating device 36, which can be caused by subjecting any region or pixel of the illuminating device 360 to a voltage greater than a certain threshold by using the mechanism outlined above. Any area or pixel is excited to emit light. A corresponding dual-tank transmission line addressing schematic is shown in Figure 16, which is connected to signal drivers 34A, 35A, and the cathode layer 310 is connected to ground. In the above, the light-emitting device 360 is located at a light-sensing device 4, the light 153752.doc -15-201203281, the sensing device 400 is lost by one of the conductive transparent polymer (for example, pED〇T) 420 and A photovoltaic polymer layer 41 0 is formed between the metal conductive layers 43A. Another data layer 37 having opaque regions or pixels 38A, 382 and transparent regions or pixels 390, 392, respectively, is located between the transmitting device 36A and the sensing device 400. These areas can be provided by ink printing. When a particular region 38〇, 382, 39〇f, 392 of the transmitting device 360 is excited to emit light, the opaqueness of the corresponding regions 38〇, 3 82, 390, 392 of the data layer is The transparent state determines whether the sensing layer 4 接收 receives the light. This provides a mechanism for reading the status of any particular region of the data layer. It can be seen that the binary data can be retrieved in the layer 37 by printing one of the opaque regions onto the other transparent layer. The micro-replication topology 325 can be advantageously incorporated into the pLED/ The interaction between the OLED layer 320 and the transparent anode layer 330 increases the local electric field to enhance photon emission. The scale of the microreplication is generally smaller than the scale of the memory unit and therefore does not require alignment. 17 shows an alternative embodiment of the apparatus of FIG. 15, wherein the light sensing layer is directed by an optical light that is transmitted through the data layer 370 to an optical source that is indicative of one of the ends of the Shishiguang debt detector at 450. Light guide 440 is substituted. The addressing mechanism illustrated in the schematic of Figure 18 is still the same as the addressing mechanism of the previous embodiment. One advantage of the optical memory configuration discussed above with respect to Figures 15 and 17 is that a light sensing mechanism effectively isolates electrical noise generated by the current 153752.doc -16 - 201203281 current in the transmission line addressing scheme. Another advantage of the optical structure is that it facilitates the extension of the method to create a variable electronic display with and without memory, the memory having substantially the same number of pixels as the memory unit. The physical structure of the change. Figure 19 depicts a display structure that does not have a memory. Elements common to the embodiments of Figures 15 and 17 are designated by a common reference numeral. The light (four) layers and circuits of the above-mentioned embodiments are omitted, and a regular pattern 5 is printed on the memory layer 370 to define the pixels 51, which are again used as shown in FIG. The transmission line addressing scheme addresses the display. The display remains operational by continuously refreshing the pixel data at a rate higher than human flicker detection (typically 5 〇 7 〇 Ηζ). This system is closer to a cathode ray tube (crt) system than a modern flat panel display, which is addressed to a single location at a given time, such as an electron beam of the same CRT. The gray scale is obtained by changing the address dwell time at a particular pixel location. The illustrated embodiment is monochromatic, but can be easily converted to color by dividing red, green, and blue pixels. The display structure of a megapixel grayscale display may require large-scale address refresh. The information content display and memory can be easily accommodated in the early-frame structure. In this embodiment the top layer waveguide is configured to allow for a dual purpose, reduced efficiency mode for both viewing and light collection to function. However, Fig. 2U shows an alternative non-optical memory cell structure. Fig. 22 shows the corresponding address of the display. The features common to the previous embodiment are indicated by the common reference numerals. 153752.doc • 17· 201203281 In this embodiment, the OLED threshold mechanism is replaced by a layer 600 having an organic semiconductor transistor or diode element 610. For example, McCuU〇ch et al., Nature Materials, Vol. 5, pp. 328-333 (April 2-6) and Berggren et al., Nature Materials, Volume 6, pages 3 to 5 (January 2, 2007) These elements are discussed in ). As indicated by the different shades 612, 614, different types of components corresponding to binary "0" and "丨" are used to record data in the layer 600. These non-optical methods rely on the relative amount of current flowing through a threshold device such as a transistor and a diode or a material that can make the resistor a variable material. In one embodiment, an active diode or transistor (as is known to have a low resistance which results in a relatively high current when addressed) may provide a type of device (e.g., corresponding to "1"). Another type of component (e.g., corresponding to "〇") can have a threshold that causes a relatively low current to be addressed when addressed, or cannot be patterned at all. The Xuanji site scheme can be used to change the phase of the material at a particular location in the layer. One suitable material is chalcogenide glass which varies between two states (crystalline and amorphous) having different resistivities after being heated. A larger voltage pulse can be used to locally heat one of the substrates. The clamp is changed and its state is changed, and a lower level voltage pulse is used to read 4.卩 position. This configuration allows the memory to become rewritable. A similar approach can be used in the optical configurations discussed above - the phase change causes different optical properties, such as near transparent to near opaque, rather than relatively high resistance to relatively low resistance. The sensing mechanism uses the differential scheme of Figure 20, where an activated threshold 153752.doc 201203281 mechanism 610 unbalances the current in a differential transmission line. "This imbalance will depend on the location that has been deposited at the location being addressed. The type of component varies. A differential amplifier 650 is used for detection to minimize common mode electrical noise. In operation, the print memory device (such as polymer diodes and transistors) may be too slow to respond to a narrow pulse width of high memory resolution. Repeated excitation of an addressed portion with a short pulse will have the effect of extending the perceived pulse width of the slow device, thereby effectively establishing a quasi-stationary wave at the threshold portion. While the addressing scheme is analogous in nature, some precision of the digital domain can be provided by patterning the memory cells at a scale that is less than the typical pulse width in the time domain. This will ensure that a fully reinforced voltage pulse (caused by the interference of the two signals) is experienced across the entire width of the threshold device to ensure maximum output. The sensing device can be set to respond only to this maximum output, thereby reducing the sensitivity of any other noise in the system. The optical memory structure using the two-dimensional transmission line addressing scheme also has the advantages of a homogeneous PLED or OLED structure, and the completely homogeneous pled or OLED structure has opacity corresponding to 〇 and 1 by using conventional ink and printing techniques. Non-volatile data memory patterning by transparent patterns. This optical method facilitates the low cost, high speed manufacturing of the roll film, which can later be converted to a printable paper card or PET substrate. This will be in contrast to the non-optical memory structure of the type disclosed in Figures 19 and 20, wherein the organic semiconductor needs to be patterned under the microscope to non-volatile data by selective printing of the organic semiconductor. Array memory 153752.doc •19· 201203281. This requires an electrical scheme to write one of the memories, resulting in further complexity requiring further microscopic patterning. The two-dimensional structure of Figure ίο also facilitates fabrication by film roll manufacturing techniques. When implemented in the optical memory structures of Figures 13 and 15, the fabrication can be broken down into three modular procedures: Procedure 1: Structure of the amalgamed roll film fabrication step a. Polymer (pled) or Other organic (OLED) light-emitting layers 320 are located on the metallized or conductive microreplicated polymer film 31. Step b. The photovoltaic layer 41 or the waveguide layer 44 is on the metallized or conductive polymer film 330. Procedure 2: Reel-to-Flex Transfer Panel Step a. Cut the laminate from step a of procedure 1 to form a panel 250 and bond it to a substrate 300, such as a printable substrate, such as paper, board Or PET. Step b, for each panel 25, ensures that the transmission line is properly terminated, for example by printing a characteristic termination impedance Zq at its edge 255. Optimized drive terminals 260 and pads for the connection of integrated circuits can also be printed. Step e. Pick up the integrated circuit and place it on the connection pads. Procedure 3: Roll-on final device fabrication Step a. Print material layer 370 or pixel pattern 500, 51〇. This non-volatile vomiting pattern can include error correction, redundancy, and alignment data bits. It can use 'standard printing equipment, including printing machine, professional inkjet printer field printer and personal desktop inkjet printer. However, conventional printers provide the highest speed manufacturing. Although inkjet printing is slower than 153752.doc 201203281, it will produce finer resolution and higher memory density. Then, the threshold layer and detector layer (4) from the previous step will be used to the poor layer. To make a non-volatile memory device. Since alignment is not required, the program can be efficiently executed in a general printing apparatus. " The above method allows for the manufacture of low-cost devices for high-information content for industrial and consumer electronics that can be handled in a high-productivity A quantity. A complete audiovisual device can be built by including a thin battery and audio circuitry and actuators on the card substrate. If RF communication is included in Shi Xixiao, the device can be used as a 1% information content storage device. In the above-mentioned materials implementation, the location and sensing of the threshold events are conveniently implemented at the 45 nm to 9 G nanometer scale in the (4) integrated circuits. In contrast, it is convenient to manufacture by depositing (in the common language "printing") an electronically active fluid over a typical area of 1 G square millimeter to (10) square millimeter having a printable line width of about 10 micrometers to 50 micrometers. Equal transmission lines and associated memory structures. However, the addressing scheme of the present invention is equally applicable to sub-micron implementations (e.g., on Shi Xi). At this scale, the 'timing will be tighter and the resolution is lower', for example, the 1〇 to 1〇〇 part of each two-dimensional Χ, γ panel is provided in the range of (10) to 1 〇〇〇〇. The resolution of the memory in the range. Micron-scale Shixi may also exist as 'amorphous stone slabs deposited on a flexible substrate (such as PET or non-recorded steel) to make active f-sub-device materials. The addressing scheme can also be combined with the conventional XY (column-row) architecture of each memory cell using a diode or a transistor such that L, a conventional patterning 153752.doc -21 · 201203281 can be used for the memory The bulk is granulated into units at the order of one million and one billion words, and the addressing scheme of the present invention can be used to further fine-grain the units to the kilobit per word. In one embodiment, the χ_γ matrix patterning provides a coarse-grained two-dimensional single 兀, which is then further resolved in the XY plane without further rounding. For example, at a line width of 00 nm, a single micron (four) meter of monolith is patterned with a local drive and sense transistor (eg, the same TFT LCD), and then the germanium is micron using the addressing scheme of the present invention. "The individual of the micro-units resolves down to about 100 to 1 memory locations, and thus no further patterning is required. ... Alternatively, the addressing scheme can be applied to the χ γ matrix perpendicular to the conventional architecture - In the three-dimensional dimension, a corresponding reading and writing program can use two threshold levels as the read/write of each CD. [Simplified Schematic] FIG. 1A and FIG. 1B are diagrams of a transmission line; Figure 1 is a diagram showing the amplitude and phase characteristics of the transmission line of Figure 1B; Figure 3 is a diagram showing one of the other transmission lines; Figure 4 is a diagram showing the output of the node 16 of Figure 3 as a function of time; The output of the point 6 to 16 changes with time; Figure 6 shows the progression of the pulse along an ideal transmission line; Figure 7 shows the progression of the pulse along a lossy transmission line; Figure 8 shows the pulse along with the spread One of the progression of the lossless line; Figure 9 shows the pulse The progress of a line 153752.doc -22· 201203281 having a certain spread but having pulse pre-equalization; FIG. 1 is a schematic view of the first embodiment of the present invention; FIG. 11 is a schematic diagram of the present invention; - Figure 2 is a schematic view of a third embodiment of the present invention; Figure 13 is a circuit diagram showing the response of a small signal diode; Figure 14 shows the current of the circuit of Figure 13 Figure 15 is a cross-sectional view of a fourth embodiment of the present invention. Figure 16 is a schematic view of a transmission line equivalent to Figure 15; Figure 17 is a cross-sectional view of a fifth embodiment of the present invention; Figure 18 is a schematic view of a transmission line equivalent to that of Figure 17; Figure 19 is a cross-sectional view of a sixth embodiment of the present invention; Figure 20 is a schematic view of a transmission line equivalent to Figure 19; Figure 21 is one of the present invention Fig. 22 is a schematic view similar to the transmission line of Fig. 21. 170 transmission line 175 driver 180 driver 185 memory unit 190 ground line 200 horizontal (X) transmission line 210 Vertical transmission line 220 drive 225 drive 153752.doc 201203281 230 drive 235 drive 250 transport layer or panel 255 four side 260 pad 300 substrate 310 first cathode layer 320 second layer 325 microreplication topology 330 third transparent anode layer 340 signal driver 350 signal Driver 360 illumination device 370 another data layer 380 opaque region or pixel 380' opaque region or pixel 382 opaque region or pixel 382' opaque region or pixel 390 transparent region or pixel 390' transparent region or pixel 392 transparent region or pixel 392' transparent Area or pixel 400 Light sensing device 410 Photovoltaic polymer layer 153752.doc -24- 201203281 420 Lower layer 430 Upper metal conductive layer 440 Optical light guide 450 Remote light detector 500 Regular pattern 510 pixels 600 layer 610 Organic semiconductor power Crystal or diode element 650 differential amplifier 153752.doc -25-