201202814 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種内傲式觸控顯示面板之晝素結構及其升》成方 法’尤指利用調整各次晝素之電容比值(cpg+cgd)/(cst+cle+cgd+epg)， 以解決具有不同透光面積之畫素所衍生之電性問題的一種内叙式觸 控顯示面板之畫素結構及其形成方法。 【先前技術】 近來由於觸控顯示面板(touch display panel)的應用越來越序 泛，因而内嵌式觸控感測元件(touchsensor)的技術也就備受重視。 内嵌式觸控感測元件是將觸控感測元件直接製作在各畫素中，犧牲 掉部分開口率(apertureratio)是無法避免的。在習知技術中，通常的 做法是把紅色次晝素、綠色次晝素、以及藍色次晝素之面積等:例 縮小，多出來的面積部分就用來放置觸控感測元件。舉例來說，原 本紅色次畫素、綠色次畫素、藍色次晝素之透光面積各佔畫素整個 面積的三分之-，若她色対素、騎次晝素、藍色次晝素之面 積皆縮小為畫素整個©積的四分之-，雜會有額細分之—的 積可用來放置__元件，可依此方式來_，_在於使= :欠晝素、綠色次畫素、藍色次畫素的透光面積仍保持_。請參 第^圖。第1 ®繪示了習知技射採用誠摘控制元件的畫 之不忍圖。如第1圖所示，由於畫素中需設置觸控感測元件丁 此紅色次畫素R、綠色次晝素G、藍色次畫素3三個次晝素之透光 201202814 面積大體上相同， 而 ’此一作法會造成亮度下降， 【發明内容】 本發明之目的之. 但透光面積小於麵整個面積的三分 之^一— 〇狄 而影響顯 不品質 構及盆开3忐方Φ ;、種内嵌式觸控顯示面板之晝辛结 構及其軸方法，以提供健的晝岭果。 狀旦烹'。 _本t = k佳實施嶋提供—種 結構。上述晝素結構包財義有 如面板之晝素 =素各久畫素分別設置於各次晝素區，且至少有一個次食素 2透光面触雜t㈣麵々、㈣。糾各次^包 Λ有—值電容、料—祕與祕間電容值 ^ 素幅1電容值〜之-薄難晶體、以及具有一 f電谷值Qt之—儲存電容。觀，各次晝素分別具有-電容比 值，電容錄絲邮…雜心义〜），且減衫之電容 比值大體上相同。 本心月之|χ佳實施例另提供—種形成内嵌式觸控顯示面板之 晝素結構的方法，包括下列步驟。首先，提供—基板，其上至少定 義有-第-衫素區與-第二次晝素區。接著，於第—次晝素區内， 預計設置H晝素，且於第二次畫素區内，預計設置一第二次 晝素。隨後，在0<Clel/clc2<i的條件下，調整Qei、c糾、Csti、Cpgi、 Cic2、Cgd2、Cst2、Cpg2其中至少一個，使第一次晝素之電容比值 201202814 (cPgl+cgdl)/(cstl+Clcl+Cgdl+Cpgi)與第 4 (Cpg2 Cgd2/(Cst2+Cle2+Cgd2+cpg2)A體上袖，其巾 躺第一次晝 素之第液asH cgdl係為第_次晝素之u極與汲極 間電容值、cstl係為第-次晝素之—第—儲存電容值、^係為第一 次晝素之H«極朗極間電容值、&係為第二次晝素之 :第二液晶電容值、cst2係、為第二次晝素之—第二儲存電容值、^ 係為第二次晝素之-第二閘極與及極間電容值、以及&係為第二 次晝素之-第二晝素電極與閘極間電^^。之後，根據調整後之 Clcl、cgdl、cstl、cpgl ’於第-次畫素區内，形成具有第—液晶電容 值clcl之-第-液晶電容、具有第—儲存電容值(：^之—第一儲存 電容、以及具有第-閘極與祕間電容值Cgdl與具有—第一晝素電 極與閘極間電容值cpg丨之-第-薄臈電晶體。並且，根據調整後之 Cic2' Cgd2、Cst2、cpg2 ’於第二次畫素區内，形成具有第二液晶電容 值clc2之-第二液晶電容、具有第二儲存電容值^之—第二儲存 電容、以及具有第二閘極與沒極間電容值Cgd2與具有—第二晝素電 極與閘極間電容值Cpg2之一第二薄膜電晶體。 本發明之内嵌式觸控顯示面板之晝素結構及其形成方法，係利 用調整各畫素之電容比值(cpg+cgd)/(Cst+Clc+Cgd+Cpg)，巧各次晝素之 電容比值大體上相同。因此’本發明不但可以適當調整紅色次書素、 綠色次晝素、藍色次纟素三個次畫素的開口率比例，來使亮度減少 情況降到最輕微，又達到均勻混色的效果，並且可以避免在各次書 素具有不同開口率比例下，可能衍生的額外次晝素電性問題。 201202814 【實施方式】 在說明書及後續的申請專利範圍當中使用了某些詞 定的元件。所屬領域巾具有财知識者應可爾，製造商可齡用 不同的名詞來稱呼同樣的树。本說明書及後續的申請專利範圍並 不以名稱縣魏作魏狀件的方式，岐从件在舰上的差 異來作為區_基準。麵篇制書及後續鱗求項當巾所提及的 「包括」係為-開放式的用言吾，故應解釋成「包括但不限定於 請參考第2圖。第2圖繪示了本發明第一較佳實施例之内喪式 觸^顯示面板之畫素結構之部份我電路示賴。如第2圖所示， 本貫知例之内嵌式觸控顯示面板之畫素結構包括一基板勘、以及 複數個次晝素，例如—第—次畫素p卜—第二次畫素^、以及一 第三次畫素P3。圖示中為了簡化’只繪示三個次晝素，但並不以此 為限。並且，於基板2〇〇上，定義有複數個次晝素區，例如一第一 次晝素區20卜一第二次晝素區202、以及一第三次晝素區203。再 者，各次晝素分別設置於各次畫素區，如第一次畫素以設置於第一 次晝素區201，第二次畫素P2設置於第二次畫素區2〇2，第三次畫 素p3設置於第三次晝素區2〇3。其中，各次畫素包括具有一液晶電 谷值clc之一液晶電容、具有一閘極與汲極間電容值Cgd與具有—畫 素電極與閘極間電容值Cpg之一薄膜電晶體、以及具有一儲存電容 值Cst之一儲存電容。例如，以第一次畫素卩丨為例，第一次晝素pl 包括具有一第一液晶電容值Clcl之一第一液晶電容、具有一第—閘 201202814 極與没極間電容值cgdl與具有一第一畫素電極與閘極間電容值cpgl 之一第一薄膜電晶體、以及具有一第一儲存電容值Cstl之一第一儲 存電容。再者’各次畫素分別具有一電容比值，電容比值定義為 (CPg+Cgd)/(Cst+Clc+Cgd+CPg) ’且各次晝素之電容比值大體上相同，換 句話說，以第一次晝素P1、第二次晝素P2為例， (Cpgl+cgdl)/(cstl 十 Clcl+Cgdl+Cpgl)與(Cpg2+Cgd2)/(Cst2+Clc2+Cgd2+Cpg2)大 體上相同。另外’一觸控感測元件240可以設置於第一次晝素區201 内’但不以此為限。並且’本實施例並不限定觸控感測元件24〇的 種類以及組成元件，因此在第2圖中並未繪示出其等效電路圖，僅 以框線表示。在本實施例中，觸控感測元件24()可以是光學觸控感 測7L件，也可以為其他合適的觸控感測元件，例如電阻式觸控感測 元件、或是電容式觸控感測元件等。 請參考第3圖，並-併參考第2圖。第3圖繪示了本發明第一 較佳實施例之内嵌式觸控顯示面板之畫素結構之部份配置示意圖。 其中第2圖料3 _為同—個實細，前者轉效電路圖來表 丁後者以配置:ττ思圖來表示，並且相同元件以相同符號來標示。 ，寻注意的是，-般顯示面板可以由兩透明基板構成，分別為一具 料膜電晶_級，簡__電晶縣板(τρτ-她），以及 I具有彩色渡光片的基板，_為彩色献絲板呀—離）。 拉避免圖不過於複雜’第3圖的配置示意圖僅綠示薄膜電晶體基 第2 位於其上的疋件。以第—次晝素P1為例，在本實施例中， 的第液B曰電奋可以為一第一次畫素電極叫(如第3圖所 201202814 示）、一共通電極25〇、以及介於第-次晝素電極211與共通電極25〇 之間的-液晶層(未不於圖中)所構成。其中，共通電極25〇可以設 置於彩色遽光片基板上，因未設置於_電晶體基板，故未於第3 圖中綠示。再者，第2圖中的第-儲存電容可以是第3圖中的一第 一儲存電極221與第-次畫素電極211間形成的共通電極上電容⑹ on common)，但並不以此為限，而可以為其他合適的元件配置。例 如，於另-實施例中，本發明之第一儲存電容可以是第一次畫素電 φ極部分重疊在閘極上形成的閘極上電容(Cst〇ngate)。再者，第2圖 中的第-薄膜電晶體可以是第3圖中標示為故的框線所圍的區 域。同樣的，以上敘述也可適用於第二次晝素p2與第三次畫素p3， 在此不再贅述。此外，如第3圖所示’至少有一個次晝权透光面 積與其餘次晝素之透光面積大小不同。其中，透光面積可以由次畫 素之畫素電極中未被其他遮光元件遮蔽的面積來決定。在本實施例 中，具有不同透光面積之兩相鄰次晝素可以分別為第一次晝素pl 與第二次晝素P2，而第一次晝素P1位於一第一次畫素區201，第 二次晝素P2位於一第二次晝素區2〇2，且第二次畫素以之透光面 積大於第一次晝素P1之透光面積。其中，第一次晝素區2〇1與第二 人旦素區202之面積可以大體上相同，而第一次畫素p丨之透光面積 小於第二次畫素P2之透光面積，因此，第一次畫素區2〇1可以有額 外的空間用來設置觸控感測元件240，但不以此為限。同樣的，本 實施例並不限定觸控感測元件24〇的種類以及組成元件，因此在第 3圖中僅以框線表示。 201202814 以下將進—步說明上述各次畫素之 參考第2圖以及第3圖。首先，對於第二以具有的規律。請一併 P2而言，如果第—次畫素ρι之 A晝素P1與第二次晝素 素P2之-第二液晶電容值^之比值#^值h與第二次晝 P1之一第-儲存電容值^與第二次書素則第—次晝素 Cst2之比值Cstl/Cst2大體上可以等於c —「、之-第二儲存電容值 第-閘極歧極間電容值且第—次畫素P1之- 次畫素π之一第一晝素電極與間極間:第 =3騎示，第—次晝素電極211之面積小 *第-〜素電極212之面積’假設在相同液晶材質、相同的丑通 電極、以及相同的畫料極與共通電極之間距下，第—液晶電ς值 c】cl <系小於第二液晶電容值&。基於Csti/Qt2大體上可以等於 “的條件’第-儲存電極221之面積可以小於第二儲存電極 222 ;而基於Cgdl/Cgd2大體上可以等於Cici/Qc2的條件，第一薄膜電 晶體231之尺寸可以小於第二薄膜電晶體232之尺寸。再者，可調 整第-畫素電極211與__面積及距離或調整第二畫素電極° 212與閘極間的面積及距離，使Cpgi/Cpg2大體上可以等於‘〜。 其次’對於第一次畫素P1與第三次畫素p3 *言，如果第一次晝素 P1之-第-液晶電容值Clel與第三次晝素P3之—第三液晶電容值 clc3之比值為clcl/c1C3，則第—次晝素P1之一第一儲存電容值Qti 與第三次畫素P3H儲存電容值Qt3之比值Cs"/C⑷大體上可 201202814 以等於clel/cle3,且第—次晝素Pn間極與祕間電容值 與第三次嫩3之-第三閘極細_容之^ 大體上可以等於⑽3，並且第，素 =，^epgl㈣μ晝素ρ3^—第三畫素電極與間極間電 谷值Pg3之比值cpgl/Cpg3大體上可以等於心‘。例如，如第3 ^示，第-次晝素電極211之面積小於第三次晝素電極213之面 ^假設在相眺晶材質、相_共通、以及相_書素電極 c ΤΓ"ΓΤ 5 2= 面上可以等於⑽3的條件，第—儲存電極 等M /c H㈣存電極223;而基於Cgdl/Cgd3大體上可以 專於cwcle3的條件，第—_電晶體231之尺寸 :體233之尺寸。同樣的，可調整第三畫素電_與‘ 的面積及雜，使“讀上可《料cwck3。 、此外帛-人晝素P卜第二次畫素P2、以及第三次晝 ^刀別用來齡：翻吨、綠色 是有兩個以上的次書素可可以时顯示其他祕，或者 第-次晝素P1糊_私色，==色。在本實施例中， 色，第Ά食去PW 色帛一次晝素P2可以用來顯示綠 -欠查辛^^ 4·來顯示藍色。並且，在本實施例中，第= ^ 小㈣等於第二次畫素 : =二=—大於第-次畫㈣之透光面： 且第二:人畫素P2可來顯示綠色。換句話說條次畫素朽' 201202814 . 第二次畫素P2、以及第三次晝素p3中，具有最大透光面積之次晝_ 素可以用來顯示綠色。據此，本實例可以盡可能使顯示綠色之次晝 素開口率為最大，以減少亮度損失，並搭配紅色與藍色之次晝素開 口率比例，來維持-S程度均勻混色的效果。 值得注意的是，以上雖僅以三個次畫素為例，但並不以此為限， 而可以是油次晝素、或四個次畫素、或五做畫料其他實施例。 另外，對次畫素電極充放電的薄臈電晶體，其只要能在閘極線開啟 的時間内使次晝素電極達到所需電位即可，因此，對應不同次晝素籲 電極面積的薄膜電晶體可以有不同的尺寸大小。例如，在本實施例 中’對於第-次畫素P1、第二次畫素P2、以及第三次晝素P3而言， 第了次畫素電極211之面積可以最小，第二次晝素電極212之面積 可以最大，而第二次晝素電極213之面積可以居中。如果對應於第 二次晝素電極212之第二薄膜電晶體232之尺寸維持不變，則對應 於第一次晝素_211之第一薄膜電晶體231之尺寸可以縮小，並 且對應於第王次晝素電極加之第三薄膜電晶體233之尺寸也可以鲁 縮小。其巾’薄職晶體之尺寸可以指的是通道寬長比__ wi_engthrati0，W/L) ’但不以此為限，並且縮小的比例可以依照 電性模擬結果來決定。因此，本實施例可以具有降低間極線負載以 及減小漏電流的優點。 關於本實關之祕式難_面板之晝素結構的形成方法， 先以兩個次畫素為例說明如下。請參考第4圖，並一併參考第2圖· 12 201202814 以及第3圖。第4圖繪示了本發明第一較佳實施例之形成内嵌式觸 控顯示面板之晝素結構的方法之流程示意圖。如第4圖所示，首先， 步驟40提供一基板2〇〇(如第2圖所示），其上可以至少定義有一第 一次畫素區201與一第二次晝素區202。接著，步驟42於第一次晝 素區201内，預計設置一第一次畫素pl，且於第二次畫素區2〇2内， 預计设置一第二次晝素p2。隨後，步驟的條件201202814 VI. Description of the Invention: [Technical Field] The present invention relates to a pixel structure of a arrogant touch display panel and a method for forming the same, in particular, by adjusting the capacitance ratio of each pixel (cpg+) Cgd)/(cst+cle+cgd+epg), a pixel structure of a touch-sensitive display panel and a method for forming the same, which solves the electrical problems caused by pixels having different light transmission areas. [Prior Art] Recently, the application of the touch display panel has become more and more important, and the technology of the in-cell touch sensor has been highly valued. The in-cell touch sensing component directly forms the touch sensing component in each pixel, and it is unavoidable to sacrifice part of the aperture ratio. In the prior art, the usual practice is to reduce the area of the red sputum, the green sputum, and the blue scorpion, etc., and the extra area is used to place the touch sensing element. For example, the original red sub-pixels, green sub-pixels, and blue sub-halogens each account for three-thirds of the entire area of the pixel, if she is a scorpion, riding a scorpion, blue times The area of the element is reduced to a quarter of the entire product of the pixel. The product of the subdivision can be used to place the __ component, which can be used in this way. _ is to make = : 昼 昼, The light transmission area of the green sub-pixel and the blue sub-pixel remains _. Please refer to the figure. The 1st figure shows the unbearable picture of a conventional technique using a control element. As shown in Figure 1, because the touch sensing component needs to be set in the pixel, the red sub-pixel R, the green sub-tin G, and the blue sub-pixel 3 are three times. The same, and 'this method will cause a decrease in brightness, [invention] The object of the present invention. However, the light transmission area is less than one-third of the entire area of the surface - the effect of the quality is not good and the opening is 3 Square Φ;, the intrinsic structure of the in-cell touch display panel and its axis method to provide a healthy 昼 果 fruit. Shaped cooking'. _ This t = k good implementation 嶋 provide - kind of structure. The above-mentioned halogen structure package has the following elements: the panel of the elemental element = each of the peripheral elements is set in each of the halogen regions, and at least one of the secondary foods 2 translucent surface touches t (four) surface defects, (four). Correcting each time ^ package Λ has - value capacitance, material - secret and secret capacitance value ^ plain 1 capacitance value ~ - thin hard crystal, and has a f electric valley Qt - storage capacitor. View, each element has a -capacitance ratio, the capacitance recorded silk mail ... miscellaneous ~), and the capacitance ratio of the reduced shirt is substantially the same. The present invention further provides a method for forming a pixel structure of an in-cell touch display panel, comprising the following steps. First, a substrate is provided on which at least a -first-sleeving region and a second secondary halogen region are defined. Next, in the first-times pixel region, it is expected to set H-cell, and in the second pixel region, a second-order pixel is expected to be set. Then, under the condition of 0 < Clel / clc2 < i, adjust at least one of Qei, c correction, Csti, Cpgi, Cic2, Cgd2, Cst2, Cpg2, so that the capacitance ratio of the first halogen is 201202814 (cPgl+cgdl) /(cstl+Clcl+Cgdl+Cpgi) and the 4th (Cpg2 Cgd2/(Cst2+Cle2+Cgd2+cpg2)A body upper sleeve, the first liquid of the liquid is asc cdl1 is the first time The value of the capacitance between the u pole and the drain of the prime, the cstl is the first-order element - the storage capacitor value, the ^ is the first time the H_ extreme polar capacitance value, & is the first The second liquid crystal capacitor value: the second liquid crystal capacitance value, the cst2 system, the second storage element value, the second storage capacitance value, the second voltage element, the second gate and the interelectrode capacitance value, And & is the second halogen element - the second halogen electrode and the gate electrode ^ ^. After that, according to the adjusted Clcl, cgdl, cstl, cpgl 'in the first-order pixel region, formed with The first-liquid crystal capacitor value clcl-the first liquid crystal capacitor has a first storage capacitor value (: ^ - the first storage capacitor, and has a first gate and a secret capacitance value Cgdl and has - a first halogen electrode Gate room a capacitance value cpg丨-the first-thin-thin transistor, and, according to the adjusted Cic2' Cgd2, Cst2, cpg2', in the second pixel region, forming a second liquid crystal capacitor having a second liquid crystal capacitance value clc2 Having a second storage capacitor value - a second storage capacitor, and a second thin film transistor having a second gate and inter-electrode capacitance value Cgd2 and having a second pixel element and a gate capacitance value Cpg2 The pixel structure of the in-cell touch display panel of the present invention and the method for forming the same are used to adjust the capacitance ratio of each pixel (cpg+cgd)/(Cst+Clc+Cgd+Cpg). The capacitance ratio is substantially the same. Therefore, the present invention can not only appropriately adjust the aperture ratio of the three sub-pixels of red sub-study, green scorpion, and blue scorpion, so as to minimize the brightness reduction. Moreover, the effect of uniform color mixing is achieved, and the problem of additional secondary halogens which may be derived under the ratio of different aperture ratios of each of the books can be avoided. 201202814 [Embodiment] In the specification and the subsequent patent application scope, a certain Some of the components The subject area has a wealth of knowledge, the person who can use the different nouns to refer to the same tree. The scope of this specification and the subsequent patent application is not in the form of the name Wei Weiwei. The difference in the ship is used as the district _ benchmark. The "include" mentioned in the essay and the follow-up syllabus is "open", so it should be interpreted as "including but not limited to please refer to Figure 2. FIG. 2 is a partial diagram showing the pixel structure of the internal touch panel of the first preferred embodiment of the present invention. As shown in FIG. 2, the pixel structure of the in-cell touch display panel of the present invention includes a substrate survey and a plurality of sub-tenucins, for example, a first pixel, a second pixel. ^, and a third pixel P3. In the figure, in order to simplify 'only three primes are shown, but not limited to this. Further, on the substrate 2, a plurality of sub-tendin regions are defined, for example, a first-order halogen region 20, a second-order halogen region 202, and a third-order halogen region 203. Furthermore, each element is set in each pixel area, for example, the first pixel is set in the first pixel area 201, and the second pixel P2 is set in the second pixel area 2〇2. The third pixel p3 is set in the second 昼素区2〇3. Wherein, each pixel includes a liquid crystal capacitor having a liquid crystal valley value clc, a gate capacitance value between the gate and the drain Cgd, and a thin film transistor having a pixel electrode and a gate capacitance value Cpg, and A storage capacitor having a storage capacitor value Cst. For example, taking the first pixel as an example, the first pixel pl includes a first liquid crystal capacitor having a first liquid crystal capacitance value Clcl, and having a first gate 201202814 pole and a non-electrode capacitance value cgdl and A first thin film transistor having a first pixel electrode and a gate capacitance value cpgl, and a first storage capacitor having a first storage capacitance value Cstl. Furthermore, 'each pixel has a capacitance ratio, and the capacitance ratio is defined as (CPg+Cgd)/(Cst+Clc+Cgd+CPg)' and the capacitance ratio of each element is substantially the same, in other words, For the first time, the alizarin P1 and the second alizarin P2 are as follows. (Cpgl+cgdl)/(cstl XClCl+Cgdl+Cpgl) is substantially the same as (Cpg2+Cgd2)/(Cst2+Clc2+Cgd2+Cpg2) . In addition, a touch sensing component 240 can be disposed in the first pixel region 201, but is not limited thereto. Further, the present embodiment does not limit the type of the touch sensing element 24A and the constituent elements, and therefore the equivalent circuit diagram is not shown in Fig. 2, and is only indicated by a hatching. In this embodiment, the touch sensing component 24 ( ) may be an optical touch sensing 7L component, or may be other suitable touch sensing components, such as a resistive touch sensing component or a capacitive touch. Control the sensing components and so on. Please refer to Figure 3 and - and refer to Figure 2. FIG. 3 is a partial schematic view showing the configuration of a pixel structure of the in-cell touch display panel according to the first preferred embodiment of the present invention. The second picture material 3 _ is the same as a real thin, the former conversion circuit diagram to the table is represented by the configuration: ττ思图, and the same components are marked with the same symbol. It should be noted that the general display panel can be composed of two transparent substrates, which are respectively a film-electric crystal-level, a simple __电晶县板 (τρτ-her), and a substrate having a color light-passing sheet. , _ is a color silk plate ah - away). The pull-and-avoiding diagram is not too complicated. The configuration diagram of Figure 3 only shows the element on which the thin-film transistor base is located. Taking the first-order halogen P1 as an example, in the present embodiment, the first liquid B曰 electric power can be called a first-time pixel electrode (as shown in FIG. 3, 201202814), a common electrode 25〇, and The liquid crystal layer (not shown in the figure) is interposed between the first-order halogen electrode 211 and the common electrode 25A. The common electrode 25A may be disposed on the color filter substrate, and is not disposed on the _transistor substrate, and thus is not shown in green in FIG. Furthermore, the first storage capacitor in FIG. 2 may be a common electrode capacitor (6) on common formed between a first storage electrode 221 and a first pixel electrode 211 in FIG. 3, but not For the sake of limitation, it can be configured for other suitable components. For example, in another embodiment, the first storage capacitor of the present invention may be a gate capacitance (Cst〇ngate) formed by overlapping the first pixel element φ pole portion on the gate. Further, the first-thin film transistor in Fig. 2 may be a region surrounded by a frame line indicated in Fig. 3. Similarly, the above description is also applicable to the second pixel p2 and the third pixel p3, and details are not described herein again. In addition, as shown in Fig. 3, at least one of the secondary light transmission areas is different from the light transmission area of the remaining secondary elements. Among them, the light transmission area can be determined by the area of the pixel electrode of the sub-pixel which is not blocked by other light shielding elements. In this embodiment, two adjacent sub-stimuli having different light-transmissive areas may be the first halogen pl and the second halogen P2, respectively, and the first halogen P1 is located in a first pixel region. 201. The second pixel P2 is located in a second pixel region 2〇2, and the second pixel has a light transmission area larger than that of the first pixel P1. Wherein, the area of the first pixel region 2〇1 and the second human pixel region 202 may be substantially the same, and the light transmission area of the first pixel p丨 is smaller than the light transmission area of the second pixel P2. Therefore, the first pixel area 2〇1 may have additional space for setting the touch sensing element 240, but is not limited thereto. Similarly, the present embodiment does not limit the types of touch sensing elements 24A and the constituent elements, and therefore is only indicated by a hatching in FIG. 201202814 The following is a description of the above-mentioned respective pixels in reference to Fig. 2 and Fig. 3. First of all, for the second to have the law. In the case of P2, if the ratio of the first pixel of the first pixel to the second liquid crystal capacitance value of the second atomic element P1 is the same as the value of the second time 昼P1 - the storage capacitor value ^ and the second booklet - the ratio of the first-order halogen Cst2 Cstl / Cst2 can be substantially equal to c - ", - the second storage capacitor value - the first gate capacitance value and the first - Subpixel P1 - one of the subpixels π between the first halogen electrode and the interpole: the third = 3 riding, the area of the first-order halogen electrode 211 is small * the area of the first-electrode electrode 212 is assumed to be The same liquid crystal material, the same ugly electrode, and the distance between the same picture electrode and the common electrode, the first liquid crystal value c] cl < is smaller than the second liquid crystal capacitance value & based on Csti / Qt2 substantially The area of the first storage electrode 221 which may be equal to "the condition" may be smaller than the second storage electrode 222; and based on the condition that Cgdl/Cgd2 may be substantially equal to Cici/Qc2, the size of the first thin film transistor 231 may be smaller than that of the second thin film The size of the crystal 232. Furthermore, the area and distance of the first-pixel electrode 211 and the __ are adjusted or the area and distance between the second pixel electrode 212 and the gate are adjusted so that Cpgi/Cpg2 can be substantially equal to ‘~. Secondly, for the first pixel P1 and the third pixel p3 *, if the first pixel P1 - the first liquid crystal capacitance value Clel and the third time pixel P3 - the third liquid crystal capacitance value clc3 The ratio is clcl/c1C3, and the ratio of the first storage capacitor value Qti of the first-order pixel P1 to the storage pixel value Qt3 of the third pixel P3H is Cs"/C(4), which can be substantially equal to clel/cle3, and - The inter-electrode Pn inter- and inter-capacity capacitance values and the third-time tender 3 - the third gate fine _ 容 ^ ^ can be roughly equal to (10) 3, and the first, prime =, ^epgl (four) μ 昼 ρ ρ3 ^ - third painting The ratio cpgl/Cpg3 of the prime electrode to the inter-electrode potential valley Pg3 can be substantially equal to the heart'. For example, as shown in FIG. 3, the area of the first-order halogen electrode 211 is smaller than the surface of the third-order halogen electrode 213, which is assumed to be in the phase twin crystal material, the phase-common, and the phase-pixel electrode c ΤΓ"ΓΤ 5 2 = the surface can be equal to the condition of (10) 3, the first storage electrode or the like M / c H (four) storage electrode 223; and based on Cgdl / Cgd3 can be generally dedicated to the condition of cwcle3, the size of the first - crystal 231: the size of the body 233 . Similarly, the area and the amount of the third pixel can be adjusted, so that "reading can be expected to be cwck3. In addition, the 帛-human P素P 卜 second pixel P2, and the third 昼^ knife Do not use age: ton, green is more than two sub-books can display other secrets, or the first-times P1 paste _ private color, == color. In this embodiment, color, the first Foraging to PW, the primary P2 can be used to display green-under-character ^^4· to display blue. And, in this embodiment, the first = ^ small (four) is equal to the second pixel: = two = - greater than the first painting (four) of the translucent surface: and second: the human pico P2 can be used to display green. In other words, the strip painting prime '201202814. The second pixel P2, and the third element In p3, the sub-intensity with the largest light-transmitting area can be used to display green color. According to this example, the present example can maximize the aperture ratio of the green color to reduce the brightness loss, and match the red and blue. The ratio of the aperture ratio of the element is used to maintain the effect of uniform color mixing at the -S level. It is worth noting that although the above is only three sub-pixels, it is not Other embodiments may be oil sub-tendin, or four sub-pixels, or five-time paint. In addition, a thin germanium transistor that charges and discharges a sub-pixel electrode, as long as it can be turned on at the gate line The secondary halogen electrode can be brought to a desired potential within a time, and therefore, the thin film transistors corresponding to the different times of the electrode area can have different sizes. For example, in the present embodiment, 'for the first pixel P1 For the second pixel P2 and the third pixel P3, the area of the second pixel electrode 211 can be the smallest, the area of the second pixel electrode 212 can be the largest, and the second pixel electrode 213 The area of the second thin film transistor 232 corresponding to the second halogen element 212 remains unchanged, and the size of the first thin film transistor 231 corresponding to the first halogen element 211 can be reduced. And the size of the third thin film transistor 233 corresponding to the second morphemic electrode can also be reduced. The size of the thin film can refer to the channel width to length ratio __wi_engthrati0, W/L) but not With this limit, and the scale of reduction can be The result of the electrical simulation is determined. Therefore, the present embodiment can have the advantages of reducing the inter-pole line load and reducing the leakage current. The secret method of the actual implementation is difficult to form the method of forming the pixel structure of the panel. The pixel is described as an example. Please refer to FIG. 4 and refer to FIG. 2, FIG. 12 201202814 and FIG. 3 together. FIG. 4 illustrates the formation of an in-cell touch display according to the first preferred embodiment of the present invention. A schematic diagram of a method for a planar structure of a panel. As shown in FIG. 4, first, step 40 provides a substrate 2 (as shown in FIG. 2) on which at least a first pixel region 201 can be defined. And a second halogen region 202. Then, in step 42 of the first pixel region 201, it is expected to set a first pixel pl, and in the second pixel region 2〇2, the expected setting A second time principal p2. Subsequently, the conditions of the steps
下’調整 Qcl、Cgdl、Csu、Cpgl、Ck2、Cgd2、匕2、Cpg2其中至少一 則吏第-次畫素之電容比值(Cpgl+Cgdi)/(Csti+Ciei+Cgdi+c與第二 人里素之電谷比值(Cpg2+Cgd2)/(Cst2+Cic2+Cgd2+Cpg2)大體上相同，其中Next 'adjust Qcl, Cgdl, Csu, Cpgl, Ck2, Cgd2, 匕2, Cpg2, at least one of the 吏-th order pixel capacitance ratio (Cpgl+Cgdi)/(Csti+Ciei+Cgdi+c and the second person The electric valley ratio (Cpg2+Cgd2)/(Cst2+Cic2+Cgd2+Cpg2) is substantially the same,
Clcl係為第-次晝素P1之一第—液晶電容值、Csti係為第一次晝素 P1之-第-儲存電容值、Cgd4為第一次晝素P1之一第一閘極與 汲極間電容值、(:pgl係為第—次晝素Pk—第―晝素電極與開極間 電雜、Cle2係為第二次畫素P2之一第二液晶電容值、Q係為第 一次晝素P2之-第二儲存電容值、Cgd2係為第二次晝素打之一第 二閘極與汲極間電容值、以及Cpg2係為第二次晝素！>2之一第二書Clcl is one of the first-order halogen P1 - the liquid crystal capacitance value, Csti is the first-order storage capacitor value of the first halogen P1, and Cgd4 is the first gate and the first one of the first halogen P1. The interelectrode capacitance value, (: pgl is the first-order pixel Pk - the first - pixel electrode and the open-electrode hybrid, Cle2 is the second pixel P2, the second liquid crystal capacitance value, the Q system is the first The second storage capacitor value of the primary P2, the Cgd2 is the second gate and the first gate and the second capacitance. The Cpg2 is the second one! Second book
素電極與閘極間電容值。其巾，G<Qel/cle2<1的條件可以指的U 一次晝素電極211之面積小於第二次晝素電極212之面積， 以此為限。 、—+ 又斤.叫”丨，丨、，〈傻，少騍46根據調整後之Cm、c di、c cpgl’於第-次晝素區201内’形成具有第一液晶電容值=之」 一液晶電容、具有帛—儲存電容值Csti之—第-儲存電容Γ以及 有第-閘極與祕間電容值Cgdi與具有第—晝錢極與閘極間, 13 201202814 值cpgl之一第一薄膜電晶體231。在本實施例中，要使第一液晶電 容具有調整後之第-液晶電容值clel，可以透過控制第—液晶電容 之第-人畫素電極211面積來進行調整，但不以此為限，而可以透 過凋整第一液晶電容的其他條件參數。例如，可以調整第一次畫素 電極211與共通電極250之間距、或是改變介於第一次晝素電極211 與共通電極250之間的液晶層種類或特性等。並且，在本實施例令， 要使第-齡電容具有罐後之第-鱗電容值，可以透過控 制第-儲存電容之第-儲存電極221面積來進行調整，但不以此為 限，而可以透過調整第一儲存電容的其他條件參數。例如，可以調 整第儲存電極221與第-次晝素電極211之間距、或是改變介於 第-儲存電極221與第-次畫素電極211間之材質種類或特性等。 同樣的，在本實施例中，要使第一薄膜電晶體231具有第一問極與 及極間電谷值Cgdl ’可以透過控制第-薄膜電晶體之尺寸與形狀來 進行調整，但不以此為限。再者，要使第一薄膜電晶體231與第一 液晶電容間具有第-畫素電極與_間電容值。，可以透過控制 間極與第—次晝素電極211間的面積及距離來進行調整，但不以此 =限。並且’步驟48根據調整後之Qe2、Cgd2、^、c邮，於第二 次畫素區内，形成具有第二液晶電容值&之—第二液晶電容、具 有第二儲存電容值Qt2之—第二儲存電容、以及具有第二閘極與沒 極間電容值&與具有第二晝素電極與閘極間電容值（^之一第二 _電晶體232。同理，第二液晶電容、第二儲存電容、以及第二 ’#膜電晶體232之調整方式’可以類似於上述第一液晶電容、第一 儲存電容、以及第-薄膜電晶體231之調整方式，在此不再資述。 201202814 此外，本實施例之内嵌式難顯示面板之晝素結構的形成方法，可 以另包括於第-次畫素區201内形成一觸控感測元件㈣，但不以 此為限。例如，可於其他次畫素區内形成觸控感測元件，且觸 控感測元件之健並不侷限於—個，可财_產品規格 求來決定。 另外，於第4圖中，有關步驟44之調整Qci、c洲、㈣、The capacitance between the element electrode and the gate. The condition of the towel, G<Qel/cle2<1, may mean that the area of the U primary halogen electrode 211 is smaller than the area of the second halogen electrode 212, and is limited thereto. , -+ and jin. Called "丨, 丨,, < silly, less 骒 46 according to the adjusted Cm, c di, c cpgl' in the first - 昼 区 201 201 201 201 201 201 201 201 201 A liquid crystal capacitor having a 帛-storage capacitance value Csti--the storage capacitor Γ and having a thyristor and a secret capacitance value Cgdi and having a first 昼 pole and a gate, 13 201202814 cpgl one A thin film transistor 231. In this embodiment, the first liquid crystal capacitor has an adjusted first liquid crystal capacitance value cle1, which can be adjusted by controlling the area of the first human pixel electrode 211 of the first liquid crystal capacitor, but not limited thereto. It can pass through other condition parameters of the first liquid crystal capacitor. For example, the distance between the first pixel electrode 211 and the common electrode 250 or the type or characteristic of the liquid crystal layer between the first pixel electrode 211 and the common electrode 250 may be adjusted. In addition, in this embodiment, the first-age capacitor has a first-scale capacitance value after the can, and can be adjusted by controlling the area of the first storage electrode 221 of the first storage capacitor, but not limited thereto. Other condition parameters of the first storage capacitor can be adjusted. For example, the distance between the storage electrode 221 and the first-order halogen electrode 211 or the type or characteristic of the material between the first storage electrode 221 and the first-order pixel electrode 211 can be adjusted. Similarly, in the embodiment, the first thin film transistor 231 has the first polarity and the inter-electrode valley Cgdl' can be adjusted by controlling the size and shape of the first-film transistor, but not This is limited. Further, the first thin film transistor 231 and the first liquid crystal capacitor are provided with a first pixel voltage and a _ capacitance value. It can be adjusted by controlling the area and distance between the interpole and the first-order halogen electrode 211, but not by this limit. And 'Step 48 according to the adjusted Qe2, Cgd2, ^, c mail, in the second pixel area, forming a second liquid crystal capacitor value & second liquid crystal capacitor, having a second storage capacitor value Qt2 a second storage capacitor, and having a second gate and interelectrode capacitance value & and having a second halogen electrode and a gate capacitance value (^ a second_transistor 232. Similarly, the second liquid crystal The capacitance, the second storage capacitor, and the adjustment mode of the second '#membrane transistor 232' may be similar to the adjustment methods of the first liquid crystal capacitor, the first storage capacitor, and the first-thin film transistor 231, and are no longer used herein. 201202814 In addition, the method for forming the pixel structure of the in-cell hard display panel of the embodiment may further include forming a touch sensing component (4) in the first pixel region 201, but not limited thereto. For example, the touch sensing component can be formed in other sub-pixel regions, and the health of the touch sensing component is not limited to one, and can be determined by the product specifications. In addition, in FIG. 4, Adjustments to Step 44 Qci, c, (4),
Clc2、cgd2、Cst2、、2其中至少—個之方式至少可以有以下兩種方 式，但不以此為限。第-種方式可以包括下列步驟。綠，先選定 第-液晶電紐Qel以及第二液晶電容值&。射，本實施例可 以依據色彩學上的需求，選定—合適的第—次晝素電極2ΐι之面積 以及-合適的第二次畫素電極212之面積，在固定相同液晶材質、 相同的共通電極、以及相_畫素電極與共通電極之間距下，可以 進而決定第-液晶電容值Qcl以及第二液晶電容值Gw。接著，計 f出Clel/Cle2之比值。隨後，調整第—儲存電容值Q與第二儲存電 容值Cst2 ’使cstl/cst2之比值大體上等於心/^2。之後，調整第一 閘極與汲關電容值Cgdl與第二_與錄間t容值Cgd2，使 Cgdl/cgd2之比值大體上等於Clei/Cie2。然後，調整第—晝素電極與間 極間電容值cpgl與第二畫素電極與閘極間電容值Cpg2，使Cpgi/Cpg2 之比值大體上等於Clel/Cle2。在Cstl/Cst2之比值、Cgdl/Cgd2之比值、 以及cpgl/cpg2之比值大體上等於Cici/Qc2的情況下，可使使第一次 晝素之電容比值(cpgl+cgdl)/(cstl+Qel+Cgdl+Cpgi)與第二次畫素之電 谷比值(CPg2+Cgd2)/(Cst2+Clc2+Cgd2+Cpg2)大體上相同。從另一個角度來 15 201202814 看’第-種方式可以選定第-次晝素為基礎，等比例放大或縮小第· 一·人晝素之C丨η、Cgd2、Cst2、cpg2，來使第一次晝素之電容比值 (Cpg1+Cgdi)/(Cstl+Clcl+Cgdl+Cpgl)與第二次晝素之電容比值 (CPg2+Cgd2)/(Cst2+Clc2+Cgd2+Cpg2)大體上相同。另外，第二種方式，則 疋分別调整 C丨cl、Cgdi、Cstl、cpg丨、Cic2、cgd2、Cst2、cpg2，來使第 -人晝素之電谷比值(cpg丨+Cgd丨)/(Cst丨+Clcl+Cgd丨+Cpgi)與第二次晝素 之電谷比值(CPg2+Cgd2)/(Cst2+Clc2+Cgd2+CPg2)大體上相同。換句話說， 第二種方式可以不侷限於Clel/Cle2之比值，也就是說Csti/Cst2之比 值、cgdl/cgd2之比值、以及cpgl/cpg2之比值可以不受Clei/Cic2之限制，· 而可以較為彈性的調整，且可以避免第二儲存電極222之面積的刻 意放大所導致的開口率降低。 關於本實施例之内嵌式觸控顯示面板之畫素結構的形成方法， 再以增加另一次畫素為例說明如下。請參考第5圖。第5圖繪示了 本發明第-較佳實施例之形成内嵌式觸控顯示面板之晝素結構之增 加另一次晝素的方法之流程示意圖。如第5圖所示，首先，步驟鲁 於基板200上定義一第三次畫素區203,並於第三次晝素區2〇3内， 預計設置一第三次晝素P3。隨後，步驟52在0<Ckl/Clc3<1的條件 下，調整C!。3、Cgd3、Cst3、Cpg3其中至少一個，使第一次晝素之電 谷比值(Cpg丨+0££11)/((^+(：丨(：1+06<1丨+(：1^1)與第三次畫素之電容比值 (Cpg3+Cgd3)/(Cst3+Clc3+Cgd3+CPg3)大體上相同’其中Clc3係為第三次晝 素之一第三液晶電容值、Cst3係為第三次晝素之一第三儲存電容值、At least one of Clc2, cgd2, Cst2, and 2 may be at least in the following two ways, but is not limited thereto. The first mode can include the following steps. Green, first select the first - liquid crystal button Qel and the second liquid crystal capacitor value & Shot, in this embodiment, the area of the appropriate first-order halogen electrode 2ΐι and the area of the appropriate second-order pixel electrode 212 can be selected according to the requirements of color, and the same common liquid crystal material and the same common electrode are fixed. And the distance between the phase pixel electrode and the common electrode, and the first liquid crystal capacitance value Qcl and the second liquid crystal capacitance value Gw can be further determined. Next, the ratio of Clel/Cle2 is calculated. Subsequently, the first storage capacitor value Q and the second storage capacitor value Cst2' are adjusted such that the ratio of cstl/cst2 is substantially equal to the heart/^2. Thereafter, the first gate and the off capacitance value Cgdl and the second_interval t value Cgd2 are adjusted such that the ratio of Cgdl/cgd2 is substantially equal to Clei/Cie2. Then, the first halogen element and the interelectrode capacitance value cpgl and the second pixel electrode to interelectrode capacitance value Cpg2 are adjusted so that the ratio of Cpgi/Cpg2 is substantially equal to Clel/Cle2. In the case where the ratio of Cstl/Cst2, the ratio of Cgdl/Cgd2, and the ratio of cpgl/cpg2 are substantially equal to Cici/Qc2, the capacitance ratio of the first halogen can be made (cpgl+cgdl)/(cstl+Qel). +Cgdl+Cpgi) is substantially the same as the electric valley ratio (CPg2+Cgd2)/(Cst2+Clc2+Cgd2+Cpg2) of the second pixel. From another angle, 15 201202814 See 'the first method can be based on the first-order morpheme, and scale up or down the C 丨 η, Cgd2, Cst2, cpg2 of the first one, to make the first The capacitance ratio of the secondary halogen (Cpg1+Cgdi)/(Cstl+Clcl+Cgdl+Cpgl) is substantially the same as the capacitance ratio of the second halogen (CPg2+Cgd2)/(Cst2+Clc2+Cgd2+Cpg2). In addition, in the second mode, C丨cl, Cgdi, Cstl, cpg丨, Cic2, cgd2, Cst2, and cpg2 are respectively adjusted to make the electric-gull ratio of the human-human element (cpg丨+Cgd丨)/( Cst丨+Clcl+Cgd丨+Cpgi) is substantially the same as the electric valley ratio (CPg2+Cgd2)/(Cst2+Clc2+Cgd2+CPg2) of the second halogen. In other words, the second mode may not be limited to the ratio of Clel/Cle2, that is, the ratio of Csti/Cst2, the ratio of cgdl/cgd2, and the ratio of cpgl/cpg2 may not be limited by Clei/Cic2, and The adjustment can be made more elastic, and the reduction in the aperture ratio caused by the intentional enlargement of the area of the second storage electrode 222 can be avoided. The method for forming the pixel structure of the in-cell touch display panel of the present embodiment will be described below by taking another pixel as an example. Please refer to Figure 5. FIG. 5 is a flow chart showing a method of adding another element of the pixel structure of the in-cell touch display panel according to the first preferred embodiment of the present invention. As shown in Fig. 5, first, a third pixel region 203 is defined on the substrate 200, and a third pixel P3 is expected to be disposed in the third pixel region 2〇3. Subsequently, step 52 adjusts C! under the condition of 0 < Ckl / Clc3 < 3. At least one of Cgd3, Cst3, and Cpg3, so that the first valley's electric valley ratio (Cpg丨+0££11)/((^+(:丨(:1+06<1丨+(:1) ^1) The capacitance ratio of the third pixel (Cpg3+Cgd3)/(Cst3+Clc3+Cgd3+CPg3) is substantially the same 'where Clc3 is the third liquid crystal capacitance value of the third element, Cst3 system For the third storage element, the third storage capacitor value,
Cgd3係為第二次晝素之一第三閘極與沒極間電容值、以及c 3係為 * 201202814 第旦素之帛二畫素電極與閘極間電容值。之後，步驟54根據 調^後^數Ck3、Cgd3、Cst3、Cpg3，於第三次畫素區203内，形成 具有第—夜晶電容值&之一第三液晶電容、具有第三儲存電容值 Cst3之-一第三儲存電容、以及具有第三間極與汲極間電容值c幻與 具有第三晝素電極與閘極間電容值一之一第三薄膜電晶體^。、 同理’第1存電容值Cst3之機方式可以透過控三儲存電極 223—之面積來進行罐，但仰料限。並且，第三雜與沒極間 籲電容值Cgd3之調整方式係透過控制第三薄膜電晶體加之 狀來進行調整。再者，第三晝素電極朗極間電容值Cpg3之調整^ 弋可、透過控制第二畫素電極犯與閘極間的面積及距離來進行調 整。The Cgd3 system is the third gate and the interelectrode capacitance value of the second halogen, and the c 3 system is the current capacitance between the electrode and the gate of the 201202814 first element. Then, in step 54, according to the adjustment number Ck3, Cgd3, Cst3, Cpg3, in the third pixel region 203, a third liquid crystal capacitor having a first-night crystal capacitance value & The value Cst3 is a third storage capacitor, and has a third inter-electrode-to-deuterium capacitance value c and a third thin-film transistor having a third pixel-to-gate capacitance value. In the same way, the first storage capacitor value Cst3 can be used to control the area of the storage electrode 223, but the tank is limited. Further, the adjustment method of the capacitance value Cgd3 between the third impurity and the non-polarity is adjusted by controlling the addition of the third thin film transistor. Furthermore, the adjustment of the capacitance value Cpg3 of the third halogen element is adjusted by controlling the area and distance between the second pixel electrode and the gate.
同樣的，於第5圖中，有關步驟52之調整Q f至少—個之方式’至少可以有以下兩種方式，但不以此為限 第二種方式可吨括下列步驟。錢，觀第三液晶電容值^ 接者，計异出Clel/Cle3之比值。隨後，調整第三儲存電容值^，使 Qtl/cs〇之比值大體上等於Clcl/Clc3。之後，調整第三閘極魏極間 電容值cgd3，使Cgdl/Cgd3之比值大體上等於&心。然後，調 三晝素電極與閘極間電容值Cpg3，使之比值大體上等於Similarly, in Fig. 5, at least the following methods can be used to adjust Qf at least one of the following steps, but not limited thereto. The second method can include the following steps. Money, view the value of the third liquid crystal capacitor ^, the ratio of Clel / Cle3. Subsequently, the third storage capacitor value ^ is adjusted so that the ratio of Qtl/cs〇 is substantially equal to Clcl/Clc3. Thereafter, the third gate-to-electrode capacitance value cgd3 is adjusted so that the ratio of Cgdl/Cgd3 is substantially equal to & Then, adjust the capacitance between the trioxad electrode and the gate Cpg3 so that the ratio is substantially equal to
Clcl/Clc3。從另-個角度來看，第—種方式可以選定第—次主 礎’等比例放大或縮小第三次晝素之Cle3、cgd3、cst3、cpg3=^ -次料之電容比值(Cpgl+Cgd+Cgd〜^ 之電谷比值(Cpg3+Cgd3y(Cst3+Clc3+Cgd3+‘^ 201202814 種方式，則是分別調整Clc3、Cgd3、cst3、以及cpg3，來使第一次畫 素之電谷比值(cpg丨+Cgd i )/(Cst丨+Cie 1+Cgd 1+cpg!)與第三次晝素之電容 比值(CPg3+Cgd3)/(Cst3+Cic3+Cgd3+CPg3)大體上相同。同理，第二種方式 了以不侷限於Clc丨/Cl。3之比值’也就是說Csti/Cst3之比值、cgdl/Cgd3 之比值、以及Cpgl/Cpg2之比值可以不受Clcl/Cl。3之限制，而可以較 為彈性的調整，來避免第三儲存電極223之面積的刻意放大所導致 的開口率降低。值得注意的是，本發明並不侷限於形成三個次畫素， 而可以類似於第三次畫素的形成方法，進一步形成一第四次畫素。 換句話說，可以依此類推，形成複數個次晝素。 以下將利用三個次晝素分別用來顯示紅色、綠色、與藍色，並 且搭配上述步驟44與步驟52中調整電容值之第一種方式來做說 明。在本實施例中，第一次晝素P1可以用來顯示紅色，第二次晝素 P2可以用來顯示綠色，而第三次畫素p3可以用來顯示藍色。由色 彩學公式計賴果’如果以第二:欠晝素· 212面齡鮮並且定 義為1，則第-次晝素電極2i2面積可以在吻叫之間變化，且第 三次晝素電極213面積可以在0.74M之間變化。據此，計算出混 成的白光，其色彩QE座標Wx和Wy差異皆不會超過〇 %，可被 產品規格接受’其中Wx和Wy差異是與同樣條件同樣製程的紅色、 綠色、與藍色次晝素面積皆相同的產品比較得 晳4 m t 件木而在相同液晶材 ，、相同的共通電極、以及相_晝素電極與共料極之間 各晝素電極面積可以決定各液晶電容之大小。 44與步驟52巾赃電容值之第—種方式 # β卩可依照步驟 飞將 Cle2、Cgd2、Cst2、與 201202814 CPg2縮小為clcl、cgdl、cstl、與cpgl之比例可在0 25〜1之間變化， 而將Ck3、Cgd3、Cst3、以及Cpg3縮小為Qe丨、c糾、^、以及& 之比例可在0.74〜1之間變化，使其滿足 (CPgI+CgdI)/(Cstl+CIcl+Cgdl+Cpgl) > (Cpg2+Cgd2)/(Cst2+Clc2+Cgd2+Cpg2) ^ 以及(C^+CgdMC^+c^+c^+Cpg3)』比值大體上相同。 —值得注意的是，於第—較佳實施射，液晶電容之晝素電極係 ，覆盍至薄膜電晶體之閘極電極上方，則電容比值定義中的Cpg不能 。略」而如果液^電容之晝素電極與薄膜電晶體之閘極電極之 門八有夠大的距離’則cpg的值將會夠小而得以在電容比值定義中 忽略。請參考第6圖與第7圖。第6圖繪示了本發明第二較佳實施 例之内故式觸控顯示面板之晝素結構之部份等效電路示意圖，而第 7圖綠示了本發明第二較佳實施例之内嵌式觸控顯示面板之畫素結 構之部份配置示意圖。其中，前者以等效電路圖來表示，後者以配 置示意圖來表示，並且相同元件沿用相同於第一較佳實施例之符號 >來，示。如第6圖與第7圖所示，在第二較佳實施例中，由於液晶 電容之畫素電極與薄膜電晶體之閘極電極之間具有一定的距離，使 的Cpg的值較小。故於此實施例中，電容比值定義中的〜可以省 $ ’使付各晝素之電容比值定成為Cgd/(Cst+Cie+Cgd)。據此，此較佳 實施例之内嵌式觸控顯示面板的晝素結構及其形成方法，相似於第 一較佳實施例，差別僅在忽略cpg。 綜上所述，本發料但可以適當_紅色次晝素、綠色次晝素、 201202814 藍色次晝素三個次畫素的開口率比例’來使亮度減少情況降到最輕 微，又達到均勻混色的效果，並且可以避免在各次晝素具有不同開 口率比例下，可能衍生的額外次畫素電性問題。更明確的說，各次 晝素在具有不同開口率比例的情況下，可能使紅色次晝素、綠色次 晝素、藍色次晝素的饋通電壓△ Vp(feedthrough voltage)差距太大， 共通電壓(Vcom)再怎麼調整，還是無法同時使紅色次晝素、綠色次 晝素、藍色次畫素三個次畫素的正負極性之液晶跨壓相等，換句話 說，如果調整Vcom電壓使其中一個次晝素的正負極性之液晶跨壓 相等，而另外兩個次畫素的正負極性之液晶跨壓可能仍有明顯差 異，因而產生晝面閃爍問題。而本發明之内嵌式觸控顯示面板之晝 素結構及其形成方法，利用調整各晝素之電容比值 (Cpg+Cgd)/(Cst+Clc+Cgd+Cpg) ’使各次畫素之電容比值大體上相同，可 有效避免次晝素之電性問題，而可獲得較佳的畫面效果。此外，本 呶明中對應不同次畫素電極面積的薄膜電晶體可以有不同的尺寸大 小，來有效的降低閘極線負載以及減小漏電流。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖繪示了習知技術中採用内嵌式觸控感測元件的晝素之示意 圖。 第2圖繪示了本發明第一較佳實施例之内嵌式觸控顯示面板之畫素 201202814 結構之部份等效電路示意圖。 第3圖綠示了本發明第一較佳實施例之内嵌式觸控顯示面板之晝素 結構之部份配置示意圖。 第4圖綠不了本發明第一較佳實施例之形成内嵌式觸控顯示面板之 晝素結構的方法之流程示意圖。 了本發明第一較佳實施例之形成内嵌式觸控顯示面板之 第6息素結構之增加另一次晝素的方法之流程示意圖。 鲁 圖、會不了本發明第二較佳實施例之内嵌式觸控顯示面板之晝素 結構之部份等效電路示意圖。 1示了本發明第二較佳實施例之内搬式觸控顯示面板之晝素 結構之部份配置示意圖。 【主要元件符號說明】 紅色次晝素 ^ B 藍色次晝素 零P1笛 第一次晝素 P3 货 第三次畫素 2〇1 ^ 第一次晝素區. 203 货— 第三次晝素區 212 货 弟二次晝素電極 221 货 第一儲存電極 223 结 _ „ 第二儲存電極 G 綠色次晝素 T 觸控感測元件 P2 第二次畫素 200 基板 202 第二次畫素區 211 第一次畫素電極 213 第三次晝素電極 222 第二儲存電極 231 第一薄膜電晶體 21 201202814 232 第二薄膜電晶體 233 第三薄膜電晶體 240 觸控感測元件 250 共通電極 C,ci 第一液晶電容值 Qti 第一儲存電容值 Cpgl 第一晝素電極與閘極間電容值 Clc2 第二液晶電容值 Cpg2 第二晝素電極與閘極間電容值 Cst2 第二儲存電容值 Clc3 第三液晶電容值 Cst3 第三儲存電容值 Cgdl 第一閘極與汲極間電容值 40,42,44 步驟 Cgd2 第二閘極與汲極間電容值 46,48 步驟 Cgd3 第三閘極與汲極間電容值 50,52,54 步驟 Cpg3 第三晝素電極與閘極間電容值 22Clcl/Clc3. From another point of view, the first method can select the first-time main base to scale up or down the capacitance ratio of Cle3, cgd3, cst3, cpg3=^ - secondary material of the third element (Cpgl+Cgd). +Cgd~^ The electric valley ratio (Cpg3+Cgd3y(Cst3+Clc3+Cgd3+'^ 201202814), the Clc3, Cgd3, cst3, and cpg3 are adjusted separately to make the first pixel's electric valley ratio (cpg)丨+Cgd i )/(Cst丨+Cie 1+Cgd 1+cpg!) is substantially the same as the capacitance ratio of the third halogen (CPg3+Cgd3)/(Cst3+Cic3+Cgd3+CPg3). Similarly, The second way is not limited to the ratio of Clc丨/Cl. 3, that is, the ratio of Csti/Cst3, the ratio of cgdl/Cgd3, and the ratio of Cpgl/Cpg2 are not limited by Clcl/Cl. The elastic ratio can be adjusted to avoid the reduction of the aperture ratio caused by the intentional amplification of the area of the third storage electrode 223. It is noted that the present invention is not limited to forming three sub-pixels, but can be similar to the third The formation method of the sub-pixels further forms a fourth pixel. In other words, it can be deduced to form a plurality of sub-tendins. The three sub-genogens are used to display red, green, and blue, respectively, and are described in the first manner of adjusting the capacitance values in the above steps 44 and 52. In this embodiment, the first time P1 can be used to display red, the second pixel P2 can be used to display green, and the third pixel p3 can be used to display blue. The color formula is used to calculate the value of 'If you use the second: 昼素素· 212 is fresh and defined as 1, the area of the first-order halogen electrode 2i2 can be changed between kisses, and the area of the third halogen electrode 213 can be varied between 0.74 M. According to this, the mixed White light, the difference between the color QE coordinates Wx and Wy will not exceed 〇%, and can be accepted by the product specifications. The difference between Wx and Wy is the same as the red, green and blue sub-success in the same process. Comparing the 4 mt pieces of wood and the same common liquid material, the same common electrode, and the area of each elemental electrode between the phase electrode and the common electrode can determine the size of each liquid crystal capacitor. 44 and step 52 The first method of capacitance value - #卩卩可依Steps to reduce Cle2, Cgd2, Cst2, and 201202814 CPg2 to clcl, cgdl, cstl, and cpgl ratio can be changed between 0 25~1, and Ck3, Cgd3, Cst3, and Cpg3 are reduced to Qe丨, c The ratio of correction, ^, and & can vary from 0.74 to 1 to satisfy (CPgI + CgdI) / (Cstl + CIcl + Cgdl + Cpgl) > (Cpg2+Cgd2) / (Cst2 + Clc2 + Cgd2 +Cpg2) ^ and (C^+CgdMC^+c^+c^+Cpg3)" The ratio is substantially the same. - It is worth noting that, in the first-preferred implementation, the pixel electrode of the liquid crystal capacitor is overlying the gate electrode of the thin film transistor, the Cpg in the capacitance ratio definition cannot. Slightly, if the liquid electrode of the liquid capacitor has a sufficiently large distance from the gate electrode of the thin film transistor, then the value of cpg will be small enough to be ignored in the capacitance ratio definition. Please refer to Figure 6 and Figure 7. 6 is a partial equivalent circuit diagram of a pixel structure of the internal touch display panel of the second preferred embodiment of the present invention, and FIG. 7 is a green view of the second preferred embodiment of the present invention. A schematic diagram of a partial configuration of a pixel structure of an in-cell touch display panel. Here, the former is represented by an equivalent circuit diagram, the latter is represented by a configuration diagram, and the same elements are shown by the same symbols as in the first preferred embodiment. As shown in Figs. 6 and 7, in the second preferred embodiment, since the pixel electrode of the liquid crystal capacitor has a certain distance from the gate electrode of the thin film transistor, the value of Cpg is small. Therefore, in this embodiment, the ratio of the capacitance ratio value can be saved by $ ’ so that the capacitance ratio of each element is set to Cgd/(Cst+Cie+Cgd). Accordingly, the pixel structure of the in-cell touch display panel of the preferred embodiment and the method of forming the same are similar to the first preferred embodiment, and the difference is only to ignore cpg. In summary, the present invention can be used to reduce the brightness reduction to the slightest and achieve the minimum ratio of the ratio of the opening ratio of the three sub-pixels of the red scorpion, the green scorpion, and the 201202814 blue scorpion. The effect of uniform color mixing, and can avoid the extra sub-pixel electrical problem that may be derived when each element has a different aperture ratio. More specifically, in the case of different ratios of aperture ratios, the ratio of the feedthrough voltage ΔVp (feedthrough voltage) of red scorpion, green scorpion and blue scorpion may be too large. How to adjust the common voltage (Vcom), it is still impossible to make the liquid crystal cross-voltages of the positive and negative polarities of the three sub-pixels of red sub-halogen, green sub-tendin and blue sub-pixel simultaneously, in other words, if the Vcom voltage is adjusted The liquid crystal cross-pressure of the positive and negative polarities of one of the secondary monomers is equal, and the liquid crystal cross-pressure of the positive and negative polarities of the other two sub-pixels may still have a significant difference, thereby causing a problem of flickering of the facet. The pixel structure of the in-cell touch display panel of the present invention and the method for forming the same use the capacitance ratio (Cpg+Cgd)/(Cst+Clc+Cgd+Cpg)' of each pixel to make each pixel The capacitance ratio is substantially the same, which can effectively avoid the electrical problem of the secondary halogen, and can obtain a better picture effect. In addition, the thin film transistors corresponding to the different pixel areas of the present invention can have different sizes to effectively reduce the gate line load and reduce the leakage current. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional use of an in-cell touch sensing element in the prior art. FIG. 2 is a partial schematic diagram showing the equivalent circuit of the pixel 201202814 structure of the in-cell touch display panel according to the first preferred embodiment of the present invention. FIG. 3 is a partial view showing a partial configuration of a pixel structure of the in-cell touch display panel of the first preferred embodiment of the present invention. Fig. 4 is a flow chart showing a method of forming a pixel structure of an in-cell touch display panel according to a first preferred embodiment of the present invention. A flow chart of a method for forming another sixth element of the sixth layer structure of the in-cell touch display panel according to the first preferred embodiment of the present invention. Lutu, and a partial equivalent circuit diagram of the pixel structure of the in-cell touch display panel of the second preferred embodiment of the present invention. 1 is a partial schematic view showing a configuration of a pixel structure of an internal touch display panel according to a second preferred embodiment of the present invention. [Main component symbol description] Red sputum ^ ^ B blue 昼 昼 zero zero P1 flute first 昼 prime P3 goods third pixel 2 〇 1 ^ first 昼素区. 203 goods - the third time 昼Prime area 212 cargo second quadruple electrode 221 cargo first storage electrode 223 knot _ „ second storage electrode G green secondary halogen T touch sensing component P2 second pixel 200 substrate 202 second pixel area 211 first pixel electrode 213 third halogen electrode 222 second storage electrode 231 first thin film transistor 21 201202814 232 second thin film transistor 233 third thin film transistor 240 touch sensing element 250 common electrode C, Ci first liquid crystal capacitance value Qti first storage capacitance value Cpgl first halogen electrode and gate capacitance value Clc2 second liquid crystal capacitance value Cpg2 second halogen electrode and gate capacitance value Cst2 second storage capacitance value Clc3 Three liquid crystal capacitor values Cst3 Third storage capacitor value Cgdl First gate and drain capacitance values 40, 42, 44 Step Cgd2 Second gate and drain capacitance value 46, 48 Step Cgd3 Third gate and drain Capacitance value 50, 52, 54 Step Cpg3 Day capacitance value between the pixel electrode and the gate 22