201201346 六、發明說明： 【發明所屬之技術領域】 本發明係關於用以保護免於受因來自外部之靜電所致之 靜電放電（ESD: Electro Static Discharge)影響之 ESD 保護 電路及具備其之半導體裝置。 【先前技術】 一般言之，半導體積體電路（IC: Integrated Circuit)由 ESD產生之突波電壓較弱而易受破壞。因此，通常於1C内 設有用以保護1C免受突波電壓影響之ESD保護用電路。 作為ESD保護用電路之一例，提案有使用將NMOS電晶 體之閘極及源極連接於接地電位（GND)之閘接地（Gate Grounded)NMOS(ggNMOS)電晶體者。例如根據圖13所示 之電路例，係具備ggNMOS電晶體91作為靜電保護電路， 與被保護電路的内部電路92並聯連接之構成。 該ggNMOS電晶體91為了使閘極與源極短路，因此一般 於對信號線路SE施加一般之信號電壓Vin之狀態下顯示斷 開（off)狀態。但對該信號線路SE施加遠大於Vin之過電壓 Vsur時，ggNMOS電晶體91之没極與基板間之pn接合被逆 偏差而產生崩潰。此時，於汲極正下方產生碰撞電離，產 生多數之孔，因此基板之電位上升。若基板電位達到0.6 V，則將汲極作為集極，將源極作為射極，將半導體基板 作為基底之寄生雙極電晶體變成動作狀態（驟回動作）。利 用該動作，可將施加於汲極之過電壓Vsur經由寄生NPN雙 極電晶體向連接有源極之接地線VSS放電。其結果，信號 154441.doc 201201346 線SE之電魔下降至以集極·射極間電阻與集極電流之乘積 所規定之維持電壓Vh。因此，_VSur原來之高電流不 會流入内部電路92内，使内部電路92受到保護。 另寄生NI>N雙極電晶體進行動作，於汲極-源極間形 成電流徑路後，集極_射極間之電流.電壓一起上升，矽 内部之發熱達到石夕之熔點142〇〇c時，NM〇s電晶體遭破 壞。 利用該驟回現象之ESD保護元件作為低耐壓電路之保護 元件非常有效，但作為高耐壓電路之保護元件時具有如下 問題。 將ESD保護元件作為高耐壓電路之保冑元件加以利用 時，該ESD保護元件亦需要作為高耐壓元件之構成。將 ESD保護元件作為高耐壓元件之構成時，係藉由將該 ggNMOS電晶體之閘極電極形成於厚氧化膜上而實現❶一 般係將閘極電極端部配置於L〇c〇s(L〇ca丨〇xidati〇n Μ SUicon:局部氧化矽）氧化臈之上。若如此之構成下施加 過電壓Vsur，則位於該閘極電極端部下方iL〇c〇s氧化膜 之部份電場會集中，電子大量捕獲於厚氧化膜之缺陷層 中，會產生局部之漏電或破壞。其結果，可能引起驟回現 象產生後立即破壞ESD保護元件。 又，即使驟回現象產生後不立即破壞ESD保護元件，由 寄生雙極電晶體之動作，汲極_源極間之阻抗亦急速下 降’如前述’施加於ESD保護元件之電壓從過電壓Vsur下 降至維持電壓Vh。 154441.doc 201201346 通常’作為ESD保護元件形成之铍晶體之擴散結構係與 被保護元件所使用之電晶體相同之結構。假設被保護元件 之額定電壓比ESD保護元件之額定電壓高時，會因驟回動 作而破壞ESD保護元件。其理由係被保護元件之額定電高 於ESD保護元件之額定電壓時，前述維持電壓Vh低於被保 護疋件之額定電壓。但另一方面，從電源電路供給相當於 被保護元件之額定電壓之電源電壓。因此，對於由ESD保 護凡件形成之寄生雙極電晶體亦持續供給高於該維持電壓 之電源電壓，因此從電源電路向ESD保護元件流入過剩電 飢由此，因ESD保護元件内部之發熱而導致ESD保護元 件受破壞。為避免如此事態，維持電壓Vh&須設定為高於 被保護元件之額定電壓。 又，作為不利用驟回現象之ESD保護元件，有利用二極 體者但，將一極體作為ESD保護元件使用時，由於動作 時之接通（ON)電阻非常大，因此若為保護内部電路而欲流 動充分之電流，則欲使接通時之電阻下降則有必要增大二 極體之佔有面積，成為需要非常大之佈局面積。 欲解決如此問題，提案有以下所示之技術。 曰本特開2007-242923號公報（以下稱為專利文獻丨）所揭 示之ESD保濩元件之構成顯示於圖丨4。圖1 *所示之Μ。保 善電路1GG之特徵在於.自形成集極接觸層之高濃度n型雜 質擴散層（N層）1〇7之下方到達場（field)氧化膜1〇8下方設 置高濃度N型(矿層)沉降層1〇3,充分確保該水平方向之寬 度X。 154441.doc 201201346 更詳細言之，ESD保護電路100於P型基板101上形成N型 磊晶層102，從該表面形成N+塑沉降層103。又，於N型磊 晶層102表面，從N+型沉降層103向水平方向遠離，形成有 成為基底之低濃度P型雜質擴散層（P·層）104 '高濃度p型雜 質擴散層（P+層）105。於P+層105中形成成為射極之高濃度 N型雜質擴散層（N++層）106。又，於N+型沉降層1〇3上具有 接觸用N++層107，在該N++層107與N++層106之間具有場氧 化膜108 » 若對圖14所示之ESD保護元件施加過電壓，則於以p-層 104與N+型沉降層103之分離所決定之耐壓（崩潰電壓）下崩 潰。利用此時所流動之電流，寄生NPN雙極電晶體開始電 晶體動作’從集極向射極流動電流。更具體言之，因電晶 體動作而流動之電流從集極接觸N++層1 07通過位於場氧化 膜108下方之N+型沉降層103，利用N型磊晶層1〇2、p-層 104、P+層1〇5、N++層106之路徑而向射極流動。 如圖14所示，使N+型沉降層103之一部份形成為位於場 氧化膜108之下方，擴大其形成寬度X從而於N+型沉降層 1〇3中形成嵌入電阻（Embedded Resistor)，於該區域内產生 電壓下降。藉此，與在場氧化膜108下方無高濃度N型沉降 層103之區域之情形相比，可實現維持電壓^^之高電壓 化。 曰本特開2007-227697號公報（以下稱為專利文獻2)中所 揭示之ESD保護元件及包含其之半導體裝置之構成顯示於 圖15。圖15所示之ESD保護元件ι1〇之特徵係如下之點： 154441.doc • 6 · 201201346 除ggNMQS電晶體⑴外，亦具備與其串聯之基底為開放之 雙極電晶體112。 更詳細言之，NM0S電晶體117與㈣保護元件…並聯 連接’間極與驅動電路116連接，没極經由負載ιΐ9與電源 V。連接’源極與接地線連接。咖保護元件㈣係串聯聯 接有基底為開放之卿型雙極電晶體112與娜刪電晶體 111 NPN型雙極電晶體Π2之集極與NM0S電晶體丨i 7之汲 極連接，射極與ggNMOS電晶體U1之汲極連接。 電晶體111之閘極及源極與接地線連接。又118係輸出端 子。 如此構成時，ESD保護元件11〇之耐壓規定為雙極電晶 體112之耐壓與ggNM〇s電晶體lu之耐壓之和。此情形 時，崩潰後之ESD保護元件之兩端間之維持電壓vh成為由 ggNMOS電晶體lu形成之寄生雙極觉晶體之集極·射極間 電壓與雙極電晶體H2之集極_射極間之電壓之和。藉此， 與雙極電晶體112不存在之情形相比，可謀求維持電壓％ 之高電壓化。 但，專利文獻1之情形中，藉由擴大N+型沉降層103之形 成寬度而寄生電阻增加’因此施加突波電壓時無法流通用 於内部電路保護之充分電流，結果有保護能力下降之虞。 並且，作為該對策需要增大保護元件其尺寸並使電阻值下 降，其必然導致ESD保護元件之佈局面積擴大之結果。 又，專利文獻2之情形中，作為ESD保護元件除ggNM〇s 電晶體外另需要雙極電晶體，因此與只以ggNM〇s電晶體 154441.doc 201201346 實現ESD保護元件之情形相比，結果當然不得不擴大佈局 面積。 【發明内容】 本發明鑑於上述問題，提供一種ESD保護電路及具備其 之半導體裝置’該ESD保護電路具有對於從低耐壓電路至 高财壓電路之各電路之ESD保護功能，並且可以小佈局面 積實現。 為達成上述目的’本發明之ESD保護電路之第1特徵在 於：其係設於具備複數之不同電源電壓之電源端子之半導 體裝置上之ESD保護電路，且包含： 第1ESD保護元件，其一端與第}電源端子所連接之第1 節點連接’另一端與接地線連接，且與半導體基板電性分 離； 第2ESD保護元件，其一端與比前述第1電源端子更高電 壓之第2電源端子所連接之第2節點連接’另一端與前述第 1節點連接，且與半導體基板電性分離。 又’本發明之ESD保護電路除上述特徵外，其第2特徵 在於：前述複數之電源端子與各不相同之節點連接， 於所連接之電源端子之電壓值相差1階之1組節點之間耳 備ESD保護元件，該ESD保護元件之一端與高電壓側之節 點連接’另一端與低電壓側之節點連接，且與半導體基板 電性分離， 前述ESD保護元件設於電壓值相差1階之各組節點之 間。 154441.doc 201201346 ，則述各個ESD保護元件可由具備複數個進行驟回動作之 半導體το件、二極體、或該等之一方或兩方之串聯電路所 構成。作為進行驟回動作之半導體元件之—例可利用使 閘極與源極短路之M〇s電晶體（ggM〇s)、連接有射極與基 底之雙極電晶體。 土 又，本發明之半導體裝置之特徵在於，具備： ESD保護電路’其具有上述第i特徵；p被保護元件， 其一端與前述第丨節點連接，另一端與前述接地線連接； 第2被保護元件’其一端與前述第2節點連接’另—端與前 述接地線連接；且 前述第2被保護元件係比前述第保護元件更高財壓之 元件。 又本發明之半導體裝置之特徵在於，具備： ESD保護電路，其具有上述第2特徵；及在前述各節點 與前述接地線之間之耐壓各不相同之被保護元件， 前述被保護元件係自與連接於該被保護元件之前述節點 連接之電源端子之輸出電壓越高則越高耐壓之元件。 根據本發明之ESD保護電路，假設施加過電壓，經由該 保護電路流通突波電壓之情形中，其後施加有過電壓之^ 點與接地線間所產生之維持電壓成為形成於該節點與接地 線間之各ESD保護元件兩端之維持電壓之合計。藉此，無 需提高各ESD保護元件之維持電壓，即可於過電麼施加後 之節點確保高電壓。使該電壓值為高於被保護元件之額定 電麼之值，從❼可防止從電源電路對咖保護元件產生過 15444I.doc 201201346 電流而使該元件遭受破壞。 並且，根據該構成’並I必要如專利文⑴之於射極·集 極間設置水平方向之隔離，因此不會導致佔有面積之擴 大。 又，可對連接各ESD保護元件之節點連接各耐壓不同之 被保護元件。即，可對連接於輸出電壓低之電源端子之節 點連接低耐壓被保護元件，對連接於輸出電壓高之電源端 子之節點連接高耐壓被保護元件。此時，與連接於輸出電 壓低之電源端子之節點連接之ESD保護元件亦作為對於低 耐壓被保護元件之ESD保護元件發揮功能，亦作為對於高 耐壓被保護元件之ESD保護元件之一部份發揮功能。 即，與配合耐壓高之元件進行ESD保護設計之情形相 比，可將各ESD保護元件之耐壓抑制為較低。例如專利文 獻2之情形中，係對各ESD保護元件利用ggNMOS電晶體與 雙極電晶體之串聯電路實現之構成，因此各ESD保護元件 之尺寸必然變大。但本發明構成之情形中，作為高耐壓用 保護元件，係兼用低耐壓用保護元件之構成，因此即使係 使用複數之保護元件之構成亦可將其尺寸之擴大抑制為最 小限度。 【實施方式】 以下，針對本發明之實施形態，參照附圖詳細說明。 圖1係顯示本發明之半導體裝置之概念之概念方塊圖。 圊1所示之半導體裝置1具有不同電源電壓之複數之電源端 子（VCC_h，VCC一m，VCC_1)。 154441.doc •10- 201201346 節點NH與高電壓之電源端早vrr u β & λ. % r而t VLC—h連接，節點NL與比 vcc_h低電壓之電源端子vcr】鱼梂 ^ 响丁 丨連接。又，節點NM與比 VCC h低電壓且比VCC 1其f - 私 H-i间電壓之中間電壓之電源端子 VCC m連接。 圖丨所示之半導體裝置丨具備：被保護元件16，其作為内 部電路，利用自高電壓輸出用電源電子vcc h供給之電壓 作為電源電壓；被保護元件17，其利用自中間電壓輸出用 電源電子VCC_m供給之電㈣μ#電壓；被保護元件 18，其利用自低電壓輸出用電源電子VCCJ供給之電壓作 為電源電壓。被料元件16、17、18係作為電源電壓以該 順序施加高電壓之構成，額定電壓亦以該順序增高。 本發明之半導體裝置1係以於施加不同電壓之各節點間 分別設置ESD保護元件為特徵之構成。即，如圖i所示， 半導體裝置1所具備之ESD保護電路1〇具有：第1£51)保護 兀件11，其設於高電壓節點NH與中間電壓節點NM之間； 第2ESD保護元件12，其設於中間電壓節點NM與低電壓節 點NL之間；第3ESD保護元件13，其設於低電壓節點1^與 接地線VSS之間。另，該等ESD保護元件丨〗〜^均與半導體 基板電性分離。 如圖1構成之情形中，低耐壓被保護元件18係利用esd 保護元件13保護其免於受ESD影響，中耐壓被保護元件i7 係利用ESD保護元件丨2及丨3之串聯連接保護其免於受esd 影響，高耐壓被保護元件16係利用ESD保護元件u、i2、 13之_聯連接保護其免於受ESd影響。 154441.doc 201201346 從高電壓之電源端子VCC_h施加突波電壓¥3111'_11時，使 突波電流依序通過ESD保護元件11、ESD保護元件12、 ESD保護元件13而流向接地線VSS。藉此，無需對高耐壓 被保護元件16施加突波電壓Vsur_h，即可使節點NH與接 地線VSS間之電壓瞬間下降，使被保護元件16受到保護。 另，藉由突波電流流通，從而於接地線VSS與節點NH間產 生之電壓從突波電壓Vsur_hT降至由ESD保護元件13之維 持電壓Vhl3、ESD保護元件12之維持電壓Vhl2、及ESD保 護元件11之維持電壓Vhl 1之和所規定之維持電壓Vhl。 同樣，從中間電壓之電源端子VCC_m施加突波電壓 Vsur_mi情形時，使突波電流依序通過ESD保護元件12、 ESD保護元件13而流向接地線VSS。藉此，無需對中間耐 壓之被保護元件1 7施加突波電壓Vsur_m，即可使節點NM 與接地線VSS間之施加電壓瞬間下降，使被保護元件17受 到保護。另，藉由突波電流流通，從而於接地線VSS與節 點NM間產生之電壓從突波電壓Vsur_mT降至由ESD保護 元件13之維持電壓Vhl3及ESD保護元件12之維持電壓Vhl2 之和所規定之維持電壓Vh2。 同樣，從低電壓之電源端子VCC_1施加突波電壓Vsur_l 時，突波電流通過ESD保護元件13流向接地線VSS。藉 此，無需對低耐壓被保護元件1 8施加突波電壓Vsur_l，即 可使節點NL與接地線VSS間之施加電壓瞬間下降，使被保 護元件18受到保護。另，突波電流流通從而於接地線VSS 與節點NL間產生之電壓從突波電壓Vsur_l降低為ESD保護 154441.doc 12 201201346 元件13之維持電壓Vh 13。 如上述，被保護S件為高耐屡時，需要將突波電流流通 後之維持電壓提高至某程度。此處,,如前述，連接高耐壓 破保護兀件16之節點NH與接地線vss間之維持電壓Vhl、 連接中耐壓被保護元件17之節點NM與接地線vss間之維 持電壓Vh2、連接低耐壓被保護元件18之節點NL與接地線 VSS間之維持電壓Vh3分別如下述數】表示。 (數1)201201346 VI. Description of the Invention: [Technical Field] The present invention relates to an ESD protection circuit and a semiconductor having the same effect for protecting against electrostatic discharge (ESD) caused by external static electricity (ESD) Device. [Prior Art] In general, a semiconductor integrated circuit (IC: Integrated Circuit) has a weak surge voltage generated by an ESD and is susceptible to damage. Therefore, an ESD protection circuit for protecting the 1C from the surge voltage is usually provided in the 1C. As an example of the ESD protection circuit, a gate grounded NMOS (ggNMOS) transistor in which the gate and the source of the NMOS transistor are connected to the ground potential (GND) is proposed. For example, according to the circuit example shown in Fig. 13, a ggNMOS transistor 91 is provided as an electrostatic protection circuit, and is connected in parallel to the internal circuit 92 of the protected circuit. In order to short-circuit the gate and the source, the ggNMOS transistor 91 generally displays an off state in a state where a normal signal voltage Vin is applied to the signal line SE. However, when the overvoltage Vsur which is much larger than Vin is applied to the signal line SE, the pn junction between the gate of the ggNMOS transistor 91 and the substrate is reversely deviated to cause collapse. At this time, collision ionization occurs immediately below the crucible, and a large number of holes are generated, so that the potential of the substrate rises. When the substrate potential reaches 0.6 V, the drain is used as the collector, the source is used as the emitter, and the parasitic bipolar transistor having the semiconductor substrate as the base is brought into an operating state (snap-back operation). By this action, the overvoltage Vsur applied to the drain can be discharged to the ground line VSS connected to the source via the parasitic NPN bipolar transistor. As a result, the signal 154441.doc 201201346 line SE is reduced to the sustain voltage Vh defined by the product of the collector-emitter resistance and the collector current. Therefore, the original high current of _VSur does not flow into the internal circuit 92, so that the internal circuit 92 is protected. In addition, the parasitic NI>N bipolar transistor operates, and after the current path is formed between the drain and the source, the current between the collector and the emitter rises, and the internal heat of the crucible reaches the melting point of the stone 142. At c, the NM〇s transistor is destroyed. The ESD protection element using this snapback phenomenon is very effective as a protection element of a low withstand voltage circuit, but has the following problems as a protection element of a high withstand voltage circuit. When an ESD protection element is used as a protection element of a high withstand voltage circuit, the ESD protection element also needs to be a high withstand voltage element. When the ESD protection element is configured as a high withstand voltage element, the gate electrode of the ggNMOS transistor is formed on the thick oxide film, and the gate electrode portion is disposed at L〇c〇s. L〇ca丨〇xidati〇n Μ SUicon: Topical ruthenium oxide). If the overvoltage Vsur is applied in such a configuration, a part of the electric field of the oxide film located below the end of the gate electrode is concentrated, and a large amount of electrons are trapped in the defect layer of the thick oxide film, causing local leakage. Or destroy. As a result, the ESD protection component may be destroyed immediately after the occurrence of a snapback. Moreover, even if the ESD protection element is not destroyed immediately after the occurrence of the snapback phenomenon, the impedance between the drain and the source is rapidly decreased by the action of the parasitic bipolar transistor. 'As described above, the voltage applied to the ESD protection element is from the overvoltage Vsur. Drop to the sustain voltage Vh. 154441.doc 201201346 Usually, the diffusion structure of a germanium crystal formed as an ESD protection element is the same as that of the transistor used for the protection element. Assuming that the rated voltage of the protected component is higher than the rated voltage of the ESD protection component, the ESD protection component is destroyed by a snap action. The reason is that when the rated power of the protected component is higher than the rated voltage of the ESD protection component, the aforementioned sustain voltage Vh is lower than the rated voltage of the protected component. On the other hand, a power supply voltage corresponding to the rated voltage of the protected component is supplied from the power supply circuit. Therefore, the parasitic bipolar transistor formed by the ESD protection device also continuously supplies a power supply voltage higher than the sustain voltage, so that excessive power is generated from the power supply circuit to the ESD protection element, and the heat is generated inside the ESD protection element. Causes damage to the ESD protection component. To avoid this, the sustain voltage Vh& must be set higher than the rated voltage of the protected component. In addition, as an ESD protection element that does not use a snapback phenomenon, when a diode is used as an ESD protection element, the ON resistance is extremely large during operation, so that the internal resistance is protected. If the circuit wants to flow a sufficient current, it is necessary to increase the occupied area of the diode when the resistance is lowered at the time of turning on, which requires a very large layout area. To solve this problem, the proposal has the technology shown below. The configuration of the ESD protection element disclosed in Japanese Laid-Open Patent Publication No. 2007-242923 (hereinafter referred to as "Patent Document") is shown in Fig. 4. Figure 1 * shows the flaw. The good-keeping circuit 1GG is characterized in that a high-concentration N-type (mineral layer) is disposed below the field oxide film 1〇8 from the high-concentration n-type impurity diffusion layer (N layer) 1〇7 forming the collector contact layer. The sedimentation layer 1〇3 sufficiently ensures the width X of the horizontal direction. 154441.doc 201201346 In more detail, the ESD protection circuit 100 forms an N-type epitaxial layer 102 on the P-type substrate 101, and forms an N+ plastic sink layer 103 from the surface. Further, on the surface of the N-type epitaxial layer 102, the N+ type sedimentation layer 103 is separated from the horizontal direction, and a low-concentration P-type impurity diffusion layer (P·layer) 104' which is a base is formed, and a high-concentration p-type impurity diffusion layer (P+) is formed. Layer) 105. A high-concentration N-type impurity diffusion layer (N++ layer) 106 serving as an emitter is formed in the P+ layer 105. Further, a N++ layer 107 for contact is provided on the N+ type sinker layer 1〇3, and a field oxide film 108 is provided between the N++ layer 107 and the N++ layer 106. If an overvoltage is applied to the ESD protection element shown in FIG. The breakdown is caused by the withstand voltage (crash voltage) determined by the separation of the p-layer 104 and the N+ type sedimentation layer 103. With the current flowing at this time, the parasitic NPN bipolar transistor starts the transistor operation 'flowing current from the collector to the emitter. More specifically, the current flowing due to the operation of the transistor passes through the collector contact N++ layer 107 through the N+ type sinker layer 103 under the field oxide film 108, and the N type epitaxial layer 1〇2, p-layer 104, The path of the P+ layer 1〇5, the N++ layer 106 flows toward the emitter. As shown in FIG. 14, a portion of the N+ type sinker layer 103 is formed to be located below the field oxide film 108, and the width X thereof is enlarged to form an embedded resistor in the N+ type sinker layer 1〇3. A voltage drop occurs in this area. Thereby, the voltage of the sustain voltage can be increased as compared with the case where the region of the N-type sinker layer 103 is not present under the field oxide film 108. The configuration of the ESD protection element and the semiconductor device including the same disclosed in Japanese Laid-Open Patent Publication No. 2007-227697 (hereinafter referred to as Patent Document 2) is shown in Fig. 15. The ESD protection component ι1〇 shown in Fig. 15 is characterized as follows: 154441.doc • 6 · 201201346 In addition to the ggNMQS transistor (1), it also has a bipolar transistor 112 which is open in series with the substrate. More specifically, the NMOS transistor 117 and the (4) protection device are connected in parallel with each other and connected to the driving circuit 116, and the terminal is connected to the power supply V via the load ΐ9. The connection 'source' is connected to the ground wire. The coffee protection component (4) is connected in series with a base-type open bipolar transistor 112 and a nano-deleted transistor 111. The NPN-type bipolar transistor Π2 is connected to the NM0S transistor 丨i 7 and the emitter is connected. The drain of the ggNMOS transistor U1 is connected. The gate and source of the transistor 111 are connected to the ground line. Another 118 series output terminal. In such a configuration, the withstand voltage of the ESD protection element 11 is defined as the sum of the withstand voltage of the bipolar transistor 112 and the withstand voltage of the ggNM〇s transistor lu. In this case, the sustain voltage vh between the two ends of the ESD protection element after the collapse becomes the collector-emitter voltage of the parasitic bipolar crystal formed by the ggNMOS transistor lu and the collector of the bipolar transistor H2. The sum of the voltages between the poles. Thereby, it is possible to maintain a higher voltage of the voltage % than in the case where the bipolar transistor 112 does not exist. However, in the case of Patent Document 1, the parasitic resistance is increased by enlarging the formation width of the N+ type sedimentation layer 103. Therefore, when a surge voltage is applied, a sufficient current cannot be shared with the internal circuit protection, and as a result, the protection ability is lowered. Further, as this countermeasure, it is necessary to increase the size of the protective element and to lower the resistance value, which inevitably leads to an increase in the layout area of the ESD protection element. Further, in the case of Patent Document 2, as the ESD protection element, a bipolar transistor is required in addition to the ggNM〇s transistor, and thus the result is compared with the case where the ESD protection element is realized only by the ggNM〇s transistor 154441.doc 201201346. Of course, I have to expand the layout area. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides an ESD protection circuit and a semiconductor device having the same. The ESD protection circuit has an ESD protection function for each circuit from a low withstand voltage circuit to a high-voltage circuit, and can be small in layout. Area realization. In order to achieve the above object, a first feature of the ESD protection circuit of the present invention is an ESD protection circuit provided on a semiconductor device having a plurality of power supply terminals of different power supply voltages, and includes: a first ESD protection element, one end of which is The first node connection to which the power supply terminal is connected is connected to the ground line and electrically separated from the semiconductor substrate. The second ESD protection element has a second power supply terminal having a higher voltage than the first power supply terminal. The second node connected to the connection is connected to the first node and electrically separated from the semiconductor substrate. Further, in addition to the above features, the ESD protection circuit of the present invention is characterized in that the plurality of power supply terminals are connected to different nodes, and the voltage values of the connected power supply terminals differ by one step between the nodes of the first order. The earphone is provided with an ESD protection component, one end of the ESD protection component is connected to the node on the high voltage side, and the other end is connected to the node on the low voltage side, and is electrically separated from the semiconductor substrate. The ESD protection component is disposed at a difference of 1 step of the voltage value. Between each group of nodes. 154441.doc 201201346, the respective ESD protection elements may be composed of a plurality of semiconductor devices, diodes, or a series circuit of one or both of them for performing a snapback operation. As the semiconductor element for performing the snapback operation, an M?s transistor (ggM?s) which short-circuits the gate and the source, and a bipolar transistor to which the emitter and the substrate are connected can be used. Further, the semiconductor device of the present invention is characterized by comprising: an ESD protection circuit having the above i-th feature; and a p-protected element having one end connected to the second node and the other end connected to the ground line; The protective element 'connects one end to the second node' and the other end is connected to the ground line; and the second protected element is a higher-voltage component than the first protection element. Further, the semiconductor device of the present invention includes: an ESD protection circuit including the second feature; and a protected element having a different withstand voltage between each of the nodes and the ground line, wherein the protected element is The higher the output voltage of the power supply terminal connected to the aforementioned node connected to the protected element, the higher the withstand voltage component. According to the ESD protection circuit of the present invention, in the case where an overvoltage is applied and a surge voltage is applied through the protection circuit, a sustain voltage generated between the point where the overvoltage is applied and the ground line is formed at the node and the ground. The sum of the sustain voltages across the ESD protection elements between the lines. Thereby, it is possible to ensure a high voltage at the node after the application of the power supply without increasing the sustain voltage of each of the ESD protection elements. The voltage value is higher than the rated value of the protected component, and the component can be prevented from being damaged by the current of the power supply circuit from the 15444I.doc 201201346. Further, according to this configuration, it is necessary to provide isolation in the horizontal direction between the emitter and the collector as in Patent (1), so that the enlargement of the occupied area is not caused. Further, it is possible to connect the protected elements having different withstand voltages to the nodes connecting the respective ESD protection elements. That is, a low withstand voltage protected element can be connected to a node connected to a power supply terminal having a low output voltage, and a high withstand voltage protected element can be connected to a node connected to a power supply terminal having a high output voltage. At this time, the ESD protection element connected to the node connected to the power supply terminal having a low output voltage functions as an ESD protection element for the low withstand voltage protected element, and also serves as one of the ESD protection elements for the high withstand voltage protected element. Part of the function. That is, the withstand voltage of each ESD protection element can be suppressed to be lower than when the ESD protection design is performed with a component having a high withstand voltage. For example, in the case of Patent Document 2, each ESD protection element is realized by a series circuit of a ggNMOS transistor and a bipolar transistor, and therefore the size of each ESD protection element is inevitably large. However, in the case of the configuration of the present invention, since the protection element for the high withstand voltage is also composed of the protection element for the low withstand voltage, the expansion of the size can be minimized even if the configuration of the plurality of protection elements is used. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a conceptual block diagram showing the concept of a semiconductor device of the present invention. The semiconductor device 1 shown in 圊1 has a plurality of power supply terminals (VCC_h, VCC_m, VCC_1) of different power supply voltages. 154441.doc •10- 201201346 Node NH and high voltage power supply terminal early vrr u β & λ. % r and t VLC—h connection, node NL and lower voltage power supply terminal vcr than vcc_h】fish 梂^ 丨 丨connection. Further, the node NM is connected to the power supply terminal VCC m which is lower than VCC h and which is higher than the intermediate voltage of the voltage between V CC 1 and f - private H-i. The semiconductor device shown in FIG. 丨 includes a protected element 16 as an internal circuit, using a voltage supplied from a high voltage output power supply electronic vcc h as a power supply voltage, and a protected element 17 using a power supply from an intermediate voltage output. The electric (four) μ# voltage supplied to the electronic VCC_m; the protected element 18 uses the voltage supplied from the low-voltage output power supply electronic VCCJ as the power supply voltage. The material to be coated 16, 17, and 18 are configured to apply a high voltage as a power source voltage in this order, and the rated voltage is also increased in this order. The semiconductor device 1 of the present invention is characterized in that an ESD protection element is provided between each node to which a different voltage is applied. That is, as shown in FIG. 1, the ESD protection circuit 1 of the semiconductor device 1 has a first £51) protection element 11 provided between the high voltage node NH and the intermediate voltage node NM; the second ESD protection element 12, which is disposed between the intermediate voltage node NM and the low voltage node NL; and a third ESD protection component 13 disposed between the low voltage node 1^ and the ground line VSS. In addition, the ESD protection components are electrically separated from the semiconductor substrate. In the case of the configuration of Fig. 1, the low withstand voltage protected element 18 is protected from ESD by the esd protection element 13, and the medium withstand voltage protected element i7 is protected by the series connection of the ESD protection elements 丨2 and 丨3. It is protected from esd, and the high withstand voltage protected element 16 is protected from ESd by the ESD protection element u, i2, 13 connection. 154441.doc 201201346 When the surge voltage ¥3111'_11 is applied from the high-voltage power supply terminal VCC_h, the surge current flows through the ESD protection element 11, the ESD protection element 12, and the ESD protection element 13 to the ground line VSS. Thereby, it is not necessary to apply the surge voltage Vsur_h to the high withstand voltage protected element 16, so that the voltage between the node NH and the ground line VSS can be instantaneously lowered, and the protected element 16 can be protected. Further, by the surge current flowing, the voltage generated between the ground line VSS and the node NH is lowered from the surge voltage Vsur_hT to the sustain voltage Vhl3 of the ESD protection element 13, the sustain voltage Vhl2 of the ESD protection element 12, and ESD protection. The sustain voltage Vhl specified by the sum of the sustain voltages Vhl1 of the elements 11. Similarly, when the surge voltage Vsur_mi is applied from the power supply terminal VCC_m of the intermediate voltage, the surge current is sequentially passed through the ESD protection element 12 and the ESD protection element 13 to the ground line VSS. Thereby, it is not necessary to apply the surge voltage Vsur_m to the intermediate-voltage-protected element 17 to instantaneously drop the applied voltage between the node NM and the ground line VSS, and the protected element 17 is protected. Further, by the surge current flowing, the voltage generated between the ground line VSS and the node NM is reduced from the surge voltage Vsur_mT to the sum of the sustain voltage Vhl3 of the ESD protection element 13 and the sustain voltage Vhl2 of the ESD protection element 12. The sustain voltage Vh2. Similarly, when the surge voltage Vsur_1 is applied from the low voltage power supply terminal VCC_1, the surge current flows through the ESD protection element 13 to the ground line VSS. Therefore, it is not necessary to apply the surge voltage Vsur_1 to the low withstand voltage protected element 18, that is, the applied voltage between the node NL and the ground line VSS is instantaneously lowered, and the protected element 18 is protected. In addition, the surge current flows so that the voltage generated between the ground line VSS and the node NL is reduced from the surge voltage Vsur_l to the ESD protection 154441.doc 12 201201346 The sustain voltage Vh 13 of the component 13. As described above, when the protected S-piece is highly resistant, it is necessary to increase the sustain voltage after the surge current flows to a certain extent. Here, as described above, the sustain voltage Vhl between the node NH of the high withstand voltage breaking protection member 16 and the ground line vss, and the sustain voltage Vh2 between the node NM and the ground line vss of the withstand voltage protected element 17 are connected. The sustain voltage Vh3 between the node NL connected to the low withstand voltage protected element 18 and the ground line VSS is represented by the following number. (Number 1)
Vhl=Vhl3+Vhl2+Vhl 1Vhl=Vhl3+Vhl2+Vhl 1
Vh2=Vhl3+Vhl2Vh2=Vhl3+Vhl2
Vh3=Vhl3 破保護元件於額定電壓越高當然耐壓亦設定越高。並 且，根據數1，係耐壓越高之被保護元件其維持電壓越高 之構成。藉此，選擇使用Vhll、Vhl2、Vhl3顯示適當值 之ESD保護元件，從而突波電流向接地線vss洩出後，亦 可將各節點NH、NM、NL之電壓（維持電壓）設定於連接於 各節點之被保護元件（16〜18)之額定電壓以上。藉由如此 δ又疋’可防止突波電流向接地線VSS洩出後，從施加電源 電壓之各電源端子（VCC_h、VCC_m、VCC_1)對ESD保護 元件流通過電流。 本發明構成之情形中，將對於低耐壓被保護元件〗8之 ESD保護元件13兼用作為對於中耐壓被保護元件17及高耐 壓被保護元件16之ESD保護元件之一部份，將對於中耐壓 被保護元件17之ESD保護元件12兼用作為對於高耐壓被保 154441.doc 13 201201346 護元件16之ESD保護元件之一部份。 藉此’對高财壓被保護元件16經由節點NH施加過電壓 時，該節點NH與接地線VSS間之耐壓Vtl規定為ESD保護 元件11之耐壓Vtl 1、ESD保護元件12之耐壓Vt2、ESD保護 元件13之耐壓Vtl3之和。同樣，對中耐壓被保護元件17經 由節點NM施加過電壓時，該節點NM與接地線VSS間之耐 壓Vt2規定為ESD保護元件12之耐壓Vtl2與ESD保護元件l3 之耐壓Vtl3之和》再者’對低耐壓被保護元件18經由節點 NL施加過電壓時，該節點NL與接地線VSS間之耐壓Vt3規 疋為E S D保護元件13之对壓V113。將其歸總以如下數2表 示0 (數2)Vh3=Vhl3 The higher the rated voltage of the broken protection component, the higher the withstand voltage is also set. Further, according to the number 1, the protected element having a higher withstand voltage has a higher holding voltage. Therefore, it is selected to use Vhll, Vhl2, and Vhl3 to display an appropriate value of the ESD protection element, so that the surge current can be discharged to the ground line vss, and the voltages (sustain voltages) of the respective nodes NH, NM, and NL can be set to be connected to The rated voltage of the protected components (16 to 18) of each node is greater than or equal to. By such δ and 疋', the surge current can be prevented from leaking to the ground line VSS, and the current is supplied to the ESD protection element from the respective power supply terminals (VCC_h, VCC_m, VCC_1) to which the power supply voltage is applied. In the case of the present invention, the ESD protection element 13 for the low withstand voltage protected element 8 is also used as part of the ESD protection element for the medium withstand voltage protected element 17 and the high withstand voltage protected element 16. The ESD protection element 12 for the medium withstand voltage protected element 17 also serves as part of the ESD protection element for the high withstand voltage protection 154441.doc 13 201201346 protection element 16. Therefore, when the high-voltage-voltage-protected component 16 is applied with an overvoltage via the node NH, the withstand voltage Vtl between the node NH and the ground line VSS is defined as the withstand voltage Vtl1 of the ESD protection element 11, and the withstand voltage of the ESD protection element 12. Vt2, the sum of the withstand voltage Vtl3 of the ESD protection element 13. Similarly, when the intermediate withstand voltage is protected by the node NM, the withstand voltage Vt2 between the node NM and the ground line VSS is defined as the withstand voltage Vtl2 of the ESD protection element 12 and the withstand voltage Vtl3 of the ESD protection element l3. When the low withstand voltage protected element 18 applies an overvoltage via the node NL, the withstand voltage Vt3 between the node NL and the ground line VSS is the voltage V113 of the ESD protection element 13. Put it back together as the following number 2 to indicate 0 (number 2)
Vtl=Vtl3+Vtl2+Vtl 1Vtl=Vtl3+Vtl2+Vtl 1
Vt2=Vtl3+Vtl2Vt2=Vtl3+Vtl2
Vt3=Vtl3 即’根據本發明之構成’高耐壓被保護元件16用£§〇保 護元件之耐壓（驟回電壓）係以3個保護元件（u、12、13)之 耐壓之合計予以規定’因此無需設計各保護元件作為高耐 壓元件。即，假設以ggNMOS電晶體形成保護元件時，無 需使該電晶體之閘極電極下方之氧化膜厚膜化，因此突波 電壓施加時產生局部漏電或破壞之虞降低。 又，與配合最高耐壓之被保護元件進行ESD保護設計時 相比’可對應被保護元件之财壓而縮小E § D保護元件之尺 寸’因此有助於全體之佈局佔有面積之縮小。 154441 .doc •14· 201201346 圖2係顯示以電路圖表現圖丨所示之方塊圖之一例。又， 將此時之ESD保護電路10之概要剖面結構圖顯示於圖3。 圖2、圖3係針對採用ggNM〇s電晶體（TH、TM、tl)作為 ESD保護元件11、12、13時之圖示。 ESD保護電路10形成於p型半導體基板21上。對於esd保 5蔓元件11及ESD保護元件12，將深N型井22(42)設於基板21 上，於該井内進而形成N型井^㈠”與卩型井24(44)。對於 ESD保護元件13，於基板21上形成有；^型井53與p型井54。 於P型井24(44、54)内之表面區域具有成為源極之高濃 度N型雜質擴散區域25(45、55)、接觸用高濃度p型雜質擴 散區域26(46、56)，以跨過N型井23(43、53)與p型井 24(44、54)之方式具有成為汲極之高濃度^^型雜質擴散區 域27(47、57)。又，於以場氧化膜31包圍之基板上之活性 區域形成閘極氧化膜28，於其上層中，於以源極25(45、 55)與汲極27(47、57)夾持之區域上方位置形成有閘極電極 29 〇 高電壓輸出用電源端子VCC—h與汲極27連接。又，中間 電壓輸出用電源端子VCC_m與汲極47連接，且與高耐壓之 ESD保護元件11之閘極電極29、源極25、接觸器26連接》 低電壓輸出用電源端子VCC一1與汲極5 7連接且與中耐壓之 ESD保護元件12之閘極電極29、源極45、接觸器46連接。 另，圖2中，ESD保護電路10内所圖示之二極體係以 灰N型井22與P型半導體基板21構成，二極體dm係以深n 型井42與P型半導體基板21構成。 154441.doc 15- 201201346 如此構成之情形中，無須如圖14之於源極_汲極間設置 較大水平方向之分離距離，因此無需對欲減少寄生電阻之 保濩兀件增大其尺寸。又，如上述，作為對於高耐壓被保 護元件16之ESD保護電路1〇之耐壓，係以ESD保護元件 11、12、13各耐壓之合計，即ggNMOOS電晶體ΤΗ、TM、 TL之耐壓之合計加以規定，因此對各電晶體之耐壓設計為 較低，亦可確保充分高之耐壓。 圖4係顯示對於圖2所示之ESD保護電路1〇之 TLP(Transmission Line Pulsing:傳輸線脈衝）評估實測資 料。圖4内F一1係顯示於將ESD保護元件以1段連接時，即 節點NL與接地線VSS間之施加電壓與電流之關係之曲線。 F_m係顯示於將ESD保護元件以2段連接時，即節點NM與 接地線VSS間之施加電壓與電流之關係之曲線。F_h係顯 示將ESD保護元件以3段連接時，即節點NH與接地線VSS 間之施加電壓與電流之關係之曲線。 根據圖4 ’可知於1段連接時之ESD保護元件耐壓（驟回電 壓）最低，以下隨著增加連接段數而耐壓變高。又可知， 若產生驟回而流通突波電流後，再次使電壓上升，則到達 驟回電壓後再次產生驟回。藉此，可知驟回現象產生後 ESD保護元件本身受破壞之情況不會產生。 另’根據上述實施形態’以3種不同電壓作為電源電壓 施加之情形為例，但2種之情形或4種以上之情形亦可以相 同方法實現ESD保護元件。 圖5係具備高電壓輸出用電源端子vcc_h與低電壓輸出 154441.doc -16· 201201346 用電源端子VCC—1時本發明之半導體裝置之概念方塊圖。 又，圖6係以電路圖表現圖5所示之方塊圖之一例，圖7係 圖6所示時ESD保護裝置之概要剖面結構圖。圖5〜圖7係分 別參照圖1〜圖3作成，對於同一部位附加同—符號。 圖5所示之半導體裝置la，亦與圖丨之半導體裝置1相 同，低耐壓被保護元件18係利用ESD保護元件13保護免於 受ESD影響，高耐壓被保護元件16係利用esd保護元件 11、12、13之串聯連接保護免於受ESD影響。並且，關於 連接高耐壓被保護元件16之節點N Η與接地線v s s間之維持 電壓Vhl、連接低耐壓被保護元件18之節點1^1^與接地線 VSS間之維持電壓Vh3，係以與上述數丨相同之方式求得。 藉此，可防止突波電流向接地線Vss洩出後，從施加電源 電壓之各電源端子（vcc_h、vcc_l)對ESD保護元件流通 過電流。 又，節點NH與接地線VSS間之驟回電壓Vtl、節點NL與 接地線VSS間之驟回電壓Vt3與上述數2相同地求得。藉 此，即使如此構成中，亦無須將各ESD保護元件以高耐壓 元件實現’因此可縮小佈局佔有面積。 另，根據上述實施形態，作為ESD保護元件之一例，係 使用ggNMOS電晶體，但亦可取代其而使用雙極電晶體或 二極體’進而亦可以該等元件之串聯電路形成。 圖8所示之半導體裝置ib所具備之ESD保護電路1〇b係在 節點NM與NL間，除ggNMOS電晶體TM外尚具備電阻R1之 構成。此時，設於節點NM與NJL間之ESD保護元件12係利 154441.doc 201201346 用ggNMOS電晶體TM與電阻R1之串聯連接構成而實現。 關於施加突波電壓時突波電流之流動方向、以及此時之電 壓變化之態樣，為與參照圖1說明者相同之原理。藉此， 於圖8之構成時，該ESD保護元件12之耐壓Vtl2係規定為 ggNMOS電晶體TM之耐壓與電阻R1之兩端間電壓之合計 值。同樣，ESD保護元件12之維持電壓Vhl2亦規定為 ggNMOS電晶體之TM維持電壓加上電阻R1之兩端間電壓 之值。 藉此，若圖8所示之ESD保護電路10b除電阻R1外係與圖 2所示之ESD保護電路10相同之構成，則將該電阻R1串聯 設置，從而可更大地確保節點NM與接地線VSS間之耐壓 Vt2及維持電壓Vh2、節點NH與接地線VSS間之耐壓Vtl及 維持電壓Vhl之值（參照上述數1、數2)。 圖9所示之半導體裝置lc所具備之ESD保護電路10c係在 節點NM與NL間，除ggNMOS電晶.體TM外尚具備二極體D1 之構成。於該構成時，ESD保護元件12之耐壓Vtl2係規定 為ggNMOS電晶體TM之耐壓與二極體D1之耐壓之合計。 同樣，ESD保護元件12之維持電壓Vhl2亦規定為ggNMOS 電晶體TM之維持電壓加上二極體D1之耐壓之值。 圖10所示之半導體裝置Id所具備之ESD保護電路10d係 在節點NM與NL之間，除ggNMOS電晶體TM外尚具備連接 有基底與射極之雙極電晶體T1之構成。於該構成時，ESD 保護元件12之耐壓Vtl 2係規定為ggNMOS電晶體TM之耐壓 與雙極電晶體T1之耐壓之合計值。同樣，ESD保護元件12 154441.doc •18· 201201346 之維持電壓Vhl2亦規定為ggNMOS電晶體TM之維持電壓 加上雙極電晶體Τ1之維持電壓之值。 圖11所示之半導體裝置le所具備之ESD保護電路10e係具 備二極體作為靜電放電保護元件11〜1 3之構成。關於在各 電源與GND間構成之二極體，可藉在ESD保護元件之低濃 度N型擴散層與P型半導體基板間形成之二極體實現。 此時，節點NH與接地線VSS間之耐壓Vtl係規定為在節 點NH-NM間、節點NM-NL間、節點NL-接地線VSS間分別 設置之各二極體D1〜D3之接合耐壓之合計值。又，節點 NM與接地線VSS間之耐壓Vt2係規定為二極體D2及D3之接 合耐壓之合計值，節點NL與接地線VSS間之耐壓Vt3係規 定為二極體D3之接合耐壓。 以接地線VSS為基準對高電壓電源VCC_h施加正突波電 壓之情形中，突波電流經過ESD保護元件11(二極體D1)、 ESD保護元件12(二極體D2)、ESD保護元件13(二極體D3) 而流向接地線VSS洩出。同樣”對中間電壓電源VCC_nUfe 加正突波電壓時，突波電流經過二極體D2、D3而流向接 地線VSS洩出。 圖12所示之半導體裝置If所具備之ESD保護電路10f係具 備連接有基底與射極之雙極二極體作為ESD保護元件 11〜13之構成。Vt3=Vtl3, that is, 'construction according to the present invention'. The high withstand voltage is protected by the protective element 16 with the voltage resistance (sudden voltage) of the protection element, which is the total withstand voltage of the three protection elements (u, 12, 13). It is specified 'therefore, it is not necessary to design each protective element as a high withstand voltage element. That is, when the protective element is formed by the ggNMOS transistor, it is not necessary to thicken the oxide film under the gate electrode of the transistor, so that local leakage or breakage occurs when the surge voltage is applied. Further, when the ESD protection design is carried out with the protected element having the highest withstand voltage, the size of the E § D protection element can be reduced in accordance with the financial pressure of the protected element, thereby contributing to the reduction in the overall layout area. 154441 .doc •14· 201201346 Figure 2 shows an example of a block diagram shown in the circuit diagram. Further, a schematic cross-sectional structural view of the ESD protection circuit 10 at this time is shown in FIG. 2 and 3 are diagrams for the case where ggNM〇s transistors (TH, TM, tl) are used as the ESD protection elements 11, 12, and 13. The ESD protection circuit 10 is formed on the p-type semiconductor substrate 21. For the esd protection 5 vine element 11 and the ESD protection element 12, the deep N-type well 22 (42) is placed on the substrate 21, and an N-type well (1) and a 卩-type well 24 (44) are formed in the well. For ESD The protective element 13 is formed on the substrate 21 with a well 53 and a p-type well 54. The surface region in the P-well 24 (44, 54) has a high-concentration N-type impurity diffusion region 25 serving as a source (45). 55) The high-concentration p-type impurity diffusion region 26 (46, 56) for contact has a bungee height across the N-well 23 (43, 53) and the p-well 24 (44, 54). The impurity diffusion region 27 (47, 57) is formed in the concentration region. Further, the gate oxide film 28 is formed on the active region on the substrate surrounded by the field oxide film 31, and in the upper layer, the source electrode 25 is used (45, 55). A gate electrode 29 is formed at a position above the region sandwiched by the drain electrodes 27 (47, 57). The high voltage output power supply terminal VCC_h is connected to the drain electrode 27. Further, the intermediate voltage output power supply terminal VCC_m and the drain electrode 47 is connected and connected to the gate electrode 29, the source 25, and the contactor 26 of the high-withstand voltage ESD protection element 11" The low-voltage output power supply terminal VCC-1 is connected to the drain 5 7 and is medium-voltage resistant. The gate electrode 29, the source 45, and the contactor 46 of the ESD protection element 12 are connected. In addition, in FIG. 2, the two-pole system shown in the ESD protection circuit 10 is composed of a gray N-type well 22 and a P-type semiconductor substrate 21. The diode dm is composed of a deep n-well 42 and a P-type semiconductor substrate 21. 154441.doc 15- 201201346 In the case of such a configuration, it is not necessary to provide a large horizontal separation between the source and the drain as shown in FIG. Therefore, it is not necessary to increase the size of the protective member for reducing the parasitic resistance. Further, as described above, as the withstand voltage of the ESD protection circuit 1 for the high withstand voltage protected element 16, the ESD protection element 11 is used. The total of the withstand voltages of 12 and 13 is the total of the withstand voltages of ggNMOOS transistors TM, TM, and TL. Therefore, the withstand voltage design of each transistor is low, and the high withstand voltage can be ensured. The TLP (Transmission Line Pulsing) evaluation data for the ESD protection circuit 1 shown in Fig. 2 is shown. The F-1 in Fig. 4 is shown when the ESD protection element is connected in one segment, that is, the node NL and A curve of the applied voltage and current between the ground lines VSS. F_m is shown in the relationship between the applied voltage and current between the node NM and the ground line VSS when the ESD protection element is connected in two stages. F_h shows that the ESD protection element is connected in three stages, that is, the node NH and the ground. The curve of the applied voltage and current between the lines VSS. According to Fig. 4', it is known that the ESD protection element has the lowest withstand voltage (sudden voltage) when connected in one stage, and the withstand voltage becomes higher as the number of connection sections increases. Further, it can be seen that if a sudden surge current is generated and the voltage is increased again, the voltage is increased again, and a sudden return occurs after reaching the sudden return voltage. Thereby, it can be seen that the situation in which the ESD protection element itself is damaged after the occurrence of the snapback phenomenon does not occur. In the above embodiment, the case where three different voltages are applied as the power source voltage is taken as an example. However, in the case of two or four or more cases, the ESD protection element can be realized in the same manner. Fig. 5 is a conceptual block diagram of a semiconductor device of the present invention when a power supply terminal vcc_h for high voltage output and a power supply terminal VCC-1 for low voltage output 154441.doc -16·201201346 are provided. 6 is an example of a block diagram shown in FIG. 5 in a circuit diagram, and FIG. 7 is a schematic cross-sectional structural view of the ESD protection device shown in FIG. 5 to 7 are prepared by referring to Figs. 1 to 3, respectively, and the same reference numerals are attached to the same portions. The semiconductor device 1a shown in FIG. 5 is also the same as the semiconductor device 1 of FIG. 5, and the low withstand voltage protected element 18 is protected from ESD by the ESD protection element 13, and the high withstand voltage is protected by the esd by the protective element 16. The series connection of components 11, 12, 13 is protected from ESD. Further, the sustain voltage Vhl between the node N Η connecting the high withstand voltage protected element 16 and the ground line vss, and the sustain voltage Vh3 between the node 1^1^ connected to the low withstand voltage protected element 18 and the ground line VSS are It is obtained in the same manner as the above number. Thereby, after the surge current is prevented from leaking to the ground line Vss, an overcurrent flows to the ESD protection element from the respective power supply terminals (vcc_h, vcc_l) to which the power supply voltage is applied. Further, the sudden return voltage Vtl between the node NH and the ground line VSS, and the sudden return voltage Vt3 between the node NL and the ground line VSS are obtained in the same manner as the above-mentioned number 2. Therefore, even in such a configuration, it is not necessary to implement each ESD protection element as a high withstand voltage element, thereby reducing the layout occupied area. Further, according to the above embodiment, a ggNMOS transistor is used as an example of the ESD protection element, but a bipolar transistor or a diode may be used instead of the series circuit of the elements. The ESD protection circuit 1b included in the semiconductor device ib shown in Fig. 8 is provided between the nodes NM and NL, and has a resistor R1 in addition to the ggNMOS transistor TM. At this time, the ESD protection element 12 provided between the node NM and the NJL is realized by 365441.doc 201201346 by connecting the ggNMOS transistor TM and the resistor R1 in series. The flow direction of the surge current and the change of the voltage at this time when the surge voltage is applied are the same as those described with reference to Fig. 1 . Therefore, in the configuration of Fig. 8, the withstand voltage Vtl2 of the ESD protection element 12 is defined as the total value of the withstand voltage between the ggNMOS transistor TM and the voltage across the resistor R1. Similarly, the sustain voltage Vhl2 of the ESD protection element 12 is also defined as the value of the TM sustain voltage of the ggNMOS transistor plus the voltage across the resistor R1. Therefore, if the ESD protection circuit 10b shown in FIG. 8 has the same configuration as the ESD protection circuit 10 shown in FIG. 2 except for the resistor R1, the resistor R1 is placed in series, so that the node NM and the ground line can be more ensured. The breakdown voltage Vt2 between the VSS and the sustain voltage Vh2, the withstand voltage Vtl between the node NH and the ground line VSS, and the value of the sustain voltage Vhl (see the above-mentioned numbers 1 and 2). The ESD protection circuit 10c included in the semiconductor device 1c shown in Fig. 9 is provided between the nodes NM and NL, and has a configuration of a diode D1 in addition to the ggNMOS transistor. In this configuration, the withstand voltage Vtl2 of the ESD protection element 12 is defined as the total of the withstand voltage of the ggNMOS transistor TM and the withstand voltage of the diode D1. Similarly, the sustain voltage Vhl2 of the ESD protection element 12 is also defined as the sustain voltage of the ggNMOS transistor TM plus the withstand voltage of the diode D1. The ESD protection circuit 10d included in the semiconductor device 1d shown in Fig. 10 is provided between the nodes NM and NL, and has a configuration in which a bipolar transistor T1 having a base and an emitter is connected in addition to the ggNMOS transistor TM. In this configuration, the withstand voltage Vtl 2 of the ESD protection element 12 is defined as the total value of the withstand voltage of the ggNMOS transistor TM and the withstand voltage of the bipolar transistor T1. Similarly, the sustain voltage Vhl2 of the ESD protection element 12 154441.doc •18·201201346 is also defined as the sustain voltage of the ggNMOS transistor TM plus the value of the sustain voltage of the bipolar transistor Τ1. The ESD protection circuit 10e included in the semiconductor device le shown in Fig. 11 has a configuration in which a diode is provided as the electrostatic discharge protection elements 11 to 13. The diode formed between each of the power sources and the GND can be realized by a diode formed between the low-concentration N-type diffusion layer of the ESD protection element and the P-type semiconductor substrate. At this time, the withstand voltage Vtl between the node NH and the ground line VSS is defined as the junction resistance of each of the diodes D1 to D3 provided between the nodes NH-NM, the node NM-NL, and the node NL-ground line VSS. The total value of the pressure. Further, the withstand voltage Vt2 between the node NM and the ground line VSS is defined as the total value of the junction withstand voltages of the diodes D2 and D3, and the withstand voltage Vt3 between the node NL and the ground line VSS is defined as the junction of the diode D3. Withstand voltage. In the case where a positive surge voltage is applied to the high voltage power supply VCC_h with reference to the ground line VSS, the surge current passes through the ESD protection element 11 (diode D1), the ESD protection element 12 (diode D2), and the ESD protection element 13 (Diode D3) The flow to the ground line VSS is released. Similarly, when the positive voltage is applied to the intermediate voltage source VCC_nUfe, the surge current flows through the diodes D2 and D3 to the ground line VSS. The ESD protection circuit 10f of the semiconductor device If shown in Fig. 12 is connected. A bipolar diode having a base and an emitter is constructed as the ESD protection elements 11 to 13.
此時，節點NH與接地線VSS間之财壓Vtl係規定為分別 設於節點NH-NM間、節點NM-NL間、節點NL-接地線VSS 間之各雙極電晶體B1〜B3之耐壓之合計值。又，節點NM 154441.doc •19- 201201346 與接地線VSS間之耐壓Vt2係規定為雙極電晶體B2及B3i 耐壓之合計值，節點NL與接地線VSS間之耐壓Vt3係規定 為雙極電晶體B3之接合耐壓。 從高電壓之電源端子VCC_h施加突波電壓Vsur_l^f，突 波電流依序通過ESD保護元件11(雙極電晶體Bl)、ESD保 護元件12(雙極電晶體B2)、ESD保護元件13(雙極電晶體 B3)，流向接地線VSS。突波電流流通後之節點NH與接地 線VSS間之維持電壓Vhl係以雙極電晶體B 1之維持電壓 Vhll、雙極電晶體B2之維持電壓Vhl2、雙極電晶體B3之 維持電壓Vhl 3之合計予以規定。 同樣，從中間電壓之電源端子VCC_m施加突波電壓 Vsur_m時，突波電流依序通過雙極電晶體B2及B3，流向 接地線VSS，其後之維持電壓Vh2係以雙極電晶體B2之維 持電壓Vhl2、雙極電晶體B3之維持電壓Vhl3之合計予以 規定。 再者，從低電壓之電源端子VCC_1施加突波電壓Vsur_l 時，突波電流通過雙極電晶體B3流向接地線VSS，其後之 維持電壓Vh3係以雙極電晶體B3之維持電壓Vhl 3予以規 定。 另，圖8〜圖10中，係連接於節點NL與NM間之ESD保護 元件12成為ggNMOS電晶體與其他元件串聯連接之構成， 此僅係一例，例如ESD保護元件11或13亦可成為如此之構 成。 又，上述各實施形態中，亦可取代ggNMOS電晶體而採 154441.doc -20- 201201346 用ggPMOS電晶體。 如以上說明’根據本發明，係各電源端子中與接地線 VSS間並未獨立設置ESD保護元件，而是藉由於供給不同 電壓之電源端子間設置ESD保護元件，從而共用ESD保護 儿件之構成，因此可縮小各ESD保護元件之區域。 【圖式簡單說明】 圖1係本發明之附ESD保護功能之半導體裝置之概念方 塊圖。 圖2係本發明之附ESD保護功能之半導體裝置之概念電 路圖。 圖3係本發明之附ESD保護功能之半導體裝置之概要剖 面結橡圖。 13 圖4係對於本發明之ESD保護電路之TLp評估實測資料。 圖5係本發明之附ESD保護功能之半導體 丁〒脰裝置之另一概 念方塊圖。 概 圖6係本發明之附ESD保護功能之半導體 衣置之另 念電路圖。 圖7係本發明之ESD保護元件之另—概要剖面結構圖。 圖8係本發明之附ESD保護功能之半導體 人带妨 卞守遐裝置之另一概 念電路圖。 圖9係本發明之附ESD保護功能之半導體 ._ A 衣罝之另一概 念電路圖。 圖10係本發明之附ESD保護功能之半導體择 衣罝之另一概 念電路圖。 154441.doc 21 201201346 置之另- '概 置之另一 '概 圖11係本發明之附ESD保護功能之半導體裝 念電路圖* 圖12係本發明之附ESD保護功能之半導體襄 念電路圖。 圖13係含ESD保護電路之電路例。 圖14係先前之ESD保護電路之構成例。 圖15係先前之ESD保護電路之構成例。 【主要元件符號說明】 1 本發明之半導體裝置 1 a 本發明之半導體裝置 lb 本發明之半導體裝置 1 c 本發明之半導體裝置 Id 本發明之半導體裝置 1 e 本發明之半導體裝置 If 本發明之半導體裝置 10 本發明之靜電放電保護電略 10a 本發明之靜電放電保護電略 10b 本發明之靜電放電保|隻電路 10c 本發明之靜電放電保護電 lOd 本發明之靜電放電保锼電 lOe 本發明之靜電放電保幾電 lOf 本發明之靜電放電保礎電路 11 ESD保護元件 12 ESD保護元件 154441.doc •22- ESD保護元件 高耐壓被保護元件 中耐壓被保護元件 低耐壓被保護元件 半導體基板 深N井 N井 p井 源極 接觸器 汲極 閘極氧化膜 閘極電極 場氧化膜 深N井 N井 P井 源極 接觸器 汲極 N井 P井 源極 接觸器 -23- 201201346 57 汲極 B1 雙極電晶體 B2 雙極電晶體 B3 雙極電晶體 D1 二極體 D2 二極體 D3 二極體 DH 二極體 DM 二極體 NH 節點 NL 節點 NM 節點 TH ggNMOS電晶體 TL ggNMOS電晶體 TM ggNMOS電晶體 VCC_ _h 電源端子 VCC_ _1 電源端子 vcc_ _m 電源端子 vss 接地線 154441.doc 24 ·At this time, the financial pressure Vtl between the node NH and the ground line VSS is defined as resistance of each of the bipolar transistors B1 to B3 disposed between the nodes NH-NM, the node NM-NL, and the node NL-ground line VSS. The total value of the pressure. Further, the withstand voltage Vt2 between the node NM 154441.doc •19-201201346 and the ground line VSS is defined as the total value of the withstand voltage of the bipolar transistor B2 and B3i, and the withstand voltage Vt3 between the node NL and the ground line VSS is defined as Bonding withstand voltage of bipolar transistor B3. The surge voltage Vsur_l^f is applied from the high voltage power supply terminal VCC_h, and the surge current sequentially passes through the ESD protection element 11 (bipolar transistor B1), the ESD protection element 12 (bipolar transistor B2), and the ESD protection element 13 ( The bipolar transistor B3) flows to the ground line VSS. The sustain voltage Vhl between the node NH and the ground line VSS after the surge current flows is the sustain voltage Vh11 of the bipolar transistor B1, the sustain voltage Vhl2 of the bipolar transistor B2, and the sustain voltage Vhl3 of the bipolar transistor B3. The total is specified. Similarly, when the surge voltage Vsur_m is applied from the power supply terminal VCC_m of the intermediate voltage, the surge current sequentially flows through the bipolar transistors B2 and B3 to the ground line VSS, and thereafter the sustain voltage Vh2 is maintained by the bipolar transistor B2. The total of the voltage Vhl2 and the sustain voltage Vhl3 of the bipolar transistor B3 is defined. Further, when the surge voltage Vsur_1 is applied from the low-voltage power supply terminal VCC_1, the surge current flows through the bipolar transistor B3 to the ground line VSS, and thereafter the sustain voltage Vh3 is applied to the sustain voltage Vhl 3 of the bipolar transistor B3. Provisions. In addition, in FIGS. 8 to 10, the ESD protection element 12 connected between the node NL and the NM is configured such that the ggNMOS transistor is connected in series with other elements, which is merely an example, for example, the ESD protection element 11 or 13 may also be The composition. Further, in each of the above embodiments, a gg PMOS transistor may be used instead of the gg NMOS transistor for 154441.doc -20-201201346. As described above, according to the present invention, the ESD protection element is not separately provided between the power supply terminals and the ground line VSS, but the ESD protection element is shared by the power supply terminals supplying different voltages, thereby sharing the composition of the ESD protection device. Therefore, the area of each ESD protection element can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a conceptual block diagram of a semiconductor device with an ESD protection function of the present invention. Fig. 2 is a conceptual circuit diagram of a semiconductor device with an ESD protection function of the present invention. Figure 3 is a schematic cross-sectional view of a semiconductor device with an ESD protection function of the present invention. 13 Figure 4 is a measured data of the TLp evaluation of the ESD protection circuit of the present invention. Fig. 5 is another conceptual block diagram of a semiconductor device with an ESD protection function of the present invention. Fig. 6 is a circuit diagram of a semiconductor device with an ESD protection function of the present invention. Figure 7 is a cross-sectional view showing another outline of the ESD protection element of the present invention. Fig. 8 is another schematic circuit diagram of the semiconductor device with the ESD protection function of the present invention. Fig. 9 is another schematic circuit diagram of the semiconductor with ESD protection function of the present invention. Fig. 10 is a schematic circuit diagram of another embodiment of the semiconductor device with ESD protection function of the present invention. 154 441 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Figure 13 is an example of a circuit including an ESD protection circuit. Fig. 14 is a configuration example of the prior ESD protection circuit. Fig. 15 is a configuration example of the prior ESD protection circuit. DESCRIPTION OF SYMBOLS OF SYMBOLS 1 The semiconductor device of the present invention 1 a semiconductor device 1b of the present invention The semiconductor device 1 of the present invention The semiconductor device 1 of the present invention The semiconductor device 1 of the present invention The semiconductor device of the present invention If the semiconductor of the present invention Device 10 Electrostatic discharge protection of the present invention 10a Electrostatic discharge protection of the present invention 10b Electrostatic discharge protection of the present invention 10c circuit 10c Electrostatic discharge protection of the present invention lOd Electrostatic discharge protection of the present invention lOe Electrostatic discharge protection several times lOf Electrostatic discharge protection circuit of the invention 11 ESD protection element 12 ESD protection element 154441.doc • 22- ESD protection element High withstand voltage Protected component withstand voltage Protected component Low withstand voltage Protected component semiconductor Substrate deep N well N well p well source contactor pole gate oxide film gate electrode field oxide film deep N well N well P source contactor bungee N well P well source contactor -23- 201201346 57 Bungee B1 bipolar transistor B2 bipolar transistor B3 bipolar transistor D1 diode D2 diode D3 diode DH DM polar body diode node NL NH node NM nodes TH ggNMOS transistor TL ggNMOS transistor TM ggNMOS transistor VCC_ _h power terminal VCC_ _1 power terminal vcc_ _m power supply terminal vss a ground line 154441.doc 24 ·