201209926 六、發明說明： 【發明所屬之技術領域】 本發明是關於一種製作電晶體的方法，尤指一種製作具 有金屬閘極之電晶體的方法。 【先前技術】 在半導體產業中，由於多晶矽材料具有抗熱性質，因此 在製作典型金屬氧化物半導體(MOS)電晶體時通常會使用多 晶矽材料來製作電晶體的閘極電極，使其源極與汲極區域得 以在高溫下一起進行退火。其次，由於多晶矽能夠阻擋以離 子佈植所摻雜之原子進入通道區域，因此在閘極圖案化之後 能容易地再進行高溫形成自行對準的源極與汲極區域。 然而，多晶矽閘極仍有許多缺點。首先，與大多數金屬 材料相比*多晶秒閘極是以南電阻值的半導體材料所形成。 這造成多晶矽閘極是以比金屬導線為低的速率在操作。為了 彌補高電阻與其相應之較低操作速率，多晶矽材料通常需要 大量與昂貴的矽化金屬處理，使其操作速率可提升至可接受 的範圍。 4 201209926 其A，多晶發間極办 嚴格來說，目前多曰曰石、易產生空乏效應（dePleti〇n effect)。 約3xl020/cm3的範固。的穆雜遭度只能達到約2x2〇2〇/cm3到 到5 X102 V c m3的條件。在間極材料中的摻雜濃度需要至少達 閘極受到偏壓時，缺下’、由於摻雜濃度上的限制，當多晶矽 層的介面上就容易產乏=子，使靠近多晶矽閘極與閘極介電 閘極介電層厚度増力/空之區。此空乏效應除了會使等效的 致元件驅動能力心等=時造成閘極電容值下降，進而導 故目前便有新的 (work function)金屬夾閘極材料被研製生產，例如利用功函數 屬間極的方法通常^取代傳統的多晶㈣極。目前製作金 料所構成的虛置間=^一基底上形成一主要由多晶石夕材 ^ 々 ’然後以乾蝕刻或濕蝕刻製程淘空虛詈 甲5的夕0日碎材料’接著再填人金屬材料以形成金屬間 極〇201209926 VI. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a transistor, and more particularly to a method of fabricating a transistor having a metal gate. [Prior Art] In the semiconductor industry, since polycrystalline germanium materials have heat resistance properties, polycrystalline germanium materials are usually used in the fabrication of typical metal oxide semiconductor (MOS) transistors to form gate electrodes of transistors, and their sources are The drain regions are annealed together at high temperatures. Secondly, since the polysilicon can block the atoms doped by the ion implantation into the channel region, the high temperature can be easily formed to form the self-aligned source and drain regions after the gate patterning. However, polysilicon gates still have a number of disadvantages. First, compared to most metallic materials, the * polycrystalline seconds gate is formed from a semiconductor material with a south resistance value. This causes the polysilicon gate to operate at a lower rate than the metal wire. In order to compensate for the high resistance and the corresponding lower operating rate, polycrystalline germanium materials typically require a large amount of processing with expensive deuterated metal to increase the operating rate to an acceptable range. 4 201209926 Its A, polycrystalline hair is extremely strict. At present, there are many meteorites, which are prone to depletion effect (dePleti〇n effect). About 3xl020/cm3 Fan Gu. The degree of miscellaneous can only reach a condition of about 2x2〇2〇/cm3 to 5 X102 V c m3. The doping concentration in the interpolar material needs to be at least as long as the gate is biased, and due to the limitation of the doping concentration, when the interface of the polycrystalline layer is easily produced, the sub-gate is close to the polycrystalline germanium gate. The thickness of the gate dielectric gate layer is the thickness/empty area. This depletion effect causes the gate capacitance value to decrease in the case of the equivalent element driving ability, etc., and thus the work function metal clip gate material is currently developed, for example, using the work function genus. The interpole method usually replaces the traditional poly (tetra) pole. At present, the dummy material formed by the gold material is formed on the substrate, and a polycrystalline stone material is formed on the substrate, and then the dry etching or wet etching process is used to empt the empty material of the 詈 日 日 5 Human metal material to form an intermetallic barrier
」而白头於掏空虛置閘極中的多晶矽材料時通常會妒 損到多晶㈣料下的閘極絕緣層，使後續製程中必需再進^ 一次熱氧化製程以形成另_個閘極絕緣層 。此過程不但繁項 耗時，且熱氧化製程中所使㈣高溫又會同時影響基底中輕 捧雜沒極或源極/及極區域的摻質分佈。因此，如何改良目前 裝裎上的瓶頸以解決上述問題即為現今一重要課題。 201209926 【發明内容】 因此本發明之主要目的是#供一 電晶體的方法，以解決上述習知製程所遇到的問題間極之 本發明較佳實施例是揭露一種製作具有金屬間極之電 晶體的方法。首先提供一基底，該基底上定義有 ί蓋==閘極絕緣層於基底上，並形成-堆疊二 伋羞閘極I彖層，且堆疊薄膜至少包含一蝕刻停止層一 晶石夕層以及-硬遮罩。接著圖案化閘極絕緣層及堆^薄膜^ 以於基底上形成-虛置閘極。隨後形 閘極’並進行-平坦化製程，以去除部分介^ 極頂部。錢去除虛置閘極中之多晶㈣、去除虛 之姓刻停止層以形成-開口以及填入一導電層於開口内以 形成一閘極。 【實施方式】 睛參照第1圖至第5圖’第！圖至第5圖為本發明較佳 實施例製作-具有金屬閘極之電晶體示意圖。如第！圖所 不，首先提供一基底12，例如一矽基底或一絕緣層上覆矽 (silic〇n-on_insulator; S0I)基底等，且在基底12上定義至少 一電晶體區14。 201209926 然後形成一由氧化物、氮化物等之介電材料所構成的閉 極絕緣詹（圖未示）在基底12表面。依據本發明之一實施例， 閘極絕緣層也可以由襯氧化層或具有高介電常數之介電材 料層所構成，其中高介電常數之介電材料例如是石夕酸給氧化 合物（HfSiO)、矽酸铪氮氧化合物（HfSiON)、氧化給(Hf〇)、 氧化鑭（LaO)、鋁酸鑭（LaAlO)、氧化鍅(ZrO)、矽酸錯氧化合 物（ZrSiO)、鍅酸铪(HfZrO)或其組合。 接著在閘極絕緣層上依序形成—由關停止層、多晶石夕 層以及硬遮罩所構成的堆疊_㈤未示）。依據本發明之較 佳實施例，制停止層較佳由一氮切層所構成，其厚度較 佳低於UK)埃’多晶石夕層較佳作為〜虛置閘極層，且其厚度 約i _埃(angst聰）。多晶石夕層可由不具有任何推質The polycrystalline germanium material in the hollow gate of the whitehead usually degrades the gate insulating layer under the polycrystalline (four) material, so that the thermal oxidation process must be further performed in the subsequent process to form another gate insulating. Floor. This process is not only cumbersome and time consuming, but also causes the high temperature distribution in the thermal oxidation process to affect the dopant distribution of the light or source/polar regions in the substrate. Therefore, how to improve the bottleneck on the current decoration to solve the above problems is an important issue today. 201209926 SUMMARY OF THE INVENTION The present invention is therefore directed to a method for providing a transistor to solve the problems encountered in the above-described conventional processes. A preferred embodiment of the present invention discloses a method for fabricating a metal having a metal interpole. The method of crystals. Firstly, a substrate is provided, wherein the substrate is defined with a 盖 cap == gate insulating layer on the substrate, and a stacked-stacked gate electrode layer is formed, and the stacked film includes at least one etch stop layer and a spar layer - Hard cover. The gate insulating layer and the stack are then patterned to form a dummy gate on the substrate. The gate is then turned on and a planarization process is performed to remove portions of the top of the dielectric. The money removes the polycrystalline (4) in the dummy gate, removes the dummy stop layer to form an opening, and fills a conductive layer in the opening to form a gate. [Embodiment] The eye is referred to in Figures 1 to 5! Figures 5 through 5 are schematic views of a transistor having a metal gate fabricated in accordance with a preferred embodiment of the present invention. As the first! Preferably, a substrate 12 is provided, such as a germanium substrate or a silic germanium-on-insulator (S0I) substrate, and the like, and at least one transistor region 14 is defined on the substrate 12. 201209926 Then, a closed-electrode insulation (not shown) composed of a dielectric material such as an oxide or a nitride is formed on the surface of the substrate 12. According to an embodiment of the present invention, the gate insulating layer may also be composed of a liner oxide layer or a dielectric material layer having a high dielectric constant, wherein the high dielectric constant dielectric material is, for example, an auric acid oxygen compound ( HfSiO), niobium oxynitride (HfSiON), oxidized (Hf〇), lanthanum oxide (LaO), lanthanum aluminate (LaAlO), yttrium oxide (ZrO), yttrium acid-oxygen compound (ZrSiO), tannic acid铪 (HfZrO) or a combination thereof. Then, sequentially formed on the gate insulating layer - a stack consisting of a shutdown stop layer, a polycrystalline layer, and a hard mask - (5) is not shown. According to a preferred embodiment of the present invention, the stop layer is preferably composed of a nitride layer, and the thickness thereof is preferably lower than that of the UK), and the polycrystalline layer is preferably used as a dummy gate layer, and the thickness thereof is About i _ ang (angst Cong). Polycrystalline stone layer can be without any push
戈由具有N+摻質的多晶_所構 等材料所m *切（S i〇2)、11切或氮氧切(Si0N) 4材科所構成，此㈣树明所Μ的·。 圖案化光阻層當作遮罩^物未示）在硬遮罩上，並利用 逐次敍❹驟，錯>彳了—®*—，以單次钱刻或 及閉極絕緣層，並制::=、多晶一刻停止層 形成-由圖案化問極絕緣二化光随層，以於電晶體區14 ''曰16、圖案化蝕刻停止層18、圖 201209926 案化多晶矽層20及圖案化硬遮罩22所構成的虛置閘極24。 然後如第2圖所示，先進行第一階段的側壁子製程，例 如沈積一由氧化矽或氧化矽/氮化矽所構成的介電層於虛置 閘極24上，接著對沈積的介電層進行一回蝕刻製程，以於 虛置閘極24側壁形成一第一側壁子26。 然後進行一淺摻雜製程，以形成所需的輕摻雜汲極。例 如，可先覆蓋一圖案化光阻層（圖未示）在電晶體區14以外的 區域，並利用該圖案化光阻層當作遮罩進行一離子佈植，將 N型或P型摻質植入虛置閘極24兩側的基底12中，以形成 一輕換雜汲極28。 隨後進行第二階段的側壁子製程，例如先依序沈積一氧 化矽層30與一氮化矽層32於基底12及虛置閘極24上，然 後對沈積的氧化矽層30及氮化矽層32進行一回蝕刻製程， 以於第一側壁子26周圍形成一第二側壁子34。 接著進行一重摻雜離子佈植製程，以形成所需的源極/ 汲極區域。如同上述形成輕摻雜汲極28的作法，可先覆蓋 一圖案化光阻層（圖未示）在電晶體區14以外的區域，然後利 用該圖案化光阻層當作遮罩進行一離子佈植製程，將N型或 P型摻質植入第二側壁子34兩側的基底12中，並搭配熱製 201209926 成擴散摻質以於第二側壁子34兩側的基底12中形成一源極 /汲極區域36，接著去除上述的圖案化光阻層。 在上述形成源極/汲極區域之前或之後，本實施例可選 擇性進行一矽基底回蝕製程並搭配—選擇性磊晶成長 (selective epitaxial growth，SEG)製程，以於源極/汲極部分形 成石夕與其他材料的磊晶層。之後可進行一自行對準石夕化金屬 (self-aligned silicide，Salicide)製程，以於源極/沒極區域 36 上形成矽化金屬層（圖未示）。由於自行對準矽化金屬製程及 選擇性磊晶成長製程均屬本領域中常見技術，在此不另加贅 述另外$，主思的疋，雖然本實施例較佳依序形成第一侧壁 子、輕摻雜汲極、第二側壁子及源極/汲極區域，但不侷限於 此，本發明又可削康製程上的需求任意調整上述形成側壁子 及掺雜區的順序，此均屬本發明所涵蓋的範圍。 • 接著形成一主要由氧化物所構成的層間介電層 (intedayer dielectric)38並覆蓋整個虛置間極24。此0層間介電 層38可包含氮化物、氧化物、碳化物、低介電係數材料中 之一或多者。 如第3圖所示，進行一化學機械研磨 mechanica丨polishing，CMP)製程或一乾蝕刻製程，去除部分 的層間介電層38、部分第一側壁子26、部分第二側壁子％ 201209926 以及硬遮罩22，並使多晶矽層20頂部約略切齊於層間介電 層38表面而受到裸露。 如第4圖所示，進行一選擇性之乾敍刻或濕I虫刻製程， 例如利用氨水(ammonium hydroxide, NH4OH)或氫氧化四甲 錄(Tetramethylammonium Hydroxide，TMAH)等#刻溶液來 掏空虛置閘極24中的多晶矽層20並停止於蝕刻停止層18 上。然後再進行一濕蝕刻製程，利用磷酸來去除由氮化矽所 構成的蝕刻停止層18，以於虛置閘極24中形成一開口 4〇 並曝露出底下的閘極絕緣層16。 值得注意的是’由於本發明較佳在閘極絕緣層The material consists of a material such as a polycrystalline material having an N+ dopant, m*cut (S i〇2), 11-cut or oxynitride (Si0N) 4 materials, and this (4) is clearly described. The patterned photoresist layer is used as a mask (not shown) on the hard mask, and utilizes successive steps, wrong > — -®*-, with a single money or a closed-loop insulation layer, and System::=, polycrystalline moment stop layer formation--patterned interrogation insulator dimming light with layer, for transistor region 14 ''曰16, patterned etch stop layer 18, Figure 201209926 polycrystalline germanium layer 20 and The dummy gate 24 formed by the patterned hard mask 22 is patterned. Then, as shown in FIG. 2, the first stage sidewall process is performed first, for example, depositing a dielectric layer composed of hafnium oxide or tantalum oxide/tantalum nitride on the dummy gate 24, followed by deposition. The electrical layer performs an etching process to form a first sidewall 26 on the sidewall of the dummy gate 24. A shallow doping process is then performed to form the desired lightly doped drain. For example, a patterned photoresist layer (not shown) may be covered in a region other than the transistor region 14, and the patterned photoresist layer is used as a mask for ion implantation, and the N-type or P-type is doped. The substrate 12 is implanted in the substrate 12 on both sides of the dummy gate 24 to form a light-changing drain electrode 28. Then, the second stage sidewall process is performed, for example, a tantalum oxide layer 30 and a tantalum nitride layer 32 are sequentially deposited on the substrate 12 and the dummy gate 24, and then the deposited tantalum oxide layer 30 and tantalum nitride are deposited. The layer 32 is subjected to an etching process to form a second sidewall 34 around the first sidewall 26. A heavily doped ion implantation process is then performed to form the desired source/drain regions. As described above, the light-doped drain electrode 28 is formed by first covering a region of the patterned photoresist layer (not shown) outside the transistor region 14, and then using the patterned photoresist layer as a mask to perform an ion. The implantation process implants an N-type or P-type dopant into the substrate 12 on both sides of the second sidewall 34, and is formed into a diffusion dopant with a heat of 201209926 to form a substrate 12 on both sides of the second sidewall 34. Source/drain regions 36, followed by removal of the patterned photoresist layer described above. Before or after the formation of the source/drain regions, the present embodiment can selectively perform a substrate etchback process and a selective epitaxial growth (SEG) process for source/drainage Part of the formation of the epitaxial layer of Shi Xi and other materials. A self-aligned silicide (Salicide) process can then be performed to form a deuterated metal layer (not shown) on the source/drain region 36. Since the self-aligned metallization process and the selective epitaxial growth process are common technologies in the art, no additional description is given here, although the first embodiment of the present invention preferably forms the first sidewall. The lightly doped drain, the second sidewall and the source/drain regions, but are not limited thereto, and the present invention can arbitrarily adjust the order of forming the sidewalls and the doped regions, respectively. It is within the scope of the invention. • An indiumday dielectric 38, which is mainly composed of an oxide, is formed and covers the entire dummy interpole 24. The inter-zero dielectric layer 38 may comprise one or more of a nitride, an oxide, a carbide, and a low-k material. As shown in FIG. 3, a chemical mechanical polishing process, or a dry etching process, is performed to remove portions of the interlayer dielectric layer 38, portions of the first sidewalls 26, portions of the second sidewalls, 201209926, and hard masking. The cover 22 is exposed such that the top of the polysilicon layer 20 is approximately aligned with the surface of the interlayer dielectric layer 38. As shown in Figure 4, perform a selective dry or wet I-insulation process, such as using ammonia hydroxide (NH4OH) or Tetramethylammonium Hydroxide (TMAH) to emptiness. The polysilicon layer 20 in the gate 24 is placed and stopped on the etch stop layer 18. Then, a wet etching process is performed to remove the etch stop layer 18 made of tantalum nitride by using phosphoric acid to form an opening 4 in the dummy gate 24 and expose the underlying gate insulating layer 16. It is worth noting that because the present invention is preferably in the gate insulating layer
所示。 π _邵份第二侧壁子34是由氣化石夕 ，如第4圖中 例以濕_去除關停止層18的時候較佳 二側壁子34中的氮化矽層3 其次， 由於餘刻停止層18較佳由氮切所構成 ，本發 201209926 ^較佳在製作第—側壁子26的日_㈣ ，，、， 子6。如此以濕蝕刻製程去除氮化石夕勒μ ^嘯便不致同時侵_貼純刻 第一側壁子26。 w 的 ，.·、後如第5圖所示，形成—高介電常數介電層42 口仙内並覆蓋閘極絕緣層16、第—侧壁子％、第二側壁子 34及層間介電層38。在本較佳實施例中，高介 層42是選“夕酸給氧化合物(刪〇)、石夕酸給氮氧化合物 (腦ON)、乳化給_)、氧化鑭(La〇)、紹酸鑭(_〇)、 氧化MZK))、錢鍅氧化合物(Ζι__、結酸給(脱r〇)，或 其組合。 接著可依據電晶體的特性選擇性沈積一金屬層（圖未示) 鲁於同”電系數介電層42表面。例如，若所製作的電晶體為 NMOS電晶體，可沈積一 N型金屬層於高介電常數介電層 42表面’其中N型金屬層較佳選自氮化鈦(TiN)、碳化钽 (TaC)、氮化鈕(TaN)、氮化矽鈕(TaSiN)及鋁等所構成的群 組。若所製作的電晶體為pM〇S電晶體，可沈積一 p型金屬 層於高介電常數介電層42表面’其中P型金屬層較佳選自 由氮化鈦(TiN)、鎢（W)、氮化鎢（WN)、鉑（Pt)、鎳(Ni)、釕(Ru)、 碳氮化钽(TaCN)或碳氮氧化鈕(TaCNO)所構成的群組。 11 201209926 隨後填入一由低電阻材料所構成的導電層44在高介電 吊數介電層42上並填滿開口 4〇。在本實施例中，導電層44 可選自銘、鶴、鈦銘合金（TiAl)、姑鶴填化物（cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。最後進行另一化 學機械研磨製程，去除第一側壁子26、第二側壁子34及層 間介電層38上部分的導電層44及高介電常數介電層42,以 於電晶體區14形成一具有金屬閘極的電晶體。 綜上所述，相較於習知金屬閘極電晶體製程，本發明較 佳在閘極絕緣層及虚置多晶矽層之間形成一由氮化石夕所構 成的姓刻停止層，如此後績在掏空多晶石夕層的時候便了將 姓刻停止層作為一保護閘極絕緣層的阻擒層，使去^夕曰 層的電漿或蝕刻溶劑不至侵蝕到底下的閘極絕緣 夕阳碎 由於 個閘極Shown. The second side wall 34 of the π_shao portion is made of gasification, and the layer of tantalum nitride 3 in the second side wall 34 is preferably removed when the stop layer 18 is wet-removed as in the case of Fig. 4, secondly, due to the The stop layer 18 is preferably made of nitrogen cut, and the present invention 201209926 is preferably used to make the day_(four), ,, and 6 of the first side wall 26 . Thus, the wet etching process is performed to remove the nitriding stone, and the first side wall 26 is not invaded. w, . . . , and then as shown in FIG. 5, forming a high-k dielectric layer and covering the gate insulating layer 16, the first-side sidewall, the second sidewall 34, and the interlayer Electrical layer 38. In the preferred embodiment, the high dielectric layer 42 is selected from the group consisting of "oxygenated oxygen compound (deletion), oxalic acid to oxynitride (brain ON), emulsified to _), cerium oxide (La 〇), Acid strontium (_〇), oxidized MZK)), 鍅 鍅 鍅 Ζ Ζ Ζ Ζ Ζ _ _ _ _ _ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Lu Yutong "electrical coefficient dielectric layer 42 surface. For example, if the fabricated transistor is an NMOS transistor, an N-type metal layer can be deposited on the surface of the high-k dielectric layer 42", wherein the N-type metal layer is preferably a group selected from the group consisting of titanium nitride (TiN), tantalum carbide (TaC), nitride nitride (TaN), tantalum nitride (TaSiN), and aluminum, etc. If the fabricated transistor is a pM〇S transistor A p-type metal layer may be deposited on the surface of the high-k dielectric layer 42. The P-type metal layer is preferably selected from the group consisting of titanium nitride (TiN), tungsten (W), tungsten nitride (WN), and platinum (Pt). ), a group of nickel (Ni), ruthenium (Ru), tantalum carbonitride (TaCN) or carbon oxynitride (TaCNO). 11 201209926 Subsequently, a conductive layer 44 composed of a low-resistance material is filled in High dielectric suspension dielectric 42 is filled with openings 4. In this embodiment, the conductive layer 44 may be selected from low resistance materials such as Ming, He, Titan, Cobalt phosphide (CoWP) or the like. Finally, another chemical mechanical polishing process is performed to remove the conductive layer 44 and the high-k dielectric layer 42 of the first sidewall 26, the second sidewall 34, and the interlayer dielectric layer 38 for the transistor region 14. Forming a transistor having a metal gate. In summary, the present invention preferably forms a nitride nitride layer between the gate insulating layer and the dummy polysilicon layer in comparison with the conventional metal gate transistor process. The surname is a stop layer, so that when the polycrystalline stone layer is hollowed out, the surname stop layer is used as a barrier layer for the protective gate insulating layer, so that the plasma or etching of the layer is removed. The solvent does not erode the underside of the gate insulation, the sunset is broken due to a gate
極絕緣層在掏空多晶矽層的過程中受到保護且不至、肖耗 盡’本發明便不需再進行一次熱氧化製程以形成另 口 絕緣層，不但降低製程時間又節省成本。 以上所述僅為本發明之較佳實施例，凡依本 明申請專 利範圍所做之均等變化與修飾，皆應屬本發明 函蓋範圍。 【圖式簡單說明】 12 201209926 第1圖至第5圖為本發明較佳實施例製作一具有金屬閘極電 晶體之不意圖。 【主要元件符號說明】 12 基底 14 電晶體區 16 閘極絕緣層 18 钱刻停止層 20 多晶矽層 22 硬遮罩 24 虛置閘極 26 第一側壁子 28 輕摻雜没極 30 氧化矽層 32 氮化矽層 34 第二側壁子 36 源極/汲極區域 38 層間介電層 40 開口 42 高介電常數介電層 44 導電層 13The pole insulating layer is protected during the process of hollowing out the polysilicon layer and is not exhausted. The present invention eliminates the need for a further thermal oxidation process to form an additional insulating layer, which not only reduces process time but also saves cost. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the patent scope of the present application are within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS 12 201209926 Figs. 1 to 5 are schematic views showing a method of fabricating a metal gate electrode according to a preferred embodiment of the present invention. [Main component symbol description] 12 Substrate 14 Transistor region 16 Gate insulating layer 18 Charging stop layer 20 Polysilicon layer 22 Hard mask 24 Virtual gate 26 First sidewall sub-28 Lightly doped immersion 30 Oxide layer 32 Tantalum nitride layer 34 second sidewall sub-36 source/drain region 38 interlayer dielectric layer 40 opening 42 high-k dielectric layer 44 conductive layer 13