201208249 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種弛張型振盪器，特別是關於一種低耗電 * 的弛張型振盪器。 【先前技術】 因近年製程控制精進以及降低成本考量，在微控制單元 (MCU)及其他電路中’積極採用内部電阻及電容做為弛張型振 蓋益(Relaxation oscillators)的件，並利用頻率校準方式校準 (trimming)電阻及電容製程變動，以便獲得準確的頻率。採用 内部電阻及電容的弛張型振盪器除在微控制單元及其他電路 中大量運用以取代石英晶體振盪器(crystal 〇scillat〇r；^ IC内部 的頻率產生之振盪源，另外也採用此電路做為微控制單元中的 . 看門狗計時器(watch dog timer, WDT)或休眠模式計時器 (sleep mode timer) ° • 而一般弛張型振盪器的設計中，盡量以原理CV==IT及 I=(V/R)得到和電壓無關的振盪時間公式T=RC。現今的1(：除 了頻率對電壓及製程變動要求嚴刻之外，對Ic内頻率產生之 振盪源及看門狗計時器亦嚴刻要求低耗電表現，以達到IC低 耗電的節能需求。一般振盪器耗電分為交流電轉態(AC transient)及直流電流路徑(DC currentpath)的耗電。而直流電 流路徑主要功用是產生對電容的充放電電流及比較器的偏壓 (bias)電流。為了達到低耗電需求，在設計概念上需要減少直 流電流路徑及降低偏壓電流源大小。但是為了降低偏壓電流源卜 3 201208249 大小以達舰耗電_準，減公式I=(v/R)，財電阻r的 阻值必須很大’例如若電阻上有3V的跨麼，電阻dc電泣要 小於3uA，則電阻需為1ΜΩ以上；若電阻上有5v的跨^， 電阻DC電流還是要小於3uA，則電阻需為167ΜΩ以上。此 例說明弛張型觀ϋ低耗電電路相電阻值敎，電阻面積增 加’使1C面積相對變很大。 θ 習知美國專利號us 6362697、us 6680656、us侧秘 所揭露之技術皆因直流電流路徑的數量過多，無法達到低耗電 的需求。而美國專利號us 7443260雖能達到低耗電的需求， 但其輸出振盪頻率並無法雜且及電容保有T=RC的線性關 係，因此容易受製程、電壓、溫度···等許多因素影響到其頻率 的準確度。 因此，-種週期頻率對電阻及電容同樣保有線性關係且低 耗電的弛張型$盪器，乃為所冀。. 【發明内容】 本發明的目的之一，在於提出一種低耗電的弛張型振盪 器。 本發明的目的之一，在於提出一種週期頻率對電阻及電容 同樣保有線性關係的弛張型振盪器。 根據本發明，一種低耗電的弛張型振盪器，包含電流源產 生電路利用第一電晶體的閘極和汲極連接形成的跨壓使電阻 產生偏壓電流’充放電電路利用該偏壓電流的鏡射電流對電容 充電以導通和§玄第·一電sa體具有相同特性的第二電晶體，再經I s ] 4 201208249 由連接於該第二電晶體之汲極與第三電晶體之閘極之間的延 遲電路’使該電容週期性地充電與放電，以產生一個與電壓無 關的振盪頻率並達到低耗電之效果。 【實施方式】 圖1是本發明弛張型振盪器之實施例。此弛張型振盪器包 含電流源產生電路1〇、充放電電路12及延遲電路14。電流源 產生電路10利用電晶體M3的閘極和没極短路連接成近似偏 壓二極體的元件，使節點A對接地點GND的跨壓為Vgs3， 並設計電流鏡16的電晶體]vq、M2具有相同特性，所以於電 阻兩端，電晶體Ml的沒極到接地點GND的跨壓同樣為 Vgs3，因而產生電流源之偏壓電流Ina=(Vgs3/R1)。又設計電 流鏡18的電晶體M4、M5、M6、M7皆具有相同的特性，即 CW/L)M4-(W/L)M5=(w/L)M6=(W/L)M7, ’ 因此忽略通道調變 idiannel length modulation)得到具有同一電流值的電流Iml、 Im2、Im3、Im4。充放電電路12包含電容α，當振盪器起振 時電流Im3會從節點b對電容C1充電’當節點b的電壓達到 NMOS電晶體M8的導通電壓Vgs8，NMOS電晶體M8被導 通，節點c的電位隨即由電源電壓vdd被拉下。延遲電路14 連接節點C，當節點C的電位被下拉到反相器取乂丨的轉態電 壓Vtrgl時，轉換反相器INV1的輸出，再經過反相器INV2， 節點ATD會產生一方波脈衝由、，，變為“〇”，此方波脈衝 再經由反相HINV3轉態“〇，，變為“i，，的信號S1，將刪〇s 電晶體M9打開，再將節點B拉到‘‘〇，，電位關掉麵〇8電晶【 5 201208249 體M8，則節點C隨即被拉回到高壓vdd，使反相器inv3由 “0”變為“Γ的信號S1關掉NMOS電晶體M9,則電容C1 重新回到充電狀態。由電晶體M8、M9與延遲電路14形成的 迴路依此對電容C1反覆的充放電’週而復始的運作。其中， 延遲電路14的反相器INV1、INV2、INV3的轉態電壓只決定 信號S1傳至NMOS電晶體M9的延遲時間，以及節點ATD 的脈衝方波的寬度’即使反相器IjsjVi、、INV3的轉態 電壓隨製程變動對節點B對電容C的充放電時間造成的影響 • 極小，因此並不會影響本發明弛張型振盪器之振盪頻率。另 外’為了得到工作週期(duty cycle)為50%的週期方波，會於延 遲電路14的節點ATD連接一除頻器20，使節點CKmjT _ 5〇%的軸方波。於其他實財，若並無要求輪出的週期 方波，則不需要於節點ATD連接除_ 2〇，直接於節點atd 輸出即可。 本發明的他張型振盪器依然遵守原理為T=RC的線性關 • 係。係根據電荷守恒原理CV=IT，將C代入電容α的電容 值’ V代入NMOS電晶體Μ8的導通電壓Vgs8，而其令的工 為電流 Im3=Im 1 =(Vgs3/Rl)，得到 公式1201208249 VI. Description of the Invention: [Technical Field] The present invention relates to a relaxation type oscillator, and more particularly to a relaxation type oscillator of low power consumption. [Prior Art] Due to the recent process control and cost reduction, the internal control resistors and capacitors are actively used in the micro control unit (MCU) and other circuits as the relaxation type oscillatory oscillators, and the frequency calibration is utilized. Mode Trim the resistance and capacitance process variations to get an accurate frequency. The relaxation type oscillator with internal resistance and capacitance is used in large quantities in the micro control unit and other circuits to replace the quartz crystal oscillator (crystal 〇scillat〇r; ^ the internal oscillation frequency generated by the IC, and this circuit is also used. For the micro control unit. Watch dog timer (WDT) or sleep mode timer ° • In the design of the general relaxation oscillator, try to use the principle CV==IT and I =(V/R) gives the voltage-independent oscillation time formula T=RC. Today's 1 (: In addition to the frequency-to-voltage and process variation requirements, the oscillation source and watchdog timer generated in the frequency of Ic It also requires strict low-power performance to meet the energy-saving requirements of IC low-power consumption. The general oscillator power consumption is divided into AC transient and DC currentpath, while DC current path is mainly The function is to generate the charge and discharge current to the capacitor and the bias current of the comparator. In order to achieve low power consumption, the design concept needs to reduce the DC current path and reduce the bias current source size. Reduce the bias current source Bu 3 201208249 size to reach the ship's power consumption _ quasi, reduce the formula I = (v / R), the resistance of the resistance r must be very large 'for example, if there is a crossover of 3V on the resistor, the resistance dc If the weep is less than 3uA, the resistance should be 1ΜΩ or more; if there is a 5v crossover on the resistor, and the resistance DC current is still less than 3uA, the resistance should be 167ΜΩ or more. This example shows the phase resistance of the relaxation type low-power circuit.敎, the increase in the area of resistance ' makes the area of 1C relatively large. θ The US patents us 6362697, us 6680656, and the technology disclosed by us are all due to the excessive number of DC current paths, which cannot meet the demand for low power consumption. Although the US patent number us 7443260 can meet the demand of low power consumption, its output oscillation frequency can not be mixed and the capacitance has a linear relationship of T=RC, so it is easily affected by many factors such as process, voltage, temperature, etc. The accuracy of the frequency. Therefore, the periodic frequency has a linear relationship with the resistor and the capacitor, and the low-power relaxation type is a device. [Explanation] One of the objects of the present invention is to propose Low power consumption Relaxation type oscillator. One of the objects of the present invention is to provide a relaxation type oscillator whose periodic frequency also maintains a linear relationship between resistance and capacitance. According to the present invention, a low power consumption relaxation type oscillator includes a current source generating circuit Using a voltage across the gate and the drain of the first transistor to create a bias current, the charge and discharge circuit uses the mirror current of the bias current to charge the capacitor to conduct and § a second transistor of the same characteristic, which is periodically charged and discharged by a delay circuit 'connected between the drain of the second transistor and the gate of the third transistor via I s ] 4 201208249, To produce a voltage-independent oscillation frequency and achieve low power consumption. [Embodiment] FIG. 1 is an embodiment of a relaxation type oscillator of the present invention. This relaxation type oscillator includes a current source generating circuit 1A, a charge and discharge circuit 12, and a delay circuit 14. The current source generating circuit 10 is connected to the element of the approximately biased diode by the gate of the transistor M3 and the short-circuit short circuit, so that the voltage across the ground point GND of the node A is Vgs3, and the transistor of the current mirror 16 is designed to be vq, M2 has the same characteristics, so across the resistor, the voltage across the pole of the transistor M1 to the ground point GND is also Vgs3, thus generating a bias current of the current source Ina=(Vgs3/R1). The transistors M4, M5, M6, and M7 of the current mirror 18 are designed to have the same characteristics, that is, CW/L) M4-(W/L)M5=(w/L)M6=(W/L)M7, ' Therefore, the current modulation Iml, Im2, Im3, Im4 having the same current value is obtained by ignoring the channel modulation idiannel length modulation. The charge and discharge circuit 12 includes a capacitor α. When the oscillator starts to oscillate, the current Im3 charges the capacitor C1 from the node b. When the voltage of the node b reaches the turn-on voltage Vgs8 of the NMOS transistor M8, the NMOS transistor M8 is turned on, the node c The potential is then pulled down by the supply voltage vdd. The delay circuit 14 is connected to the node C. When the potential of the node C is pulled down to the transition voltage Vtrgl of the inverter, the output of the inverter INV1 is switched, and then the inverter INV2 is passed, and the node ATD generates a square wave pulse. From , , , to "〇", the square wave pulse is again turned via the inverted HINV3 "〇,, becomes the signal of S1, the signal S1 is turned on, and the transistor M9 is turned on, and then the node B is pulled. ''〇,, the potential turns off the surface 〇8 晶晶 [ 5 201208249 body M8, then the node C is then pulled back to the high voltage vdd, so that the inverter inv3 is changed from "0" to "Γ signal S1 turns off the NMOS In the case of the crystal M9, the capacitor C1 is returned to the state of charge. The circuit formed by the transistors M8, M9 and the delay circuit 14 thus repeats the charging and discharging operation of the capacitor C1. The inverter INV1 of the delay circuit 14 is used. The transition voltages of INV2 and INV3 only determine the delay time of the signal S1 to the NMOS transistor M9, and the width of the pulse square wave of the node ATD' even if the transition voltages of the inverters IjsjVi and INV3 vary with the process to the node B. The effect of the charge and discharge time of capacitor C • Very small, so it is not Affecting the oscillation frequency of the relaxation type oscillator of the present invention. In addition, in order to obtain a periodic square wave with a duty cycle of 50%, a frequency divider 20 is connected to the node ATD of the delay circuit 14 to make the node CKmjT _ 5〇 % axis square wave. For other real money, if there is no periodic square wave that is required to be rotated, it is not necessary to connect the node ATD except _ 2〇, and output directly to the node atd. The principle of T=RC is still adhered to. According to the principle of conservation of charge CV=IT, the capacitance value of C substituted into capacitor α is substituted into the conduction voltage Vgs8 of NMOS transistor ,8, and the current is the current Im3. =Im 1 =(Vgs3/Rl), get the formula 1
Cl*(Vgs8)=(Vgs3/Rl)*T。 201208249 1 2Im2 Vgs3= ^UnCox(W/L) M3 +VtM3， 公式2 1 2Im4 Vgs8= ]jUnCox(fV/L) ug +VtM8， 公式3 將電晶體M3及M8設計為相同特性得到VtM3 = VtM8，又因為 電流Im2及Im4相同，得到Cl*(Vgs8)=(Vgs3/Rl)*T. 201208249 1 2Im2 Vgs3= ^UnCox(W/L) M3 +VtM3, Equation 2 1 2Im4 Vgs8= ]jUnCox(fV/L) ug +VtM8, Equation 3 Design the transistors M3 and M8 to have the same characteristics to get VtM3 = VtM8, And because the currents Im2 and Im4 are the same,
Vgs3=Vgs8。 公式 4 最後，將公式4代入公式1，便可以得到 T=C1*R1。 公式 5 • * * I · 根據公式5可知電容C1的充放電週期(τ)和電源電壓vdd無 關’只對電阻R1及電容C1有線性關係，以利於校準因製程 變動之電阻及電容，獲得準確的振盪頻率。由於節點ATD連 接的除頻器20會對節點ATD的脈衝方波除頻，因此節點 CKOUT輸出的50%的週期方波的頻率週期 Tclk=2T=2*Cl*Rl。 圖2是圖1實施例之相關節點波形圖。節點b為鋸齒三 角波的電容充放電波形，而節點C為一脈衝波形，節點ATD 為一脈衝方波。再經由除頻器20對節點ATD的脈衝方波除 頻’於此振盪器的輸出CKOUT產生一工作週期(duty cycle)為pi 7 201208249 50%的週期方波。 圖3是本發明之第二實施例，是根據相同的想法將_〇§ 電晶體由PMOS電晶體取代，而PMOS電晶體改為_〇8電 晶體’亦可得到同樣的效果。 本發明低耗電的弛張型振盪器除了保有頻率對電壓變動 之低敏感性，其週期頻率對電阻及電容同樣保有線性關係 T=RC，所以當製程變動時只要調整電阻或電容就能達到頻率 校準(trimming)的目地。而在低耗電需求中，本發明的弛張型 振盪器電路將直流電流路徑省略到只剩4個直流電流路徑 Im卜Im2、Im3、lm4，因此在耗電部分得到改善。另外，在 低耗電需求中，還需要降低直流電流路徑上的電流源大小，而 本發明的電路’根據公式Iml=(Vgs3/R1)可知電源電壓的 大小對電流並無影響’在高壓如5V^上更能突顯其優點。 且以0.5um製程為例，電晶體M3的Vgs3約〇 75v，根據公 式Iml=(Vgs3/Rl)，電流Iml達到3uA以下時電阻R1只需2观 Ω ’與前例說明比較’此電路電阻值約為前例的六分之一，此 代表節省了 1C中内部電阻所佔用的面積。 以上對於本發明之較佳實施例所作的敘述係為闡明之目 的，而無意限定本發明精確地為所揭露的形式，基於以上的教 導或從本發_魏解f而作修改或變化是可能的，實施例 係為解說本發明的原理以及讓熟f該項技術者以各種實施例 利用本發明在實際應用上而選擇及敘述，本發明的技術思想企 圖由以下的申請專利範圍及其均等來決定。 201208249 【圖式簡單說明】 圖1係本發明弛張型振盪器之實施例； 圖2係圖1實施例之相關節點波形圖；以及 圖3係本發明的第二實施例。 【主要元件符號說明】 10 電流源產生電路 12 充放電電路 14 延遲電路 16 電流鏡 18 電流鏡 20 除頻器Vgs3 = Vgs8. Equation 4 Finally, by substituting Equation 4 into Equation 1, you can get T=C1*R1. Equation 5 • * * I · According to Equation 5, the charge-discharge cycle (τ) of the capacitor C1 is independent of the power supply voltage vdd. 'There is only a linear relationship between the resistor R1 and the capacitor C1 to facilitate calibration of the resistance and capacitance due to process variations. Oscillation frequency. Since the frequency divider 20 connected to the node ATD divides the pulse square wave of the node ATD, the frequency period of the 50% periodic square wave outputted by the node CKOUT is Tclk = 2T = 2 * Cl * Rl. Figure 2 is a waveform diagram of the associated node of the embodiment of Figure 1. Node b is a capacitive charging and discharging waveform of the sawtooth triangular wave, and node C is a pulse waveform, and the node ATD is a pulse square wave. Then, the frequency square wave of the node ATD is divided by the frequency divider 20 to produce a periodic square wave with a duty cycle of pi 7 201208249 50%. Fig. 3 is a second embodiment of the present invention, which is obtained by replacing the PMOS transistor with a PMOS transistor according to the same idea, and the PMOS transistor is changed to _8 transistor. In addition to maintaining low sensitivity of frequency to voltage variation, the low-power relaxation oscillator of the present invention also maintains a linear relationship T=RC for resistance and capacitance, so that the frequency can be adjusted by adjusting the resistance or capacitance when the process changes. The purpose of calibration. In the low power consumption requirement, the relaxation type oscillator circuit of the present invention omits the DC current path to only four DC current paths Im Bu Im2, Im3, and lm4, and thus the power consumption portion is improved. In addition, in the low power consumption demand, it is also necessary to reduce the current source size on the direct current path, and the circuit of the present invention 'according to the formula Iml=(Vgs3/R1), the magnitude of the power supply voltage has no influence on the current 'at high voltage 5V^ can highlight its advantages. Taking the 0.5um process as an example, the Vgs3 of the transistor M3 is about v75v. According to the formula Iml=(Vgs3/Rl), when the current Iml reaches 3uA or less, the resistor R1 only needs 2 Ω Ω 'Compared with the previous example'. About one-sixth of the previous example, this represents the area occupied by the internal resistance in 1C. The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the present invention to the disclosed form. It is possible to make modifications or variations based on the above teachings or from the present invention. The embodiments are described and illustrated in the practical application of the present invention in various embodiments, and the technical idea of the present invention is intended to be equivalent to the scope of the following claims and their equals. To decide. 201208249 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an embodiment of a relaxation type oscillator of the present invention; FIG. 2 is a waveform diagram of a related node of the embodiment of FIG. 1; and FIG. 3 is a second embodiment of the present invention. [Main component symbol description] 10 Current source generation circuit 12 Charge and discharge circuit 14 Delay circuit 16 Current mirror 18 Current mirror 20 Frequency divider