TW201208035A - Multi-chip stacked assembly with ground connection of EMI shielding - Google Patents

Abstract

Disclosed is a multi-chip stacked assembly with ground connection of EMI shielding. There are lower and upper chips disposed on a substrate and a shielding tape interposed between the two chips. The lower chip is electrically connected to the substrate by two designed kinds of electrically connecting components, for example, a plurality of first bonding wires and a second bonding wire having a higher wire loop than the one of the first bonding wires. Therein, the second bonding wire connect ground pad of the lower chip with ground structure in the substrate. The shielding tape consists of a metal shield core, an adhesive layer for attaching to the upper chip, and a FOW layer for attaching to the lower chip. Partial sections of the first and second bonding wires are embedded in the FOW layer. By the loop height difference of the two kinds of bonding wires, only the second bonding wire is in contact with the metal shield core to achieve ground connection of EMI shielding.

Description

201208035 VI. Description of the Invention: t TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a multi-wafer stack structure having a 'shield ground.' [Prior Art] According to the 'new generation of electronic products, the powerful and small size is the demand, and the integrated circuit (1C) inside the product is bound to move toward the operation speed, high component density and high complexity. Due to the increased operation speed and component density of the integrated circuit, the integrated circuit easily generates electromagnetic interference (EMI) with other electronic devices, which reduces the operational efficiency of the integrated circuit. . Among them, electromagnetic interference refers to the damage caused by an electromagnetic body that is to be received by an electromagnetic body. Each electronic component uses a current for its operation, which is surrounded by an electromagnetic field. The surrounding electromagnetic field interferes with the electronic components in the surrounding area, causing the performance of the electronic components to be reduced. In particular, as the size of the semiconductor package is light and thin, the easiest way to reduce the package size is to use multiple wafers. Stacking, but the shrinkage of the RF module encounters a bottleneck. Because the RF chip is sensitive to electromagnetic field interference, the stacked type wafer has been unable to overcome the electromagnetic field interference. Therefore, how to protect the integrated circuit chip in the multi-wafer stack structure from electromagnetic interference becomes a problem worth studying and solving. Figure 1 is a conventional multi-chip package structure 100 having a shield ground. The multi-chip package structure 100 includes a substrate 11A, a first 201208035 wafer 120, a second wafer 15A, a first sealing body 181, a second encapsulant 182, and a metal lid 160. The first chip 120 is a radio frequency chip (RF Chip), and the second chip is a baseband chip (BB Chip), which is a non-stacked structure of individual bonded crystals and sealed. The first wafer 120 and the second wafer 15 can be fixed on the substrate by adhesive bonding, and the first wafer is respectively made by a plurality of first bonding wires 131 and second bonding wires 132. The second package 150 is electrically connected to the substrate 11 (), and the first sealing body 181 covers the first wafer 120 and the first bonding wire 131; the second sealing body 182 is coated with the The second wafer 15 is bonded to the second bonding wire 132 to protect the wafer and the bonding wires. However, the conventional multi-chip package structure i 需 needs to include a formed metal cover 16 as an electromagnetic shield and connected to the ground line of the substrate 11 , and the first wafer 12 , the first bonding wire The 131 and the first encapsulant 181 are disposed in the metal cover 16 to protect the first wafer 120 from electromagnetic interference, and the high density of the multi-wafer stack and the miniaturization of the package size cannot be achieved. In addition, since the metal cover 160 of the multi-chip package structure of the prior art needs to be separately fabricated by an open mold machine and assembled with the sealant formed by the mold seal, it is equivalent to structural design or assembly operation. The complexity is complicated, so not only the time required for the process is increased, but also the size M of the package of different sizes requires a corresponding increase in the design cost and the manufacturing cost. Some people have proposed an improved structure in the shielded grounded multi-wafer stack structure, such as the 201208035 disclosed in Japanese Patent Publication No. 1244179, which has a shielding structure between the two semiconductor wafers and has a ground layer with the substrate. Electrical connection. The shielding structure is composed of a conductive paste, a conductive wire and a blank wafer. The conductive paste is formed on the blank wafer and the conductive wire is fixed in the conductive paste, and the upper wafer is fixed on the conductive paste. According to this structure, the conductive wire is to be connected from one side of the substrate across the two semiconductor wafers to the ground layer on the other side of the substrate. The length of the conductive line is too long to cause collapse, and the conductive line is extra for the shielding structure. The grounding wire of the design is also required to add a corresponding grounding structure on the substrate. Further, the conductive adhesive contacts the back surface of the upper wafer, and a problem of leakage current is likely to occur. In addition, the substrate of the structure needs to be redesigned additionally to design a grounding pad corresponding to the shielding structure to affect the circuit design of the substrate itself, and the manufacturing cost thereof is also increased. [Invention] In view of this, the main object of the present invention is A multi-wafer stack structure with shielding grounding is provided, which can directly utilize the existing grounding structure of the substrate, and the ground connection of the electromagnetic interference is not changed without changing the substrate and additionally adding a bonding wire dedicated to the shielding grounding. 'Effects the interference of electromagnetic fields effectively and simplifies multi-wafer stacking. The purpose of this month is to provide a multi-wafer stack structure with shield grounding, without the need for additional metal covers, and to further reduce the size of the package structure. The object of the present invention and solving the technical problem thereof is to adopt the following technical methods.

The case was realized. The present invention jg-^a.Q discloses a multi-chip stack with shield grounding

The stacked structure 'includes a substrate, a cage B day dice, a plurality of first bonding wires, 201208035 • a second bonding wire, a second wafer, and a shielding tape. The substrate has an upper surface on which a plurality of fingers and a ground structure are disposed. The first wafer is disposed on the substrate, and one of the main surfaces of the first wafer is provided with a plurality of solder pads and a ground pad. The first bonding wires have a first line arc and connect the solder pads of the first wafer to the fingers of the substrate. The second bonding wire has a second line arc larger than the first line arc and connects the ground pad of the first wafer to the grounding structure of the substrate. The second wafer is stacked on the first wafer. The shielding tape is interposed between the first wafer and the second wafer, the shielding tape is composed of a metal shielding core layer, a layer of a magnetic layer on the metal shielding core layer, and a layer of the metal shielding layer. a layer of a glue layer under the core layer, wherein the layer of adhesive layer is attached to a back surface of one of the second wafers, the line of adhesive layer is attached to the active surface of the first wafer, and The first bonding wire and the second bonding wire are partially embedded in the wire coating layer, and only the second wire is made by the height difference between the second wire arc and the first wire arc. Contacting the metal shield core layer to form a shield ground electrical connection. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing multi-wafer stack configuration, the first wafer system can be a baseband wafer. The second wafer is a radio frequency wafer. In the multi-wafer stack configuration described above, the metal shield core layer may be selected from one of copper foil and aluminum foil. In the foregoing multi-wafer stack construction, the shielding tape can be a wafer size shield of the same size as the second wafer, attached to the second wafer at the wafer level 201208035 r and cut during the wafer. Formed simultaneously with the second wafer, such that the die layer completely covers the back side of the second wafer. In the foregoing multi-wafer stack configuration, the second wafer and the mask tape may each be no smaller than the first wafer. In the aforementioned multi-wafer stack configuration, the first bonding wires may be reversely wired. The second fresh wire is a positive wire bonding. In the foregoing multi-wafer stack configuration, a plurality of third bonding wires and a gel may be further included. The third bonding wires are electrically connected to the second wafer to the substrate. The encapsulation system is formed on the upper surface of the substrate to seal the first wafer, the second wafer, the shielding tape, the first bonding wires, the second bonding wires, and the third bonding wires. In the foregoing multi-wafer stack configuration, the curing temperature of the bonding layer may be higher than the glass transition temperature of the coating layer and lower than the curing temperature of the coating layer. The present invention also discloses the application of another multi-wafer stack having a shield ground to include a substrate, a first wafer, a ground bond wire, a second wafer, and a shield tape. The substrate has an upper surface on which a plurality of leads and a ground structure are provided. The first wafer is placed on the substrate. The active surface of the first wafer is provided with a plurality of pads and a ground pad. The leads are connected to the pads of the first wafer. The ground bonding wire has a grounding structure that is higher than a line arc of the leads and connects the ground pad of the first wafer to the substrate. The second wafer is stacked on the first wafer. The shielding tape is interposed between the first wafer and the second wafer, the shielding tape is composed of a metal screen 201208035 to cover the core layer, a layer of a bonding layer on the metal shielding core layer, and a layer The wire-shielding layer under the metal shielding core layer is adhered to the back surface of the second wafer, and the covered knee layer is attached to the active surface of the first wafer. And the lead wires and the ground bonding wire are partially embedded in the wire coating layer, and the ground wire is contacted to the metal shielding core layer by the height I′ of the wire arc relative to the wires. Forming a shield grounding electrical connection. θ can be seen from the above technical solution, the shielded grounded stack structure of the present invention has the following advantages and effects: by means of upper and lower B-plates, shielding tape, welding wires of different arc heights (or lead wires and As a technical means of the present invention, the specific combination relationship of the height difference of the lower wafer grounding wire can be achieved by using the existing grounding structure of the substrate without changing the substrate and additionally adding a bonding wire dedicated to the shielding ground. Grounding shielded electromagnetic interference

It effectively blocks the interference of electromagnetic fields and simplifies multi-wafer stacking. The specific combination of the upper and lower wafers, the shielding tape, the welding lines of different arc heights (or the height difference between the lead wires and the lower wafer grounding wires), as one of the technical means of the present invention, does not require a metal cover, and can be further reduced. The volume of the package construction. The specific combination of the upper and lower wafers, the shielding tape, the welding lines of different arc heights (or the height difference between the lead wires and the lower wafer grounding wires) can be one of the technical means, and can be completed in the existing wire bonding process. The effective blocking effect of electromagnetic interference. r ο τ t ί 8 201208035 [Embodiment] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which The basic architecture or implementation method only shows that the components and combinations associated with the case 'g are not drawn in the actual number, shape, and size of the actual implementation. Some size ratios are proportional to other related sizes. Exaggeration or simplification of processing to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to a first embodiment of the present invention, a multi-wafer stack structure having a shield ground is exemplified in a cross-sectional view of Fig. 2 and a cross-sectional view of the elements in the processes of Figs. 3A to 3C. The multi-chip stack structure 200 mainly comprises a substrate 21, a first wafer 22, a plurality of first bonding wires 230, a second bonding wire 24, a second wafer 25A, and a shielding tape 260. The substrate 210 has an upper surface 211, and the upper surface 2u is provided with a plurality of fingers 2 1 2 and a ground structure 2 1 3 . The substrate 2 丨 0 is used to provide electrical connection and as a wafer carrier of the multi-wafer stack structure, usually a printed circuit board, or a ceramic carrier board, a glass substrate or a circuit film. The upper surface 211 is typically the surface on which the wafer is disposed and covered by the encapsulant. Specifically, the substrate 21 is a multilayer circuit board (not shown) having a circuit layer or a power layer and a ground layer. In a specific embodiment, the substrate 210 The internal system may be pre-formed with a ground layer and electrically connected to 201208035. The ground structure 213 of the upper surface 211 may include a ground ring surrounding the first wafer. The periphery of 220. In various embodiments, suitably designed ground structures can also be of different shapes, such as strips, T-shapes or fingers. The first wafer 220 is disposed on the substrate 210. One active surface 221 of the first wafer 220 is provided with a plurality of signal pads 222 and a ground pad 223. The first wafer 220 is a semiconductor element formed with an integrated circuit (1C), such as a memory, a logic element or an application specific integrated circuit (ASIC), which is divided by a wafer. And out. The first wafer 22 can be affixed to the substrate 210 by a die attach material such as tape, B-stage adhesive or Die Attach Material (DAM). The pads 222 are connected to the outer ends of the integrated circuit, and are usually made of aluminum or copper. The ground pad 223 is used for non-signal transmission to connect to the ground structure to prevent the first chip 2 2 from being disturbed by external noise. The second wafer 250 is stacked on the first wafer 220. The second wafer 25 has an active surface 251 and a back surface 252. In this embodiment, the second wafer 25 is disposed on the first wafer 22A with the active surface 251 facing upward. In addition, in this embodiment, the first wafer 220 can be a BB chip, and the second wafer 25 can be a RF chip, which can be a small stacked wafer type. . In other embodiments, the first wafer 22 can also be a radio frequency wafer, and the second second wafer 250 can also be a base frequency wafer. When the lower layer wafer is a high frequency wafer, the grounding structure of the ground layer of the lower layer 10201208035* is grounded by a grounding wire (ie, the second bonding wire MO), and the grounding wire is electrically connected. The structure of the shielding tape 260 is provided to provide electrical shielding to prevent noise and interference ((^^^^^) effect when the electrical signal is operated at a high frequency. (Detailed structure is detailed later) As shown in FIG. 3A, in the embodiment, the first bonding wires 230 and the second bonding wires 240 are wire bonding wires formed by wire bonding, and may be gold wires or copper wires. The first bonding wire 23 has a first wire arc 231 and connects the pads 222 of the first wafer 22 to the fingers 212 of the substrate 210 to signal the first wafer 22 Electrically connected to the substrate 210. The second bonding wire 240 has a second wire arc 241 larger than the first wire arc 231 and connects the ground pad 223 of the first wafer 220 to the ground structure of the substrate 210. 213, the ground electrode of the lower layer wafer is turned on to the ground line of the substrate 210, so that the basic structure of the second bonding wire 240 is known. The grounding structure for connecting the ground electrode of the first wafer 220 to the substrate 21 is used. Therefore, as shown in FIG. 3A, the second line arc 241 of the second bonding wire 240 is higher than the first a first line arc 231 of the bonding wire 230, the first line arc 231 and the first line arc 2 4 1 have a height difference η, where the term "line arc" refers to the welding line at the highest point. The height of the height can be made by using a welding needle head (not shown) to make different lengths and angles on the path of the line arc to form a fresh line with different lines of arc southness. The finger 212 and the ground structure 213 are respectively disposed at different distances from the first wafer 220 such that the first bonding wires 23 连接 connected thereto and the second bonding wires 240 have different line arc heights. , can also be used 201208035 to use different directions of wire bonding to achieve different wire arc height of the wire. As shown in Figure 3, in the present embodiment, the first wire and the second wire 240 can be Forward line (f〇rward b〇nding), the first fresh line 240 can have a larger angle of bending and longer The wire is moved to a path to reach a lower arc. However, without limitation, in a variant embodiment, as shown in FIG. 4, the first bonding wires 23〇 may also be reverse bonding. Forming, that is, the first bonding wire 23〇, the ball end is thermocompression bonded to the inner pads 212 of the substrate 210, and the tail ends are thermocompression bonded to the first pads 222 of the first wafer 220. The first line arc 23丨 is provided with a lower and more horizontal level. As shown in FIG. 2, the shielding tape 26 is interposed between the first wafer 220 and the second wafer 250. The tape 26 is composed of a metal shield core layer 261, a die bond layer 262 on the metal shield core layer 261, and a wire coating layer under the metal shield core layer 261 (Film-〇Ver-Wire). , the structure of the bonding layer 262 is attached to the back surface 251 of the second wafer 25 , and the coating layer 263 is attached to the active surface of the first wafer 22 . 22ι, and the first bonding wire 230 and the second bonding wire 24 are partially embedded in the coating layer 2 63 by the second wire arc 241 and the The height difference between the one-line arcs 231 only causes the second bonding wires 24 to contact the metal shielding core layer 26 1 to form a shield grounding electrical connection. Therefore, it is known that the second bonding wire 240 extends to the upper and lower sides. The shielding tape 260 between the wafers can be grounded to the grounding structure of the substrate 21, without additionally adding a grounding bonding wire dedicated to shielding the grounding connection, and facilitating the simplification of the polycrystalline 12 201208035 chip stacking operation. Therefore, the present invention can utilize the substrate 2 and the grounding structure 2 1 3 and the grounding bonding wire to achieve the grounding connection for shielding electromagnetic interference without changing the substrate, thereby effectively blocking the interference effect of the electromagnetic field. Specifically, the shielding tape 260 has electromagnetic shielding and upper

The lower wafer is adhered to the bonding wire, and is connected to the grounding pad 223 of the first wafer 220 and the metal shielding core layer 261 by the second bonding wire 24, and then connected to the substrate 2 The grounding structure 2丨3 is used to impart the grounding effect of the electromagnetic shielding to the multi-wafer stack structure 200. Therefore, the multi-wafer stack structure 200 of the present invention does not require an additional metal cover, and can further reduce the volume of the package structure. In detail, the shielding tape 26 has at least two layers of sandwich sandwich structure, and the metal shielding core layer 261 is selected from one of copper foil and aluminum foil, and the hole structure is such that the adhesive layer The 262 is not in contact with the cover tape layer 263 and the shield tape 260 has a suitable rigidity. The shielding tape 26 is in the form of a complete sheet to be fully attached to the back side 252 of the second wafer 25 . Therefore, the shielding tape 26 can be a wafer size shield of the same size as the second wafer 25, which is attached to the second wafer 250 at the wafer level and is cut at the wafer and the first The two wafers 25 are simultaneously formed, so that the die layer 262 completely covers the 250 and 220, the back surface 252 of the second die 25 . Preferably, as shown in FIG. 2, the shielding tape 260 of the second wafer may be no smaller than the first wafer to achieve complete shielding between the first wafer 220 and the second wafer 250. The second wire arc 241 [S] 13 201208035 can be effectively ensured to be pulled out by the second bonding wire 240. The metal shielding core layer 261 can be contacted. Further, as shown in Fig. 2, the multi-wafer stack structure 2 can further include a plurality of third bonding wires 270 and a gel 280. The third bonding wires 270 are electrically connected to the second pads 25 to the plurality of fingers 212 of the substrate 21 . The encapsulant 280 is formed on the upper surface 211 of the substrate 210 to seal the first wafer 22 , the second wafer 250 , the shielding tape 260 , the first bonding wires 230 , and the second bonding wires 240 . And the third bonding wire 270 provides proper package protection against electrical short-circuiting® and dust contamination. The encapsulant 280 can be an Epoxy Molding Compound (EMC), and can be transferred to the upper surface 211 of the substrate 21 by transfer molding. In addition, the multi-wafer stack structure 200 may further include a plurality of external terminals 290' disposed on the lower surface of the substrate 210. The external terminals 290 may comprise a plurality of solder balls, solder pastes, contact pads or contact pins, and the like. In this embodiment, the external terminals 290 are solder balls (ser 1 (Jer • bal1), thereby forming a multi-wafer ball grid array package, and the first wafers are mounted on the multi-wafer stack structure 200. 220 and the second wafer 25 are electrically connected to an external printed circuit board (PCB). Please refer to the cross-sectional views of FIGS. 3A to 3C, and the present invention further illustrates that the shielding tape 260 is formed in the first The process of the active surface 221 of a wafer 22 to demonstrate the efficacy of the present invention. As shown in FIG. 3A, the first bonding wires 23A and the second bonding wires 24 can be made different by various methods. a line arc of height (described in 201208035), wherein the second line arc 241 of the second bonding wire 240 is higher than the first line arc 231 of the first bonding wires 230, the first line arc 231 and The second line arc 241 has a height difference η. Preferably, the first bonding wire 230 and the second bonding wire 240 are made of gold (Au) to provide better forgeability. And ductility. Alternatively, copper wire with better conductivity can be used instead of Ben, and because the hardness of the copper wire is more south than in the subsequent process, when the wire bonding layer 263 is pressed down to the second bonding wire 240, the second bonding wire 240 can have a higher hardness without generating Wire mesh apse or/and deformation. As shown in Figures 3B and 3C, the shielding tape 260 is pre-attached to the back surface 252 of the second wafer 250. Preferably, the die layer The curing temperature of 262 may be higher than the glass transition temperature (Tg) of the coating layer 263 and lower than the curing temperature of the coating layer 263. Specifically, the coating layer 263 It has a buffering elasticity 'and has a B-stage or semi-curing property when it is bonded, and can generate adhesion and fluidity when heated to a proper die-bonding temperature to complete the first bonding wire 230 and the second welding. The partial coating of the wire 240. Since the curing temperature of the bonding layer 262 is higher than the glass transition temperature of the coating layer 263, the bonding temperature in the upper wafer is higher than that of the coating. The glass transition temperature of layer 263 does not allow the layer to be cured, usually the temperature of the crystal The degree is about 40 degrees Celsius to 2 degrees Celsius 'the adhesive layer 2 6 2 is viscous' for bonding the bonding layer 2 6 2 with the first wafer 250. The shielding tape 260 is thermocompression bonded. To the first wafer 220, the temperature of the hot press is about one hundred degrees Celsius to five degrees Celsius 201208035 Baidu, and during the hot pressing process, a suitable pressing force is applied to make the covered knee layer 263 paste. Attaching to the active surface 221 ′ of the first wafer 22 并 and causing the first bonding wire 23 〇 and the second bonding wire 240 of the covering layer 263 to be partially covered, and ensuring & It will be affected by the mold flow to create a line. In particular, as shown in FIG. 3, the second line arc 241 of the second bonding wire 240 is electrically connected to the metal shielding core layer 26 to form the multi-chip stack structure. ^ 200 < electromagnetic shielding shield grounding circuit,

In addition, the electromagnetic radiation interference is effectively reduced, so that the interference effect of the electromagnetic field can be eliminated in the existing wiring process. Preferably, the thickness of the coating layer 263 is equal to or less than the thickness of the first line arc 241 (referred to as the height of the highest point of the first wafer 22 到 to the second bonding line 240) So that the second line can be electrically connected

The metal shield core layer 261 is touched. In addition, the thickness of the bonding layer 263 may be greater than the thickness of the bonding layer 262 and the metal shielding core layer 26, and the bonding layer 262 is only used to adhere the back surface 252 of the second wafer 25 The thickness of the coating layer 263 may be less than the thickness of the coating layer 263. For example, the thickness of the bonding layer 262 may be about 丨〇25. 5 (^m, the thickness of the metal core layer 261 may be about 1 〇 to 25 em, to have a screen electromagnetic. Briefly describe the formation method of the shielding tape 26 ,, the metal shielding core layer 261 can be After the template is plated or formed as a metal foil, after the wire coating layer 263 is printed, the die-cut layer 262 can be printed on the wafer by a wafer dicing tape to form the shielding tape 26 〇. As shown in the figure, when the shielding tape 26 is adhered to the "201208035 piece 220", the shielding tape 260 is completely attached to the active surface 221 of the r-th wafer 220. Since the second bonding wire 240 has a comparative High height 'so the second bonding wire 24 can electrically contact the metal shielding core layer 261' and lower The first bonding wire 230 is controllably not in contact with the metal shielding core layer 261. According to a second embodiment of the present invention, another multi-wafer stacking structure having a shield ground is illustrated in the wearing diagram of FIG. The main components in the same manner as the first embodiment will be denoted by the same reference numerals and will not be further described. The multi-wafer stack structure 300 mainly includes a substrate 210, a first wafer 220, a grounding wire 340, and a second. The wafer 250 and a shielding tape 260. In the present embodiment, as shown in FIG. 5, the multi-wafer stack structure 300 is a Cavity Down Ball Grid Arrays (CDBGA) semiconductor. a package member, the substrate 21 has a cavity 315' for receiving the first wafer 220, and the wire bonding layer 263 is further attached to the upper surface 211 of the substrate 210, so the multi-chip The stack structure 300 can have a lower package height. The upper surface 2 11 of the substrate 21 is provided with a plurality of leads 3 14 and a ground structure 2 1 3 . The leads 314 are connected to the first wafer 220. The pads 2 22 . The 314 series may be an internal component of the substrate 210 or an externally attached lead inner lead, and the lead wires 314 may be press-contacted to the first wafer by an Ib bonding head. The solder pads 222 of the 220 are electrically connected to the first wafer 220. In this embodiment, the active 201208035 surface 221 of the first wafer 220 and the upper surface of the substrate 210 211 is located at the same level or slightly lower than 'the wires 3 14 are not horizontal, but horizontal. The ground wire 340 has a wire arc 341 higher than the lead wires 314 and connects the ground pad 223 of the first wafer 22 to the ground structure 21 of the substrate 21 . In this embodiment, as shown in FIG. 5, the wire bonding layer 263 is attached to the active surface 221 of the first wafer 220, and the leads 314 and the ground bonding wire 34 are partially connected. Embedded in the wire coating layer 263, the height difference of the wire arc 341 relative to the leads 314 causes the ground wire 340 to contact the metal shielding core layer 261 to form a shield grounding electrical connection. Effectively reduce the interference of electromagnetic radiation. The above is only a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above by way of preferred embodiments, it is not intended to limit the invention, any skilled practitioner, Any simple modifications, equivalent changes, and (4) made within the technical scope of the present invention are still within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS A cross-sectional view of a multi-chip package structure having a shield ground is known. Fig. 2 is a cross-sectional view showing a multi-wafer stack structure having a shielded ground according to a first embodiment of the present invention. Figures 3 to 3C are schematic cross-sectional views of elements in a process in accordance with a multi-wafer stack construction of the first embodiment of the present invention. [S3 18 201208035 示 缭 , , 在 在 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例 例Another example of the implementation of the 〇 图 具 具 具 具 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 依 第 依 依 依 依 依 依 依 依 依 依 第 依 依 依 第 第 第 第 第 第 第 第 第No. 高度 Η 高度 高度 高度 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 Refers to 222 solder 塾 200 multi-chip stack structure 210 substrate 211 upper surface 2 1 3 ground structure 220 first wafer 221 active surface 223 ground pad 230 first bond wire 230 'first bond wire 240 second bond wire 250 second wafer 260 Shielding tape 231 first line arc 231 'first line arc 241 second line arc 251 active surface 252 back side 261 metal shield core layer 19 201208035 262 bonding layer 263 270 second bonding wire 280 sealing body 290 300 multi wafer stacking structure 314 Lead Line 315 340 Grounding welding wire 341 Covering glue layer External terminal Rongjing hole Line arc

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Claims (1)

201208035. VII. Patent application scope: 1. A multi-wafer stack structure with shielding grounding, comprising: a substrate having an upper surface, wherein the upper surface is provided with a plurality of fingers and a grounding structure; The wafer is disposed on the substrate, and one active surface of the first wafer is provided with a plurality of radii and a ground 塾; the plurality of first bonding wires have a first line arc and are connected to the first wafer The solder pads to the plurality of fingers of the substrate; the second solder wire ' has a second line arc larger than the first line arc and connects the ground pad of the first chip to the ground of the substrate a second wafer is stacked on the first wafer; and a shielding tape is disposed between the first wafer and the second wafer. The shielding tape is composed of a metal shielding core layer. a die bond layer on the metal shield core layer and a wire bond layer under the metal shield core layer, wherein the die bond layer is attached to a back surface of one of the second wafers, The cover tape layer is attached to the first The active surface of the sheet, and the first bonding wire and the second bonding wire are partially embedded in the coating layer, and the height difference between the second line arc and the first line arc The second bonding wire is only brought into contact with the metal shielding core layer to form a shield grounding electrical connection. 2. A multi-wafer stack structure having a shielded ground according to claim 1 wherein the first wafer is a baseband wafer and the second 21 〇 12 〇 8 〇 35 曰曰 is a radio frequency wafer. 3. A multi-wafer stack having a shielded ground according to the first aspect of the patent application; ^ ^ wherein the metal shield core layer is selected from one of copper pigs and aluminum foil. 4' root Φ 1 main * 甲甲 is called the patented range i, the shielded grounded multi-chip stack structure i U k, wherein the shielding tape is a same size as the second wafer Attached to the wafer level The first ruthenium film is formed simultaneously with the second wafer during wafer dicing such that the mold layer completely covers the back surface of the 晶片 three wafer. 5. A multi-positive sheet stacking structure having a shielded joint according to claim 1, 2, 3 or 4, wherein the second wafer and the masking tape are both not smaller than the first wafer. 6. A multi-wafer stack structure having a shielded ground according to the scope of claims 2, 3 or 4 of the patent application, wherein the first solder wires are reversed wires. The second wire is a positive wire. 7' according to the patent application scope, the plurality of wafer stacking structures 2, 3 or 4 have shielding connections, and further comprising: a plurality of third bonding wires ' electrically connecting the third wafer to the substrate; - sealing: The body is formed on the upper surface of the substrate to seal the first wafer, the second wafer, the shielding tape, the first bonding wires, the second bonding wires, and the third bonding wires. 8' according to (4) a multi-wafer stack structure having a shield grounding, wherein the curing temperature of the adhesive layer is higher than the glass transition temperature of the coating layer and lower than the coating adhesive 22 201208035 Μ layer Curing temperature. 9. A multi-wafer stack structure having a shield ground, comprising: a substrate having an upper surface on which a plurality of leads and a ground structure are disposed; a first wafer disposed on the substrate The active surface of one of the first wafers is provided with a plurality of fresh sputum and a ground sluice, wherein the leads are connected to the pads of the first wafer; a grounded zinc wire has a higher than the leads a line arc is connected to the ground pad of the first wafer to the ground structure of the substrate; a second wafer is stacked on the first wafer; and a shielding tape is disposed on the first wafer The shielding tape is composed of a metal shielding core layer, a bonding layer on the metal shielding core layer and a coating layer under the metal shielding core layer. The adhesive layer is attached to the back surface of one of the second wafers, and the adhesive layer is attached to the active surface of the first wafer, and the leads are partially embedded with the ground bonding wire. In the covered glue layer, by the line The height difference of the arc relative to the leads causes the ground wire to contact the metal shield core layer to form a shield ground electrical connection. 1 . The multi-wafer stack structure having shielding grounding according to claim 9 of the patent application, wherein the substrate has a cavity for accommodating the first wafer and attaching the covered knee layer to the The upper surface of the substrate. twenty three