201143099 六、發明說明： 【發明所屬之技術領域】 本發明有關於一種薄膜電晶體（thin film transistor, TFT )裝置，特別是有關於一種用於主動式陣列平面顯示 器中具有遮光層的多閘極薄膜電晶體（multi-gate TFT)裝 置。 【先前技術】 馨近年來’主動式陣列平面顯示器的需求快速的增加， 例如主動式陣列液晶顯示器（active matrix liquid crystal display，AMLCD)顯示器。主動式陣列液晶顯示器通常利 用薄膜電晶體作為晝素及驅動電路的開關元件，而其可依 據主動層所使用的材料分為非晶矽（a_Si)及多晶矽薄膜電 晶體。 上述薄膜電晶體裳置包括閘極電極及具有通道區、源 極及汲極區的主動層’用以將影像資訊回應至顯示裝置的 鲁 晝素電極。然而’當晝素區的薄膜電晶體裝置處於關閉的 狀態（OFF state)且若光（例如，背光源）照射到主動層 (例如，圖案化的半導體層）時，主動層内會產生電子電 洞對而形成光漏電流（photo leakage current )，使得影像 品質降低。 【發明内容】 本發明一實施例提供一種影像顯示系統。此系統包括 一多閘極薄膜電晶體裂置，其包括：·一基底、一主動層、 9109-A34987TWF_P2010005 201143099 I» 第^第一閘極結構以及第一及第二遮光層。基底具有一 晝素區。主動層設置於基底的畫素區上，包括第二^第二 原和；及極區、第一及第二通道區以及一通道連接區。第一 通道區鄰接第一源極及極區的一第一輕摻雜區與通道連 ^區的-第三輕摻雜區，且第二通道區鄰接第二源極淡極 2的一第二輕摻雜區與通道連接區的—第四輕捧雜區。第 一及第二閘極結構設置於絲層上結別對應於第一及第 二通道區’其中第—及第二閘極結構彼此電性連接。第一 及第二遮光層設置於基底與主動層之間。第一遮光層對應 於第-輕摻雜區且橫向延伸至至少一部分的第一通道區; 方而第_遮光層對應於第二輕摻雜區且橫向延伸至至 一部分的第二通道區下方。 【實施方式】 鏐 以下說明本發明實施例之製作與使用。然而，可輕易 了解本發明所提供的實_❹於制以特定方法 使用本發明，並非用以侷限本發明的範圍。 、 林發㈣施狀影像顯示_。第1圖緣示 出根據本發明—實施例之影像顯示系統，特別是 ==#膜電晶體(TFT)裝置2⑻的影像顯示系統:、並 2問極缚膜電晶體裝置可為N型或p型且包括且有 :晝素區1>的-基底⑽。基底】⑼可由石英 了 =材料:構成。-緩衝請可選擇性地設置於ί • ，以作為基底100與後續所形成的主動声 黏著層或是污染阻障層。緩衝層1〇4可為一單== 9109-A34987TWF_P2〇l〇〇〇5 , 201143099 構。舉例而言，緩衝層104可由一氧化矽、一氮化矽、或 其組合所構成。 一主動層106設置於基底100的晝素區p上。主動層 106可由非晶矽或多晶矽所構成。在本實施例中，主動層 1〇6包括：一第一源極/汲極區1〇7a、—第二源極/汲極區 腿、1 -通道區106c、-第二通道區1G6g以及連接 第一及第二通道區106C及i〇6g的一通道連接區i〇7c。在 中，第—源極級極區隐係作為多閘極薄膜電 j裳置·的源極而第二源極/祕區】_則作 ill電「晶體裝置2〇0的沒極。在另一實施例中，第一源 =及極區1G7a可作為多閘極薄膜電晶體裝置細的沒極 源極㈣區職則作為多閘極薄膜電 的=。在本實施例中，第—源極後極區_化〇 一重摻雜區l〇6a及一第一軔換 弟 i〇7b Γ 1Λ^ 修雜k 1061及—第二輕摻雜卩 -第::二雜區咖包括一第三重摻雜區Μ6:、 弟—“雜£嶋及—第四輕摻雜區贿。 106c鄰接第一輕摻雜區 、區 -ϋΓ* D興第二輕摻雜區106d，j笛 一通道區106g鄰接第二輕換 且第 106f〇 祕與第四輕穆雜區 上且分二：第=第_第結構設置於主動層⑽ -及第二問極結構彼此=s:06c叫其中第 -閘極介電層及一閘極層u 苐、T極結構包括至少 中’閘極介電層可包括由氧層。在一實施例 礼化矽所構成的絕緣層108及位 9109-A34987TWF P2010005 201143099 於其上方且由氮化矽所構成的絕緣層11〇。同樣地，第二 閘極結構包括至少一閘極介電層（例如，絕緣層1〇8及位 於其上方且由氮化矽所構成的絕緣層112)及一閘極層 所構成的疊層。 在本貝％例中，為了防止或降低因基底〗下方背光 源（未繪示）照射主動層106而引發的光漏電流，一遮光 層102，„又置在基底1〇〇與主動層106下方的緩衝層104 之間，以遮蓋整個主動層106而避免光照射到主動層1〇6。 遮光層102可由金屬、半導體材料（例如，矽）或其他吸 光材料所構成。 需注意的是上述實施例中具有二個閘極及二個通道 區多閘極薄膜電晶體裝置200僅為範例說明，然而實際的 閘極與通道區的數量可取於設計需求，並不以此為限。 接下來’ s青參照第2至7圖，其繪示出根據本發明其 他不同實施例之具有多閘極薄膜電晶體裝置的影像顯示^ 統，其中相同於第1圖的部件係使用相同的標號並省略其 說明。請參照第2圖中，不同於第】圖所示的實施例/多 閘極薄膜電晶體裝置20 0具有分隔的第一遮光層丨〇 2 a及第 二遮光層102b，其設置於基底100與主動層1〇6之間。特 別的是第一遮光層102a對應於第一輕摻雜區1〇补且橫向 延伸至至少一部分的第一通道區l〇6c下方，而第二遮光層 l〇2b對應於該第二輕摻雜區i〇6h且橫向延伸至至少一部 分的該第二通道區1(^下方。第一及第二遮光層隐及 102b可相同或相似於遮光層1〇2 (繪示於第i圖）。在本 實施例中，第一及第二遮光層l〇2a及102b完全遮蓋第一 9109-A34987TWF P2010005 g 201143099 及第二輕摻雜區106b及106h及局部遮蓋第一及第二通道 區l〇6c及i06g而露出通道連接區1〇乃。由於位於第一源 極/汲極區l〇7a的第一輕摻雜區勵與第二源極/沒極區 的第二輕摻雜區1〇6h處容易引發較嚴重的光漏電 流’因此本實施例中第一及第二遮光層l〇2a及職的排 置可核降低主動層1〇6中的光漏電流。在其他實施例 中第及第一遮光層102a及l〇2b可進一步延伸，以完 _ 全遮蓋第—及第二通道區106c及106g。 请參照第8圖，其繪示出汲極電流（Id)與閘極電壓 (Vg)轉移特性曲線圖，其中曲線入及6為第}圖中多閘 極薄膜電晶體裝置200分別在汲_源電壓（m 〇.以及 1〇V的轉移特性曲線，而曲線C及D為第2圖中多閘極薄 膜電晶體裝£ 200分別在及-源電壓為0.1 V及10V的轉移 特性曲線。由於遮光層1〇2與主動層1〇6 (繪示於第丨圖） 之間的耦合效應（couplingeffect)，使得起始電壓 φ 在相對低汲源電壓（Vds)與相對高汲·源電壓操作下產生 偏移（如曲線A及B所示）。而分隔的第一及第二遮光層 l〇2a及l〇2b降低了耦合效應，使得起始電壓在相對低汲_ 源電壓與相對高汲-源電壓操作下幾乎一樣（如曲線c及d 所示）。 ^請參照第3圖，不同於第2圖所示的實施例之處在於 第二遮光層102b經由第二通道區1〇6g下方橫向延伸至第 四輕摻雜區1〇6f下方，以完全遮蓋第二通道區1〇6g及第 四輕摻雜區1〇6f。在另一實施例中，第一遮光層1〇2&也經 由第一通道區106c下方橫向延伸至第三輕摻雜區1〇6(1下 9109-A34987T WF_P2010005 〇 201143099 方，以完全遮蓋第一通道區 如第4圖所示。 106c及第三輕摻雜區1〇6d， 清麥照第5圖，不同於第2圖所示的實施例之處在於 多閘極薄膜電晶體裝置200更包括一分隔的第三遮光層 l〇2c:其位於第一與第二遮光層1〇2&及1〇孔之間、對應 於第二輕摻雜區106d以及橫向延伸至至少一部分的第一 通道區106c下方，以完全遮蓋第三輕摻雜區i〇6d及局部 遮蓋第-通道區版。第三遮光層腿可相同或相似於第 -與第二遮光層l〇2a及職。在另一實施例中，第三遮 光層102c可對應於第四輕摻雜區腑以及橫向延伸至^ 少一部分的第二通道區106g下方，以完全遮蓋第四輕_ 區106f及局部遮蓋第二通道區1〇6g。又另一實施例中 二遮光層102b經由第二通道區1〇6g下方橫向延伸至第四 輕摻雜區106f下方，以完全遮蓋第二通道區i〇6g及第四 輕掺雜區106f，如第6圖所示。 請參照第7圖，不同於第5圖所示的實施例之處在於 多閘極薄膜電晶體裝置細更包括一分隔的第四遮光屏 刪，其位於第-與第二遮光層腿及贿之間、對^ 於第四輕掺㈣以及橫向延伸至至少—部分的第二通 道區106g下方’以完全遮蓋第四輕摻雜區丽及局部 蓋第二通道區106g。第四遮光層删可相同或相似 三遮光層102c。 可以理解的是第3至7圖的實施例中，分隔的遮先層 可降低了耦合效應’使得起始電壓在相對低源電壓盘相 對高汲-源電壓操作下幾乎一樣。 ' 9109-A34987TWF P2010005 10 201143099 根據上述實施例，由於在主動層中源極區與汲極區的 輕摻雜區下方對應設置了分隔的遮光層，因此可有效降低 主動層内的光漏電流。再者，相較於完全遮蓋主動層的多 閘極薄膜電晶體裝置，具有分隔的遮光層的多閘極薄膜電 晶體裝置可降低遮光層與主動層之間的耦合效應，進而避 免起始電壓在相對低没-源電壓與相對高没源電壓操作下 產生不必要的偏移而導致顯示裝置的顯示異常。 第9圖係繪示出根據本發明另一實施例之具有影像顯 • 示系統方塊示意圖，其可實施於一平面顯示（flat panel display，FPD)裝置300或電子裝置500，例如一筆記型電 腦、一手機、一數位相機、一個人數位助理（personal digital assistant, PDA)、一桌上型電腦、一電視機、一車用顯示 器、或一攜帶型DVD播放器。平面顯示裝置300可具有之 前所述的多閘極薄膜電晶體裝置200,而平面顯示裝置300 可為液晶顯示面板。如第9圖所示，平面顯示裝置300包 括一多閘極薄膜電晶體裝置，如第1至7圖中的薄膜電晶 * 體裝置200所示。在其他實施例中，電子裝置500可具有 平面顯示裝置300。如第9圖所示，電子裝置500包括： 一平面顯示裝置300及一輸入單元400。再者，輸入單元 400係耦接至平面顯示器裝置300，用以提供輸入信號（例 如，影像信號）至平面顯示裝置300以產生影像。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 9109-A34987TWF P2010005 11 201143099 【圖式簡單說明】 第1至7圖係繪示出根據本發明各個實施例之具有多 閘極薄膜電晶體裝置之影像顯示系統剖面示意圖； 第8圖係繪示出汲極電流與閘極電壓轉移特性曲線 圖； 第9圖係繪示出根據本發明另一實施例之具有影像顯 示系統方塊示意圖。 【主要元件符號說明】 100〜基底； 102〜遮光層； 102 a〜第一遮光層； 102b〜第二遮光層； 102c〜第三遮光層； 102d〜第四遮光層； 104〜緩衝層； 106〜主動層； 106a〜第一重摻雜區； 106b〜第一輕摻雜雜區； 106c〜第一通道區； 106d〜第三輕摻雜區； 106e〜第三重摻雜區； 106f〜第四輕摻雜區； 106g〜第二通道區； 9109-A34987TWF P2010005 12 201143099 106h〜第二輕摻雜區； 106i〜第二重摻雜區； 10 7 a〜第'一源極/汲極區； 107b〜第二源極/没極區； 107c〜通道連接區； 108、110、112〜絕緣層； 114、116〜閘極層； 200〜多閘極薄膜電晶體裝置； 300〜平面顯示裝置； 400〜輸入單元； 500〜電子裝置； P〜晝素區。201143099 VI. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor (TFT) device, and more particularly to a multi-gate having a light shielding layer for use in an active array flat panel display A multi-gate TFT device. [Prior Art] In recent years, the demand for 'active array flat panel displays' has rapidly increased, such as active matrix liquid crystal display (AMLCD) displays. Active array liquid crystal displays generally use a thin film transistor as a switching element of a halogen and a driving circuit, and can be classified into an amorphous germanium (a_Si) and a polycrystalline germanium thin film transistor according to materials used in the active layer. The thin film transistor skirt includes a gate electrode and an active layer having a channel region, a source and a drain region for responding to image information to a lupin electrode of the display device. However, when the thin film transistor device of the halogen region is in an OFF state and if light (for example, a backlight) is irradiated onto the active layer (for example, a patterned semiconductor layer), electron electricity is generated in the active layer. The hole is opposite to form a photo leakage current, which degrades the image quality. SUMMARY OF THE INVENTION An embodiment of the invention provides an image display system. The system includes a multi-gate thin film transistor split including: a substrate, an active layer, 9109-A34987TWF_P2010005 201143099 I» a first gate structure and first and second light shielding layers. The substrate has a halogen region. The active layer is disposed on the pixel area of the substrate, including the second and second regions; and the polar regions, the first and second channel regions, and the one channel connection region. The first channel region is adjacent to a first lightly doped region of the first source and the polar region and the third lightly doped region of the channel region, and the second channel region is adjacent to the second source of the second source The second lightly doped region is connected to the channel-connected region. The first and second gate structures are disposed on the wire layer to correspond to the first and second channel regions, wherein the first and second gate structures are electrically connected to each other. The first and second light shielding layers are disposed between the substrate and the active layer. The first light shielding layer corresponds to the first lightly doped region and extends laterally to at least a portion of the first channel region; and the first light shielding layer corresponds to the second lightly doped region and extends laterally to a portion of the second channel region . [Embodiment] 制作 The production and use of the embodiments of the present invention will be described below. However, it is to be understood that the invention is not limited by the scope of the invention. , Lin Fa (four) Shi image display _. 1 is a view showing an image display system according to an embodiment of the present invention, in particular, an image display system of a ==# film transistor (TFT) device 2 (8): and a bipolar film transistor device can be N-type or The p-type includes and includes: a substrate (10) of the halogen region 1>. Substrate] (9) can be made of quartz = material: composition. - Buffering may optionally be provided at ί. as the active acoustic adhesion layer or the contamination barrier layer formed on the substrate 100 and subsequently. The buffer layer 1〇4 can be a single == 9109-A34987TWF_P2〇l〇〇〇5, 201143099. For example, the buffer layer 104 may be composed of tantalum oxide, hafnium nitride, or a combination thereof. An active layer 106 is disposed on the pixel region p of the substrate 100. The active layer 106 may be composed of amorphous germanium or polycrystalline germanium. In this embodiment, the active layer 1〇6 includes: a first source/drain region 1〇7a, a second source/drain region leg, a 1-channel region 106c, a second channel region 1G6g, and A channel connection area i〇7c connecting the first and second channel regions 106C and i〇6g. In the middle, the first source-source polar region is used as the source of the multi-gate thin film and the second source/secret region is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In another embodiment, the first source=and the pole region 1G7a can be used as a multi-gate thin film transistor as a fine gate source of the multi-gate thin film transistor device. In this embodiment, the first Source rear pole region _ 〇 〇 a heavily doped region l 〇 6a and a first 轫 弟 〇 i 〇 b b b Λ Λ 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 A third heavily doped region Μ6:, brother - "Miscellaneous and - the fourth lightly doped area bribe. 106c abuts the first lightly doped region, the region - ϋΓ * D Xing second lightly doped region 106d, the j flute channel region 106g is adjacent to the second light swap and the 106f secret and the fourth light miscellaneous region are divided into two : the first _th structure is disposed on the active layer (10) - and the second interrogation structure is = s: 06c, wherein the first gate dielectric layer and the gate layer u 苐, the T pole structure comprises at least a middle gate The dielectric layer can include an oxygen layer. In an embodiment, the insulating layer 108 is formed and the insulating layer 11 is formed thereon by a layer of 910-A34987TWF P2010005 201143099. Similarly, the second gate structure comprises a stack of at least one gate dielectric layer (for example, the insulating layer 1 8 and the insulating layer 112 formed thereon and composed of tantalum nitride) and a gate layer . In the example of Benbey, in order to prevent or reduce the light leakage current caused by the backlight (not shown) under the substrate, the light shielding layer 102 is disposed on the substrate 1 and the active layer 106. Between the buffer layers 104 below, the entire active layer 106 is covered to prevent light from being irradiated onto the active layer 1 〇 6. The light shielding layer 102 may be composed of a metal, a semiconductor material (for example, germanium) or other light absorbing material. The multi-gate thin film transistor device 200 having two gates and two channel regions in the embodiment is merely an example, but the actual number of gate and channel regions may be determined by design requirements, and is not limited thereto. Referring to Figures 2 to 7, there is shown an image display system having a multi-gate thin film transistor device according to other different embodiments of the present invention, wherein components identical to those of Figure 1 are labeled with the same reference numerals. The description is omitted. Referring to FIG. 2, the embodiment/multi-gate thin film transistor device 20 shown in FIG. 2 has a first light-shielding layer a2 a and a second light-shielding layer 102b. Set on the substrate 100 Between the active layer 1 and 6. In particular, the first light shielding layer 102a corresponds to the first lightly doped region 1 and extends laterally to at least a portion of the first channel region 16c, while the second light shielding layer 1 〇2b corresponds to the second lightly doped region i〇6h and extends laterally to at least a portion of the second channel region 1 (the lower portion. The first and second light shielding layer concealment 102b may be the same or similar to the light shielding layer 1〇) 2 (shown in Figure i). In this embodiment, the first and second light shielding layers 10a and 102b completely cover the first 9109-A34987TWF P2010005 g 201143099 and the second lightly doped regions 106b and 106h and the portion Covering the first and second channel regions l〇6c and i06g to expose the channel connection region 1 . Because the first lightly doped region and the second source/no source are located in the first source/drain region l〇7a In the second lightly doped region of the polar region, the light leakage current is easily induced at 1〇6h. Therefore, in the embodiment, the first and second light shielding layers 10a and 2a can reduce the active layer 1〇6. In other embodiments, the first and first light shielding layers 102a and 102b can be further extended to completely cover the first and second Channel regions 106c and 106g. Please refer to FIG. 8 , which shows a graph of the drain current (Id) and gate voltage (Vg) transfer characteristics, wherein the curve is entered into a multi-gate thin film transistor in FIG. The device 200 is respectively in the 汲_source voltage (m 〇. and the transfer characteristic curve of 1 〇V, and the curves C and D are the multi-gate thin film transistor package 200 in Fig. 2, respectively, and the source voltage is 0.1 V and 10V transfer characteristic curve. Due to the coupling effect between the light shielding layer 1〇2 and the active layer 1〇6 (shown in the figure), the starting voltage φ is at a relatively low source voltage (Vds) and The offset is generated under relatively high voltage and source voltage operation (as shown by curves A and B). The separated first and second light shielding layers 10a and 2b reduce the coupling effect, so that the starting voltage is almost the same under relatively low 汲 source voltage and relatively high 汲-source voltage operation (such as curves c and d). Shown). Please refer to FIG. 3, which is different from the embodiment shown in FIG. 2 in that the second light shielding layer 102b extends laterally below the second channel region 1〇6g to below the fourth lightly doped region 1〇6f to completely The second channel region 1〇6g and the fourth lightly doped region 1〇6f are covered. In another embodiment, the first light shielding layer 1〇2& also extends laterally below the first channel region 106c to the third lightly doped region 1〇6 (1下9109-A34987T WF_P2010005 〇201143099) to completely cover the first One channel region is shown in Fig. 4. 106c and the third lightly doped region 1〇6d, the clear wheat photo is shown in Fig. 5, which is different from the embodiment shown in Fig. 2 in the multi-gate thin film transistor device 200. Further comprising a partitioned third light shielding layer 10c2: between the first and second light shielding layers 1〇2& and 1 pupil, corresponding to the second lightly doped region 106d and laterally extending to at least a portion of the first Below the one channel region 106c, the third lightly doped region i〇6d is completely covered and the first channel region is partially covered. The third light shielding layer legs may be the same or similar to the first and second light shielding layers 102a. In another embodiment, the third light shielding layer 102c may correspond to the fourth lightly doped region 腑 and the second channel region 106g extending laterally to a portion thereof to completely cover the fourth light_region 106f and the partial opaque portion. The second channel region is 1〇6g. In still another embodiment, the second light shielding layer 102b is disposed under the second channel region 1〇6g Extending laterally below the fourth lightly doped region 106f to completely cover the second channel region i〇6g and the fourth lightly doped region 106f, as shown in Fig. 6. Referring to Fig. 7, different from Fig. 5 The illustrated embodiment is that the multi-gate thin film transistor device further includes a separate fourth blackout screen, which is located between the first and second light-shielding legs and the bribe, and the fourth light blend (four) and Extending laterally to at least a portion of the second channel region 106g below to completely cover the fourth lightly doped region and the partial cover second channel region 106g. The fourth light shielding layer may be the same or similar to the three light shielding layer 102c. In the embodiment of Figures 3 through 7, the separate masking layer reduces the coupling effect' such that the starting voltage is nearly the same as the relatively low source voltage disk is relatively high-source voltage operation. ' 9109-A34987TWF P2010005 10 201143099 According to the above embodiment, since the separated light shielding layer is disposed under the light doped region of the source region and the drain region in the active layer, the light leakage current in the active layer can be effectively reduced. Furthermore, compared with the complete Multi-gate film covering the active layer A crystal device having a multi-gate thin film transistor device with a separate light shielding layer reduces the coupling effect between the light shielding layer and the active layer, thereby preventing the initial voltage from being generated under relatively low no-source voltage and relatively high source voltage operation Unnecessary offset causes display abnormality of the display device. Fig. 9 is a block diagram showing an image display system according to another embodiment of the present invention, which can be implemented in a flat panel display (FPD). The device 300 or the electronic device 500, such as a notebook computer, a mobile phone, a digital camera, a personal digital assistant (PDA), a desktop computer, a television, a vehicle display, or a portable device DVD player. The flat display device 300 can have the multi-gate thin film transistor device 200 described above, and the flat display device 300 can be a liquid crystal display panel. As shown in Fig. 9, the flat display device 300 includes a multi-gate thin film transistor device as shown in the thin film electro-crystal device 200 of Figs. In other embodiments, electronic device 500 can have a flat display device 300. As shown in FIG. 9, the electronic device 500 includes: a flat display device 300 and an input unit 400. Furthermore, the input unit 400 is coupled to the flat panel display device 300 for providing an input signal (for example, an image signal) to the flat display device 300 to generate an image. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. 9109-A34987TWF P2010005 11 201143099 [Simplified Schematic] FIGS. 1 to 7 are schematic cross-sectional views showing an image display system having a multi-gate thin film transistor device according to various embodiments of the present invention; FIG. 8 is a view A graph of a drain current and a gate voltage transfer characteristic; FIG. 9 is a block diagram showing an image display system according to another embodiment of the present invention. [Description of main component symbols] 100 to substrate; 102 to light shielding layer; 102 a to first light shielding layer; 102b to second light shielding layer; 102c to third light shielding layer; 102d to fourth light shielding layer; 104 to buffer layer; ~ active layer; 106a ~ first heavily doped region; 106b ~ first lightly doped hetero region; 106c ~ first channel region; 106d ~ third lightly doped region; 106e ~ third heavily doped region; 106f~ The fourth lightly doped region; 106g to the second channel region; 9109-A34987TWF P2010005 12 201143099 106h~ the second lightly doped region; 106i~ the second heavily doped region; 10 7 a~the first source/dippole 107b~second source/nothing area; 107c~channel connection area; 108,110,112~insulation layer; 114,116~gate layer; 200~multi-gate thin film transistor device; 300~flat display Device; 400~ input unit; 500~ electronic device; P~ 昼素区.
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