201145563 六、發明說明： 【發明所屬之技術領域】 本揭示内容是有關於一種發光二極體，且特別是有關 於一種覆晶發光二極體。 【先前技術】 請參考第1圖，第1圖是習知的覆晶發光二極體封裝 製程的步驟流程圖。傳統的覆晶發光二極體製程包括至少 _ 七個步驟：首先，如步驟101所示，將晶圓上的多個晶粒 110以擴晶技術取出。接下來，如步驟102所示，以一第 一機器手臂210及其真空吸嘴211取下晶粒；如步驟103 所示，第一機器手臂210翻轉晶粒110;如步驟104所示， 晶粒110被翻轉後交由一第二機器手臂220及其真空吸嘴 221接手。當然，另一種可行的做法是採用藍膜翻轉技術 來實現上述過程。然後，如步驟105所示，將晶粒110上 的金屬突球（Bump)lll精準定位在一覆晶轉接板 φ (Board) 120上的導電接點121。之後，如步驟106所示，以 微波等方式加熱金屬突球111，使晶粒110與覆晶轉接板 120電性連接。最後，如步驟107所示，利用點膠技術封 裝晶粒110與覆晶轉接板120間的空隙，至此完成一晶片 130之封裝製作；此外，晶片130通常還需要再進行一次 烘烤，以固化點膠時填充之材料。至此，晶片130方為一 可直接使用的產品；使用時，晶片130係利用覆晶轉接板 120上預設之導電結構，與一電路板上的電路再進行電性 連接。 [ 201145563 【發明内容】 因此，本揭示内容之技術態樣是在提供一種覆晶發光 二極體晶粒，以免除晶片之封裝製程。 根據本揭示内容一技術態樣，提出一種覆晶發光二極 體晶粒，包括一第一型摻雜半導體層、一第二型摻雜半導 體層、一第一電極層、一第二電極層及一絕緣層。第二型 摻雜半導體層鋪設於第一型摻雜半導體層之底面，第一電 • 極層鋪設於第一型摻雜半導體層之底面且不接觸第二型摻 雜半導體層，而且具有一裸露面積以供直接塗佈一導電接 合劑。第二電極層鋪設於第二型摻雜半導體層之底面，且 具有一裸露面積以供直接塗佈導電接合劑。絕緣層則位於 第一電極層與第二電極層間，以電性隔離且支撐第一電極 層與第二電極層。 根據本揭示内容又一技術態樣，提出一種覆晶發光二 極體晶粒陣列，包括多個前述之覆晶發光二極體晶粒，以 參 及一金屬圖案層。金屬圖案層係用以對每一個覆晶發光二 極體晶粒裡面的第一電極層與第二電極層進行選擇性電性 連接’以串並聯這些覆晶發光二極體晶粒。 值得注意的是，根據本技術態樣其他實施方式，當導 電接合劑選用銀膠時，上述的裸露面積須至少625平方微 米’以供直接塗佈。當導電接合劑選用錫膏時，上述的裸 露面積須至少10000平方微米，以供直接塗佈。此外，在 覆晶發光二極體晶粒的細部結構上，更可鋪設一金屬反射 層於第二型摻雜半導體層與第二電極層間；鋪設一布拉; 5 201145563 反射結構於金屬反射層與第二型摻雜半導體層間；以及， 鋪設一透光覆蓋層於第一型摻雜半導體層之頂面。承上所 述’在覆晶發光二極體晶粒的細部結構上，更可設計一粗 化結構於透光覆蓋層之外表面與第一型掺雜半導體層之側 表面。此外，透光覆蓋層可為一圖案化藍寶石基板。 因此，上述諸實施方式之覆晶發光二極體晶粒及其陣 列，可在晶圓製造過程上，即實現可直接被使用之完整成 品；因而省略傳統覆晶發光二極體封裝製程的所有步驟； Φ 無論在設備上、成本上與耗時上，皆展現長足之進步。 【實施方式】 狄=年覆日日封裴技術被提出來時，是為了解決傳統邏輯 運f明片對於電性的過度敏感問題。舉例來說，傳統邏輯 2曰曰粒被封裝成晶片時，需經打線(Wire Bonding)，但打 的電感效應；[覆晶封聚技術提出以覆晶 ==線。然而，此-技術遂成既有之以，而 、、子。用於覆晶發光二極體晶片之置上。 :人f於多年實務經驗及長期觀察與努力，遂研：發 徵，終_本創作以-掃^運异日日片之各種特 請參考第2圖，第2圖是本揭示内容 罐構示意圖。$2圖中，本;= Γ〇1/二極艘晶粒300包括-第-型摻雜半導:ί 3(Π、-第二型摻雜半導體層3〇2、一第一電極二導體層 第二電極層304及一絕緣層3()5。第二型摻雜半^、- 201145563 鋪設於第一型摻雜半導體層301之底面，第一電極層303 鋪設於第一型摻雜半導體層301之底面且不接觸第二型摻 雜半導體層302,而且具有一裸露面積以供直接塗佈一導 電接合劑。第二電極層304鋪設於第二型摻雜半導體層302 之底面’且具有一裸露面積以供直接塗佈導電接合劑。絕 緣層305則位於第一電極層303與第二電極層304間，以 電性隔離且支樓第一電極層303與第二電極層304。 其中，為了在晶圓製程上實現長條狀直立的第一電極 層303，以利用其侧面面積增加整體裸露面積，而供直接 爹佈導電接合劑，本實施方式利用絕緣層305來支撐第-層30:，使其在製作過程中不會崩塌⑼化㈣，且在成 更為牛固’不至於因外力而彎曲接觸第二電極層304 这紐路。另一方面，當第一電極層303與第二電極層304 皆=有相當大之體積時，兩者可能產生電弧而短路；故， 絕緣層3〇5可隔離第一電極層303與第二電極層304以防 灿路。此外，雖然絕緣層305、第-電極層3〇3與第二 電極層304勢必產生電容效應；但其對於以發光為目的之 籲覆晶發光二極體晶粒3〇〇而言，卻不構成危害；反之 範圍裸露面積的第-電極層3G3與第二電極層綱有利於 散熱，以對抗發光二極體所真正在乎的光衰問題。 值得注意的是’ ^要直接塗佈銀膠以作為導電接合 劍第電極層3〇3與第二電極層3〇4之裸露面積為25微 米（micro meter)乘25微米以上；若要直接塗佈錫膏以作 導電接合劑’第-電極層303與第二電極層綱之裸露面 積為100微米乘100微米以上。此外，第一型推雜半導體 7 201145563 層301可為一 p型半導體層，且第二槊摻雜半導體層302 可為一 η型半導體層，或反之亦可。半導體層之材料可為 紹砷化鎵、砷化鎵填化物、磷化鎵、磷化銦鎵鋁 '磷化銦 鎵紹、銦氮化鎵、氮化鎵、鋁磷化鎵、硒化鋅、碳化矽等 材料。 請一併參考第3Α圖、第3Β圖及第3C圖，其皆是本 技術態樣三種實施方式之覆晶發光二極體晶粒的結構示意 圖。其係在晶圓製程階段，於晶粒上設置可直接被使用的 • 大電極結構，進而免除傳統晶粒被封裝成晶片的後段製 程。第3Α圖中，第二電極層304可先被大範圍地設置在 第二型摻雜半導體層302上；當第一電極層303所能應用 之側面積仍可能不足以直接沾黏導電接合劑時，絕緣層3〇5 可部分覆蓋在第二電極層304上，第一電極層303再朝第 二電極層304方向鋪設於絕緣層305上。第3Β圖中，第一 電極層303與第二電極層304皆可進行兩階段的製作；亦 即先以傳統製程分別實現兩金屬層於第一型掺雜半導體層 鲁 301與第二型摻雜半導體層3〇2上，再增加晶圓製程形成 絕緣層305以及兩個大電極於兩金屬層上，以分別完成第 一電極層303與第二電極層304。第3C圖中，若擔心第一 電極層303與第二電極層304過於接近，可能容易短路； 則可利用絕緣層305拉開第一電極層303與第二電極層3〇4 之距離。 值得注意的是，在第3Β圖中，覆晶發光二極體晶粒 3〇〇更包括一防護層306。防護層306係為一絕緣材料形成 的絕緣薄膜’用以形成薄膜保護功能，以增加覆晶發光；e 201145563 極體晶粒3〇〇的壽命。在製程上，防護層3〇6可利 (Spin Coating)或電子搶(E-gUn)等技術，形成於第一捻 半導體層301與第二型摻雜半導體層3〇2之正面或例=雜 承上所述，第3A圖、第3B圖及第3C圖中的覆晶發 光二極體晶粒，係在晶圓製作過程中，例如沉積、曝光、 顯影、蝕刻等步驟，即形成用以作為正負電極的第一電極 層303與第二電極層304。然後，再經切割便可成為能夠 獨立使用的覆晶發光二極體晶片。換句話說，傳統覆晶技 _ 術之擴晶、翻轉、轉置、微波、點膠乃至於烘烤等封裝製 程所需要的没備可以被節省下來。此外，傳統覆晶發光二 極體的擴晶、翻轉、植球、晶粒與基板之壓合、注膠以及 烘烤等製程步驟所耗費的時間也可被節省下來。 請再參考第4圖，第4圖是本揭示内容另一實施方式 之覆晶發光二極體晶粒陣列的結構示意圖。第4圖中，本 實方c*方式之覆bb發光一極體晶粒陣列400，係在前述晶圓 加工的最後階段，再以金屬層製作工藝，形成一跨晶粒4〇1 φ 間的金屬圖案層4〇2 ’以電性串並聯多顆晶粒4〇1。然後， 各晶粒401不再切割分離，而是依其金屬圖案層402所定 義之顆數作為一陣列（array)使用。藉此’多顆覆晶發光二 極體晶粒40卜在晶圓階段即已完成電性上的串並聯結構， 進而使其得以直接電性連接交流或直流電源。反觀傳統覆 晶發光二極體，須先將晶粒以覆晶轉接板封褒成晶片，再 於一額外的電路板上進行電性的串並聯。 接下來，請再參考第5圖。第5圖是第3A圖之覆晶 發光一極體晶粒的禅細結構不意圖。為了提升覆晶發光二s 201145563 極體晶粒310的發光效率’覆晶發光二極體晶粒301的細 部結構上，更可鋪設一透光覆蓋層311於第一型摻雜半導 體層301之頂面，以及鋪設一金屬反射層312於第二型摻 雜半導體層302與第二電極層間。金屬反射層312位於真 正發光的PN接面下方，可用以將向下發散的光線反射回 透光覆蓋層311，亦即整體覆晶發光二極體晶粒310的發 光側。更進一步的說，吾人亦可在覆晶發光二極體晶粒310 所附著之電路板上，設計反射面以反射PN接面向下發散 的光線。 請再參考第6圖。第6圖亦是第3A圖之覆晶發光二 極體晶粒的詳細結構示意圖。第6圖中，吾人亦可鋪設一 布拉格反射結構(Bragg reflector)313於金屬反射層與第二 型摻雜半導體層間。其中，布拉格反射結構313係由兩種 以上介電係數不同的材料，交錯排列而成。而且，各層的 厚度設計為光線波長的四分之一，以構成一種四分之一波 長多層糸統(quarter-wave-stack multi-layered system)，相當 於簡單的一維光子晶體。藉此，由於頻率落在能隙範圍内 的電磁波無法穿透’布拉格反射結構313的反射率可以高 達99%以上。它沒有一般金屬反射鏡的吸收問題，又可以 透過改變材料的折射率或厚度來調整能隙位置。 另一方面’透光覆蓋層之上表面，亦即覆晶發光二極 體晶粒310的背面發光侧，可設計有一粗化結構314。同 理，透光覆蓋層與第一型摻雜半導體層之周圍侧表面，皆 可設有此一粗化結構314。粗化結構314之設計原理介紹 如下： r 201145563 一般而言’LED半導體層的折射率約2.4,對於空氣的 全反射角約24.5度。LED晶片通常切割成矩形，約8%的 光線可射出晶片之外，92%的光線則封閉在晶片之内轉換 成熱。破壞全反射角可提升LED光線射出率，在晶片的 表面做表面粗化的工程，可以得到提升出光率的效果。值 得注意的是，LED表面粗化其表面粗度必須大於2倍波長 才有明顯的出光效率。非矩形的晶片外形或晶片内做細小 的非矩形切割也都可提升出光效率。 此外’透光覆蓋層之材質可為一藍寶石基板(八丨2〇3)、 填化鎵(GaP)、矽膠、玻璃或鉄弗龍等透光材料。值得注意 的疋’ S選用藍寶石基板作為透光覆蓋層時，可設計一圖 案315於其與第一型換雜半導體層交界之一侧，進而形成 一圖案化藍寶石基板。最後，從製程的角度來說，前述之 金屬反射層可與第二電極層於同一製程中同時完成。 綜上所述’本實施方式之覆晶發光二極體，可以免去 焊線機（約12萬美元）或覆晶植球機（約6〇萬美元）、固 曰日機或表面黏著貼片機（Surface Mounting Technology，SMT) 等設備，乃至於消耗性備料與覆晶轉接板的支出。在製造 成本及單位時間產能上皆顯著提升。 雖然本發明已以諸實施方式揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 11 201145563 為讓本揭示内容之上述和其他目的、特徵、優點與實 施例能更明顯易懂，所附圖式之說明如下： 第1圖是習知之覆晶發光二極體晶片封裝製程的步驟 流程圖。 第2圖是本揭示内容一實施方式之覆晶發光二極體晶 粒的結構示意圖。 第3A圖是本揭示内容另一實施方式之覆晶發光二極 體晶粒的結構不意圖。 φ 第3B圖是本揭示内容又一實施方式之覆晶發光二極 體晶粒的結構不意圖。 第3C圖是本揭示内容再一實施方式之覆晶發光二極 體晶粒的結構示意圖。 第4圖是本揭示内容一實施方式之覆晶發光二極體晶 粒陣列的結構示意圖。 第5圖是第3A圖之覆晶發光二極體晶粒的詳細結構 示意圖。 • 第6圖是第3A圖之覆晶發光二極體晶粒的詳細結構 示意圖。 主要元件符號說明 101-107 :步驟 111 :金屬突球 120 :覆晶轉接板 110 :習知之覆晶發光二極體 晶粒 121 :導電接點 r , 130:習知之覆晶發光二極體210:第一機器手臂 12 201145563 片 晶 01246240 200π^-0110 第二機器手臂 211、221 :真空吸嘴 300 、 310 ' 320 ' 330 、 401 第一型摻雜半導體層 覆晶發光二極體晶粒 第二型摻雜半導體層 303 :第一電極層 第二電極層 305 :絕緣層 防護層 311 :透光覆蓋層 金屬反射層 313 :布拉格反射結構 粗化結構 315 :圖案 覆晶發光二極體晶粒陣420 :金屬圖案層 13201145563 VI. Description of the Invention: [Technical Field of the Invention] The present disclosure relates to a light-emitting diode, and more particularly to a flip-chip light-emitting diode. [Prior Art] Please refer to Fig. 1, which is a flow chart showing the steps of a conventional flip chip LED package process. The conventional flip-chip photodiode process includes at least seven steps: First, as shown in step 101, a plurality of dies 110 on the wafer are removed by a crystal expansion technique. Next, as shown in step 102, the die is removed by a first robot arm 210 and its vacuum nozzle 211; as shown in step 103, the first robot arm 210 flips the die 110; as shown in step 104, the crystal The pellet 110 is turned over and then taken over by a second robotic arm 220 and its vacuum nozzle 221. Of course, another feasible approach is to use the blue film flip technology to achieve the above process. Then, as shown in step 105, the bumps 111 on the die 110 are accurately positioned on the conductive contacts 121 on the flip-chip φ (Board) 120. Thereafter, as shown in step 106, the metal ball 111 is heated by microwaves or the like to electrically connect the die 110 to the flip chip board 120. Finally, as shown in step 107, the gap between the die 110 and the flip chip 120 is encapsulated by a dispensing technique, thereby completing the package fabrication of the wafer 130. In addition, the wafer 130 usually needs to be baked again. The material that is filled when the dispensing is cured. At this point, the wafer 130 is a ready-to-use product; in use, the wafer 130 is electrically connected to a circuit on the circuit board by using a predetermined conductive structure on the flip-chip board 120. [201145563] SUMMARY OF THE INVENTION Therefore, the technical aspect of the present disclosure is to provide a flip chip light-emitting diode die to avoid a wafer packaging process. According to a technical aspect of the present disclosure, a flip-chip light emitting diode die is provided, including a first type doped semiconductor layer, a second type doped semiconductor layer, a first electrode layer, and a second electrode layer. And an insulating layer. The second type doped semiconductor layer is laid on the bottom surface of the first type doped semiconductor layer, and the first electrode layer is laid on the bottom surface of the first type doped semiconductor layer and does not contact the second type doped semiconductor layer, and has a The exposed area is used to directly coat a conductive bonding agent. The second electrode layer is laid on the bottom surface of the second type doped semiconductor layer and has a bare area for directly coating the conductive bonding agent. The insulating layer is located between the first electrode layer and the second electrode layer to electrically isolate and support the first electrode layer and the second electrode layer. According to still another aspect of the present disclosure, a flip-chip light emitting diode die array is provided, comprising a plurality of the foregoing flip chip light emitting diode grains to participate in a metal pattern layer. The metal pattern layer is used for selectively electrically connecting the first electrode layer and the second electrode layer in each of the flip-chip light-emitting diode dies to serially connect the flip-chip light-emitting diode dies. It is to be noted that, in accordance with other embodiments of the present technology, when the conductive bonding agent is selected from silver paste, the exposed area described above must be at least 625 square micrometers for direct coating. When a solder paste is selected for the conductive bonding agent, the exposed area described above must be at least 10,000 square microns for direct coating. In addition, in the detailed structure of the flip-chip light-emitting diode die, a metal reflective layer may be disposed between the second-type doped semiconductor layer and the second electrode layer; laying a bra; 5 201145563 reflective structure on the metal reflective layer And a second type of doped semiconductor layer; and a light transmissive cover layer is disposed on the top surface of the first type doped semiconductor layer. In the detailed structure of the flip-chip light-emitting diode, it is also possible to design a roughened structure on the outer surface of the light-transmitting cover layer and the side surface of the first-type doped semiconductor layer. In addition, the light transmissive cover layer can be a patterned sapphire substrate. Therefore, the flip-chip light-emitting diode crystal grains of the above embodiments and the array thereof can realize the complete finished product which can be directly used in the wafer manufacturing process; thus omitting all the conventional flip-chip light-emitting diode packaging process Steps; Φ Shows great progress in terms of equipment, cost and time. [Embodiment] When the Di=Year-day coverage technology was proposed, it was to solve the problem of excessive sensitivity of the traditional logic. For example, when traditional logic 2 is packaged into a wafer, it needs to be wire bonded (Wire Bonding), but the inductive effect is applied; [Crystal sealing technology is proposed to cover the crystal == line. However, this - technology has become both, and, and. It is used for the placement of flip-chip light-emitting diode chips. :Man f in years of practical experience and long-term observation and hard work, Yan Yan: levy, the end _ this creation to - sweep the various days of the special day please refer to Figure 2, Figure 2 is the content of this disclosure schematic diagram. In the $2 figure, the ;1/dipole die 300 includes a -type-type doped semiconductor: ί 3 (Π, - the second type doped semiconductor layer 3 〇 2, a first electrode two conductor a second electrode layer 304 and an insulating layer 3 () 5. The second type doping half, - 201145563 is laid on the bottom surface of the first type doped semiconductor layer 301, and the first electrode layer 303 is laid on the first type doping The bottom surface of the semiconductor layer 301 does not contact the second type doped semiconductor layer 302, and has a bare area for directly coating a conductive bonding agent. The second electrode layer 304 is laid on the bottom surface of the second type doped semiconductor layer 302. And having a bare area for directly coating the conductive bonding agent. The insulating layer 305 is located between the first electrode layer 303 and the second electrode layer 304 to electrically isolate and the first electrode layer 303 and the second electrode layer 304 of the branch In order to realize the strip-shaped upright first electrode layer 303 on the wafer process, the total exposed area is increased by the side area thereof, and the conductive bonding agent is directly bonded, and the present embodiment uses the insulating layer 305 to support the first layer. - Layer 30: so that it will not collapse during the production process (9) (4), and become more cattle Solid' does not bend and contact the second electrode layer 304 due to external force. On the other hand, when both the first electrode layer 303 and the second electrode layer 304 have a relatively large volume, both may cause an arc and short circuit. Therefore, the insulating layer 3〇5 can isolate the first electrode layer 303 and the second electrode layer 304 from being blocked. Further, although the insulating layer 305, the first electrode layer 3〇3 and the second electrode layer 304 are bound to have a capacitive effect However, it does not pose a hazard to the luminescent light-emitting diode die 3 以 for the purpose of illuminating; otherwise, the first electrode layer 3G3 and the second electrode layer of the bare area are favorable for heat dissipation, Against the problem of light decay that the light-emitting diode really cares about. It is worth noting that ^ ^ directly coated with silver glue as the conductive joint sword electrode layer 3〇3 and the second electrode layer 3〇4 bare area of 25 microns (micro meter) multiplied by 25 microns or more; if the solder paste is directly applied as a conductive bonding agent, the exposed area of the first electrode layer 303 and the second electrode layer is 100 micrometers by 100 micrometers or more. Miscellaneous semiconductor 7 201145563 layer 301 can be a p-type semi-conductor a layer, and the second germanium-doped semiconductor layer 302 can be an n-type semiconductor layer, or vice versa. The material of the semiconductor layer can be gallium arsenide, gallium arsenide filler, gallium phosphide, indium gallium phosphide 'Indium gallium phosphide, indium gallium nitride, gallium nitride, aluminum gallium phosphide, zinc selenide, tantalum carbide, etc. Please refer to Figure 3, Figure 3 and Figure 3C together. The schematic diagram of the structure of the flip-chip light-emitting diode die of the three embodiments of the technical aspect is arranged in the wafer process stage, and the large electrode structure can be directly used on the die, thereby eliminating the conventional die being encapsulated into The back end of the wafer process. In the third embodiment, the second electrode layer 304 may be disposed on the second type doped semiconductor layer 302 in a wide range; when the first electrode layer 303 can be applied, the side area may not be sufficient to directly adhere the conductive bonding agent. The insulating layer 3〇5 may partially cover the second electrode layer 304, and the first electrode layer 303 is further laid on the insulating layer 305 toward the second electrode layer 304. In the third embodiment, the first electrode layer 303 and the second electrode layer 304 can be fabricated in two stages; that is, the two metal layers are respectively formed in the first type doped semiconductor layer 301 and the second type by conventional processes. On the impurity semiconductor layer 3〇2, a wafer process is further formed to form an insulating layer 305 and two large electrodes are formed on the two metal layers to complete the first electrode layer 303 and the second electrode layer 304, respectively. In Fig. 3C, if the first electrode layer 303 and the second electrode layer 304 are too close to each other, the short circuit may be easily caused. The insulating layer 305 may be used to pull apart the distance between the first electrode layer 303 and the second electrode layer 3?4. It should be noted that in the third figure, the flip-chip light-emitting diode die 3 〇〇 further includes a protective layer 306. The protective layer 306 is an insulating film formed of an insulating material for forming a thin film protection function to increase flip-chip light emission; e 201145563 The life of the polar body crystal 3 。. In the process, the protective layer 3〇6 spin coating or electron grab (E-gUn) and the like, formed on the front side of the first germanium semiconductor layer 301 and the second type doped semiconductor layer 3〇2 or example = As described in the hybrid, the flip-chip light-emitting diode grains in the 3A, 3B, and 3C are in the process of wafer fabrication, such as deposition, exposure, development, etching, etc. The first electrode layer 303 and the second electrode layer 304 are used as positive and negative electrodes. Then, it can be cut into a flip-chip light-emitting diode wafer that can be used independently. In other words, the need for conventional flip-chip technology, such as crystal expansion, flipping, transposition, microwave, dispensing, and even baking, can be saved. In addition, the time taken for the process of crystallizing, flipping, ball-planting, lamination of the die and substrate, injection molding, and baking of conventional flip-chip LEDs can also be saved. Referring to FIG. 4 again, FIG. 4 is a schematic structural view of a flip-chip LED array of another embodiment of the present disclosure. In Fig. 4, the bb-emitting one-pole array 400 of the actual c* mode is formed in the final stage of the wafer processing, and then a metal layer is formed to form a cross-die 4〇1 φ. The metal pattern layer 4〇2' electrically connects a plurality of crystal grains 4〇1 in parallel. Then, each of the crystal grains 401 is no longer cut and separated, but is used as an array according to the number defined by the metal pattern layer 402. Thereby, the plurality of flip-chip light-emitting diode dies 40 have completed the electrical series-parallel structure at the wafer stage, thereby enabling direct connection of the AC or DC power source. In contrast, conventional flip-chip LEDs must first be packaged into wafers with flip-chip adapters and then electrically connected in series with an additional circuit board. Next, please refer to Figure 5 again. Fig. 5 is a schematic view showing the zen structure of the flip-chip light-emitting one-crystal grain of Fig. 3A. In order to enhance the light-emitting efficiency of the flip-chip light-emitting diode s 201145563 polar body die 310, a light-transmissive cover layer 311 may be deposited on the first-type doped semiconductor layer 301 in a detailed structure of the flip-chip light-emitting diode die 301. The top surface and a metal reflective layer 312 are disposed between the second type doped semiconductor layer 302 and the second electrode layer. The metal reflective layer 312 is located below the PN junction of the true illumination and can be used to reflect the downwardly diverging light back to the light transmissive cover layer 311, i.e., the light emitting side of the monolithic epitaxial LED die 310. Furthermore, we can also design a reflective surface on the circuit board to which the flip-chip diode 310 is attached to reflect the PN light to diverge downward. Please refer to Figure 6 again. Fig. 6 is also a detailed structural diagram of the flip chip of the flip-chip light emitting diode of Fig. 3A. In Fig. 6, we can also lay a Bragg reflector 313 between the metal reflective layer and the second doped semiconductor layer. The Bragg reflection structure 313 is formed by staggering two or more materials having different dielectric constants. Moreover, the thickness of each layer is designed to be one quarter of the wavelength of the light to form a quarter-wave-stack multi-layered system, which is comparable to a simple one-dimensional photonic crystal. Thereby, the reflectance of the electromagnetic wave which is within the energy gap cannot penetrate the 'Bragd reflection structure 313' can be as high as 99% or more. It does not have the absorption problem of a typical metal mirror, and it can adjust the position of the energy gap by changing the refractive index or thickness of the material. On the other hand, the upper surface of the light-transmitting cover layer, i.e., the back side light-emitting side of the flip-chip light-emitting diode die 310, may be formed with a roughened structure 314. Similarly, the light-transmissive cover layer and the peripheral side surface of the first type doped semiconductor layer may be provided with the roughened structure 314. The design principle of the roughened structure 314 is as follows: r 201145563 In general, the refractive index of the LED semiconductor layer is about 2.4, and the total reflection angle for air is about 24.5 degrees. The LED wafer is usually cut into a rectangular shape, about 8% of the light can be emitted outside the wafer, and 92% of the light is enclosed within the wafer and converted into heat. Destruction of the total reflection angle enhances the LED light emission rate, and the surface roughening of the surface of the wafer can improve the light extraction rate. It is worth noting that the surface roughness of the LED must be greater than 2 times the wavelength of the surface to have significant light extraction efficiency. Non-rectangular wafer shapes or small non-rectangular cuts in the wafer also enhance light extraction efficiency. In addition, the material of the light transmissive cover layer may be a sapphire substrate (eight 丨 2 〇 3), filled gallium (GaP), silicone rubber, glass or krypton. It is noted that when the sapphire substrate is used as the light-transmitting cover layer, a pattern 315 can be designed on one side of the interface with the first-type semiconductor layer to form a patterned sapphire substrate. Finally, from the viewpoint of the process, the aforementioned metal reflective layer can be simultaneously completed in the same process as the second electrode layer. In summary, the flip-chip light-emitting diode of the present embodiment can be dispensed with a wire bonding machine (about 120,000 US dollars) or a flip chip ball machine (about 60 million US dollars), a solid-state machine or a surface adhesive sticker. Equipment such as Surface Mounting Technology (SMT), and even consumables and flip-chip adapters. Significant improvements in manufacturing costs and unit time productivity. The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention, and it is obvious to those skilled in the art that various modifications and refinements can be made without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood. Flow chart of the steps of the bulk wafer packaging process. Fig. 2 is a schematic view showing the structure of a flip-chip light-emitting diode according to an embodiment of the present disclosure. Fig. 3A is a schematic view showing the structure of a flip-chip light-emitting diode crystal according to another embodiment of the present disclosure. φ Fig. 3B is a schematic view showing the structure of a flip chip light-emitting diode crystal according to still another embodiment of the present disclosure. Fig. 3C is a schematic view showing the structure of a flip chip light-emitting diode according to still another embodiment of the present disclosure. Fig. 4 is a schematic view showing the structure of a flip-chip light-emitting diode array according to an embodiment of the present disclosure. Fig. 5 is a view showing the detailed structure of the flip chip of the flip-chip light emitting diode of Fig. 3A. • Figure 6 is a detailed schematic diagram of the flip-chip light-emitting diode die of Figure 3A. Main component symbol description 101-107: Step 111: Metal ball 120: flip chip adapter plate 110: conventional flip chip light-emitting diode die 121: conductive contact r, 130: conventional flip chip light-emitting diode 210: first robot arm 12 201145563 plate crystal 01246240 200π^-0110 second robotic arm 211, 221: vacuum nozzle 300, 310 '320 '330, 401 first type doped semiconductor layer flip-chip light emitting diode crystal grain Second type doped semiconductor layer 303: first electrode layer second electrode layer 305: insulating layer protective layer 311: light transmissive cover layer metal reflective layer 313: Bragg reflection structure roughening structure 315: pattern flip chip light emitting diode crystal Grain array 420: metal pattern layer 13