201135709 六、發明說明： 【發明所屬之技術領域】 本發明相關於' 種液晶顯不面板及相關驅動方法，尤指 一種提供高晝面均勻性之液晶顯示面板及相關驅動方法。 【先前技術】 液晶顯示器（liquid crystal display，LCD)具有低輻射、體 積小及低耗能等優點，已逐漸取代傳統的陰極射線管顯示器 (cathode ray tube display, CRT) ’因而被廣泛地應用在筆記型 電腦、個人數位助理（personal digital assistant，PDA)、平面 電視，或行動電話等資訊產品上。傳統液晶顯示器之驅動方 式是利用源極驅動電路（source driver )、閘極驅動電路（gate # driver)和時序控制器（timing controller)等來驅動面板上 的晝素單元以顯示影像，或是使用結合前述單一功能驅動電 路之整合型驅動電路。 請參考第1圖，第1圖為先前技術中液晶顯示面板上一 畫素單元PX之示意圖。晝素單元ρχ包含一薄膜電晶體（thin film transistor，TFT )開關TFT、一液晶電容Clc和一儲存電 容CST ’耦接於一資料線DL、一閘極線GL，以及一共同電 201135709 壓VC0M。閘極線GL用來傳送一閘極驅動訊號SG，資料線 DL用來傳送一源極驅動訊號SD，而薄膜電晶體開關TFT 則依據閘極驅動訊號SG來控制源極驅動訊號SD對液晶電 容Clc和儲存電容Cst之充電路徑。 請參考第2圖，第2圖為先前技術中晝素單元PX驅動 方法之示意圖。第2圖顯示了閘極驅動訊號SG、源極驅動 訊號SD和晝素電極電位VP之波形。為了避免液晶材質發 生永久性的極化，一般會以相反極性之源極驅動訊號SD來 驅動液晶顯示面板，例如在晝素單元PX之驅動週期T1内 之水平選擇期間T0N1 (亦即對畫素單元PX充電的期間）， 源極驅動訊號SD具正極性電位VDH ;在晝素單元PX之驅 動週期T2内之水平選擇期間T0N2，源極驅動訊號SD具負 極性電位VDL，其中VDH和VDL之值相關於畫素單元PX 在相對應驅動週期内欲顯示影像之灰階值。另一方面，閘極 驅動訊號SG之致能電位（高電位）和除能電位（低電位） 分別由VGH和VGL來表示。 在正極性驅動週期T1内之水平選擇期間T0N1内，閘極 驅動訊號SG具致能電位VGH，此時薄膜電晶體開關TFT 會被導通，源極驅動訊號SD會對液晶電容CLC和儲存電容 CST充電，以讓晝素電極電位VP達到源極驅動訊號SD之準 位VDH。在負極性驅動週期T2内之水平選擇期間T0N2内， 201135709 閘極驅動訊號SG具致能電位VGH，此時薄膘電晶 TFT會被導通，源極驅動訊號81)會對液晶電容阳體開關 電容Cst充電’以讓晝素電極電位VP 諸存 之準位VDL。在驅動週期T1内之非水平選擇期間琥SD 及驅動週期Τ2内之非水平選擇期間T〇FF2，閘極以 SG具除能電位VGL·，此時薄膜電晶體開關τ ^ 旒 r1會破關閉。 在理想情況下，畫素電極電位VP在薄臈電晶體開關tf 、 關閉後應該維持在預定準位VDH或VDL。秋^ FT被 …、而’由於當埔 膜電晶體TFT關閉時，晝素電極並未連接至任何電壓、、' 是處在浮動（floating)狀態，此時畫素電極周圍 ’、而 <►1壬何電壓變 動會透過其寄生電容耦合至晝素電極，並且改蠻复 又电壓。換 而言之，在閘極驅動訊號SG從致能電位切換至除能電位的 瞬間，薄膜電晶體開關TFT之寄生電容會在其閘極造成―於 通電壓（feed-through voltage) VFD，此種因寄生電容而造成的 電壓變動量會讓晝素電極電位vp偏離正極性驅動週期T1 之預定值VDH而降至約（VDH-Vfd)，或是偏離負極性驅動 週期T2之預定值VDL而降至約（VDL-Vfd)。若以（:仙來 表示薄膜電晶體開關TFT之閘極與汲極之間的寄生電容，饋 通電壓VFD和晝素單元整體寄生電容CP之值有如下關係： VFD= (VGH-VGL) *Cgd/(CLc+Cst+Cgd) =(VGH-VGL) *CP (1) 饋通電壓VFD會造成晝面閃爍（image flicker)的情形， 201135709 由於薄膜電晶體開關TFT内無法避免地存在著寄生電容，一 般會透過調整共同端之共同電壓VC0M來補償，進而改善畫 面閃爍以提升顯示品質。 請參考第3圖，第3圖為先前技術中一種液晶顯示面板 100以其驅動方式之示意圖。液晶顯示面板100之顯示區300 包含主動區域A1〜A5，每一主動區域包含複數個晝素單 元，每一畫素單元之結構如第1圖所示。液晶顯示裝置100 之非顯示區内設有一整合型驅動電路110，其包含一電荷泵 120、一源極驅動電路130、一閘極驅動電路140和一時序控 制器150。電荷泵120可將輸入電壓以倍頻方式升壓，時序 控制器150可提供整合型驅動電路110運作時所需之時脈訊 號，而整合型驅動電路110再依此提供開啟薄膜電晶體開關 TFT所需之閘極驅動訊號SG和對應於顯示影像之源極驅動 訊號SD。舉例來說，電荷泵120會提供一參考電位VGH， 整合型驅動電路120再依此提供為具致能電位VGH之閘極 驅動訊號SG。 針對液晶顯示面板100上不同區域内之薄膜電晶體開關 TFT，其寄生電容可能會因為製程或其它因素而不盡相同， 因此在關閉瞬間會造成不同程度的馈通效應。先前技術之整 合型驅動電路110係依據主動區域A1〜A5内某一特定區域 之顯示品質來決定閘極驅動訊號SG之致能電位VGH，再以 201135709 具固定致能電位VGH之閘極驅動訊號SG來驅動液晶顯示 面板100上所有晝素。舉例來說’若針對液晶顯示面板1〇〇 中央部份之畫素單元特性來決定閘極驅動訊號SG之致能電 位VGH，如此雖可改善主動區域A3之晝面閃爍，但相鄰主 動區域A3之主動區域A2和A4可能仍有輕微晝面閃蝶，而 最兩側之主動區域A1和A5可能仍有嚴重的晝面閃爍。因 此’針對液晶顯示面板上不同位置之晝素單元，先前技術並 籲無法以相同幅度來補償饋通電壓所造成的影響，面板上部分 區域仍會發生不同程度的晝面閃爍，因此會影響整體顯示晝 面的均勻度。 【發明内容】 本發明提供一種提供高晝面均勻性之液晶顯示面板，其 包含一顯示區，其包含複數個主動區域’每一主動區域包含 鲁複數個晝素單元；以及一整合型驅動電路，其包含一升壓電 路’用來提高一輸入電壓以提供該整合型驅動電路運作所需 之一操作電壓；以及一電壓分壓/選擇電路，其依據該操作電 壓和每一主動區域内晝素單元之特性來分別提供具不同致 能電位之驅動訊號至相對應之主動區域。 本發明另提供一種液晶顯示面板之驅動方法，其包含提 供具不同致能電位之複數組閘極驅動訊號；以及依據該液晶 201135709 顯示面板上-特定區域内顯示晝面之均勾度，輸出該複數組 閘極驅動訊號中一相對應之閘極驅動訊號至該特定區域。 【實施方式】 請參考第4圖，第4圖為本發明中—液晶顯示面板彻 以及其驅動方式之示意圖。液晶顯示面板之顯示區· 包含主動(1域A1〜An ’每-主動區域包含複數個畫素單 元’每-畫素單元之結構如第i圖所示。液晶顯示裝置彻 之非主動(1域内設有—整合型驅動電路，其包含一源極 驅動電路130、一閘極驅動電路140和一時序控制器15〇、 一:壓電路，和一電壓分墨/選擇電路_。升壓電路谓 可提高輸入電壓，時序控制器15〇可提供整合型驅動電路 =0運作時所需之時脈訊號，而整合型驅動電路侧可依據 母一主動區域内晝素單元之特性來提供開啟薄膜電晶體開 胃F T所需之間極驅動訊號s G，和對應於顯示影像之源極驅 動訊號SD。 厂請參考第5圖至第7圖，第5圖為本發明一實施例中升 路500之示意圖，第6圖為本發明一實施例中電壓分壓 ’、擇電路600之示意圖，而第7圖為本發明一實施例中電塵 選擇電路_運料之示㈣。在第5圖所示之實施例 升堅電路500包含複數個電荷栗501〜504和-整流器 201135709 510，電荷泵501〜503可利用其内部電容Cl〜C4將一交流 輸入電壓AVDD以倍頻方式升壓，進而提供整合型驅動電路 420運作所需之操作電壓VINT1、VINT2、VGHMAX* VGL 等。整流器510則可將交流輸入電壓AVdd轉換為整合型驅 動電路420運作所需之一直流電壓DVDD。 在第6圖所示之實施例中，電壓分壓/選擇電路6〇〇包含 • 一分壓電路610和一選擇電路62〇。分壓電路610可由一包 含複數個串聯電阻R1〜Rn之電阻串來實施，而選擇電路62〇 可為一 n對1多工器。分壓電路610可透過電阻Ri〜5^來 为壓VGHMAX電壓’並於兩相鄰電阻之間輸出η組電位vghi 〜VGHn。選擇電路620再依據一選擇訊號SEL來輸出電位 VGH0〜VGHn中其中一組相對應之電壓值以作為閘極驅動 訊號SG’之致能電位。假設當選擇訊號SEL之值為ooh〜0nH 時，電壓分壓/選擇電路600輸出之閘極驅動訊號sg，分別具201135709 VI. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display panel and related driving method, and more particularly to a liquid crystal display panel and a related driving method for providing high kneading uniformity. [Prior Art] Liquid crystal display (LCD) has the advantages of low radiation, small size and low energy consumption, and has gradually replaced the traditional cathode ray tube display (CRT). Notebook computer, personal digital assistant (PDA), flat-screen TV, or mobile phone and other information products. The driving method of the conventional liquid crystal display is to drive the pixel unit on the panel to display an image by using a source driver, a gate driver, and a timing controller. An integrated drive circuit incorporating the aforementioned single function drive circuit. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a pixel unit PX on the liquid crystal display panel of the prior art. The pixel unit ρχ includes a thin film transistor (TFT) switching TFT, a liquid crystal capacitor Clc and a storage capacitor CST′ coupled to a data line DL, a gate line GL, and a common power 201135709 pressure VC0M . The gate line GL is used to transmit a gate driving signal SG, the data line DL is used to transmit a source driving signal SD, and the thin film transistor switching TFT controls the source driving signal SD to the liquid crystal capacitor according to the gate driving signal SG. The charging path of Clc and storage capacitor Cst. Please refer to FIG. 2, which is a schematic diagram of the PX driving method of the halogen unit in the prior art. Fig. 2 shows the waveforms of the gate drive signal SG, the source drive signal SD, and the pixel electrode potential VP. In order to avoid permanent polarization of the liquid crystal material, the liquid crystal display panel is generally driven by the source driving signal SD of opposite polarity, for example, during the horizontal selection period T0N1 in the driving period T1 of the pixel unit PX (ie, the pixel is During the charging of the unit PX), the source driving signal SD has a positive polarity potential VDH; during the horizontal selection period T0N2 in the driving period T2 of the pixel unit PX, the source driving signal SD has a negative polarity potential VDL, wherein VDH and VDL The value is related to the gray level value of the image to be displayed in the pixel unit PX during the corresponding driving period. On the other hand, the enable potential (high potential) and the discharge potential (low potential) of the gate drive signal SG are represented by VGH and VGL, respectively. During the horizontal selection period T0N1 in the positive polarity driving period T1, the gate driving signal SG has an enabling potential VGH, at which time the thin film transistor switching TFT is turned on, and the source driving signal SD will be the liquid crystal capacitor CLC and the storage capacitor CST. Charging so that the pixel electrode potential VP reaches the level VDH of the source driving signal SD. During the horizontal selection period T0N2 in the negative polarity driving period T2, the 201135709 gate driving signal SG has an enabling potential VGH, at which time the thin germanium TFT will be turned on, and the source driving signal 81) will be a liquid crystal capacitor male switch. The capacitor Cst is charged 'to allow the pixel electrode potential VP to remain at the level VDL. During the non-horizontal selection period in the driving period T1, the non-horizontal selection period T〇FF2 in the driving period Τ2 and the driving period Τ2, the gate is de-energized by the SG with the potential VGL·, and the thin film transistor switch τ ^ 旒r1 is broken. . Ideally, the pixel potential VP should be maintained at a predetermined level VDH or VDL after the thin transistor switch tf, turned off. Autumn ^ FT is ..., and 'because when the Pu film transistor TFT is turned off, the halogen electrode is not connected to any voltage, ' is in a floating state, at this time around the pixel electrode ', and < ►1When any voltage change is coupled to the halogen electrode through its parasitic capacitance, it is quite complex and voltage. In other words, when the gate driving signal SG is switched from the enabling potential to the de-energizing potential, the parasitic capacitance of the thin film transistor switching TFT causes a “feed-through voltage” VFD at its gate. The amount of voltage fluctuation caused by the parasitic capacitance causes the pixel electrode potential vp to deviate from the predetermined value VDH of the positive polarity driving period T1 to about (VDH-Vfd) or deviate from the predetermined value VDL of the negative polarity driving period T2. Drop to about (VDL-Vfd). If (: sen represents the parasitic capacitance between the gate and the drain of the thin film transistor switching TFT, the value of the feedthrough voltage VFD and the overall parasitic capacitance CP of the pixel unit has the following relationship: VFD = (VGH-VGL) * Cgd/(CLc+Cst+Cgd) =(VGH-VGL) *CP (1) Feedthrough voltage VFD causes image flicker, 201135709 Unavoidable parasitic due to thin film transistor switching TFT The capacitor is generally compensated by adjusting the common voltage VC0M of the common terminal, thereby improving the flicker of the screen to improve the display quality. Please refer to FIG. 3, which is a schematic diagram of a driving mode of the liquid crystal display panel 100 in the prior art. The display area 300 of the display panel 100 includes active areas A1 to A5, each active area includes a plurality of pixel units, and the structure of each pixel unit is as shown in Fig. 1. A non-display area of the liquid crystal display device 100 is provided with a The integrated driving circuit 110 includes a charge pump 120, a source driving circuit 130, a gate driving circuit 140 and a timing controller 150. The charge pump 120 can boost the input voltage in a frequency multiplying manner, and the timing controller 150 The integrated driving circuit 110 provides the gate driving signal SG required to turn on the thin film transistor switching TFT and the source driving signal SD corresponding to the display image. For example, the charge pump 120 provides a reference potential VGH, and the integrated driving circuit 120 is further provided as a gate driving signal SG having an enabling potential VGH. For a thin film transistor in different regions of the liquid crystal display panel 100. Switching TFTs, whose parasitic capacitance may vary depending on the process or other factors, may cause different feedthrough effects at the moment of turn-off. The prior art integrated driver circuit 110 is based on a specific one in the active areas A1 to A5. The display quality of the area determines the enable potential VGH of the gate drive signal SG, and then drives all the pixels on the liquid crystal display panel 100 with the gate drive signal SG of the fixed enable potential VGH of 201135709. For example, if it is for liquid crystal The pixel unit characteristic of the central portion of the display panel 1 determines the enabling potential VGH of the gate driving signal SG, so that the active region can be improved. The face of the field A3 flickers, but the active areas A2 and A4 of the adjacent active area A3 may still have a slight facet, while the active areas A1 and A5 on the most sides may still have severe face flashing. The pixel unit in different positions on the liquid crystal display panel, the prior art does not compensate for the influence of the feedthrough voltage with the same amplitude, and some areas of the panel still have different degrees of facet flicker, thus affecting the overall display surface. The present invention provides a liquid crystal display panel that provides high kneading uniformity, and includes a display area including a plurality of active regions each of which includes a plurality of pixel units; An integrated driving circuit comprising a boosting circuit 'used to increase an input voltage to provide an operating voltage required for operation of the integrated driving circuit; and a voltage dividing/selecting circuit based on the operating voltage and each The characteristics of the pixel unit in the active region are respectively provided to drive signals with different enable potentials to corresponding active regions. The present invention further provides a driving method for a liquid crystal display panel, which comprises providing a complex array gate driving signal with different energizing potentials; and outputting the uniformity of the display surface in a specific area on the display panel of the liquid crystal 201135709 A corresponding gate drive signal in the complex array gate drive signal to the specific area. [Embodiment] Please refer to FIG. 4, which is a schematic view showing the liquid crystal display panel and its driving method in the present invention. The display area of the liquid crystal display panel includes active (1 domain A1~An 'per-active area contains a plurality of pixel units'. The structure of each pixel unit is as shown in Fig. i. The liquid crystal display device is completely inactive (1 An integrated driving circuit is provided in the domain, and includes a source driving circuit 130, a gate driving circuit 140, a timing controller 15A, a voltage circuit, and a voltage ink dividing/selecting circuit. The circuit is said to increase the input voltage, the timing controller 15〇 can provide the integrated driving circuit=0 clock signal required for operation, and the integrated driving circuit side can be opened according to the characteristics of the pixel unit in the active area of the parent The thin-film transistor appendix FT requires a polar drive signal s G, and a source drive signal SD corresponding to the display image. Please refer to FIG. 5 to FIG. 7 , and FIG. 5 is a riser according to an embodiment of the present invention. FIG. 6 is a schematic diagram of a voltage dividing voltage 'and a selection circuit 600 according to an embodiment of the present invention, and FIG. 7 is a diagram showing the electric dust selection circuit _ transportation material according to an embodiment of the present invention. The embodiment of the sturdy circuit 500 includes a complex The charge pumps 501 to 504 and the rectifiers 201135709 510, the charge pumps 501 to 503 can boost the AC input voltage AVDD by a multiplying method by using the internal capacitors C1 to C4, thereby providing the operation required for the operation of the integrated driving circuit 420. The voltages VINT1, VINT2, VGHMAX* VGL, etc. The rectifier 510 converts the AC input voltage AVdd into one DC voltage DVDD required for the operation of the integrated driving circuit 420. In the embodiment shown in Fig. 6, the voltage dividing voltage / The selection circuit 6A includes a voltage dividing circuit 610 and a selection circuit 62. The voltage dividing circuit 610 can be implemented by a resistor string including a plurality of series resistors R1 RRn, and the selecting circuit 62 can be a n The voltage dividing circuit 610 can pass the resistors R5 to 5^ to the voltage VGHMAX voltage and output the n sets of potentials vghi to VGHn between the two adjacent resistors. The selecting circuit 620 is further based on a selection signal SEL. The voltage value corresponding to one of the output potentials VGH0 VVGHn is used as the enable potential of the gate drive signal SG'. It is assumed that when the value of the selection signal SEL is ooh~0nH, the voltage division/selection circuit 600 outputs the gate Pole drive signal Sg, respectively
籲致能電位VGH0〜VGHn，其中VGH0〜VGHn和VGHMAX 之關係如下所示： VGH0=VGHMAx ； VGH1=VGHMAx-AV1 ； VGH2=VGHMax-A V2 ； VGHn=VGHMAx-A Vn ； 其中△ VI〜△ Vn之值由電阻Rl〜Rn來決定。 9 201135709 第7圖之實施例顯示了閘極驅動訊號SG’、源極驅動訊 號SD、畫素電極電位VP以及選擇訊號SEL之波形。如第7 圖所示，閘極驅動訊號SG’之致能電位由選擇訊號SEL之值 來決定。假設在奇數驅動週期（ΤΙ、T3、…等）内係以具正 極性電位VDH之源極驅動訊號SD來充電晝素單元，而在 偶數驅動週期（T2、T4、…等）内係以具負極性電位VDL 之源極驅動訊號SD來充電晝素單元，其中VDH和VDL之 值相關於晝素單元在相對應驅動週期内欲顯示影像之灰階 值。在正極性驅動週期内之水平選擇期間（T0N1、T0N3、... 等）内，閘極驅動訊號SG’具致能電位（VGH1、VGH3、... 等），此時薄膜電晶體開關TFT會被導通，源極驅動訊號SD 會對液晶電容Clc和儲存電容Cst充電’以讓畫素電極電位 VP達到源極驅動訊號SD之準位VDH。在負極性驅動週期 内之水平選擇期間（T〇N2、T〇N4、_. ·等）*閘極驅動訊號SG 具致能電位（VGH2、VGH4、…），此時薄膜電晶體開關TFT 會被導通，源極驅動訊號SD會對液晶電容CLC和儲存電容 CST充電，以讓畫素電極電位VP達到源極驅動訊號SD之準 位VDL。在驅動週期T1〜Τη内之非水平選擇期間T0FF1〜 T〇FFn ’ 當閘極驅動訊號SG切換至除能電位VGL時，薄膜 電晶體開關TFT之寄生電容會在其閘極分別造成饋通電壓 VfDI 〜T FD1。 如第7圖和公式（1 )所示，在每一驅動週期 内T1〜Τη所造成之饋通電壓VFD1〜VFDn分別相關於閘極驅 10 201135709 動訊號SG之致能電位VGH1〜VGHn，而致能電位VGH1〜 VGHn之值由選擇訊號SEL之值（例如OOH〜OnH)來決定。 換而言之，發明之整合型驅動電路420可依據選擇訊號SEL 分別提供η組具不同致能電位VGH1〜VGHn之閘極驅動訊 號 SG1 〜SGn。 因此，本發明可依據面板特性來改變選擇訊號SEL之 值，如此整合型驅動電路420會輸出相對應之閘極驅動訊號 至液晶顯示面板400特定區域内之晝素單元。舉例來說，針 對第4圖所示之液晶顯示面板400，本發明可依據每一主動 區域A1〜An内晝面閃爍的程度，分別以具不同致能電位 VGH1〜VGHn之閘極驅動訊號來驅動相對應主動區域内之 畫素單元。假設主動區域A1〜An内之晝素單元其整體寄生 電谷由CP丨〜CPn來表示’且Cpi<CP2<...<cPn，此時 VGHl>VGH2>.">VGHn’如第7圖所示。然而，致能電位 VGH1〜VGHn之大小關係依據面板特性來決定，第4圖和 第7圖僅為本發明之實施例，並不限定本發明之範疇。 如刖所述，由於製程或其它因素，液晶顯示面板上 不同區域内之薄膜電晶體開關TFT其寄生電容可能相異， 此會造成不同程度的饋通電壓，面板各個區域晝面閃燦的 度也會相異。本發明係依據每一主動區域内晝素單元之特程 來決定其相對應閘極驅動訊號之致能電位。因此，針對、夜^ 201135709 顯示面板上不同位置之晝素單元，本發明能以相對應幅度來 補仏饋通電>1所造成的影響，進而以實值上相同幅度來改善 晝面閃爍’進而提升整體顯示畫面的均勾度。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均㈣化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為先前技術中液晶顯示面板上—晝素單元之示意圖。 第2圖為先前技術中晝素單元驅動方法之示意圖。 第3圖為先前技術中一液晶顯示面板以及其驅動 圖。 、、不思 第4圖為本發明中一液晶顯示面板以及其驅動方式之示意 圖0 第5圖為本發明一實施例中升壓電路之示惫圖。 第6圖為本發明一實施例中電壓分壓/選擇電路之示音圖 · 第7圖為本發明一實施例中電壓分壓/選擇電路運^之示 【主要元件符號說明】 薄膜電晶體開關The potentials VGH0 VVGHn are called, wherein the relationship between VGH0 VVGHn and VGHMAX is as follows: VGH0=VGHMAx; VGH1=VGHMAx-AV1; VGH2=VGHMax-A V2; VGHn=VGHMAx-A Vn; where Δ VI~Δ Vn The value is determined by the resistors R1 to Rn. 9 201135709 The embodiment of Fig. 7 shows the waveforms of the gate drive signal SG', the source drive signal SD, the pixel electrode potential VP, and the selection signal SEL. As shown in Fig. 7, the enable potential of the gate drive signal SG' is determined by the value of the selection signal SEL. It is assumed that the source driving signal SD having the positive potential VDH is charged in the odd driving period (ΤΙ, T3, ..., etc.) to charge the pixel unit, and in the even driving period (T2, T4, ..., etc.) The source of the negative polarity potential VDL drives the signal SD to charge the pixel unit, wherein the values of VDH and VDL are related to the gray level value of the image to be displayed by the pixel unit during the corresponding driving period. In the horizontal selection period (T0N1, T0N3, ..., etc.) in the positive polarity driving period, the gate driving signal SG' has an enabling potential (VGH1, VGH3, ..., etc.), and at this time, the thin film transistor switching TFT It will be turned on, and the source driving signal SD will charge the liquid crystal capacitor Clc and the storage capacitor Cst to allow the pixel electrode potential VP to reach the level VDH of the source driving signal SD. During the horizontal selection period (T〇N2, T〇N4, _., etc.) in the negative polarity driving period*, the gate driving signal SG has an enabling potential (VGH2, VGH4, ...), at which time the thin film transistor switching TFT will When turned on, the source driving signal SD charges the liquid crystal capacitor CLC and the storage capacitor CST so that the pixel electrode potential VP reaches the level VDL of the source driving signal SD. In the non-horizontal selection period T0FF1 to T〇FFn' in the driving period T1 to Τη, when the gate driving signal SG is switched to the de-energizing potential VGL, the parasitic capacitance of the thin film transistor switching TFT causes a feedthrough voltage at its gate, respectively. VfDI ~ T FD1. As shown in FIG. 7 and the formula (1), the feed-through voltages VFD1 V VFDn caused by T1 to Τη in each driving cycle are respectively related to the enable potentials VGH1 VVGHn of the gate drive 10 201135709 motion signal SG, and The values of the enable potentials VGH1 V VGHn are determined by the value of the selection signal SEL (for example, OOH to OnH). In other words, the integrated driving circuit 420 of the invention can respectively provide n gate driving signals SG1 to SGn having different enabling potentials VGH1 VVGHn according to the selection signal SEL. Therefore, the present invention can change the value of the selection signal SEL according to the panel characteristics, so that the integrated driving circuit 420 outputs a corresponding gate driving signal to the pixel unit in a specific region of the liquid crystal display panel 400. For example, for the liquid crystal display panel 400 shown in FIG. 4, the present invention can respectively use the gate driving signals with different enabling potentials VGH1 VVGHn according to the degree of flickering of the inner surface of each active area A1~An. Drives the pixel units in the corresponding active area. It is assumed that the overall parasitic electric valley of the unit cells in the active areas A1 to An is represented by CP丨~CPn' and Cpi<CP2<...<cPn, at this time VGH1>VGH2>.">VGHn' Figure 7 shows. However, the magnitude relationship of the enabling potentials VGH1 to VGHn is determined depending on the panel characteristics, and the fourth and seventh drawings are merely examples of the present invention, and do not limit the scope of the present invention. As described in the above, due to process or other factors, the parasitic capacitance of the thin film transistor switching TFT in different regions on the liquid crystal display panel may be different, which may cause different levels of feedthrough voltage, and the degree of flashing in various areas of the panel It will also be different. According to the invention, the enabling potential of the corresponding gate driving signal is determined according to the special process of the pixel unit in each active region. Therefore, for the pixel unit at different positions on the display panel of the night 201135709, the present invention can compensate for the influence caused by the energization >1 with the corresponding amplitude, and further improve the surface flashing with the same amplitude on the real value. In turn, the overall display screen is improved. The above is only the preferred embodiment of the present invention, and all the modifications and modifications made by the patent application scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view of a halogen unit on a liquid crystal display panel of the prior art. Fig. 2 is a schematic view showing a method of driving a halogen element in the prior art. Fig. 3 is a liquid crystal display panel of the prior art and its driving diagram. 4 is a schematic diagram of a liquid crystal display panel and a driving method thereof. FIG. 5 is a schematic diagram of a boosting circuit according to an embodiment of the present invention. 6 is a sound diagram of a voltage dividing/selecting circuit according to an embodiment of the present invention. FIG. 7 is a diagram showing a voltage dividing/selecting circuit according to an embodiment of the present invention. [Main component symbol description] Thin film transistor switch
PX 畫素單元 TFT 12 201135709PX pixel unit TFT 12 201135709
Clc 液晶電容 C1 〜C4 内部電容 Cst 儲存電容 R1 〜Rn 電阻 DL 資料線 610 分壓電路 GL 閘極線 620 選擇電路 500 升壓電路 600 電壓分壓/選擇電路 510 整流器 A1 〜An 主動區域 SD 源極驅動訊號 130 源極驅動電路 SG 閘極驅動訊號 140 閘極驅動電路 300 顯不區 150 時序控制器 100、 400 液晶顯不面板 110、 420 整合型驅動電路 120 > 501〜504 電荷泵 13Clc liquid crystal capacitor C1 ~ C4 internal capacitor Cst storage capacitor R1 ~ Rn resistor DL data line 610 voltage divider circuit GL gate line 620 selection circuit 500 boost circuit 600 voltage divider / selection circuit 510 rectifier A1 ~ An active area SD source Pole drive signal 130 source drive circuit SG gate drive signal 140 gate drive circuit 300 display area 150 timing controller 100, 400 liquid crystal display panel 110, 420 integrated drive circuit 120 > 501~504 charge pump 13