201135437 六、發明說明： 【發明所屬之技術領域】 [0001 ] 本發明涉及一種供電電路’尤指一種電腦主機板上之cpu (Central Processing Unit ’中央處理器）供電電路 〇 【先前技術】 [0002] 一種如圖1所示之傳統之CPU供電電路包括一PWM ( Pulse-Width Modulation，脈寬調製）控制器晶片及 一驅動晶片，所述驅動晶片連接至一對M0SFET (場效應 管）’所述PWM控制器晶片輸出pwM信號至所述驅動晶片 以控制所述M0SFET之導通、(斷開之次序及轉間從而調整 輸出至CPU之電壓。PWM信號之工.作週期越大，輸出電壓 越大；PWM信號之工作週期越小，輸出電壓越小。所述驅 動晶片可為一 ADP3120A晶片，其包括一 Vcc電源引腳， 當該Vcc電源引腳之電壓範圍在4. 15V〜13. 2V之間時， ADP3120A晶片可正常工作。ADP3120A晶片在一最佳工 作電壓（如10V)下工作時，其輸出效專最佳，可降低電 能消耗’提高整個供電電路效能。然目前主機板上之電 源僅能提供12V、5V之電壓至所述驅動晶片，因此驅動晶 片之輸出效率不能最優化，造成不必要之電能浪費。 【發明内容】 [0003] 鑒於以上内容，有必要提供一種較為節能之CPU供電電路 〇 [0004] —種CPU供電電路，包括一脈寬調製控制器晶片、一與所 述脈寬調製控制器晶片相連之驅動晶片、一與所述驅動 099111540 表單編號A0101 第4頁/共13頁 0992020420-0 201135437 3曰片相連之第—場效應管及—與所述驅動晶片相連之第 昜效應管，所述驅動晶片接有—電源，所述脈寬調製 控制器晶片輸出脈寬調製信號至所述驅動晶片以控制所 述第-場效應管及第二場效應管之導通/截止狀態從而控 制輪出至咖之電壓，所述驅動晶片之電源輸人端接有I =壓調節器’所述電壓調節轉所述電源之電_節至 -優化電壓值提供給職驅動晶片㈣之電路。 [0005] Ο [0006] Ο [0007] 099111540 相較於習知技術，本發明CPU#雷雪w + 供電電斜·^料電壓調節 。至所述驅動晶片之電源調節至—優化電壓值， 驅動晶片找優化電難下工_，其輸岐率 可節省電能。 【實施方式】 請參閱圖2 ’本發明⑽供電電路—較佳實齡式包括一 PW二控制器晶片1。、一驅動晶片2。、一第一場效應管Μ 及一第二場效應管Q2。所述第一場效應管y及第二場致 =’2均為N溝道金屬氧化物半導體場效應管。所述: b曰片20之-對驅動信號輸出端與所述第—場效應管Μ及 第-場效應管Q2相連，所述PWM控制器晶片1Q輸出 號至所述驅動晶片20以控制所述第—場效應_及第信 場效應管Q2之導通/截止次序及時間，從而控制輪&〜 機板上咖之電壓。所述第1錢管Q1在-個週期内主 通之時間越長，輸出至CPlI之電壓越高。 導 ’述驅動晶片20包括-電虔調節器2卜_第一運算故 器23及-第二運算放大器25。所述電屋調節器以之^大 端與所述驅動晶片2G之電源5丨腳Vec相連並集成於所^ 表單編號A0I01 第5頁/共13頁 故魏 201135437 動晶片20内，所述電壓調節器21之輸出端與所述第二運 算放大器25相連。所述驅動晶片20之電源引腳Vcc與主機 板上之12V電源相連並接有一電容C1。所述第一運算放大 器23之一第一接線端接有一二極體D1及一電容C2，所述 二極體D1之陽極與所述12V電源相連，陰極與所述第一運 算放大器23之第一接線端相連。所述第一運算放大器23 之一第二接線端（驅動信號輸出端）藉由一電阻R2與所 述第一場效應管Q1之閘極相連，所述第一運算放大器23 之一第三接線端藉由串接之電阻R1及電容C3連接至第一 運算放大器23之第一接線端。所述第二運算放大器25之 驅動信號輸出端與所述第二場效應管Q2之閘極相連。所 述第一場效應管Q1之汲極與所述12V電源相連，源極與所 述第二場效應管Q2之汲極相連，所述第二場效應管Q2之 源極接地。所述第一場效應管Q1之源極及第二場效應管 Q2之汲極共同連接至一電感L1之一端，電感L1之另一端 連接至一電壓輸出端Vout ; —電容C4之一端與該電壓輸 出端Vout相連，另一端接地。 [0008] 所述CPU供電電路工作時，所述PWM控制器晶片10輸出一 PWM信號至所述驅動晶片20，當所述PWM信號為高電平時 ，所述驅動晶片20之第一運算放大器23輸出驅動信號使 場效應管Q1導通、Q2截止，所述電感L1及電容C4開始儲 能；當所述PWM信號為低電平時，所述驅動晶片20之第二 運算放大器25輸出驅動信號使場效應管Q2導通、Q1截止 ，所述電感L1對電容C4充電。由於所述電感L1及電容C4 具有阻止電流及電壓突變之作用，所述CPU供電電路可輸 099111540 表單編號A0101 第6頁/共13頁 0992020420-0 201135437 出穩定之低壓直流電壓（如1. 3 V )至* 化 王機板上之CPU。經 所述電壓調節器21之調節作用，所述 電源可降低至一 穩疋之優化電壓（如l〇V)並輸出至所 曾_ 〜24驅動晶片20内之 第二運算放大器25，在該優化電壓值下τ & r工作時，所述驅 動晶片20之輸出效率最優，可減少不 要之電能浪費。 [0009] ❹ [0010] [0011] G [0012] [0013] [0014] 099111540 請參閱圖3 ’在本發明CPU供電電路另— 杈佳實施方式中 ’-電壓調節器3()連接於所述m電源及所述驅動晶片2〇 之電源引腳VCC之間，可將12V電源降壓至_優化之電麼 值（如10V)輪出至所述驅動晶片20，闵 因而使所述驅動晶 片20之輸出效率最優。 在本發明触實施方式巾，料電壓—如㈣可包 括電阻、穩壓二極體、三極管等元件。所述PWM控制器晶 片1〇可外接多個驅動晶片，以組成多相供電電路給主機 板上之CPU供電。 综上所述，本發明係合乎杳明專利申請條件，爰依法提 出專利申請。惟，以上所述僅為本發明之較佳實施例， 舉凡熟悉本案技藝之人士其所爰依本案之創作精神所作 之等效修飾或變化，皆應涵蓋於以下之申請專利範圍内 【圖式簡單說明】 圖1是一傳統之CPU供電電路之組成圖。 圖2是本發明CPU供電電路一較佳實施方式之組成圖。 圖3是本發明CPU供電電路另一較佳實施方式之組成圖。 【主要元件符號說明】 表單編號A0101 第7頁/共13頁 〇 201135437 [0015] PWM控制器晶片： 10 [0016] 驅動晶片.2 0 [0017] 電壓調節器：21 '30 [0018] 第一運算放大器 ：23 [0019] 第二運算放大器 :25 [0020] 二極體.D1 [0021] 電容：C1-C4 [0022] 電阻：R1-R2 [0023] 電感：L1 099111540 表單編號 A0101 第 8 頁/共 13 頁 0992020420-0201135437 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a power supply circuit, particularly a CPU (Central Processing Unit 'Power Supply Circuit) power supply circuit on a computer motherboard [Prior Art] [0002] A conventional CPU power supply circuit as shown in FIG. 1 includes a PWM (Pulse-Width Modulation) controller chip and a driver chip connected to a pair of MOSFETs (Field Effect Transistors) The PWM controller chip outputs a pwM signal to the driving chip to control the turn-on of the MOSFET, (the order of disconnection and the turn to adjust the voltage output to the CPU. The greater the period of the PWM signal, the higher the output voltage 2VV. The voltage of the Vcc power supply pin is 4.15V~13. 2V. The voltage is in the range of 4. 15V~13. 2V. When working, the ADP3120A chip can work normally. When the ADP3120A chip is operated at an optimal working voltage (such as 10V), its output efficiency is optimized, which can reduce the power consumption. Power supply circuit performance. However, the power supply on the motherboard can only provide 12V, 5V voltage to the drive chip, so the output efficiency of the drive chip can not be optimized, resulting in unnecessary waste of power. [Abstract] [0003] In the above, it is necessary to provide a more energy-saving CPU power supply circuit. [0004] A CPU power supply circuit includes a pulse width modulation controller chip, a driving chip connected to the pulse width modulation controller chip, and a device Drive 099111540 Form No. A0101 Page 4 / Total 13 Page 0992020420-0 201135437 3 相连 connected to the FET and the 昜 effect transistor connected to the drive wafer, the drive chip is connected to the power supply, The pulse width modulation controller chip outputs a pulse width modulation signal to the driving chip to control an on/off state of the first field effect transistor and the second field effect transistor to control a voltage to the battery, the driving The power supply input terminal of the chip is connected with an I = voltage regulator 'the voltage is adjusted to the power of the power supply to the optimized voltage value to provide the circuit for the driver chip (4). 5] Ο [0006] 0007 [0007] 099111540 Compared with the prior art, the present invention CPU #雷雪 w + power supply voltage adjustment. The power supply to the drive chip is adjusted to - optimize the voltage value, drive The wafer can be optimized and the power is saved. The transmission rate can save power. [Embodiment] Please refer to FIG. 2 'The invention (10) power supply circuit - the preferred age type includes a PW two controller chip 1. One drive wafer 2. a first field effect transistor and a second field effect transistor Q2. The first field effect transistor y and the second field effect = '2 are both N-channel MOSFETs. The b-chip 20 has a pair of driving signal output terminals connected to the first field effect transistor and the first field effect transistor Q2, and the PWM controller chip 1Q outputs a number to the driving chip 20 to control the The first-field effect _ and the on/off sequence and time of the FET Q2 are controlled to control the voltage of the wheel & The longer the first main tube Q1 is main-passed in one cycle, the higher the voltage output to CPlI. The driving wafer 20 includes a -electron regulator 2, a first arithmetic processor 23, and a second operational amplifier 25. The electric house regulator is connected to the power supply 5 of the driving chip 2G, Vec, and integrated in the form number A0I01, page 5 of 13 An output of the regulator 21 is coupled to the second operational amplifier 25. The power pin Vcc of the driving chip 20 is connected to a 12V power supply on the host board and connected to a capacitor C1. One of the first operational amplifiers 23 is connected to a diode D1 and a capacitor C2. The anode of the diode D1 is connected to the 12V power supply, and the cathode and the first operational amplifier 23 are connected. The first terminals are connected. The second terminal (drive signal output end) of one of the first operational amplifiers 23 is connected to the gate of the first field effect transistor Q1 via a resistor R2, and the third terminal of the first operational amplifier 23 is connected. The terminal is connected to the first terminal of the first operational amplifier 23 by a resistor R1 and a capacitor C3 connected in series. The driving signal output end of the second operational amplifier 25 is connected to the gate of the second field effect transistor Q2. The drain of the first field effect transistor Q1 is connected to the 12V power supply, the source is connected to the drain of the second field effect transistor Q2, and the source of the second field effect transistor Q2 is grounded. The source of the first FET Q1 and the drain of the second FET Q2 are connected in common to one end of the inductor L1, and the other end of the inductor L1 is connected to a voltage output terminal Vout; The voltage output terminal Vout is connected and the other end is grounded. [0008] When the CPU power supply circuit is in operation, the PWM controller chip 10 outputs a PWM signal to the driving chip 20, and when the PWM signal is high level, the first operational amplifier 23 of the driving chip 20 Outputting the driving signal to turn on the FET Q1, Q2 is turned off, the inductor L1 and the capacitor C4 start to store energy; when the PWM signal is low, the second operational amplifier 25 of the driving chip 20 outputs a driving signal to make the field The effect transistor Q2 is turned on, Q1 is turned off, and the inductor L1 charges the capacitor C4. Since the inductor L1 and the capacitor C4 have the function of blocking the sudden change of current and voltage, the CPU power supply circuit can input 099111540 Form No. A0101 Page 6 / Total 13 Page 0992020420-0 201135437 A stable low voltage DC voltage (such as 1.3) V) to the CPU of the king board. Through the adjustment of the voltage regulator 21, the power supply can be reduced to a stable optimized voltage (eg, 10 V) and output to the second operational amplifier 25 in the NAND 24 drive wafer 20, where When the τ & r operation is performed under the optimized voltage value, the output efficiency of the driving chip 20 is optimal, and unnecessary power waste can be reduced. [0009] [0011] [0012] [0014] [0014] Please refer to FIG. 3 'In the CPU power supply circuit of the present invention - another preferred embodiment - the voltage regulator 3 () is connected to the Between the m power supply and the power supply pin VCC of the driving chip 2, the 12V power supply can be stepped down to an optimized power value (such as 10V) to the driving chip 20, thereby making the driving The output efficiency of the wafer 20 is optimal. In the embodiment of the invention, the material voltage, such as (4), may include components such as a resistor, a voltage regulator diode, and a triode. The PWM controller chip 1 can externally connect a plurality of driving chips to form a multi-phase power supply circuit to supply power to the CPU on the host board. In summary, the present invention is in accordance with the conditions of the patent application, and the patent application is filed according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art to the spirit of the present invention should be included in the following patent claims. Brief Description] Figure 1 is a composition diagram of a conventional CPU power supply circuit. 2 is a block diagram of a preferred embodiment of a CPU power supply circuit of the present invention. 3 is a composition diagram of another preferred embodiment of the CPU power supply circuit of the present invention. [Main component symbol description] Form No. A0101 Page 7 of 13 35201135437 [0015] PWM controller chip: 10 [0016] Driver chip. 2 0 [0017] Voltage regulator: 21 '30 [0018] Operational Amplifier: 23 [0019] Second Operational Amplifier: 25 [0020] Diode. D1 [0021] Capacitance: C1-C4 [0022] Resistor: R1-R2 [0023] Inductance: L1 099111540 Form No. A0101 Page 8 / Total 13 pages 0992020420-0