201123738 .Λ^νν.-0019-TW 31935twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種取樣保持電路及其消除方法，且 特別是有關於一種類比訊號的取樣保持電路及其消陝 法。 '、’于、 【先前技術】 鲁 '日$生’舌中所產生的物理讯號大多是以類比訊號的 形式存在，然而由於數位訊號具有方便資料的編輯、分&、 儲存以及較佳的抗雜訊能力等優點，因此在應用上通常會 利用類比數位轉換器將類比訊號轉換成數位訊號。 θ 類比數位轉換裔在無線通訊系統及可攜式視訊影像 裝置領域的應用扮演著重要的角色，而隨著無線通訊系統 及:攜式視訊影像裝置的快速成長’對於類比數位轉換器 的阿轉換速度的要求也日益提高。而在許多種類的類比數 • _換器的架構中，又以管線式類比數位轉換器(pipelined malogidig^ c〇nverter，pipelined ，最能達到高速的輪 入性能和快速處理能力。 —般的類比數位轉換器皆會在其前端設置一取樣保 持電路’用以把類比訊號保留住。由於取樣時間極短，取樣 輪出，一串斷續的窄脈衝。要把每個取樣的窄脈衝信號數位 化丄而要一疋的時間，因此在兩次取樣之間，應將取樣的類 比k號暫時儲存到下個取樣脈衝到來，這個動作稱之為保 寺根據數位讯號處理的基本原理，Nyquist取樣定理，若要 201123738 tt^uu^-uu 19-TW 3 j 935twf.doc/n ，正確且忠f地魏所娜_比峨，必須取樣頻率至少 率的2倍。因此類比數位轉換的速度往往決定於 路的操作頻率，隨著類比數位轉換器的處理訊 越，對與其游配的取樣保持電路的操作頻率 ^ ^越來越高，如何使取難持電路的操作辭提昇至 付5貫際需求儼然是一重要課題。 圖1料縣樣路於雜 】。圖=如中多個電容C1A輕接不同 =電2，傳統的取樣保持電路“ 栝電谷C3A、C4A、多個電容C1A、多個 ^大器102與電壓產生器辦。其中電壓產生哭m = 2出參考 VRP、VRN。圖2的實 =容=電容CU之電容^ 於伴持狀雜時批二二⑽、C/128。取樣保持電路⑽ 和==tr A、C2A連接到參考電厂堅響 :=參考電堡VRN’以使取樣保持電路1〇 樣的類比訊號的正偏移或負偏移電壓。並中 _等於負的參考電壓V聰，即術〜= 與不同電壓的轉接方式與電容αΑ相同另:此】 再头述。傳統的取樣保持電路觸雖可消 f不 偏移電屋，但在實際應用時，偏移電 種的環i兄因素或類比訊號的 θ各 保持電路在類比訊號的偏移電壓量小時，^吏=的取樣 各個數來消除偏讀，且每一個電容不是輕接：： 201123738 no-^y-0019-T w 31935twf.d〇c/n 產考電壓vrn，_提供參考電壓 大電位。如t卜一成破抽取大電流，造成參考電塵被拉低一 一來，參考電壓需要較長的時間回復至原來 •的電位，而使得取樣保持 2 降低類比數位轉換器的轉換效率。又又·制’進而 【發明内容】 類比訊!路及其消除方法’可消除 速度。 ^移· ’越高舰數位轉鋪的操作 元、多個電ί、出—保持電路’包括一取樣電路單 於一第二狀態時消’於取樣保持電路處 控制模_接上述電容，依直流偏移電壓。 述電容•接至—共模電壓的個數二 =上 移電壓的電容大小。另外 、疋用於桃仏偏 單元，於直流偏移電壓_3=^元^;=取樣電·路 訊號所包含的交流訊號。$路處於ι狀鱗輸出類比 訊號號實施例中’上述之類比訊號包括—波形 #一開關、—第三開關、一第四開關、一第 201123738 ,i〇-^uv^-wl9-TW 31935twf.doc/n :開關以及一第一電容、一第二電容。其中，第一開關、 第一開關分別接收波形訊號與接地訊號。第—電容之第一 端減第—關，第二電容之第—端祕第二_。第三 開_接於第-電容的第二端與第二電容的第二端之間。 第四開關與第-電容並聯。第五開關與第二電容並聯。其 中第-開關、第二關和第三關受控於—第—訊號，而 於第-狀態時開啟，並於第二狀態時關閉。另外，第四、 •狀態時關閉，並於 第五開關受控於一第二訊號，而於第 第二狀態時開啟 在本發明之-實施例中，上述之保持電路單元包括一 操作放^器、-第三電容以及—第四電容。操作放大器之 正輸入端與負輸人端分別输第—電容的第二端與第二電 容的第二端，接收取樣電路單元取樣的舰訊號，並於操 作放大器的第-輸出端與第二輸出端輸出類比訊號所包含 的交流城。第三電料接崎作放大器的场入端 -輸出端之間。第四電容軸接於操作放大器的負輸入丸 與第二輸出端之間。 1 一 ；^本發明之-實施例中，上述之第—訊號的電位與第 一说说的電位不同時為高電位。 號。在本發明之-實施例中，上述讀形訊號為弦波訊 在本發明之-實施例中，上述之 制單=及㈣多場其中，上述多工_^^控 且上述夕工态的輸出端耦接對應的上述電容，各個多工器 -0019-TW 31935twf.doc/n 201123738 接收一第一參考電虔、一第一 受控於控制單元，以於輪。共模電虔’並 考電壓以及共模電壓之其5輪出卓-參考電壓、第二參 在本發明之一實施例令， 五電容和多驾六電容衫個電容分為多個第 操作放大器的正輸入端，電容之第-端減 值;各個第六電容之第的電容 且各個第六電容具有不同的電=作放h的負輸入端， 先，肖除方法，其步驟包括:首 時二路:處::第-狀態 ==壓ίΠΓ。繼之，藉由；制 :二==偏移電壓的電容大:= 由保持电路早兀於取樣保持電路處於 類比訊號所包含的交m ⑦κ㈣輸出 基於上述，本發明可依_比訊 小’調整用於消除偏移電厂堅量的電容個數，=二 说的直流偏移電壓，並提高類比數位轉換器的操作速度。 為:本:，上述特徵和優點能更明顯易懂，下:特 舉貫鈀例，並配合所附圖式作詳細說明如下。 【實施方式】 因此，本發明之實施例揭露一種取樣保持電路，可依 201123738 HS-20〇y-UUl9-TW 3l935twf.d〇c/n 據類比訊號的偏移電壓量調整用於消除 :===電r參考回 …號二= 的類比數位轉崎轉電路搭配 爾細闡述本發明的實施例，附圖舉例 ;二1:示範實施例’其中相同標號指示同樣或相 圖。二保持電路的示意 .多個電容CN用以消除取樣電路單 的直流偏移電壓。批剎描έη Qn/I π取樣5孔號 之直流偏_=:=== =輸，類比訊號S1所包含的交流 :V:負責提供消除直流偏移電壓所須的參考ίϊ 蝴繼(C〇mm〇nV〇1_M。並中， 的直流偏移電财為正偏移錢或負電 Π:值=訊號S1為一弦波訊號，其原本之波峰 值波合值以及中心準位分別為lv、 ，過程中可能產生正偏壓或負偏壓，而 值、波谷f以及中心準位分別提高或降低-電位值:、 圖4疋依照本發明一實施例之偏移電壓消除方法的流 201123738 no-zwy-OO 19-TW 31935twf.doc/n 程圖。以下將配合圖3與圖4說明訊號的 請同時參關3與圖4。料，取樣電 處於取樣狀態時取樣一 ::: 的電容如肖_比訊號S1所包= 偏衫_驟s姻）。㈣模㈣4則於取樣 呆持狀態時，依據類比訊號S1的直流偏移 電小與—共模麵VCM連接的電容CN個數，201123738 .Λ^νν.-0019-TW 31935twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a sample and hold circuit and a method for eliminating the same, and in particular to an analog signal The sampling and holding circuit and its elimination method. ', 'Yu, [Prior Art] The physical signals generated in the tongue of Lu's Day are mostly in the form of analog signals. However, digital signals have the convenience of editing, sorting, storing, and better data. The anti-noise ability and the like, so the analog signal converter is usually used to convert the analog signal into a digital signal. θ analog-to-digital conversion plays an important role in the field of wireless communication systems and portable video imaging devices, and with the rapid growth of wireless communication systems and portable video imaging devices, the conversion of analog digital converters The speed requirements are also increasing. In many kinds of analogy and _ converter architectures, pipelined analogy digital converters (pipelined malogidig^c〇nverter, pipelined, can achieve high-speed round-robin performance and fast processing capability. The digital converter will have a sample-and-hold circuit at its front end to retain the analog signal. Since the sampling time is extremely short, the sampling wheel is out, a series of intermittent narrow pulses. The narrow pulse signal of each sample is digitized. It takes a glimpse of time, so between the two samples, the sampled analog k should be temporarily stored to the next sampling pulse. This action is called the basic principle of the temple based on digital signal processing, Nyquist sampling. Theorem, if 201123738 tt^uu^-uu 19-TW 3 j 935twf.doc/n, correct and loyal to Wei Naina _ than 峨, must sample the frequency at least 2 times. Therefore, the analog digital conversion speed is often Determined by the operating frequency of the road, with the analog signal processing of the analog converter, the operating frequency of the sample-and-hold circuit that matches it is getting higher and higher, how to improve the operation of the difficult-to-hold circuit It is an important issue to pay for the 5 consecutive requirements. Figure 1 shows the sample road in the county. Figure = If the multiple capacitors C1A are connected differently = electricity 2, the traditional sample and hold circuit "栝电谷C3A, C4A, A plurality of capacitors C1A, a plurality of capacitors 102 and a voltage generator are used. The voltage is generated by crying m = 2 out of reference VRP, VRN. The real = capacity of Figure 2 = the capacitance of the capacitor CU ^ with the companion timing batch 2 Two (10), C/128. The sample-and-hold circuit (10) and ==tr A, C2A are connected to the reference power plant to resonate: = reference to the electric castle VRN' to make the positive or negative bias of the analog signal of the sample-and-hold circuit 1 Shift voltage. And _ is equal to the negative reference voltage V Cong, that is, operation ~= The transfer mode with different voltages is the same as the capacitance αΑ. Another: This is described again. The traditional sample-and-hold circuit can be eliminated without offset. Electric house, but in practical applications, the offset factor of the bias type or the θ of the analog signal keeps the circuit at the offset voltage of the analog signal, and the number of samples is eliminated to eliminate the partial read, and each A capacitor is not lightly connected: 201123738 no-^y-0019-T w 31935twf.d〇c/n The test voltage vrn, _ provides a large reference voltage If the reference current is pulled down one by one, the reference voltage takes a long time to return to the original potential, and the sample hold 2 reduces the conversion efficiency of the analog digital converter. And again · system 'and then [invention content] analogy! Road and its elimination method 'can eliminate the speed. ^ Shift · 'the higher the ship's digital transfer operation unit, multiple electric, output - hold circuit' includes a When the sampling circuit is in a second state, the control mode is connected to the capacitor at the sampling and holding circuit, and the voltage is offset by the DC. Capacitor • Connected to – the number of common mode voltages = the size of the capacitor that moves up the voltage. In addition, the 疋 is used for the Peach 仏 unit, and the DC offset voltage is _3=^元^;= The AC signal included in the sampling electric signal. $路在ι状鳞output analog signal number in the embodiment of the above-mentioned analog signal includes - waveform #一开关, - third switch, a fourth switch, a 201123738, i〇-^uv^-wl9-TW 31935twf .doc/n: switch and a first capacitor and a second capacitor. The first switch and the first switch respectively receive the waveform signal and the ground signal. The first end of the first capacitor is reduced by the first-off, and the second of the second capacitor is the second-end. The third open_ is connected between the second end of the first capacitor and the second end of the second capacitor. The fourth switch is connected in parallel with the first capacitor. The fifth switch is connected in parallel with the second capacitor. The first switch, the second switch and the third switch are controlled by the -first signal, and are turned on in the first state and turned off in the second state. In addition, the fourth state is turned off, and the fifth switch is controlled by a second signal, and when the second state is turned on. In the second embodiment, in the embodiment of the present invention, the holding circuit unit includes an operation. , - third capacitor and - fourth capacitor. The positive input end and the negative input end of the operational amplifier respectively input the second end of the capacitor and the second end of the second capacitor, receive the ship signal sampled by the sampling circuit unit, and operate at the first output end and the second end of the operational amplifier The output outputs the communication city included in the analog signal. The third material is connected between the field input and output terminals of the amplifier. The fourth capacitor shaft is connected between the negative input pulse of the operational amplifier and the second output terminal. In the embodiment of the present invention, the potential of the first signal is higher than the first potential. number. In the embodiment of the present invention, the read signal is a sine wave. In the embodiment of the present invention, the above-mentioned single-order and (four)-multiple fields, wherein the multiplex control and the above-mentioned eve state The output end is coupled to the corresponding capacitor, and each multiplexer -0019-TW 31935twf.doc/n 201123738 receives a first reference power, and a first control unit, for the wheel. The common mode electric 虔 'and the voltage and the common mode voltage of its 5 rounds - reference voltage, the second reference in one embodiment of the present invention, the five capacitors and the multi-drive six capacitors capacitors are divided into multiple operations The positive input end of the amplifier, the first end of the capacitor is derated; the first capacitor of each sixth capacitor and each sixth capacitor has a different electric input = the negative input end of the reset h, first, the divisor method, the steps include: First time and two roads: at:: - state == pressure ΠΓ. Then, by: system: two == offset voltage of the capacitor is large: = the hold circuit is earlier than the sample and hold circuit is in the analog signal included in the intersection of m 7κ (four) output based on the above, the present invention can be small according to _ Adjust the number of capacitors used to eliminate the offset power plant's capacity, = the DC offset voltage, and increase the operating speed of the analog digital converter. For: Ben: The above features and advantages can be more clearly understood. The following is a special example of palladium, which is described in detail below with reference to the drawings. [Embodiment] Therefore, an embodiment of the present invention discloses a sample-and-hold circuit that can be adjusted according to the offset voltage of the analog signal according to 201123738 HS-20〇y-UUl9-TW 3l935twf.d〇c/n for: ==Electrical r References... No. 2 = analogy digital transshipment circuit arbitrarily exemplifies an embodiment of the present invention, the accompanying drawings are exemplified; 2: Exemplary embodiment 'where the same reference numerals indicate the same or phase diagram. Description of the two holding circuits. A plurality of capacitors CN are used to cancel the DC offset voltage of the sampling circuit. Batch brake έη Qn/I π sampling 5 hole number DC offset _=:=== =Transmission, analog signal S1 contains AC: V: Responsible for providing the reference necessary to eliminate DC offset voltage ϊ 蝴 继 (C 〇mm〇nV〇1_M. In the middle, the DC offset power is positive offset money or negative power: value=signal S1 is a string signal, and its original peak-to-peak value and center level are respectively lv , a positive bias or a negative bias may be generated in the process, and the value, the valley f, and the center level are respectively increased or decreased - the potential value: FIG. 4 is a flow of the offset voltage elimination method according to an embodiment of the present invention 201123738 No-zwy-OO 19-TW 31935twf.doc/n The process diagram will be described below with reference to Figure 3 and Figure 4. Please refer to Figure 3 and Figure 4. The sample is sampled at the sampling state::: Capacitor such as Xiao _ than the signal S1 package = partial shirt _ s s marriage. (4) Mode (4) 4 is in the sampling state, according to the DC offset of the analog signal S1, and the number of capacitors CN connected to the common mode surface VCM,
ϋ疋祕'肖_比職si之錢财電壓的電容大小 (v驟S406)。其中，與共模電壓VCM 參與消除直流偏移電壓的動作，因此可減輕產生參考= yRP、VRN的電壓產生器遍的負擔，當連接到電壓產生 器308的電容（：^^個數變少時，電壓產生器3〇8被抽取的 電流也隨之減小，參考電壓VRp、VRN回復原來電位的時 間也將縮短。因此電壓產生器3G8可依據直流偏移電麗的 大小提供_的參考電壓VRp、VRN，獨如傳統取樣保 ，電路的電壓產生H持續地被抽取大電流，而拉長參考電 【VRP、VRN回復至原來電位的時間，而使得取樣保持電 路的操作頻率受到限制。最後，保持電路單元306輪出消 除類比訊號S1之直流偏移電壓後所獲得的類比訊號S2， 亦即保持電路單元306輸出類比訊號S1所包含的交流訊 號S2(步驟S408)。藉由調整與共模電壓VCM連接的電容 CN個數，可使電壓產生器308所須提供給電容CN的充電 電荷變少’因而參考電壓VRP、VRN被拉低的電位減小， 縮短了麥考電壓VRP、VRN回復原來電位的時間，使取樣 201123738ϋ疋 Secret 'Shaw _ than the size of the capacitor of the money of the Si voltage (v step S406). Wherein, the common mode voltage VCM participates in the action of eliminating the DC offset voltage, thereby reducing the burden of generating the voltage generators of the reference = yRP, VRN, when the capacitance connected to the voltage generator 308 (: ^^ is less) At the same time, the current drawn by the voltage generator 3〇8 is also reduced, and the time for the reference voltages VRp and VRN to return to the original potential is also shortened. Therefore, the voltage generator 3G8 can provide a reference according to the magnitude of the DC offset. The voltages VRp and VRN are the same as the conventional sampling guarantee. The voltage of the circuit generates H continuously to draw a large current, and the reference voltage [VRP, VRN returns to the original potential time), so that the operating frequency of the sample-and-hold circuit is limited. Finally, the hold circuit unit 306 rotates the analog signal S2 obtained after the DC offset voltage of the analog signal S1 is removed, that is, the hold circuit unit 306 outputs the AC signal S2 included in the analog signal S1 (step S408). The number of capacitors CN connected to the common mode voltage VCM can reduce the charge charge that the voltage generator 308 has to supply to the capacitor CN. Therefore, the potentials at which the reference voltages VRP and VRN are pulled down are reduced. Shortened McCaw voltage VRP, VRN response time of the original potential, the sampling 201123738
Ht>-2Uuy-u^l9-TW 31935twf.doc/n ==可的提二下:個訊號的取樣保持，進而提 圖5是依照本發明另一實施例之取樣保持 ::圖。請參照圖5 詳細來說，上述之類比訊號si可== 波形訊號vw與-接地訊號VG，而取樣電路單元 包括開關SW1〜S奶以及電容α ' C2。其中開關swi、 SW2分別接收-波形訊號vw(例如是弦波訊號声 訊號VG ’且分別與電容α、C2的第一端轉接。開關挪 耦接於電容Cl、C2的第二端之間。開關SW4、sw 別與電容a、C2並聯。 u 上述之開關SW1〜SW3受控於一第一訊號PH1，在取 樣保持電路300處於取樣狀態時開啟，並於保持狀能時關 閉。另外，開關SW4、SW5則受控於一第二訊號PH2，而 在取樣保持電路300處於取樣狀態時關閉’並於保持狀態 時開啟。其中第一訊號PH1和第二訊號PH2之電位不^ 時為高電位。 另外，控制模組304包括控制單元502以及多個多工 态504。其中控制單元502耦接此些多工器5〇4,而各個多 工器504的輸出端耦接相對應的電容CN，各個多工器504 具有三個輸入端，分別接收參考電壓VRP、VRN以及共模 電壓VCM。各個多工器504受控於控制單元502，以輪出 麥考電壓VRP、VRN以及共模電壓VCM其中之一。控制 單凡502則接收波形訊號VW與接地訊號VG以決定各個 多工器504的輸出。 201123738 ^〇〇19-TW 31935twf.doc/n 保持電路單元306包括操作放大器508與電容C3、 C4。其中操作放大器5〇8的正、負輸入端分別耦接電容 Cj、C2的第二端。此外，操作放大器5〇8的正、負輸入 端亦耦接控制模組304所包含的多個電容CN。電容C3耦 接於插作放大器5〇8的正輸入端與輸出端v〇p之間，電容 C4則耦接於操作放大器5〇8的正負入端與輸出端v〇N之 間。Ht>-2Uuy-u^l9-TW 31935twf.doc/n == can be exemplified: sample hold of a signal, and FIG. 5 is a sample hold diagram in accordance with another embodiment of the present invention. Referring to FIG. 5 in detail, the above analog signal si can be == waveform signal vw and -ground signal VG, and the sampling circuit unit includes switches SW1 to S milk and capacitor α 'C2. The switches swi and SW2 respectively receive a waveform signal vw (for example, a sine wave signal VG ′ and are respectively switched to the first ends of the capacitors α and C2. The switch is coupled between the second ends of the capacitors C1 and C2. The switches SW4 and sw are connected in parallel with the capacitors a and C2. ◆ The switches SW1 to SW3 are controlled by a first signal PH1, which is turned on when the sample and hold circuit 300 is in the sampling state, and is turned off when the state is maintained. The switches SW4 and SW5 are controlled by a second signal PH2, and are turned off when the sample-and-hold circuit 300 is in the sampling state, and are turned on when the state is held. The potentials of the first signal PH1 and the second signal PH2 are not high. In addition, the control module 304 includes a control unit 502 and a plurality of multiplexers 504. The control unit 502 is coupled to the multiplexers 5〇4, and the output ends of the multiplexers 504 are coupled to corresponding capacitors. CN, each multiplexer 504 has three inputs, respectively receiving reference voltages VRP, VRN and a common mode voltage VCM. Each multiplexer 504 is controlled by the control unit 502 to turn off the McCaw voltages VRP, VRN and common mode. One of the voltages VCM. Control single 5 02 receives the waveform signal VW and the ground signal VG to determine the output of each multiplexer 504. 201123738 ^〇〇19-TW 31935twf.doc/n The holding circuit unit 306 includes an operational amplifier 508 and capacitors C3, C4. The positive and negative input terminals of the 〇8 are respectively coupled to the second ends of the capacitors Cj and C2. In addition, the positive and negative input terminals of the operational amplifier 5〇8 are also coupled to the plurality of capacitors CN included in the control module 304. Capacitor C3 The capacitor C4 is coupled between the positive input terminal and the output terminal v〇N of the operational amplifier 5〇8. The positive input terminal and the output terminal v〇N of the operational amplifier 5〇8 are coupled between the positive input terminal and the output terminal v〇N.
$取樣保持電路300處於取樣狀態時，開關SW1、SW2 為開啟狀態，而開關SW4、SW5為關閉狀態，因此電容 Cl C2可透過開關SW1、SW2接收波形訊號與接地 訊號VG。另外開M SW3於此時亦為開啟狀態，使得電容 =C2的第二端間為短路狀態，波形訊號與接地訊 ^ VG,所^供的電荷將被儲存於電容Cl、C2中。 當取樣保持電路期處於保持狀態時，開關撕、 =、SB為關閉狀態，而與電容α、Q並聯 為開啟狀態，分別於電容C1心的兩端之間 的’進而使電容Ο、C2於取樣狀態中所儲有 :::破轉移’與多個電容CN、電容所儲 何起進行電荷的重新分配。此時，和制置_ 形訊號VW與接地訊號VG的直流偏：電壓：二減 電容CN與參考電壓VRN、VRp以及 ：夕低 接關係，調整至適於消除直产偏VCM的相 比訊號心正偏移電二偏時例如當. 加電谷CN輕接至參考電壓VRp的個數，而減 11 201123738 n〇-zuW-w19-TW 31935twf.d〇c/n 二主M 的個數。相反地，若類比訊號S1的負偏移電 =^形越嚴重時，控制單* 5()2增加電容cN祕至參考 VRN的錄’喊少输至共模電壓的個數， 以使取樣保持電路300.可於操作放大器5⑽的輸出端 ΟΡ>,ν〇Ν，出類比訊號S1所包含的交流訊號幻。 ^ ^ ^ Ιί ί ^ C1N „ 士口。其中多個電容C1N麵接操作放 、的正輸人端’而多個電容C2N祕操作放大器 谓的的負輪入端。其中，各個電容⑽具有不同的電; 3，各，電容C2N亦林_電容值。® 6是依照本發明 電容⑽接不同電壓的示意圖。請參照圖6, 本貫細例雖以具有8個不同電容值的電容說明切換盘電容 cm麵接的電麈的操作情形，然不以此為限，本領域豆有 通::識=可參照本實施例’類推出不同電容個數的實 %方式。本貫_巾各個電容之電容值分別為c、⑺、 =4、⑽、⑽、C/32、C/64、c/128。其^個電容與參 考電壓或共模電壓VCM的連接狀態分別由多工器％ 控制。而控制單元502為依據—控制碼控制各個多。工哭504 的5出電壓’以決定各個電容的連接狀態。圖7為二圖 6實施例之控制碼的示意圖。請參照圖7，控制碼包括一同 位位元(parity b_ 8個位元，其中同位位元外的8個位元 分別蚊® 6實施财各個電容的連接狀態 值為〇時’控制單元逝控制多工器綱於輪 ^ 考電麼，以使電容可減至參考電壓，而當位元值為二時， 201123738 nw-00l9-TW 31935fwfd〇c/n . 電谷亦可透過多工器504搞接至共模電麗vcm。 由於取樣保持電路300具有參考電壓VRp以及 ‘ ^ VRN兩财考錢，因此f制錄元來決定電^ ^接轉?電壓、VRP或VRN。例如可設定當同位位元 '，·、且决定電容連接狀態之位元值為J時 參_VRp，以使電 參考電f術；若蚊電容連接狀態之位元值若為4 _ 制單元5〇2控制多工器504輸出共模電壓VCM，以倍 電，柄接至參共模電壓VCM。而當同位位元為q，而決= 連料1時，㈣絲脸共模電墨 定電容連接狀態之位元值為㈣，則電 ==tVRN。因此’控制本實施例中各個電容的執Ϊ 狀㈣要9個位凡，藉由控制各個電容與參考電壓或 :^^^連接狀態，即可決^於消除該直流偏移電 •料，由於本實施例所揭露之各㈣容的電容值 同，使用者可依據實際情形的需求調整各個電容的輕接 =、’以他接絲考電壓VRp或VRN的電料致於過大 :，小’使取樣保持電路3⑻可利用最少的電容達成消除 j比錢所包含的直流偏移電壓的目的，進而提昇取樣保 持電路300的操作頻率。 ’、 舉例來說，當類比訊號S1的正偏移電壓很大時，可 使ΓΓ立元之值為1，而其它決定電容cin連接狀態的位 兀：.、1 ’以使控制單元5〇2各個控制多工器5〇4皆輪出 13 201123738When the sample hold circuit 300 is in the sampling state, the switches SW1 and SW2 are turned on, and the switches SW4 and SW5 are turned off. Therefore, the capacitor Cl C2 can receive the waveform signal and the ground signal VG through the switches SW1 and SW2. In addition, the open M SW3 is also turned on at this time, so that the second end of the capacitor = C2 is short-circuited, and the waveform signal and the grounding signal ^ VG, the charge supplied will be stored in the capacitors Cl, C2. When the sample-and-hold circuit is in the hold state, the switch is torn, =, SB is off, and the capacitors α and Q are in parallel, respectively, respectively, between the two ends of the core of the capacitor C1, thereby making the capacitance Ο, C2 The sampling state stores:::breaking transfer' with multiple capacitors CN and capacitors to store the redistribution of charge. At this time, the DC offset of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ When the heart is positively biased, for example, when the power-up valley CN is connected to the reference voltage VRp, the number of the two main Ms is reduced by 11 201123738 n〇-zuW-w19-TW 31935twf.d〇c/n . Conversely, if the negative offset of the analog signal S1 is more serious, the control unit *5()2 increases the capacitance cN to the reference VRN's recording, and the number of common mode voltages is reduced to make the sampling. The holding circuit 300 can be operated at the output of the amplifier 5 (10) ΟΡ >, ν 〇Ν, the analog signal contained in the analog signal S1 is illusory. ^ ^ ^ Ιί ί ^ C1N „ 士口. Among them, a plurality of capacitors C1N are connected to the positive input terminal of the operation, and a plurality of capacitors C2N are operated by the negative wheel input terminal. Among them, each capacitor (10) has a different 3, each, capacitor C2N is also _ capacitance value. о 6 is a schematic diagram of the capacitor (10) connected to different voltages according to the present invention. Please refer to Figure 6, the present example is switched with a capacitance description with 8 different capacitance values. The operating condition of the electric capacitor with the surface of the disk capacitor is not limited to this. In this field, there is a pass::== Refer to the 'class of the present embodiment' to introduce the actual number of different capacitors. The capacitance values of the capacitors are c, (7), =4, (10), (10), C/32, C/64, c/128. The connection state of the capacitor and the reference voltage or the common mode voltage VCM is respectively multiplexed by the multiplexer. Control unit 502 controls each of the multiple output voltages of the worker cry 504 to determine the connection state of each capacitor according to the control code. Fig. 7 is a schematic diagram of the control code of the embodiment of Fig. 6. Referring to Fig. 7, The control code includes a parity bit (parity b_ 8 bits, of which 8 bits outside the parity bit) When the connection state value of each capacitor is 〇, the control unit lapses to control the multiplexer to control the voltage, so that the capacitance can be reduced to the reference voltage, and when the bit value is two, 201123738 Nw-00l9-TW 31935fwfd〇c/n. The electric valley can also be connected to the common mode electric vcm through the multiplexer 504. Since the sample and hold circuit 300 has the reference voltage VRp and the '^VRN two money test, the f system The recording element determines the voltage, VRP or VRN. For example, it can be set to _VRp when the parity bit ', ·, and the bit value of the capacitor connection state is J, so that the electrical reference is f If the bit value of the mosquito capacitor connection state is 4 _ unit 5 〇 2 control multiplexer 504 outputs the common mode voltage VCM, to double the stalk to the reference common mode voltage VCM, and when the parity bit is q , and == When the material is connected, the bit value of the (four) silk-face common mode electro-optic fixed capacitor connection state is (4), then the electric power == tVRN. Therefore, the control of each capacitor in this embodiment (four) is required to be 9 By controlling the connection state of each capacitor and the reference voltage or :^^^, it is possible to eliminate the DC offset electric material, because The capacitance values of the respective (four) capacitors disclosed in the embodiments are the same, and the user can adjust the light connection of each capacitor according to the actual situation, and the electric material of the voltage of the VRp or the VRN is too large: The sample-and-hold circuit 3 (8) can achieve the purpose of eliminating the DC offset voltage included in the j-weight with a minimum of capacitance, thereby increasing the operating frequency of the sample-and-hold circuit 300. ', for example, when the analog signal S1 has a positive offset voltage When large, the value of the ΓΓ立元 can be set to 1, and the other bits that determine the connection state of the capacitor cin are: ., 1 ' so that the control units 5 〇 2 each control multiplexer 5 〇 4 are all turned out 13 201123738
Hb-2UUy-uul9-TW 31935twf.doc/n t電Ur類比進了各個電容_皆_至參考電壓 的正偏移電：不大::唬S1的正偏移電壓。若類比訊號S1 ':.=!=二使部分決定電容⑽連接狀態的 壓VCM。 ^ C1N耦接至共模電 類似地’若類比訊號S1的負偏移電壓很 同位位元之值為〇 ’而並它決定 ^大時’可使 =1= 2C1N皆轉接至參考電壓·，以消 壓不大i ll移電壓。若類比訊號幻的負偏移電 0而二分決定電容C1N連接狀態的位元值： 八他的位元值為i，以使部份 、、、 考電壓娜，而其他的^en^clN_至參 :他的電A⑽轉接至共模電壓VCM。 今cm相同，在此不再贅述。 乃八，、免 小，===發明可依伽tb訊號的偏移電壓量次 調整用於#除偏移電壓量的電容個數，以次 "5虎的直流偏移電壓，邗裎古雔士金 ’、貞比吼 龄太^ 數位職㈣操作速度。 样明H已以實施例揭露如上，然其並非用以限交 =純所屬技術領域中具有通常知識者，在不脫2 ^明之精，範圍内，當可作些許之更動與潤飾，2 ;明之保護範®當視伽之申請專利範_界定者為準。 14 201123738Hb-2UUy-uul9-TW 31935twf.doc/n t Electric Ur analogy into each capacitor _ all _ to the reference voltage of the positive offset: not large:: 唬 S1 positive offset voltage. If the analog signal S1 ':.=!= two, the part determines the voltage VCM of the connection state of the capacitor (10). ^ C1N is coupled to the common mode power similarly. 'If the negative offset voltage of analog signal S1 is very similar to the value of 同' and it determines that ^ is large, then =1 = 2C1N is transferred to the reference voltage. , to suppress the voltage is not large i ll shift voltage. If the analog signal is negatively offset by 0, the binary value determines the bit value of the connection state of the capacitor C1N: eight of its bit values are i, so that the part, , and the test voltage, and the other ^en^clN_ To the reference: his electric A (10) is transferred to the common mode voltage VCM. The same cm is now, and will not be described here. Is eight, free from small, === invention can be adjusted according to the offset voltage of the gamma tb signal for the number of capacitors divided by # offset voltage, in order to "5 tiger's DC offset voltage, 邗裎古The gentleman's gold, the 贞 吼 吼 too ^ number of positions (four) operating speed. The sample H has been disclosed as above in the embodiment, but it is not used to limit the number of people who have the usual knowledge in the technical field, and can make some changes and refinements in the range of 2, Ming, 2; Ming's Protection Fan® is subject to the definition of the patent application. 14 201123738
-0019-TW 31935twf.doc/n 【圖式簡單說明】 圖。 圖。圖i是雜取樣_電轉簡狀鱗的等效電路 圖2是依照圖1中多個電容:似_不同電壓的示意 圖 圖3是依照本發明一實施例之取樣保持 電路的示意 程圖 圖4是依照本發明—實施例之偏移電壓消除方 法的流 圖 圖5是依照本發明另—實施例之取樣保持電路的牙 示意 同電=:本發明圖5實施例之多個電―不 圖 圖7為依照圖6實施例之控制碼的示音 【主要元件符號說明】 100、300 :取樣保持電路 102 ' 508 =操作放大器 104 ' 308 :電壓產生器 302 :取樣電路單元 304 :控制模組 306 :保持電路單元 502 :控制單元 504 :多工器 15 201123738 iis-/uuy-uul9-TW 31935twf.doc/n 51 :類比訊號 52 :類比訊號所包含的交流訊號 VW:波形訊號 VG :接地訊號?.. " ·· VCM :共模電壓 VRP、VRN :參考電壓 SW1〜SW5 :開關 C1〜C4、CN、C1N、C2N、C1A〜C4A :電容 PH1 :第一訊號 PH2 :第二訊號 VOP、VON :輸出端 S402〜S408:消除直流偏移電壓的步驟 16-0019-TW 31935twf.doc/n [Simple diagram of the diagram] Figure. Figure. Figure i is an equivalent circuit of a hetero-sampling_electrical-simplified scale. Figure 2 is a schematic diagram of a plurality of capacitors according to Figure 1: different voltages. Figure 3 is a schematic diagram of a sample-and-hold circuit in accordance with an embodiment of the present invention. FIG. 5 is a flow diagram of an offset voltage canceling method according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a tooth of a sample and hold circuit according to another embodiment of the present invention. 7 is the sound of the control code according to the embodiment of FIG. 6 [Main component symbol description] 100, 300: sample and hold circuit 102 ' 508 = operational amplifier 104 ' 308 : voltage generator 302 : sampling circuit unit 304 : control module 306 : Holding circuit unit 502 : Control unit 504 : multiplexer 15 201123738 iis-/uuy-uul9-TW 31935twf.doc/n 51 : Analog signal 52 : AC signal included in the analog signal VW: Waveform signal VG : Ground signal? .. " ·· VCM: Common mode voltage VRP, VRN: Reference voltage SW1~SW5: Switches C1~C4, CN, C1N, C2N, C1A~C4A: Capacitor PH1: First signal PH2: Second signal VOP, VON : Output terminals S402~S408: steps to eliminate DC offset voltage 16