TW201123522A - Semiconductor wafers and semiconductor devices and methods of making semiconductor wafers and devices - Google Patents

Abstract

Semiconductor wafers, semiconductor devices, and methods of making semiconductor wafers and devices are provided. Embodiments of the present invention are especially suitable for use with substrate substitution applications, such in the case of fabricating vertical LED. One embodiment of the present invention includes a method of making a semiconductor device, the method comprising providing a substrate; forming a plurality of polishing stops on the substrate, each of the plurality of polishing stops including ceramic material; growing one or more buffer layers on the substrate; and growing one or more epitaxial layers on the one or more buffer layers. Additionally, the steps of applying one or more metal layers to the one or more epitaxial layers, affixing a second substrate to the one or more metal layers and removing the base substrate using a mechanical thinning process may be performed.

Description

201123522 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor wafers and semiconductor devices, and more particularly to a method of fabricating semiconductor wafers and semiconductor devices. This application is a continuation-in-part of U.S. Patent Application Serial No. 12/134,682, filed on Jun. 2, 2008, the disclosure of which is hereby incorporated by reference. [Prior Art] A semiconductor wafer fabrication system for semiconductor device fabrication is a well-developed technical field. There are many different methods of fabricating semiconductor wafers, and there are many known methods of fabricating semiconductor devices from prefabricated wafers. Semi-physical devices are now ubiquitous in modern technology devices and equipment. Although many wafers and semiconductor devices are built on a "spray substrate" or the like, some devices are preferably constructed on a sapphire substrate, such as a gallium nitride (GaN) based vertical light emitting diode (LED). . In some known processes, the sapphire substrate is removed using a laser lift-off (LL0) process to expose various n-type layers for subsequent etching and removal, such that an n-type electrode can be contacted with lightly doped A hetero-n-type GaN layer. However, the manufacture of GaN-based vertical LEDs and other semiconductor devices has been

Known methods have limitations because the LLO process can be inadequate, damaging, and inefficient in manufacturing reliable, efficient LEDs. In addition, due to various

The similar residual selectivity of the GaN layer makes it difficult to distinguish the interface between the different layers. Therefore, there is a need for a method of fabricating a semiconductor device that addresses the shortcomings of known methods. 145592.doc 201123522 SUMMARY OF THE INVENTION In accordance with an embodiment of the present invention, a semiconductor wafer is disclosed. The semiconductor includes: a substrate; a plurality of ceramic polishing stops on the substrate; one or more buffer layers grown on the substrate; and one or more epitaxial layers on the one or more buffer layers. According to another embodiment of the present invention, a light emitting diode is disclosed. The light emitting diode comprises: a substrate; a plurality of semiconductor layers grown on the substrate, wherein the plurality of semiconductor layers comprise an active layer and a plurality of ceramic polishing stops; and applied to the plurality of semiconductor layers One or more electrodes of one or more. According to another embodiment of the present invention, a method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device includes: providing a substrate; forming a plurality of ceramic polishing stops on the substrate; growing one or more buffer layers on the substrate; and growing on the one or more buffer layers One or more insect layers. Other embodiments of the invention will be apparent from the description of the appended claims. It will be appreciated that the invention may be embodied in other and different embodiments and various modifications may be made without departing from the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, reference is made to the accompanying drawings, The structural and other K5592.doc 201123522 changes were made under the conditions of the target river. Furthermore, the various embodiments and aspects from each of the various embodiments can be used in any suitable combination. Therefore, the drawings and detailed description are to be regarded as illustrative rather In general, the present invention relates to semiconductor wafers, semiconductor devices, and methods of making iiMU® and devices. Embodiments of the present invention are suitable for use in conjunction with a substrate in which the application of a semiconductor wafer or a semiconductor device facilitates the application of a new second substrate to the substrate. Figure (1) is generally a method of fabricating a semiconductor wafer. Figures 7 to 13 are generally related to the use of reference drawings! A method of fabricating a semiconductor device by the semiconductor wafer described in 6. Figures UA through 22C are generally related to a second embodiment of a semiconductor wafer and a method of fabricating a semiconductor wafer and semiconductor device. This second embodiment includes a light enhancement layer that can be used, for example, to reduce dislocations, reduce stacking errors during epitaxial lateral overgrowth, and achieve improved internal quantum efficiency. In an embodiment of the invention, the polishing stop comprises a ceramic material and the polishing stops are useful as a light enhancing layer. The embodiments shown and described with respect to the various figures can be used in the fabrication of LEDs, and in particular in the fabrication of vertical LEDs based on GaN. However, it will be appreciated that the methods illustrated are not limited to any particular engineering application and that any suitable semiconductor device can be fabricated in accordance with embodiments of the present invention, such as LEDs, laser diodes, transistors, and other power devices, freestanding semiconductor materials. Growth and production and other suitable applications. In the fabrication of GaN-based LEDs, in particular, removing the base sapphire substrate and replacing the base sapphire substrate with a new substrate has the following advantages: for example, improved thermal management, passing the surface pattern on the newly exposed surface 145592. Doc 201123522 Physicochemically achieved enhanced uniformity of light extraction and current distribution. In accordance with an embodiment of the present invention, in general, a mechanical thinning method (eg, grinding, grinding, polishing, and/or polishing) is used in the fabrication of semiconductor devices (eg, fabrication of LEDs). Chemical mechanical polishing) to perform removal of the sapphire substrate. In accordance with embodiments of the present invention, a polishing stop is provided during the wafer growth or wafer fabrication stage, thereby providing higher yield and improved device performance. The prefix "u_" used throughout the description indicates undoped or lightly doped, "P-" indicates P-type or positive, and "n_" indicates n-type or negative. Referring now to the drawings, Figure 1 is a cross-sectional view showing the formation of a display polishing stop for a semiconductor wafer in accordance with one embodiment of the present invention. Provide a substrate 1 〇〇. A polishing stopper 丨〇2 is formed on the substrate. The polishing stops can be formed using any suitable method. According to an exemplary method known as a subtractive method, a layer of hard material is applied to the entire surface of the substrate. Then, a pattern is formed in the hard material layer, thereby removing unnecessary portions of the hard material layer and leaving only the desired polishing stoppers 1〇2. According to another exemplary method known as the addition method, a mask pattern is formed across the surface of the substrate 1 to leave holes or grooves or other openings of a desired shape. A hard material is then deposited across the substrate 100 and the hard material is deposited into the openings. Then, the mask pattern is removed to leave a polishing stopper 1〇2 along the surface of the substrate 100. The application and removal of the mask can be performed using a known photoresist process. According to one embodiment, the polishing stopper ι 2 is formed on the substrate 1A. However, according to another embodiment, the polish stop 1 2 is formed on other layers of the semiconductor wafer. 145592.doc 201123522 An exemplary substrate is formed from sapphire, which is well suited for vertical LED fabrication processes. Embodiments of the invention may be particularly suitable for use with a type, non-ruthenium material. In a bismuth-V material, the epitaxial growth process can be important in the construction and operation of devices that are later formed on a semiconductor wafer. However, the application of the invention is not necessarily limited to such materials, and any other suitable substrate material may be used in accordance with embodiments of the present invention. The hard material is any suitable hard material. In an exemplary embodiment, the hard material is the hardest of all materials used in a wafer or device. The hard material may be a diamond film or a diamond-like carbon (1) 1 ^ (:) film. Other suitable hard materials for use as polishing stop 102 can be, for example, diamond, diamond-like carbon (DLC), titanium nitride (TiNx), titanium tungsten (TiWx) alloys, transition metal nitrides, or other suitable materials. The size of the polishing stop can be any width and height required for the particular application of the wafer being fabricated. Moreover, the term "hard" used to describe the polishing stop 102 is not intended to be limited to a given example or to any particular hardness or softness level, but may be any material suitable for accomplishing any of the methods set forth. 2 is a cross-sectional view showing the growth of a display layer of a semiconductor wafer according to an embodiment of the present invention. After the hard material is applied to the substrate 100 in the form of a polishing stopper 1〇2, on the substrate 1〇〇 One or more epitaxial layers 104, 106 are grown thereon. A buffer layer 1 〇 4, such as a u GaN layer, is grown on the substrate 100 in the illustrated embodiment shown in Figure 2. Although only one epitaxial layer is shown. 106 is grown on the buffer layer 1 〇 4, but this layer is intended to represent any suitable semiconductor material layer that can be grown according to the number of applications - similarly, although only one buffer layer 1 〇 4 is shown, this layer Imagine Table 145592.doc 201123522 shows one or more buffer layers as required. An exemplary configuration for epitaxial growth (which can be used to produce GaN LEDs) contains one of the sapphire substrates grown on the sapphire substrate. Miscellaneous or light The doped u_Gais^ is followed by one or more highly doped n•type GaN (n_GaN) layers, an active layer with multiple quantum well (MQW) structures, and a piGaN (p_GaNw. However, as illustrated The illustrated examples are not intended to limit the invention to any particular number or order of different epitaxial layers. In general, it may be difficult to know... (the thickness of the scratch layer, and it is also difficult to clearly know u-GaN and the remaining layers ( For example, the interface or junction between the n_type layers. Therefore, the ability to do this in the known fabrication method is difficult to be 'costly and/or impossible. This is the implementation of the present invention. The example also provides for the explicit removal of the u-GaN layer, & and knows where the sapphire substrate removal should be stopped, to the extent required. Figure 3 is a semiconductor wafer in accordance with one embodiment of the present invention. A cross-sectional view showing the formation of the optical stop on an epitaxial layer. In the embodiment illustrated in FIG. 3 - i, one or more first buffer layers 1 〇 4 are grown on the substrate 1 〇〇 Then, in the first buffer layer 1〇4, the j-shaped polishing stopper 102 is formed. Another phantom buffer layer 105 is grown on the light stop 1 〇 2. Then, one or more worm layers 1 〇 6 may be grown on the second buffer layer 105. As illustrated with reference to Figure 2, although Only one ^1〇6 is grown on the second buffer layer 1〇5, but this layer is intended to represent any suitable number of layers of semiconductor material that can be grown according to specific shoulder requirements. Figure 4 is implemented in accordance with one embodiment of the present invention. A cross-sectional view showing the formation of a display structure of a semiconductor wafer in an epitaxial layer. The exemplary embodiment illustrated in FIG. 4 is 145592.doc 201123522. The exemplary embodiment is similar to FIG. 2 and has a substrate 1 A polishing stop 102 applied to the substrate 100, one or more buffer layers 1 〇 4 and one or more epitaxial layers 1 生长 6 grown on the one or more buffer layers 104. Light altering material 108 is added to one or more buffer layers 1〇4. In the case of the lED, the light altering material 108 can be used to enhance the light scattering light scattering element. For example, the photonic crystal structure can be added by etching or by adding a material such as hafnium oxide (SiOJ or tantalum nitride (SiN)). The photonic structure can also be a vacuum or a material. The material is not included in the predetermined position within the layer. Figure 5 is a cross-sectional view showing the formation of a polishing stop in combination with the display of a semiconductor wafer and a stop layer in accordance with an embodiment of the present invention. An exemplary embodiment is similar to FIG. 2, having a substrate 100, a polishing stop 丨〇2 applied to the substrate 1 'one or more buffer layers 104, 105, and grown in one or more buffer layers. One or more smectic layers 106 on 〇4, 1 〇5. In addition, an etch stop layer 103 is grown in or between one or more buffer layers 1 〇 4. The etch stop layer 1 〇 3 is etched later. This may be advantageous during the process. In one embodiment, a highly selective wet money engraving will be used. However, dry etching and other suitable surname methods known to those skilled in the art may also be used. One or more stop layers may be used. After removing the substrate 100 For example, the etching process may terminate at the stop layer 103. The stop layer may also function as a leakage reduction layer, such as when a wafer is later fabricated using a wafer, etc. According to one embodiment, the stop layer 1〇3 is an AlInGaN layer having one of A1JnyGa(1_x_y)N properties. In one embodiment, X is less than or equal to about 〇35. 145592.doc 201123522 In another embodiment, x is less than or equal to about 0.4. In another embodiment, X may be in the range of 0.2 to 〇 5. In one embodiment, y is less than or equal to about 0.1. Another implementation, y is less than or equal to about 2. 2 or in 〇 〇5 to 0.25. However, other suitable values as well as other ranges of X and y values may be used. According to another embodiment, the stop layer ι 3 may have

One of the properties of the AlxGh-yN layer is a highly doped layer of α1~ν. One possible thickness of the AiGaN layer may be less than 0, 2 μππβ. In another embodiment, the thickness of the aig layer may be equal to about 0.2 μm. In an embodiment, the thickness of the layer should be

Thin enough for η doping into the Α1Ν layer. If a thicker 2AixGa(ix)N layer is used as the stop layer, the molar fraction should be less than that of the group 35 to more easily dope the Si into the AlGaN layer. The stop layer provides high (four) selectivity. - A high-selective method uses photoelectrochemicals) wet (4), which is a high-bandgap phase. The PEC etching is an electro-optical effect on the electron hole, which enhances the oxidation and reduction reactions in an electrochemical reaction. According to an embodiment of the present invention, the stop layer 103 may also include an -AiN/GaN superlattice structure. The superlattice stop layer includes a GaN layer and an -A1N layer, which together form a _ ΑΐΝ / (^ Ν superlattice (~ 30AV30A.) Stop layer. The superlattice structure is made up of adjacent MM and

A GaN layer is formed. The superlattice structure can include any desired number of layers and GaN pairs. Figure 6 is a cross-sectional view showing the formation of a polishing stop layer for a semiconductor day and day circle in accordance with an embodiment of the present invention. The exemplary embodiment illustrated in Figure 6 is similar to Figure 2' which has a substrate just applied to the substrate ι 105 and grown on a polishing stop 102, one or more buffer layers 1 〇 4 145592. Doc • II • One or more epitaxial layers 1〇6 on 201123522 or more buffer layers 104,105. Further, a polishing stop layer 110 is added to each of the polishing stoppers 102. The polish stop layer 110 can reduce stress or lattice mismatch between the polish stop 102 and the buffer layer ι4. The polish stop layer 110 can also be used for the reduction of dislocations in the lateral growth of the stray crystal. According to one embodiment, each of the polishing stops 102 is fabricated from a first material 'and each of the polishing stop layers is made from a second material' providing a difference between the two materials. . According to another embodiment, the polishing stop layer may completely surround and cover the polishing stop such that any portion of the polishing stop does not contact the envelope adjacent to the polishing stop 1〇2. The semiconductor wafers described with reference to Figures 1 through 6 with reference to Figures 7 through 13 can be further used to fabricate semiconductor devices. Figure 7 is a cross-sectional view showing the formation of a polishing stop member in accordance with one embodiment of the present invention. The exemplary embodiment illustrated in Figure 7 includes the components shown in Figure 2 in addition to the other layers. The semiconductor device 150 includes a substrate 2, a polishing stop 202 applied to the substrate 2, one or more buffer layers grown on the substrate 2, and one grown on the one or more buffer layers 204. Or a plurality of epitaxial layers 2〇6. Additionally, additional layers may be added to one or more epitaxial layers 2〇6 during a fabrication of the semiconductor device using a build-up or lamination process or any other suitable fabrication process. In the illustrated embodiment, semiconductor device 15A includes one or more metal layers 220, 222. The one or more metal layers 22, 222 may be any of the materials required for the application, such as ohmic contacts, reflections 145592.doc 201123522 mirrors, plated seed layers, bonding materials, stress buffer layers, or other metals Floor. Figure 8 is a cross-sectional view showing the formation of a built-in contact of a semiconductor device in accordance with an embodiment of the present invention. The exemplary embodiment illustrated in FIG. 8 is similar to the exemplary embodiment shown in FIG. 7. The semiconductor device i 5 has a substrate 200' applied to the substrate 1 抛光 polishing stop 2 生长 2, growth One or more buffer layers 2〇4 on the substrate, one or more conductive layers 2〇5 grown on one or more buffer layers 204, one or more grown on one or more conductive layers 205 One epitaxial layer 2〇6 and one or more metal layers 22〇, 222 added to one or more epitaxial layers 206. The semiconductor device 15 further includes a built-in n•type contact 224 extending to one of the one or more conductive layers 2〇5. The n-type contact 224 may be surrounded by an insulating material 226 to prevent or reduce adhesion to other semiconductor device layers. contact. Figure 9 is a cross-sectional view showing the formation of a new substrate of a semiconductor device in accordance with an embodiment of the present invention. The exemplary embodiment illustrated in FIG. 9 is similar to the exemplary embodiment shown in FIG. 7. The semiconductor device has a substrate 200, a polishing stop applied to the substrate 2, and is grown on One or more buffer layers 2〇4 on the substrate 200, one or more epitaxial layers 2〇6 grown on one or more buffer layers 204, and one or more added to one or more epitaxial layers 206 A plurality of metal layers 22, 222. The semiconductor device 15 further includes a first substrate 230 bonded or plated to one or more metal layers 22, 222. For example, the second substrate can be formed of any suitable material, such as copper or other materials suitable for use as a substrate for a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a patterned plating layer of a semiconductor device according to an embodiment of the present invention, 145592.doc -13 - 201123522. The exemplary embodiment illustrated in FIG. 1 is similar to the exemplary embodiment shown in FIG. 9. The semiconductor device 150 has a substrate 200, a polishing stop 202 applied to the substrate 200, and one grown on the substrate 200. Or a plurality of buffer layers 204, one or more roofing layers 206 grown on one or more buffer layers 204, and one or more metal layers 220, 222 added to one or more of the seed layers 2〇6 And bonding or plating to one of the one or more metal layers 220, 222, the second substrate 230. In the illustrated embodiment, the patterned plating layer 232 of the second substrate 230 facilitates slicing and stress relief when the semiconductor device 150 is separated into individual individual components. In one embodiment, the patterned plating layer 232 is formed using a photoresist process. Figure 11 is a cross-sectional view showing the removal of a display substrate of a semiconductor device in accordance with an embodiment of the present invention. The exemplary embodiment illustrated in FIG. 1A is similar to the exemplary embodiment illustrated in FIG. 9 in that the semiconductor device 15 has a polishing stop formed in one or more buffer layers 2〇4 applied to the substrate 200. Piece 202 (Figs. 9 and 1), one or more epitaxial layers 206 grown on one or more buffer layers 2〇4, added to one or more of one or more epitaxial layers 2〇6 The metal layers 220, 222 and the first substrate 230 bonded or plated to the one or more metal layers 22, 222. When compared with Figures 9 and 1B, the substrate 2 has been removed in the only example illustrated in Figure η. In one embodiment, the substrate 200 is removed by a mechanical thinning process which generally involves milling, grinding, polishing or chemical mechanical polishing of the surface as a private part. Other removal methods are available. However, in conjunction with the practice of the present invention, the use of a mechanical thinning method provides advantages in speed and accuracy. As illustrated in Fig. 11, the removal by the mechanical thinning process stops at the end of the polishing stop 202 as shown in Fig. 11 145592.doc -14- 201123522. Since the polishing stop #202 is formed of a hard material, mechanical thinning can be stopped explicitly and precisely at the position of the polishing stops, leaving the remaining layer. Furthermore, the flatness of the remaining surface can be controlled within the required limits by using the polishing stop 2〇2'. Figure 12 is a cross-sectional view showing a surface change of an exemplary semiconductor device of a semiconductor device in accordance with an embodiment of the present invention. The exemplary embodiment illustrated in FIG. 12 is similar to the exemplary embodiment illustrated in FIG. 12, with semiconductor device 150 having a polishing stop formed in one or more buffer layers 204 applied to substrate 2 2〇2 (FIGS. 9 and 1), one or more epitaxial layers 2〇6 grown on one or more buffer layers 204, one or more metal layers added to one or more epitaxial layers 206 22〇, 222 and a second substrate 23〇 bonded or plated to one or more metal layers 220, 222. At least a portion of the buffer layer 204 has been removed during the one (four) process thereby exposing at least a portion of the polishing stop 202. A plurality of different LED features have been displayed on the semiconductor device for illustrative purposes. For example, the surface texture 240, the passivation 242 and the ohmic contact or bond pad 244, a microlens 246, and a transparent contact layer (10) are shown in '(d). Additionally, a rounded plating layer 232 is formed in the second substrate 230 and the one or more metal layers 22, 222 to promote release when the semiconductor skirt 150 is separated into individual individual components. Alpha knives Figure 13 is a cross-sectional view showing the formation of a built-in contact for a semiconductor attack in accordance with an embodiment of the present invention. The exemplary embodiment illustrated in Figure 13 is similar to the exemplary embodiment illustrated in Figure 12, which further includes 145592.doc • 15-201123522 extending to one of the one or more conductive layers 205 built in n_ Type Contact 224 The β n_ type contact 224 may be surrounded by an insulating material 226 to prevent or reduce contact with other semiconductor layers. Referring now to Figures 14A through 21, a semiconductor wafer and a method of fabricating a semiconductor are shown and illustrated. Unless otherwise stated, embodiments of semiconductor wafers that are not shown in Figures MA through 21 and methods of fabricating the same are similar to the embodiments and methods described with reference to Figures i through 3. Figure 14A is a cross-sectional view showing the formation of a polishing stop of a semiconductor wafer in accordance with an embodiment of the present invention. A substrate 14 is provided. A polishing stop 1402 is formed on the substrate. The polishing stop 1402 can be formed using any suitable method. A layer of hard material is applied to the entire surface of the substrate 1400 in accordance with an exemplary method known as a subtractive method. A pattern is then formed in the layer of hard material to remove unwanted portions of the layer of hard material and leave only the desired polish stop 14〇2. For example, reactive ion etching (RIE) can be used to form a pattern of hard materials. The polishing stop can also be formed by chemical vapor deposition or physical vapor deposition. According to another conventional method known as the additive method, a mask pattern is formed across the surface of the substrate to leave holes or grooves or other openings of a desired shape. Then, a hard material is deposited across the substrate 14 in the form of a nanostructure or on the substrate 14A. In another embodiment, the H recess method can be used to completely penetrate the holes of the hard material and fill the holes with a semiconductor material. Thus, the semiconductor material can be joined by other semiconductor materials or on both sides of the hard material. According to one embodiment, the polishing stop member is formed on the base 145592.doc -16 - 201123522 plate 1400. However, according to another embodiment, a polish stop 1402 is formed on other layers of the semiconductor wafer. According to one embodiment, the polishing stops can be formed on a patterned substrate as shown and described in Figure 14B. An exemplary substrate is formed from sapphire, which is well suited for vertical LED fabrication processes. Embodiments of the invention may be particularly suitable for use with a type m-v, non-antimony material. In the Type III-V material, the epitaxial growth process can be important in the construction and operation of devices that are later formed on a semiconductor wafer. However, the application of the present invention is not necessarily limited to such materials, and any other suitable substrate material may be used in accordance with the embodiments of the present invention. The hard material used with reference to Figs. 14A to 22C contains a ceramic material or a ceramic-based material. In one embodiment, the ceramic is boron nitride or a material based on boron nitride. However, according to another embodiment, other ceramic materials such as TiSiN or ΤιΑΙΝ may be used. According to one embodiment, a transition metal nitride material can be used. According to one embodiment, the friction coefficient of the hard material is lower than the coefficient of friction of the original substrate and the semiconductor layer on the substrate. Any suitable form of boron nitride can be used, such as cubic boron nitride, ternary boron nitride, carbonized borax boron (CBN), yttrium ternary system, boron nitride (GeBN), fluoronitridation shed (BFN). ), boron oxynitride (BN〇), boron nitride fiber, boron nitride nanoweb, nitrided nanostructure (for example, including nanotubes, nanowires, nanocones, and nanohorns) Or a compound containing a nitrided butterfly. In one embodiment, the ceramic material is transparent to a light system emitted from an active layer formed in a semiconductor wafer according to an embodiment of the present invention, and the ceramic material has a lower than that of the ceramic material. One of the refractive indices of the refractive index of the semiconductor layer. As a result of the use of a hard material having a refractive index lower than the active area, the amount of light to be reflected can be reduced by 145592.doc 17 201123522. According to one embodiment, the ceramic material is grown in a high pressure environment or in a high temperature environment or in both high pressure and high temperatures. Forming ceramic materials (eg, nanotubes) can be performed using the following techniques: (4) arc discharge techniques, arcing electrodes (including boron) in an inert atmosphere or Ns or helium; (b) at a high temperature (eg , 1200. Underarm-inert atmosphere towel for laser ablation with nano-sized Ni&c. powder mixed nitride (BN) powder; (勹 substitution reaction, such as cnt, which is at high temperature (for example, 15 s) used under n2 - CNT template B2 〇 3 powder: into BN nano tube; (4) chemical vapor deposition precursor at one of the high temperature of > 1 generation (for example, 1 仏〇汨, 1仏仏) + catalyst (for example, or

NlB powder); or (e) using element B ball milling in a Μ% gas, followed by thermal annealing at a high temperature (eg, 10 ° C to 120 (TC) at 乂 or ^. The hard material polishing stop can be patterned or grown in any suitable pattern or shape. For example, each polishing stop can have a circular rectangle, a triangle, or a conical shape. Any pattern of knives can be placed on the semiconductor wafer, such as any suitable grid pattern. The size and spacing of the pattern of the polishing stop can be optimized for a particular application. According to one embodiment, the polishing The stop member may be composed of a stack of one of a plurality of layers, at least one of which comprises a boron nitride-based material. Soil, according to an exemplary embodiment, by dry etching (eg, hydrogen gas 145592.doc Etching RIE) under 201123522 to perform etching of hard materials (eg, boron nitride nano-cones or nano-pillars). This etching method involves physical etching by high-energy ion collision and by reactive hydrogen atoms/ Ion Learn to etch both. The reaction involved in Chemistry# can be N·(surface)+xH(g)4NHx(g); B(surface)+xH(g)—BHx(g). Use a metal etch Mask (for example,

Ti, A1 or Au) to induce preferential RIE. According to one embodiment, hard material patterning can be achieved by depositing and then stripping the mask over the patterned mask. However, the use of a suitable embedding material, such as a boron nitride-based material on a substrate, can not only improve the dislocation density and stacking errors in the epitaxial layer to achieve better internal quantum efficiency, but also assumes that the embedded material has a high hardness rating. The embedded material can also act as a polishing stop during substrate removal. In addition, by appropriately adjusting the boron nitride-based material, the intermediate refractive index (η~1.7 to 2.1) can also be helpful when compared with GaN (n~2.5) and air (n~1). For scattering and / or enhanced light extraction. The microcolumn structure in the Cory n-GaN layer is in the microcolumn. The light output power of the led sample at 350 mA is improved by 39% compared with the conventional 111 (^1^/(:11 LED light output power. This improvement is due to the scattering of emitted light at the surface of the microcolumn. The probability of increase is increased. A better light extraction efficiency can be achieved by further optimizing the micro-pillar pitch'. Figure (10) shows the formation of a non-polishing stop of a semiconductor wafer according to another embodiment of the present invention. A cross-sectional view. In the embodiment illustrated in Figure 14B, polishing stop 1402 is grown into substrate 1400 or grown below the surface of substrate 1400. During the growth process, holes or recesses are made 145592.doc -19 · 201123522 The material that is formed into the substrate 1400' and used to form the polishing stop 14〇2 is at least partially located in the holes or recesses. FIG. 14C shows a semiconductor wafer according to another embodiment of the present invention. A cross-sectional view of the formation of a polished 彳 stopper. According to one embodiment, each of the polishing stops 1402 is fabricated from a first material, and each of the polishing stops 1402 includes a second material. a conformal layer or cover 1403. The difference between the two materials provides an advantage. In the example illustrated in the figures, the polishing stop layer completely surrounds and covers the polishing stop so that no part of the polishing stop is in contact Adjacent to the encapsulation layer of the polishing stop just 2. However, the conformal layer may also cover a portion of the polishing stop 1402, such as the top of the polishing stop 14〇 2. For example, the conformal layer 14〇3 may include _ 2 or 8 chests or a plurality or layers of one or more of these materials'. In another embodiment, the conformal layer 14 0 3 provides the same as the polishing stop illustrated and described with reference to FIG. Figure 15 is a cross-sectional view showing the growth of a crystal layer of a semiconductor wafer in accordance with an embodiment of the present invention. Immediately after the hard material is applied to the substrate in the form of a polishing stop, the substrate is grown. One or more smectic layers, 1406. In the illustrated embodiment illustrated in Figure 15, a buffer layer is grown on the substrate ring, such as a -u_GaN layer or (10) cladding layer. a crystallized layer 14〇6 is grown in The layer is just above, but this layer is intended to represent any suitable layer of semiconductor material that can be grown according to the requirements of a particular application. An example configuration for the growth of insect crystals (which can be used to produce GaN LEDs) One of the sapphire substrates 14 145592.doc -20- 201123522 undoped or lightly doped u-GaN layer 1404, followed by one or more twisted doped n-type GaN (n a layer of -GaN), one of a plurality of quantum well (Mqw) structures, and a p-type GaN (p-GaN) layer. However, the illustrated examples are not intended to limit the invention to any particular number or order. Different worm layers. Figure 16 is a cross-sectional view showing the formation of a polishing stop of a semiconductor wafer on an epitaxial layer in accordance with one embodiment of the present invention. In the illustrated embodiment shown in Figure 6, one or more first buffer layers 1404 are grown on substrate 14A. Then, a polishing stopper 1402 is formed on one of the first buffer layers 14A4. Another one or more buffer layers 1405 may be grown on the polishing stop 14〇2. One or more epitaxial layers 1406 can then be grown on the second buffer layer 14A5. As similarly illustrated with reference to Figure 15, although only one layer 1406 is shown grown on the second buffer layer 14A5, this layer 14"6 is intended to represent any suitable number of layers of semiconductor material that can be grown according to the particular application requirements. . Figure 17 is a cross-sectional view showing the formation of a polishing stop in combination with the display of a semiconductor wafer and an etch stop layer 1403 in accordance with one embodiment of the present invention. The exemplary embodiment illustrated in Figure 17 is similar to Figure 5, having a substrate 1400, a polishing stop 1412 applied to the substrate 14, and one or more buffer layers 1404, 1405 and grown in one Or a plurality of buffers of one or more epitaxial layers 14〇6 on the 1414, 1405. Additionally, an etch stop layer 14〇3 is grown in or between one or more buffer layers 1404, 1405. The button stop layer 1403 can be advantageous during a later etching process. In one embodiment, a homogenous selective wet residue will be used, but dry (four) and other methods of consuming techniques known to those skilled in the art can be used. One or more stop layers may be used to remove subsequent processes after the substrate 1400. For example, the etching process can be terminated at stop layer 1403. The stop layer can also be used as a leak reduction layer, for example, when a wafer is used to fabricate a transistor or the like later. The semiconductor wafers now described with reference to Figs. 18 through 21' with reference to Figs. 14 through 17 can be further used to fabricate semiconductor devices. Figure 18 is a cross-sectional view showing the formation of a display device for a semiconductor device (4) according to an embodiment of the present invention. The exemplary embodiment illustrated in Figure 18 includes the components shown in Figure 2 in addition to the other layers. The semiconductor device 1850 includes a substrate 14 , a light holding stop 1402 applied to the substrate 14 , one or more buffer layers 1404 grown on the substrate 1400 , and grown on one or more buffer layers 14 4 . One or more epitaxial layers "Μ. Additionally, additional layers may be added to one or more epitaxial layers 1 406 during the fabrication of the semiconductor device using a build-up or lamination process or any other suitable fabrication process. In an embodiment, the semiconductor device 185 includes one or more metal layers 42 〇 丨 422. One or more metal layers, 1422 may be any of the materials required for a particular application, such as ohmic contacts, mirrors , a seeding layer, a bonding material, a stress buffer layer or other metal layer. One or more metal layers 1420, 1422 may be patterned and they need not be in full contact with each other. Figure 19 is an embodiment of the invention A cross-sectional view of a semiconductor device showing the formation of a new substrate. An exemplary yoke example illustrated in FIG. 19 is similar to the exemplary embodiment shown in FIG. 8, a semiconductor device 丨85〇 There is a substrate 1400, a polishing stop 1402 applied to the substrate 1400, a 145592.doc • 22· 201123522 one or more buffer layers 14〇4 on the substrate 1400, one grown on one or more buffer layers 1404 or A plurality of epitaxial layers 14A6 and one or more metal layers 142A, 1422 added to one or more epitaxial layers 1406. The semiconductor device 1850 further includes bonding or plating to one or more metal layers 1420, 1422 A second substrate 143. For example, the second substrate 143 can be formed of any suitable material, such as copper or other material suitable as a substrate for a semiconductor device. Figure 20 is an embodiment of the present invention - One of the cross-sectional views of the display substrate removal of the semiconductor device. The exemplary embodiment illustrated in FIG. 20 is similar to the exemplary embodiment shown in FIG. 19, and the semiconductor device 185 has one or more formed on the substrate 1400. One or more epitaxial layers 1406 grown in one or more buffer layers 14A4, added to one or more epitaxial layers 14 in a buffer layer 14A4 (Fig. 19) One of 〇6 Or a plurality of metal layers 1420, 1422 and a second substrate 143 接合 bonded or plated to one or more metal layers 1420, 1422. When compared to Figure 9, in the embodiment illustrated in Figure 2A The substrate 14 has been removed. In one embodiment, the substrate 14 is removed by a mechanical thinning process which generally involves milling, grinding, polishing the surface as part of the process Or chemical mechanical polishing. Other removal methods can be used. However, the use of a mechanical thinning method in conjunction with embodiments of the present invention provides increased speed, accuracy, and throughput advantages. As illustrated in Fig. 20, the removal by the mechanical thinning process is stopped at the end of the polishing stopper 14?. Since the polishing stop 1402 is formed of a hard material, mechanical thinning can be stopped explicitly and precisely at the position of the polishing stop, leaving the remaining layer. In addition, by using the polishing stop 1402, the flatness of the remaining surface can be controlled within the required limits. Figure 21 is a cross-sectional view showing a semiconductor device in accordance with an embodiment of the present invention. The exemplary embodiment illustrated in FIG. 21 is similar to the exemplary embodiment illustrated in FIG. 2A, with semiconductor device 1850 having a polishing stop 1402 formed in one or more buffer layers 1404 applied to substrate 1400 ( 19), one or more epitaxial layers 1406 grown on one or more buffer layers 14A4, one or more metal layers 1420, 1422 added to one or more of the seed layer 1406, and bonded or plated A second substrate 1430 overlying one or more metal layers 142, 1422. At least a portion of the buffer layer 1404 has been removed during a remainder of the process' thereby exposing at least a portion of the polishing stop 丨4〇2. Additionally, a non-conductive isolation layer 1432 is formed in the second substrate 1430 and the one or more metal layers 1420, 1422 to promote slicing and stress relief when the semiconductor device 1850 is separated into individual individual components. Figure 22A is a vertical led structure 2200 in accordance with an exemplary embodiment of the present invention. The vertical LED structure 2200 includes a replacement substrate 2202, a p-metal 2204, a p-GaN layer 2206, a multiple quantum well layer 2208, an n-GaN layer 2210, a polishing stop 2214, and an n-GaN layer 2210 or The n-GaN layer 2210 and one of the electrodes 2216 on the polishing stop 2214. Figure 22B is a vertical led structure 2300 in accordance with one embodiment of the present invention. In Figure 22B, the GaN buffer layer 2212 of the vertical LED structure 2300 has been etched such that the electrode 2216 can directly contact the n-GaN layer 2210 ^ leaving portions of the GaN buffer layer under the polish stop 2214 and the polish stop 2214. Similarly, any suitable layer 145592.doc -24-201123522 can be etched as required by a particular embodiment. Figure 22C is a vertical LED structure 2400 in accordance with one embodiment of the present invention. The vertical LED structure shown in Figure 22C is similar to the vertical LED structure shown in Figure 22B. However, in the vertical LED structure 2400 shown in Fig. 22C, the polishing stop 2214 near the electrode 2216 has also been removed when compared to Fig. 22B. Thus, the polishing stop 22丨4 can remain on the LED structure or be removed, depending on the requirements of the particular application. Figure 23 is a flip-chip LED structure in accordance with another exemplary embodiment of the present invention. The flip chip LED structure 2500 is configured as a flip chip LED comprising a sapphire substrate 23 〇 2, a __p_ metal layer 2322, a 卜

a GaN layer 2306, a multiple quantum well layer 2308, an n-GaN layer 2310, a GaN buffer layer 2312, a polishing stop layer 2314, and an 11_electrode 2324 formed on the n_GaIy^ 23 10 structure. 23〇〇 soldering to a submount 2326 ° In a conventional semiconductor wafer, when a mechanical thinning method is applied, if the plane to be polished is very large, the variation of the layer thickness may be too large for useful practical applications. . In accordance with an embodiment of the present invention, the polishing stop is included to effectively reduce the size of the plane such that the variation of the thickness of the towel is reduced, even if the overall size of the plane is large. (d) can be obtained by controlling the size of the polishing stop and/or the distance between them - an acceptable range of micronization. "The polishing stop is generally shown as a square or rectangle, = the polishing stop according to an embodiment of the invention may be tied to a shape, such as a line, a point, a circle, a triangle or a rectangle" and may be located in a flat position on the plane . 〇

145592.doc -25- 201123522 While the invention has been particularly shown and described with reference to the embodiments of the invention, it will be understood that Make a change. For example, although the semiconductor device illustrated in the embodiments of FIGS. 14A through 23 incorporates a polishing stop applied to the sapphire substrate, other embodiments of the semiconductor devices may be applied to the semiconductor device. - a polishing stop for the worm layer, as explained above with reference to Figures 3 and 16. Therefore, the above description is intended to provide an exemplary embodiment of the invention, and the scope of the invention is not limited by the specific examples provided. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing the formation of a polishing stop for a semiconductor day and day circle according to the present invention; FIG. 2 is a view showing a semiconductor wafer according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing the formation of a light stop of a semiconductor wafer on an epitaxial layer according to an embodiment of the present invention; FIG. 4 is an embodiment of the present invention. Example < _ A cross-sectional view showing the formation of a photonic structure in an epitaxial layer; FIG. 5 is a polishing stopper in combination with a display and an etch stop layer of a semiconductor wafer according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing the formation of a polishing stop layer of a semiconductor wafer according to an embodiment of the present invention; FIG. 7 is a display polishing stop of a semiconductor device according to an embodiment of the present invention; 1 is a cross-sectional view showing the formation of a built-in contact of a semiconductor device in accordance with an embodiment of the present invention; FIG. 9 is a BRIEF DESCRIPTION OF THE DRAWINGS FIG. 10 is a cross-sectional view showing the formation of a patterned substrate of a semiconductor device according to an embodiment of the present invention; FIG. 11 is a cross-sectional view showing a patterned plating layer of a semiconductor device according to an embodiment of the present invention; 1 is a cross-sectional view showing a display substrate removal of a semiconductor device according to an embodiment of the present invention; FIG. 12 is a cross-sectional view showing a surface change of an exemplary semiconductor device of a semiconductor device according to an embodiment of the present invention; 1A is a cross-sectional view showing the formation of a built-in contact of a semiconductor device; FIG. 14A is a cross-sectional view showing the formation of a display polishing stop of a semiconductor wafer according to an embodiment of the present invention; 1 is a cross-sectional view showing the formation of a polishing stop of a semiconductor wafer according to another embodiment of the present invention; and FIG. 14C is a cross-sectional view showing the formation of a polishing stop of a semiconductor wafer according to another embodiment of the present invention. Figure 15 is a cross-sectional view showing the growth of a display epitaxial layer of a semiconductor wafer in accordance with an embodiment of the present invention; 1 is a cross-sectional view showing the formation of a polishing stop of a semiconductor wafer on a silicon oxide layer; FIG. 1 is a display of a semiconductor wafer and an etch stop according to an embodiment of the present invention. A cross-sectional view showing the formation of a polishing stop of a layer combination; 145592.doc • 27-201123522 FIG. 1 is a cross-sectional view showing the formation of a polishing stop of a semiconductor device according to an embodiment of the present invention; FIG. 1 is a cross-sectional view showing the formation of a new substrate of a semiconductor device; FIG. 20 is a cross-sectional view showing a display substrate removal of a semiconductor device according to an embodiment of the present invention; 1 is a cross-sectional view showing a surface variation of an exemplary semiconductor device of a semiconductor device; FIG. 22A is a vertical LED structure according to an embodiment of the present invention; and FIG. 22B is a vertical LED structure according to an embodiment of the present invention. Figure 22C is a vertical LED structure in accordance with one embodiment of the present invention; and Figure 23 is a flip-chip [ED structure] in accordance with another embodiment of the present invention. [Main component symbol description] 100 substrate 102 polishing stopper 1 03 etching stop layer 104 worm layer/first buffer layer 105 second buffer layer 106 worm layer 108 light changing material 110 polishing stop layer 150 semiconductor device 200 substrate 145592 .doc •28· 201123522 202 204 205 206 220 222 224 226 230 232 240 242 244 246 248 1400 1402 1403 1404 1405 1406 1420 1422 1430 Polishing stop buffer layer Conductive layer worm layer metal layer metal layer built-in η-type touch Point Insulation Material Second Substrate Patterned Plating Surface Textured Passivation Bond Pad Microlens Transparent Contact Layer Substrate Polishing Stopper Conformal Layer/Cover Layer / Li Inscribed Stop Layer Insect Layer / First Buffer Layer / u-GaN Layer second buffer layer worm layer metal layer metal layer second substrate 145592.doc -29- 201123522 1432 non-conductive isolation layer 1850 semiconductor device 2200 vertical LED structure 2202 replacement substrate 2204 p-metal 2206 p-GaN layer 2208 multi-quantum well Layer 2210 n-GaN layer 2212 GaN buffer layer 2214 polishing stop 2216 electrode 2300 vertical LED structure 2302 sapphire substrate 2306 p-GaN layer 2308 Quantum well layer 2310 n-GaN layer 2312 GaN buffer layer 2314 2322 2324 η- polish stop layer electrode base 2400 2326 2500 vertical structure LED flip chip LED structure p- metal layer 145592.doc -30-

Claims (1)

201123522 VII. Patent application scope: 1_ A semiconductor wafer, comprising: a substrate; a plurality of light-stopping members on the substrate, (4) a stopper for encapsulating ceramic materials; 3 one or more grown on the substrate a buffer layer; and one or more epitaxial layers on the one or more buffer layers. 2. The semiconductor wafer of claim 1, wherein each of the plurality of polishing stops comprises a boron nitride based material. 3. The semiconductor wafer of the present invention, wherein the plurality of polishing stops, the plurality of polishing stops, and at least one of each of the plurality of (four) light stops comprises nitriding based Boron material. 4. The semiconductor wafer of claim 1, wherein each of the plurality of polishing stops is a multilayer polishing stop and at least one of the layers of the plurality of polishing stops comprises a transition metal Nitride material. 5. The semiconductor wafer of claim 1, wherein the plurality of polishing stops are formed using reactive ion residue (RIE). 6. The semiconductor wafer of claim 1, wherein the plurality of polishing stops are transparent to visible light. 7. The semiconductor wafer of claim 1, wherein one of the one or more epitaxial layers has an adjacent layer of a refractive index adjacent to the plurality of polishing stops, and wherein The mother of the plurality of polishing stops has a refractive index lower than a refractive index of the adjacent semiconductor layer. The semiconductor wafer of claim 1, wherein each of the polishing stops comprises a conformal layer applied to an associated polishing stop, and wherein the plurality of polishing stops are Each of the plurality of conformal layers comprises boron nitride and each of the plurality of conformal layers is fabricated from a semiconductor or dielectric material. 9. The semiconductor wafer of claim 6, wherein each of the conformal layers overlies at least one side of the associated polishing stop. 10. The semiconductor wafer of claim 1 wherein the plurality of polishing stops comprises a light enhancement layer. 11. A light emitting diode comprising: a substrate; a plurality of semiconductor layers grown on the germanium substrate, wherein the plurality of semiconductor layers comprise at least one active layer and a plurality of polishing stops, the plurality of polishing stops Each of them comprises a ceramic material; and one or more electrodes applied to one or more of the plurality of semiconductor layers. 12. The light emitting diode of claim 11, wherein the plurality of polishing stops comprise a boron nitride based material. The light-emitting diode of claim 11, wherein each of the plurality of polishing stops is a multilayer polishing stop and at least one of each of the plurality of polishing stops comprises nitrogen-based Boron material. 14. The light emitting diode of claim 11, wherein each of the plurality of polishing stops is a multilayer polishing stop and at least one of each of the plurality of polishing stops comprises a transition metal Nitride material. 15. The light-emitting diode of claim 11 wherein the one or more epitaxial layers of the 145592.doc 201123522 are the same as the hershes, the plurality of polishing stops of the adjacent layer, Each of the number of sanitary seals has a refractive index lower than the refractive index of the late neighboring layer. 16. The light-emitting diode of claim 11, wherein each of the polishing stops comprises a layer applied to the -_ joint stop, and wherein each of the plurality of polishing stops A boron nitride-based material is included and each of the plurality of conformal layers is fabricated from a semiconductor or dielectric material. 17. The light-emitting diode of claim η, wherein each of the polishing stops comprises a pattern on a surface of the substrate, and wherein the polishing stops are used for light extraction of light scattering elements . 18. A method of fabricating a semiconductor device, the method comprising: providing a substrate; forming a plurality of polishing stop horns on the substrate, each of the plurality of polishing stops comprising a ceramic material; on the substrate Growing one or more buffer layers; and growing one or more epitaxial layers on the one or more buffer layers. 19. The method of claim 18, wherein each of the plurality of ceramic polishing stops comprises a boron nitride based material. The method of claim 18, wherein the step of forming the plurality of ceramic polishing stops comprises growing one or more boron nitride structures on one of the one or more epitaxial layers. 21. The method of claim 18, wherein the step of forming the plurality of ceramic polishing stops comprises growing one or more boron nitride structures on the substrate. 22. The method of claim 21, further comprising etching the one or more boron nitride structures using reactive ion milling (RIE). 23. The method of claim 21, wherein the step of growing one or more boron nitride structures comprises forming a plurality of holes in the substrate and growing the one or more boron nitride structures in the holes in the substrate . 24. The method of claim 18, further comprising forming a conformal layer on each of the plurality of polishing stops, and wherein each of the plurality of polishing stops comprises boron nitride based The material and each of the plurality of conformal layers are fabricated from a semiconductor or dielectric material. 25. The method of claim 18, further comprising: attaching a second substrate to the one or more metal layers; and removing the substrate using a mechanical thinning process. 145592.doc