201121218 六、發明說明： 【發明所屬之技術領域】 本發明係關於-種交錯式無橋功率因數修正器及控制方法，特別是指 能提供-低損失、高功率密度之功率因數修正器及其㈣方法，可普遍應 用於各類電祕肖產品’制是體積受限需要高功轉雜歧中、高功 率輸出的應用。 【先前技術】 傳統的交流對直流電源轉換器（ACtoDCConverter)，包含整流及直 流電源轉換H，如所示’整流-般_四顆二鋪接成橋式的型式來 達成’也就是橋式整流器，而直流轉換器的部份為了達到高功率因數並降 低總諧波失真率（THD)，升壓型的轉換器（B〇〇st con贈er)是最常見的 應用。隨著-些新應用的需求，並献相關電源品f及效能要求的規範， 各式電源架構（topologies)及控制方法相繼被提出，其中無橋式功率因數 修正器（BridgelessPFC)及交錯式功率因數修正器（InterleavedpFC)，是 最典型的代表，無橋式功率因數修正器，顧名思義其將傳統電源架構中由 二極體組成的橋式整流器省略，更精確的描述是利用兩只主動開關 (POWERMOSFET，IGBT, BJT)取代原本橋式整流器中的兩顆低端（L〇w Side)二極體，並且利用和輸入交流電源串接的電感組成一升壓轉換器，如 圖二A所示，另一種無橋式功率因數修正器，則是將橋式整流器的一組上 下臂用主動開關來取代，如圖二B所示，右側上下臂二極體決定電流的流 向，而左側上下臂主動開關和輸入電感構成一升壓轉換器，如前所述此升 壓架構的目地是為了達成高功因數及低諧波失真的要求，利用回授控制的 201121218 技巧並適當的切換主動開關，將可以達到和傳統架構—樣的效果，且因為 利用主動開關取代了被動開關（二極體），所以電源轉換過程中因為二極體 順向電餅（fb贈dvoltage’）所以造損失㈣蝴請的導通損 ^所取代，在絕大多數的應用中主動開關的導通損耗將 遠小於二極體的損耗’因此無橋式功率因數修正器是著眼於改善電源轉換 效率而衍生出的電路形式。 另-種被提出的架構是交錯式辨因數修正器，如圖三所示，相對於 無橋式功率S數修正H，此種電源架觀更加狀注目，交錯式切換的技 巧已廣泛應用於高功率密度的直流對直流電源轉換时，例如個人電腦中 央處理II (mi)所使關VRM電源，及高辨應姻通訊電源，所謂交 錯式是將-個以上的電源轉換器並聯在，，並且將每—組電源轉換器的 切換頻率同步並且各自產生相位延遲，延遲的角度由並聯的數量決定⑽脱 Delay為360 / N ’ N代表轉換器的數量），因為切換訊號的相互交錯，這將 會使得輸出、輸人_電流產生_ (CaneellatiGn)的侧，如此電流連 波將會隨著並聯數量的增加而減少，並且達到倍頻的作用，這將有利於輸 出壚波器及前端EMI舰㈣設計及贿賴小，同時功率分散於N組轉 換器中也將有助於散熱及效率的提升，交錯式功率因數修正器也是利用這 樣的原理，將兩組以上的升壓轉換器並聯在—起，並且利用回授控制的技 巧達到高功率因數的電源轉換。 由此可見，不論是無橋式功率因數修正器或是交錯式功率因數修正 器，皆有不同之優點及應用領域，因此若能夠結合兩者之優點，來達到轉 換電路應用最大化’使其具有能提供低損失及高神密度魏之功率因數 201121218 修正器，並可普遍應用於各類電源應用產品，即為目前相關產業界亟甲、解 決的課題。 本案發明人鑑於上述習用之方法所衍生的各項缺點，乃亟思加以改良 創新，並經多年苦心孤歸心研究後，來完成本件交錯式無橋辨因數修 正器及控制方法。 【發明内容】 本發明之目的即在於提供一種交錯式無橋功率因數修正器及控制方 法’係為了能達到_結合了上述兩種轉換n的優點讀生出㈣新電路 架構’除了具有無橋式功率因數修正器減少被動開關的損耗外，也利用交 錯式切換的技巧來降低輸^電流毅的以、，並且增加魏頻率來優化 濾波器的設計，藉以提升整體轉換效率及功率密度。 達成上述發明目的之交錯式無橋轉隨修正狀控财法，該交錯 式無橋功率因數修正ϋ係包含了交流輸人電源、輸人電感（Li' h)、四顆 主動元件（Q,〜Q4)、兩顆被動元件（Di、D2)及輸出電容（c。）及輸出電 阻（RL)，其中該四顆主動元件串接為全橋的形式，並分為不同驅動相位的 兩組開關，其中—組控制開關直接受控於控制電路，而另—組則 關，而該交流輸人電源-端係與輸人電_接，而另—端係姻於第一被 動讀及第-被動件之間’另外該被動元件，係會與—組控制開關、一 組整流開關、-輸出電容及—輸出電崎行並聯，而該二顆被動元件主要 作用為導引電流的流向； 該交錯式無橋功率因數修正器係可連接一控制訊號處理器及一控制電 路而該控制訊號處理器係包含了一輸出電遷衰減器、一輸入電壓衰減器、 201121218 一絕對值電路、一比較器'一比例積分電路、一相乘電路，其中該輸出電 壓衰減器係與父錯式無橋功率因數修正器及比較器賴接，係可將輸出的高 壓轉換為較低的電壓，以便於控制電路之電路訊號的處理，並將此回授信 號和一精密的基準電Μ參考準位（命令）做比較，得到控制電路的電壓誤 差I，並且經由比例積分(Proportional-Integral)電路的運算得到電壓迴路的 控制量，此訊號將和輸入電源的衰減量相乘得到輸入電流控制電路的電流 參考準位（命令），而輸入電流的迴授量則是經由電流感測器，再經過Ki (衰減器）的衰減及絕對值電路的轉換負半週所得到’將此輸入電流回授 量’和電流參考準位做比較得到電流的誤差量，此誤差量同樣的經由比例 積分電路的運算，制最後輸㈣控糖，此控婦蚊了輸出驅動訊號 的工作週期（duty cycle ); 由於控制電路將產生兩組相位移180度的控制開關驅動訊號，因此由 兩組比較器及相移⑽度的三肖絲當作脈波寬度觀器（ρ—训她 Modulator)，因此輸出控制量經過此一脈波寬度調變器後，得到兩組控制開 關驅動訊號，再經由-個互次或閘電路（XC)R)並搭配換相訊號，來確保 輸入負半猶㈣關及整關_錢，最後將此城再㈣反相器得 到對應的互補開關訊號。 【實施方式】 睛參閱圖四及圖十為本發a月交錯式無橋功率因數修正器及控制方法之 平均電流控制電路架構圖及實施例示意圖，如圖中所示，其中係包括： 一父錯式無橋功率因數修正器1，係與控制訊號處理器2及控制電路3 耦接，由圖六中可知，該交錯式無橋功率因數修正器丨係包含了交流輸入 201121218 .電源、輸入電感（Ll、L2)、四顆主動元件（Q广Q4)、兩顆被動元件（Dl、 DO及輸出電容（C〇)及輸出電阻（rl); 一控制訊號處理器2，係包含了一輸出電壓衰減器21、一比較器 221，222、-比例積分電路231,232、-相乘電路24、—絕對值電路251，252、 -輸入電壓衰減器26、-電流感測器27及—衰減器28，其中該輸入電廢 衣減器20及電流感測器27係與交錯式無橋功率因數修正器耦接，而該輸 入電壓衰減器26及電流感· 27分職接至絕對值電路％及衰減器28， _而該輸出電壓衰減器21係與交錯式無橋功率因數修正器1及比較器221搞 接，係可將輸出的高壓轉換為較低準位的直流電壓值，以便於控制電路3 之電路訊號的處理’並藉由比較器221將此回授信號和一精密的基準電壓 參考準位（命令）做比較，得到電壓誤差量，再經由比例積分電路231的 運算得到電壓迴路的控制量，此訊號將和輸入電源的參考值相乘（藉由相 乘電路24)得到輸入電流控制電路的電流參考準位（命令），其中輸入電源 的參考值係經由輸入電壓衰減器26及絕對值電路251來得到，而輸入電流 * _授則是經由電流感測器27，再經過衰減器28的衰減及絕對值電路的 252轉換負半週所得到，將此輸入電流回授量至比較器222，並與輸入電流 控制電路的電流參考準位做比較來得到電流的誤差量，此誤差量同樣的經 由比例積分電路232的運算，得到最後輸出至控制電路3的輸出控制量， 此控制量決定了輸出驅動訊號的工作週期（dutycycle); 一控制電路3,係與交錯式無橋功率因數修正器1及控制訊號處理器2 耦接，由於控制電路3將決定兩組相位移180度的控制開關驅動訊號，因 此由兩組比較器及相移18〇的三角波，來當作脈波寬度調變器（pu丨seWidth 201121218201121218 VI. Description of the Invention: [Technical Field] The present invention relates to an interleaved bridgeless power factor corrector and a control method thereof, and more particularly to a power factor corrector capable of providing low loss and high power density and (4) The method can be widely applied to all kinds of electric secret products. The system is a medium-constrained application requiring high power and high frequency output. [Prior Art] The traditional AC-to-DC power converter (ACtoDCConverter) includes rectification and DC power conversion H, as shown in the 'rectifier-like_four-two-bridge-bridge type to achieve', that is, bridge rectifier In order to achieve high power factor and lower total harmonic distortion (THD) in the DC converter, a boost converter (B〇〇st con er) is the most common application. With the requirements of some new applications, and related specifications for power supplies and performance requirements, various power architectures (topologies) and control methods have been proposed, among which bridgeless power factor corrector (Bridgeless PFC) and interleaved power The Factor Corrector (InterleavedpFC) is the most typical representative. The bridgeless power factor corrector, as its name suggests, omits the bridge rectifier consisting of diodes in the traditional power architecture. More precise description is the use of two active switches ( POWERMOSFET, IGBT, BJT) replaces the two low-side (L〇w Side) diodes in the original bridge rectifier, and uses a resistor connected in series with the input AC power to form a boost converter, as shown in Figure 2A. Another type of bridgeless power factor corrector replaces the upper and lower arms of the bridge rectifier with active switches. As shown in Figure 2B, the right upper and lower arm diodes determine the current flow, while the left and right arms are left and right. The active switch and the input inductor form a boost converter. As mentioned above, the purpose of the boost architecture is to achieve high power factor and low harmonic distortion requirements, using feedback control. 201121218 Tips and proper switching of the active switch will achieve the same effect as the traditional architecture, and because the active switch replaces the passive switch (diode), the power conversion process is due to the diode forward electric cake (fb The dvoltage') is replaced by the loss (4) of the butterfly's conduction loss. In most applications, the conduction loss of the active switch will be much smaller than the loss of the diode. Therefore, the bridgeless power factor corrector is focused on improvement. A form of circuit derived from power conversion efficiency. Another proposed architecture is an interleaved discriminator, as shown in Figure 3. Compared to the no-bridge power S-number correction H, this power grid view is more noticeable. Interleaved switching techniques have been widely used. When the high-power density DC-to-DC power supply is converted, for example, the personal computer central processing II (mi) is used to turn off the VRM power supply, and the high-definition communication power supply, the so-called interleaving is to connect more than one power converter in parallel, And the switching frequency of each set of power converters is synchronized and each generates a phase delay, and the delay angle is determined by the number of parallel connections (10) Delay is 360 / N 'N represents the number of converters), because the switching signals are interlaced, this Will cause the output, input _ current to generate _ (CaneellatiGn) side, so the current continuous wave will decrease as the number of parallel increases, and achieve the frequency multiplication effect, which will benefit the output chopper and front-end EMI Ship (4) design and bribery, while the power is dispersed in the N sets of converters will also contribute to heat dissipation and efficiency improvement, the interleaved power factor corrector is also using this principle, the two The boost converters above the group are connected in parallel and utilize the technique of feedback control to achieve high power factor power conversion. It can be seen that whether it is a bridgeless power factor corrector or an interleaved power factor corrector, there are different advantages and application fields, so if the advantages of both can be combined, the conversion circuit application can be maximized. It has a power factor 201121218 corrector that can provide low loss and high god density, and can be widely applied to various power application products, which is the subject of the current industry industry armor. In view of the shortcomings derived from the above-mentioned methods, the inventor of the present invention has improved and innovated, and after years of painstaking research, the interlaced bridgeless factor corrector and control method are completed. SUMMARY OF THE INVENTION The object of the present invention is to provide an interleaved bridgeless power factor corrector and control method 'in order to achieve _ combined with the advantages of the above two types of conversion n read (4) new circuit architecture 'in addition to having a bridgeless The power factor corrector reduces the loss of the passive switch, and also uses the technique of interleaving switching to reduce the input current, and increases the Wei frequency to optimize the filter design, thereby improving the overall conversion efficiency and power density. The staggered bridgeless power correction method for achieving the above-mentioned object of the invention includes the AC input power source, the input inductor (Li'h), and four active components (Q, ~Q4), two passive components (Di, D2) and output capacitor (c.) and output resistor (RL), wherein the four active components are connected in series in the form of a full bridge, and are divided into two groups of different driving phases. The switch, wherein the group control switch is directly controlled by the control circuit, and the other group is turned off, and the AC input power source-end is connected to the input power, and the other end is married to the first passive read and the first - between the passive parts, the passive component is connected in parallel with the group control switch, a set of rectifier switches, the output capacitor and the output electric wave, and the two passive components mainly serve to guide the current flow; The interleaved bridgeless power factor corrector is connected to a control signal processor and a control circuit, and the control signal processor comprises an output electromigration attenuator, an input voltage attenuator, a 201121218 absolute value circuit, and a Comparator's one-point integral a multiplying circuit, wherein the output voltage attenuator is coupled to the father-missing bridgeless power factor corrector and the comparator, and converts the output high voltage to a lower voltage to facilitate control of the circuit signal of the circuit. Processing, and comparing the feedback signal with a precise reference power reference level (command) to obtain a voltage error I of the control circuit, and obtaining a control value of the voltage loop through operation of a proportional integral (Integral) circuit This signal will be multiplied by the attenuation of the input power to obtain the current reference level (command) of the input current control circuit, and the feedback current of the input current is passed through the current sensor and then attenuated by Ki (attenuator). And the absolute half-cycle of the absolute value circuit is obtained by comparing 'this input current feedback amount' with the current reference level to obtain the error amount of the current. The same error amount is calculated by the proportional integral circuit to make the final output (four) control. Sugar, the control cycle of the output drive signal (duty cycle); because the control circuit will generate two sets of phase-shifted 180-degree control switch drive signal, Therefore, two sets of comparators and three-dimensional phase shift (10) degrees are used as the pulse width observer (ρ-training Modulator), so after the output control amount passes through the pulse width modulator, two sets of control switches are obtained. Drive the signal, and then pass through a mutual or gate circuit (XC) R) and match the commutation signal to ensure that the input negative half (four) off and the customs clearance _ money, and finally the city (four) inverter is correspondingly complementary Switch signal. [Embodiment] FIG. 4 and FIG. 10 are schematic diagrams showing an average current control circuit structure diagram and an embodiment of an a month interleaved bridgeless power factor corrector and a control method, as shown in the figure, wherein: The parent-missing bridgeless power factor corrector 1 is coupled to the control signal processor 2 and the control circuit 3. As can be seen from FIG. 6, the interleaved bridgeless power factor corrector includes an AC input 201121218. Input inductor (Ll, L2), four active components (Q Guang Q4), two passive components (Dl, DO and output capacitor (C〇) and output resistor (rl); a control signal processor 2, includes An output voltage attenuator 21, a comparator 221, 222, a proportional integration circuit 231, 232, a multiplication circuit 24, an absolute value circuit 251, 252, an input voltage attenuator 26, a current sensor 27, and an attenuation The device 28, wherein the input electric waste reducer 20 and the current sensor 27 are coupled to the interleaved bridgeless power factor corrector, and the input voltage attenuator 26 and the current sense 27 are connected to the absolute value circuit. % and attenuator 28, _ and the output voltage is degraded The reducer 21 is connected to the interleaved bridgeless power factor corrector 1 and the comparator 221, and can convert the output high voltage into a lower level DC voltage value to facilitate the processing of the circuit signal of the control circuit 3 The comparator 221 compares the feedback signal with a precise reference voltage reference level (command) to obtain a voltage error amount, and then obtains a control amount of the voltage loop through the operation of the proportional integration circuit 231, and the signal is input and input. The reference value of the power source is multiplied (by the multiplication circuit 24) to obtain the current reference level (command) of the input current control circuit, wherein the reference value of the input power source is obtained through the input voltage attenuator 26 and the absolute value circuit 251, and The input current * _ is obtained by the current sensor 27, and then by the attenuation of the attenuator 28 and the negative half cycle of the 252 conversion of the absolute value circuit, and the input current is fed back to the comparator 222, and the input current The current reference level of the control circuit is compared to obtain the error amount of the current, and the error amount is similarly calculated by the proportional integration circuit 232 to obtain the output finally outputted to the control circuit 3. The control quantity determines the duty cycle of the output drive signal; a control circuit 3 is coupled to the interleaved bridgeless power factor corrector 1 and the control signal processor 2, since the control circuit 3 will determine two The phase-shifting 180-degree control switch drives the signal, so the two sets of comparators and the triangular wave with a phase shift of 18 来 are used as the pulse width modulator (pu丨seWidth 201121218).
Modulator)’而輸出控制量經過此一脈波寬度調變器後，得到兩組控制開關 驅動訊號’再經由一個互次或閛電路（X〇R)並搭配換相訊號，來確保輸 入負半週時控制開關及整流開關的互換，最後將此訊號再經過反相器得到 對應的互補開關訊號（實施例示意圖請參考圖十）；另外由圖十一中可知， 為電感電流iL1、iu輸入電流iac的示意波形圖，為便於波形的繪製，我們 將duty視為固定，由示意的波形可以得知，輸入電流將和輸入電壓波形同 相’得到高功因數低諧波失真的電源轉換。 清參閱圖五及圖十二為本發明交錯式無橋功率因數修正器及控制方法 之臨界導通控制電路架構圖及實施例示意圖，如圖中所示，其中係包括一 交錯式無橋功率因數修正器1、控制訊號處理器2、控制電路3，其中該控 制訊號處理11 2係包含了-輸出《衰減H 2卜-比鮮22、-比例積分 電路23、一相乘電路24、一絕對值電路25、一輸入電壓衰減器26 ,而該 輸入電壓衰減ϋ 26健交錯絲橋辨目數修正器i及麟值電路25搞 接另外°亥輸出電壓衰減器21係與交錯式無橋功率因數修正器1及比較器 22耦接，因此輸出電壓將經由輸出電壓衰減器21，得到等比例的電壓回授 ϊ，並且和一精密的基準電壓，作比較後得到電壓的誤差量，此誤差量經 由比例積分電路23的運算，得到電壓迴路的輸出量，並且再和輸入電壓衰 減1相乘而得到電流的比較訊號（係為一輸入電流控制電路的電流參考 準位，來決定輸出驅動訊號的工作週期）； °月參閱圖十二所示，當輸入正半週時，換相訊號為ΰ，若控制電路開 始啟動此時啟動電路輸出2組相位差丨如度的脈衝訊號，將相繼使得 正反讀出為高準位，所以q2、q4亦將相料通，此時賴上的電流將隨 201121218 輸人電賴大小及時間逐漸上升，制電感電流的迴授訊號Ζι、Z2大於電 流比較訊號’此時對應的SR正反器輸出將被清除為零，因此& ' q4將分 職關閉，Q〗、Q3隨即被導通，械時因電感跨壓為負，所以電感電流隨 時間下降，當電感電流小於零時，ZCD輸出為高準位，如此將啟動下一個 切換週期’如此週而復始達_個线的控制。 凊參閱圖六為本發明交錯式無橋功率因數修正^及控制方法之交錯式 無橋功率因數修正器之實施例示意圖，如圖情示，交錯式無橋功率因數 _修正器其中係包含： -交流輸人電源，其中_端係、與輸人電感一山減，而另一端係麵 接於第-被動元件Dl及第二被動元件巧之間； -輸入電感，係包含有第—輸人電感^及第二輸人電感^，其中該第 -輸入電感Ll-端_接於第_主航件Q及第二主動元件&之間而 “第輸入電感L2則輕接於第三主動元件a及第四主動元件仏之間； 魯主動耕’係包含有第__主動元件A、第二主動元件q”第三主動 -Q3及第四主動元件Q4，其中該四顆主動元件Q广Q4串接為全橋的形 式’並分為不同軸相位的兩組開關，其中一組控制開關直接受控於控制 電路，而另一組則為整流開關； 被動元件係包含有第一被動元件Di、第二被動元件，該第一被 動儿件D,之陰極係輕接於第二被動元件〇2之陽極，並且兩相連接之被動 "1 2係s與組控制開關、—組整流關、-輸出電容〇)及-輸 出電阻RL進打並聯，而該二顆被動元件Di、D2主要作用為導引電流的流 201121218 件，缒由’轉細辨料級來選擇適#的半導體元 I _路3輸出驅動戰來進行·_閉，其找Ql〜Q4串接 為全橋的形式，Ql、卩2及〇 串接 相互延遲]80许 “、不同驅動相位的兩組開關，此兩組開關 且在门度’同—組開關中為互補動作’也就是當Q2導通時Ql截止， 且在同-個半週中，有组 接找難㈣路，而互補的另一 組為整〃丨(_開關，當輸入正半週時 输_關，Ql、Q3為整流開關， 輸入負核時Qi、Q4_關，Q2、Q4為整流開關； 因此當輸彻Vae蝴CA所㈣抑的共接點連接 到輸入電源的負端，此時若輸入電流大於零，則此電流將使得D2順偏導通 並導引回輸入電源負端’而Di將因為D2的導通使得其因而逆偏截止，同 理當輸入電源負半週時，如圖七B所示(輸入電源、負半週時的電路，此 時電感連接到電源負端因此將由Qi、Q3控制電感的儲能時間，〜2 1 當作整流路逕侧），_偏導通㈣偏截止，因此不論輸入電源正半 週亦或負半週，電_可以f效__轉流型柄升壓轉換器； 首先我們先就輸入正半週時的電路狀態及其對應的波形來做說明，為 了分析方便起見仙必驗設娜的鮮（>16Khz)獻綠人電源頻率 ⑼〜麵）’此假設在現實的應用中是成立的，有了這個假設之後雖然輸 入為正負交㈣魏’但在—個婦週射輸入電源可視為定值，當 Q2導通時輸入電源經由〇2及D2對電感Li儲能，此時Q2為控綱關，由 控制電路決定Ll儲能的時間，t Q2受控制電路的作用_止，為了確保 Q,的導通不會因為〇2賴止延遲而造成輸出短路，因此&必需延後一小 段時間導通’此段時間我們稱之為死區（deadtime)，這段時間因為^能量 201121218 的連續性，Ql的背接二極體將會導通，並且將Li的能量對負載釋放，因為 Q!導通前背接二極體已先導通’所a Q!將操作在零電壓導通的狀態，如此 切換損失將可以大幅減小，同理q3、Q4的動作也和Qi、Q2相同，只是相 位滯後18G度’由如圖八A及圖八精對應的波形中可知；、iL2的波形 因為相位魏遲，產錢形相加時的_ (eaneeUatiGn)作用，因此可以得 到較小的輸人漣波電流，且其頻率加倍，而輸出電流因為相位及流過整流 開關（Q丨、Q3)電流的不連續，可以分為2種狀態，當Dut淨le<5〇%時 輸出漣波因域過整_關錢減的作職誠小且鮮加倍，而Duty Cyde>50〇/0時振幅不變但頻率加倍’因此雖然Du㈣de>·沒有產生抵 消的侧，但因為頻率加倍健有利於輸出濾波器的設計；另外基於相同 的原理’如此的電路_可以拓制N相的細，如圖九所示，每一組訊 號延遲相位為36G度+ N ( N代表開_總組數）^ 本發明所提供之紐式無橋轉因數修⑼及㈣方法，與其它習用 技術相互比較時，更具備下列優點： 1·本發明之交錯式無橋功糊雜正狀控财法，係省略了前級 橋式整流ϋ來達聽量轉換過財切鋪失的纽降低，因此可 以達到高轉換效率的目的。 2·本發明之交錯式無橋功率因雜正^及控财法，财以達到輸 出、入漣波抵銷及倍頻的作用’因此輸人電感及輸出電容可以選 擇體積較小的元件，更進—步達到提升功率密度的目的。 3.本發明之交錯式無橋功率因數修正器及控制方法，係可以依據功 率需求何生衫相的顧，另外本發明亦可達顺频雜訊的目 201121218 的’並且不用特別選擇特定二極體，因此可以選用更常用且低價 的二極體’而共模雜訊則可以經由輸入共模電感（多相的應用將 輸入電感使用同一顆鐵心，並且連接為共模電感的型態）的濾 除’並且若電路操作在高功率的應用電路必定為連續導通模式， 因此電源跳動(Power bounce)造成共模雜訊的問題將不存在。 上列詳細說明係針對本發明之一可行實施例之具體說明，惟該實施例 並非用以限制本發明之專利範圍，凡未脫離本發明技藝精神所為之等效實 施或變更，均應包含於本案之專利範圍中。 綜上所述，本案不但在技術思想上確屬創新，並能較習用物品增進上 述夕項功效’應以充分符合新雜及進步性之法定發明專利要件，爰依法 提出申μ ’懇4貴局核准本件發明專利巾請案，以勵發明，至感德便。 【圖式簡單說明】 圖一為習知之功率因數修正器電路示意圖； 圖二Α為f知之無橋式辨因數修正器示意圖； 圖二；6為習知之無橋式功率因數修正器示意圖； 圖二為習知之交錯式功率因數修正器示意圖； 圖四為本發明交錯式無橋功率因祕正^及控制方法之平均電流控制 電路架構圖； 圖五為本發明交錯式無橋功率因數修正器及控制方法之臨界導通控制 電路架構圖； 器及控制方法之交錯式無橋功 圖六為本發明交錯式無橋功率因數修正 率因數修正器之實施例示意圖； 12 201121218 • 圖七八為本發财錯式無橋轉因雜正n及控财故輪人正半週 等效電路實施例示意圖； 圖七8為本發明交錯式無橋功率因雜正狀控财法之輪入負半週 等效電路實施例示意圖； ' 圖八Α為本發败錯式無橋轉隨修正^及㈣方法之輪入正半週 D<50%時波形示意圖； U為本發明交料無橋辨隨修正驗㈣料讀入正半週 • D>50%時波形示意圖； 圖九為本發明交錯式無橋功率因數修正器及控制方法之多相交錯式無 橋功率因數修正器實施例示意圖； 圖十為本發贼錯式無橋功率隨修正肢㈣方法之平均電流控制 電路實施例示意圖； 圖十-為本發明交錯式無橋功率因數修正器及控制方法之電感電流 iu ' iu輸入電流‘的示意波形圖；以及 圖十一為本發較錯式無橋辨隨修㈣及控翁法之臨界導通控 制電路實施例示意圖。 【主要元件符號說明】 1 交錯式無橋功率因數修正器 2 控制訊號處理器 21 輸出電壓衰減器 22 比較器 1 13 201121218 221 比較器 222 比較器 23 比例積分電路 231 比例積分電路 232 比例積分電路 24 相乘電路 25 絕對值電路 251 絕對值電路 252 絕對值電路 26 輸入電壓衰減器 27 電流感測器 28 衰減器 3 控制電路Modulator)' After the output control amount passes through the pulse width modulator, two sets of control switch drive signals are obtained, and then a mutual or 閛 circuit (X〇R) is matched with the commutation signal to ensure the input negative half. During the week, the control switch and the rectification switch are interchanged. Finally, the signal is further passed through the inverter to obtain the corresponding complementary switching signal (refer to FIG. 10 for the schematic diagram of the embodiment); and as shown in FIG. 11, the input is the inductor current iL1 and iu. The schematic waveform of the current iac, in order to facilitate the drawing of the waveform, we regard the duty as fixed. It can be known from the schematic waveform that the input current will be in phase with the input voltage waveform to obtain a power conversion with high power factor and low harmonic distortion. FIG. 5 and FIG. 12 are schematic diagrams showing a schematic diagram of a critical conduction control circuit and an embodiment of an interleaved bridgeless power factor corrector and a control method thereof, as shown in the figure, including an interleaved bridgeless power factor. Corrector 1, control signal processor 2, control circuit 3, wherein the control signal processing 11 2 includes - output "attenuation H 2 Bu - ratio fresh 22, - proportional integration circuit 23, a multiplication circuit 24, an absolute The value circuit 25, an input voltage attenuator 26, and the input voltage attenuation 健 26 交错 交错 丝 丝 辨 辨 辨 辨 及 及 及 麟 麟 麟 麟 麟 麟 麟 麟 麟 麟 麟 麟 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出The factor corrector 1 and the comparator 22 are coupled, so that the output voltage will be supplied to the voltage attenuator 21 to obtain a proportional voltage feedback, and compared with a precision reference voltage, the error amount of the voltage is obtained. The amount is obtained by the operation of the proportional integration circuit 23, and the output of the voltage loop is obtained, and then multiplied by the input voltage attenuation 1 to obtain a comparison signal of the current (which is a current reference of an input current control circuit) Level: to determine the duty cycle of the output drive signal); ° month shown in Figure 12, when the input is half a cycle, the commutation signal is ΰ, if the control circuit starts to start, the start circuit outputs 2 sets of phase difference 丨If the pulse signal of the degree will make the positive and negative readouts as high level, so q2 and q4 will also pass through the phase. At this time, the current will increase gradually with the size and time of the input power, and the inductor current will be increased. The feedback signal Ζι, Z2 is greater than the current comparison signal' At this time, the corresponding SR flip-flop output will be cleared to zero, so & 'q4 will be closed, Q, Q3 will be turned on, and the mechanical time will be crossed by inductance. The voltage is negative, so the inductor current decreases with time. When the inductor current is less than zero, the ZCD output is at a high level, which will initiate the next switching cycle 'this cycle and then repeat the control of _ line.凊 Referring to FIG. 6 is a schematic diagram of an embodiment of an interleaved bridgeless power factor corrector and an interleaved bridgeless power factor corrector according to the present invention. As shown in the figure, the interleaved bridgeless power factor _ corrector includes: - AC input power, in which the _ terminal system is reduced with the input inductor, and the other end is connected between the first passive component Dl and the second passive component; - the input inductor includes the first input a human inductor ^ and a second input inductor ^, wherein the first input inductor L1 - terminal _ is connected between the first _ primary carrier Q and the second active component & and "the first input inductor L2 is lightly connected to the third Between the active component a and the fourth active component ;; the active cultivator includes the __active component A, the second active component q, the third active-Q3 and the fourth active component Q4, wherein the four active components Q Guang Q4 is serially connected in the form of a full bridge and is divided into two sets of switches with different shaft phases. One group of control switches is directly controlled by the control circuit, and the other group is a rectifier switch. The passive component system includes the first switch. Passive component Di, second passive component, the first passive component D, The pole is lightly connected to the anode of the second passive component 〇2, and the two-phase passive passive "1 2 system s is connected in parallel with the group control switch, the group rectifier switch, the -output capacitor 〇), and the output resistor RL. The two passive components Di and D2 mainly function as a current-carrying current 201121218, and the semiconductor element I_channel 3 output driving war is selected by the 'transfer fine-graining level to perform the _-closing. Ql~Q4 are serially connected in the form of full bridge, Ql, 卩2 and 〇 are connected in series with each other] 80", two sets of switches with different drive phases, and the two sets of switches are complementary in the door degree 'same-group switch The action 'that is, when Q2 is turned on, Ql is cut off, and in the same half-week, there is a group connection to find the hard (four) way, and the other complementary group is the whole 〃丨 (_ switch, when the input is half a week, the input _ Off, Ql, Q3 are rectifier switches, Qi, Q4_ off, Q2, Q4 are rectifier switches when inputting negative nuclei; therefore, when the common contact of Vae butterfly CA (4) is connected to the negative terminal of the input power supply, at this time If the input current is greater than zero, this current will cause D2 to turn on and lead back to the input power supply 'end' and Di will be turned on because of D2. Therefore, the reverse bias is cut off. Similarly, when the input power supply is negative for half a cycle, as shown in Figure 7B (the input power supply, the circuit at the negative half cycle, the inductor is connected to the negative terminal of the power supply, so the energy storage of the inductor will be controlled by Qi and Q3. Time, ~2 1 is used as the side of the rectification path), _ partial conduction (4) is off-cut, so regardless of the positive or negative half cycle of the input power supply, the _ can be __ converter type sleeve boost converter; First, enter the circuit state and its corresponding waveform when the positive half cycle is used. For the sake of analysis convenience, the immortality of the syllabus (>16Khz) is given to the green power frequency (9) ~ face) 'This assumption is in reality The application is established. After this assumption, although the input is positive and negative (four) Wei', the input power supply can be regarded as a fixed value. When Q2 is turned on, the input power is stored in the inductor Li via 〇2 and D2. At this time, Q2 is the control off, the control circuit determines the time of Ll energy storage, and t Q2 is controlled by the control circuit. In order to ensure the conduction of Q, the output will not be short-circuited due to the delay of 〇2, so & Must be delayed for a short period of time to turn on 'this time I Called deadtime, this time because of the continuity of ^201121218, Ql's back-connected diode will be turned on, and the energy of Li is released to the load, because Q! turns on the front back diode It has been turned on 'a Q! It will operate in the state of zero voltage conduction, so the switching loss can be greatly reduced. Similarly, the actions of q3 and Q4 are the same as Qi and Q2, but the phase lag is 18G degrees. It can be seen from the waveforms corresponding to A and Fig. 8; the waveform of iL2 is _ (eaneeUatiGn) when the phase of the production is added, so that a smaller input chopping current can be obtained, and the frequency is doubled. The output current can be divided into two states due to the phase and the discontinuity of the current flowing through the rectifier switch (Q丨, Q3). When the Dut net le < 5〇%, the output chopping domain is over-quantified. The job is small and fresh double, while Duty Cyde>50〇/0 has the same amplitude but doubles the frequency' so although Du(4)de> has no offset side, but because the frequency doubles the advantage of the output filter design; The principle of 'such a circuit _ can expand the N phase As shown in FIG. 9, the delay phase of each group of signals is 36G degrees + N (N represents the number of open_total groups). The method for repairing the no-bridge factor (9) and (4) provided by the present invention is mutually compatible with other conventional technologies. In comparison, the following advantages are obtained: 1. The staggered bridgeless function of the present invention is a method of omitting the pre-stage bridge rectification ϋ to achieve the reduction of the listener's conversion, and thus High conversion efficiency can be achieved. 2. The interleaved bridgeless power of the present invention has the effect of output, input and offset cancellation and frequency doubling due to the miscellaneous positive control and the wealth control method. Therefore, the input inductor and the output capacitor can select smaller components. Go further and achieve the goal of increasing power density. 3. The interleaved bridgeless power factor corrector and the control method of the present invention can be based on the power demand, and the present invention can also achieve the goal of 201121618 of the frequency noise. Polar body, so you can use the more common and low-cost diodes', while common-mode noise can pass the input common-mode inductor (multi-phase application uses the same core for the input inductor and is connected to the common mode inductor). "Filtering" and if the circuit is operated in a high-power application circuit must be in continuous conduction mode, the problem of power bounce causing common mode noise will not exist. The detailed description of the preferred embodiments of the present invention is intended to be limited to the scope of the invention, and is not intended to limit the scope of the invention. The patent scope of this case. In summary, this case is not only innovative in terms of technical thinking, but also able to enhance the above-mentioned effects of the above-mentioned items in comparison with the use of items. 'It should be in accordance with the statutory invention patents that fully meet the new and progressive nature. The bureau approved the application for the invention patent towel, in order to invent the invention, to the sense of virtue. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a conventional power factor corrector circuit; FIG. 2 is a schematic diagram of a bridgeless factor correction device; FIG. 2; FIG. 6 is a schematic diagram of a conventional bridgeless power factor corrector; The second is a schematic diagram of a conventional interleaved power factor corrector; FIG. 4 is a schematic diagram of an average current control circuit of the interleaved bridgeless power source and the control method; FIG. 5 is an interleaved bridgeless power factor corrector of the present invention. And the control method of the critical conduction control circuit architecture diagram; the interleaved bridgeless power diagram of the apparatus and the control method is a schematic diagram of an embodiment of the interleaved bridgeless power factor correction rate factor corrector of the present invention; 12 201121218 • Figure 7-8 The schematic diagram of the equivalent circuit of the half-week equivalent circuit of the miscellaneous n-type and the control of the financial man who is wrong with the financial model; Figure 7 is the negative half of the interleaved bridgeless power due to the positive control method of the present invention. Schematic diagram of the embodiment of the equivalent circuit of the week; 'Figure 8Α is the schematic diagram of the waveform of the fault-free no-bridge rotation with the correction ^ and (4) the round-in positive half-cycle D<50%; U is the bridge of the invention Follow-up (4) The material is read into the positive half cycle • D> 50% waveform diagram; Figure 9 is a schematic diagram of the embodiment of the multi-phase interleaved bridgeless power factor modifier of the interleaved bridgeless power factor modifier and control method of the present invention; Schematic diagram of an embodiment of the average current control circuit of the method for correcting limbs (4) of the present invention; FIG. 10 - the inductor current iu ' iu input current of the interleaved bridgeless power factor corrector and the control method of the present invention A schematic waveform diagram; and FIG. 11 is a schematic diagram of an embodiment of a critical conduction control circuit of a fault-free bridgeless repair (four) and a control method. [Main component symbol description] 1 Interleaved bridgeless power factor corrector 2 Control signal processor 21 Output voltage attenuator 22 Comparator 1 13 201121218 221 Comparator 222 Comparator 23 Proportional integration circuit 231 Proportional integration circuit 232 Proportional integration circuit 24 Multiplying circuit 25 Absolute value circuit 251 Absolute value circuit 252 Absolute value circuit 26 Input voltage attenuator 27 Current sensor 28 Attenuator 3 Control circuit