TW201121215A - PWM controller of low UVLO voltage. - Google Patents

Abstract

The present invention discloses a PWM controller of low UVLO voltage suitable for a switching power supply, which includes a power supply terminal coupled to a main input voltage via a starting resistor and coupled to a reference ground via a capacitor, and an output terminal coupled to the gate of a main-side transistor, wherein the main-side transistor requires a minimum gate-controlled voltage. The PWM controller of low UVLO voltage includes: a UVLO unit for performing a hysteresis comparison between a UVLO_ON voltage and a UVLO_OFF voltage on a supply voltage of the power supply terminal, so as to generate a control signal, wherein the UVLO_OFF voltage can be as low as the minimum gate-controlled voltage; a PWM unit enabled by the control signal to generate a PWM signal; and a driving stage including a PMOS transistor coupled to the PWM signal by a gate, coupled to the supply voltage by a source and coupled to the output terminal by a drain.

Description

201121215 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a pWM controller for a switching power supply application, and particularly to a two-stage low-cut thief power supply standby standby UVLQ _. 2 1 ^ [Prior Art] In switching power supply applications, such as AC to DC conversion, a power supply PWM controller is used to generate a gate control signal to drive a power ^ to input power to the transmission -_ Period (which must be met - specifications, for example

3/i), the pressure will be - the main input voltage is - the starting resistance pair - the holding capacitor is charged and gradually rises, and before the supply voltage does not exceed a high threshold voltage - U 'the gate control signal will not be generated, Its t _ is the abbreviation for Un-aged Hometown Lock. Once the closed-control signal is enabled due to the supply voltage, it will not be disabled until the supply voltage is lower than the low-threshold voltage-UVL0-0FF voltage. (4): Force = Energy == Nothing but - The length of the wire is fine. For the description of the system, please refer to Figure 1, which shows the block diagram of the main circuit including a conventional application. As shown in FIG. 1, the TM-control 11 (10), the dynamic resistor 105, the holding capacitor 109: a main-side coil 1〇7, a main-side operating transistor 108, and a current sensing resistor are used in the middle L. Supply _ VCC power supply of the PWM controller 100 ^ a ^ test s ^ Vcs, which is the cross-voltage of the current sense resistor 109, the center of the light phase threat - reference tilt (not shown in Figure 1) error μ , shouting students sent to the box _ transistor (10) letter ~ 201121215 No. V. . The PWM controller 100 includes a UVL0 unit 1 , a PWM unit 102, a high side NMOS transistor 103, and a low side NMOS transistor 104. The UVL0 unit 101 is configured to perform a hysteresis comparison with a UVLO-ON voltage and a UVL0_0FF voltage on the supply voltage Vcc of the power supply terminal to generate a control signal EN having a consistent state and a disabled state, wherein the The UVLO-OFF voltage must be at (the minimum gate voltage of the primary side NMOS transistor 108 + the threshold voltage of the high side NMOS transistor 103) to ensure safe operation of the primary side NMOS transistor 108. After the power is turned on, the supply voltage Vcc is gradually increased by a level lower than the voltage of the UVL0-0N. At this time, the control signal EN is in the disabled state; when the supply voltage Vcc exceeds the UVL0_0N voltage, the control is performed. The signal EN becomes and remains in the enabled state unless the supply voltage Vcc falls below the UVL0_0FF voltage. That is, the l|VL0_0N voltage and the UVL0_0FF voltage are respectively used to turn on and stop the supply of electricity.

Pressure Vcc adjustment procedure. The typical value of the UVL0_0N voltage is about 15 V, and the typical value of the UVL0_0FF voltage is about 9 V'. The typical value of the minimum gate voltage of the main side NM0S transistor 1〇8 is about 7 V' and the high side NM0S transistor 103 Its threshold voltage has a blood type value of approximately 2V. ? The P·cell 1〇2 powered by the supply voltage Vcc is coupled to the control signal εν φ , and is enabled in the enabled state to generate a pair according to the current sensing signal Vcs and the feedback signal vFB. The complementary PWM signals Vh and Vl are disabled when the control signal en is in the disabled state. The high-side NM0S transistor 1〇3 has a gate terminal coupled to Vh, coupled to the supply, one of the voltages Vcc, and a source terminal coupled to the main side NM〇s transistor 1〇8. To generate a high level of the gate control signal VG. The low-side NM〇S transistor 1〇4 is used to control the low level of the gate control signal VG, which has a gate terminal of VL, coupled to the "Hainan side-shun 0S transistor 1 〇3 source One of the extremes is extreme, and it is lightly connected to the source-source extreme. The _ signal high level is approximately (the supply 赖να - the threshold voltage of the high side NMOS transistor 103). The series combination of the starting resistor 105 and the holding capacitor 1〇6 is coupled between a main [201121215 input voltage v1N and the reference ground to provide a starting current path of the supply voltage Vcc. The starting resistor 105 has a typical value of 2 Μ Ω, and the typical value of the holding capacitor 1 〇 6 is l 〇 eF and the typical value of V 1 N is 127 V or 373 volts. At a typical value of 2 Ω, the starting resistor 105 consumes about 7 sec at VIN of 373V. In order to meet the lOOmW standby power requirements of the switching power supply application, in this case, the pWM controller; and other parts will have only 3 〇mW of power consumption space, which will be difficult to achieve. The main side coil 107 is for storing magnetic energy when the main side NM〇s transistor 1〇8 is turned on, and is supplied by the main input voltage V1N.

The main-side NMOS transistor 108 has a gate terminal coupled to the gate control signal Vg, a terminal connected to the primary side coil 1〇7, and a source terminal coupled to the current sensing resistor 1〇9. To act as a switch in the main-side current path composed of the main-side coil 1〇7 and the current-sense resistor 1〇9. The current sensing resistor 109 is coupled between the source of the main side NM〇s transistor 8 and the current of the current path to generate the current sense of the starting resistor 105. The majority of the standby power required for switched power applications occupies the resistance of the starting resistor 1Q5 as expected to be as large as possible to reduce standby power consumption for switched power applications. However, since the resistance of the starting resistor 1 must be lower than the specification of the -maximum rugged starter, for example, up to 3 seconds, it is difficult to reduce the standby power consumption of the switching power supply application. In the case where the starting resistor 105 is amplified, one way to avoid increasing the starting period is to use a smaller holding capacitor. However, the smaller holding capacitor 1〇6, because it retains a smaller amount of charge, when the pair of complementary smooth signals % and Vl are enabled, there is a possibility that the supply voltage Vcx cannot be maintained above the voltage. Risk, which may make the switched power application not function properly. Another way to solve this problem is to reduce the UVL〇_〇N voltage and the UVL0-0FF voltage. However, the reduction of the UVL 〇 〇 电压 电压 voltage and the 〇 〇 〇 FF voltage will result in a lower supply of Vcc, the high material of the job record Ve, equal to (supply electricity 201121215 f Vcr i Hai high side N job crystal 103 The threshold voltage (about 2v)) will also be reduced, and the queen will operate. The high level of the idle control signal must be higher than the minimum on-resistance of the minimum gate of the transistor (10). The system uses a heavy load current and its main side _ transistor version 疋. The high level of signal % is lower than the minimum gate voltage, and ~=M0S transistor 1〇8 will be destroyed due to over-power _R p〇wER) consumption. Therefore, there is a need to provide a solution for switched power applications that can reduce standby power consumption without prior to your J NM0S transistor. In addition, the invention proposes to reduce the standby power consumption of the switched power supply application. 2 The solution uses a larger starting resistor and replaces the conventional PWM controller with a controller. Electric stem said [Summary of the invention] (d) is to provide a reduction in the switching power supply application standby power consumption 曰 will violate the provisions of the __ and there is no risk of burning the main side brain S-electrode. % 心本t Another purpose is to provide a simple voltage controller for reducing the switching power supply application. The purpose of the non-burning main side transistor is the purpose of the present invention. A ThunderTM controller having a power supply terminal for the main input voltage and by-capacitance to - reference ground, and - to - the gate terminal of the main side transistor, wherein the main side transistor requires - Πν二: The voltage is controlled to operate safely, the low lJVL. The voltage controller includes: UVLO to perform a comparison with the supply voltage of the power supply terminal and the hysteresis voltage of the one and the forbidden voltage to generate a wide-ranging control number, and the GFF voltage can be as low as the minimum 4 ϋ The PWM unit is 'disabled when the control signal is in the enable state, and is generated by the b-PWM signal' and is disabled when the control signal is in the disabled state

[S 201121215 ί 3 3 signal; and a driver stage, which has a touch s transistor to connect the TM signal by its end, the source is extremely secretive to the supply voltage, and a faintly known light connection Output.

In order to achieve the above objectives, the present invention proposes a low-density and light-weight controller for a power supply application, which has a power supply terminal for being connected to the main input voltage and the capacitor by means of a private mountain. The surface is connected to the reference ground, and the = terminal is lightly connected to the gate terminal of the main-side transistor, wherein the main-side transistor is included with a minimum gate voltage for safe operation, and the low-surface voltage controller package The UVL0 unit is configured to perform a hysteresis comparison with a beta voltage and a -UVLQ-QFF voltage to supply a voltage to one of the power supply terminals to generate a control signal of the -enable state and the energy state. The GFF can be as low as the minimum = control voltage, and the -P-face unit is caused when the control signal is in the enable state, and the raw-PWM signal is disabled when the control signal is in the disabled state. β generating the PWM signal; a boosting circuit for generating an inverted signal of the forward signal 'where the high level of the inverted signal is higher than the supply voltage; and a driving stage having an NM0S transistor An extreme coupling is coupled to the inverted signal by a gate terminal thereof The supply voltage and a source are coupled to the output terminal. The detailed description of the structure, features, and aspects of the present invention is set forth in the appended claims. [Embodiment] FIG. 2 is a block diagram showing a main circuit of a switching power supply application including a low UVL voltage PWM controller according to a preferred embodiment of the present invention. As shown in FIG. 2, the main circuit includes a low UV0 voltage PWM controller 200, a dynamic resistor 205, a holding capacitor 20A, a main side coil 207, a main side NMOS transistor 208, and a current sensing resistor 209. .

In the main circuit, the low UVL voltage supplied from a supply voltage Vcc is used to sense a voltage Vcs, which is a voltage across the current sensing resistor 209, and one time. The signal yFB is given as an error signal of an output voltage relative to a reference voltage I (not shown in FIG. 2), and a gate signal VG is sent to the main side transistor 2〇8. The PWM controller 200 includes a UVOL unit 201, a PWM unit 202, a high side p_ transistor 2〇3, and a low side NM〇s transistor 2〇4. The UVLO unit 201 is configured to perform a hysteresis comparison with a low UVLO-ON voltage and a low UVL0_0FF voltage on the supply voltage Vcc of the power supply terminal to generate a control signal EN having a consistent state and a disabled state. The low uvl 〇 〇 ff voltage can be as low as the minimum gate voltage of the main side NMOS transistor 208, which is typically about 7 volts. After the power is turned on, the supply voltage Vcc is gradually increased by a level lower than the low UVL〇-〇N voltage. At this time, the control signal is in the disabled state; when the supply voltage Vcc exceeds the low UVL0_0N voltage. The control signal EN becomes and remains in the enabled state unless the supply voltage Vcc falls below the low UVL〇-〇FF voltage. That is, the low UVLO-ON voltage and the low UVLCL0FF voltage are respectively used to turn on, to suspend the adjustment procedure of the supply voltage VCC, and the supply voltage Vcc can therefore be controlled to a low level - which can be as low as Low UVL 〇 J) FF voltage. The low uvl nn voltage helps provide a short start-up period, and the PWM controller 2 消耗 consumes less power when the supply voltage Vcc is at a lower level. The cis-unit 2G2 powered by the supply voltage Vcc is tied to the control signal en, and is subjected to the wire in the verification state, and the thief is used to extinguish the measurement Ves and the feedback-stimulus-simplified signal V1' and the control signal. When the EN is in the disabled state, the directional side PMOS transistor 2〇3 has a gate terminal of the secret V1, minus the supply, the voltage source Vcc-source terminal, and the light connection to one of the main transistors is not 钿' A high level of the S-th gate control signal Vg is generated. The low-side circular s transistor is configured to generate a low level of the gate control signal 1, which has a W-threshold terminal, and is switched to the - terminal of the source terminal of the high-side PMGS transistor 203, and _ to a parameter - Source extreme. The high level of the gate control signal Vg can be as high as the supply voltage = the high side PMGS transistor 203 is at a low level to its source - depending on zero. Then 'the supply voltage - low level - the adjustment procedure is subject to the =201121215 unit 201 of the low UVLO-ON voltage and the low UVL 〇 J) FF voltage: the voltage Vcc should be as low as the minimum closed control voltage It can be used to generate a high level of the gate control signal Vg required for the inter-control voltage requirement.

The series combination of the starting resistor 205 and the holding capacitor 2〇6 is connected to a main, and the starting current path I between the input voltage vIN and the reference ground to provide the supply voltage Vce is in accordance with the switching power supply. The standby power consumption requirement and the requirement of the 3-second start-up period 'The resistance of the starting resistor 2〇5 can be larger than the typical value leakage, for example, ^ΜΩ” and because of the low voltage of the surface unit 2〇1, Low __OT arrangement' The simple capacitor 2Q6 can still be maintained at this typical value. Under the condition of 4 Ω, the starting resistance 2 〇 5 has a power consumption of about 35 mW when Vin is 37, and due to the low fox voltage, the starting period is 3 seconds. The main side coil 207 is configured to store magnetic energy when the main side turn transistor is turned on, and is supplied by the main input voltage y1N. The main side _S t crystal 208 has a gate terminal that is lightly connected to the gate control signal Vg, and is lightly connected to the main side coil 207 - no extreme and lightly connected to one source terminal of the current sensing resistor 2〇9, It functions as a switch in the main-side current path composed of the main-side coil 2〇7 and the current sensing resistance period. The current sensing resistor 209 is coupled between the source terminal of the main side _s transistor 2〇8 and the reference ground to generate a current sensing signal Vcs by carrying a current of the catenary path. »Because the power consumption of the starting resistor 205 is greatly reduced, the starting period can also meet the requirements. Therefore, the preferred embodiment of the present invention can solve the problem of the switching power supply application and the low standby. Moreover, since the supply voltage of the bribe is better than that of the I, the power consumption of the PWM controller can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 3 is a block diagram showing the main circuit of a switching power supply application including a low UVL 〇 voltage PWM controller according to another preferred embodiment of the present invention. As shown in FIG. 3, the main circuit includes a low fox voltage PWM controller 300, a starting resistor [201121215 306, holding the electric valley 307, a main side coil 308, a main side nm 〇 S transistor 309, and a current. The resistance is 31 〇.

In the main-side circuit, the low-UV0 voltage PWM controller _ bribe-current signal Vcs, which is supplied by a supply voltage Vcc, is the cross-voltage of the current-sensing resistor gas and a feedback signal Vfb. It is an error signal of an output voltage with respect to a reference voltage (not shown in FIG. 3), and is generated to one of the main side NM〇s transistors 3〇9 gating k number VG. The PWM controller 3 includes a UVL unit 3〇1, a pwM

Single turn 302, a boost circuit 3〇3, a high side NMOS transistor 304, and a low side NMOS transistor 305. The UVL0 unit 301 is configured to perform a hysteresis comparison with a low UVL0-0N voltage and a low UVL0_0FF voltage on the supply voltage Vcc of the power supply terminal to generate a control signal having an energy state and a disable state. EN, wherein the low uvl 〇 〇 ff voltage can be as low as the minimum gate voltage of the 6 um main side NM0S transistor 309, which is typically about 7V. After the power is turned on, the supply voltage Vcc is gradually increased by a voltage lower than the low UVL〇〇N voltage, and the control signal EN is in the disabled state; when the supply voltage Vcc exceeds the low UVL0_0N voltage, The control signal εν becomes and remains in the edge enable state 'unless the supply voltage Vcc drops below the low UVL 〇-〇FF voltage. That is, the low UVL0-ON voltage and the low UVLO_0FF voltage are respectively used to turn on and stop the adjustment procedure of the supply voltage Vcc, and the supply voltage Vcc can be adjusted to a low level as low as low. UVL〇_〇FF voltage. The low uvl 〇j)n voltage helps provide a short start-up period, and the PWM controller 300 consumes less power when the supply voltage Vcc is at a lower level. The pwm unit 302 powered by the supply voltage Vcc is enabled when the control signal EN is in the enable state to generate a PWM signal VL according to the current sensing signal Vcs and the feedback signal VTM. The control signal EN is disabled when it is in the disabled state. The boosting circuit 303 is configured to generate a boosting signal Vbh which is an inverted signal of the pWM signal w and a high level of the boosting signal vBH is higher than the supply voltage Vcc. FIG. 4 is a circuit diagram showing the tearing of the boosting circuit implemented in accordance with the preferred embodiment of the present invention. As shown in FIG. 4, the 4-boost circuit includes an nm〇S transistor 401-405, a capacitor 406-410, and a phase circuit 41, and the capacitors are composed of: The kesen charge pump is generated by a pair of complementary_signals M and (10) to generate a boosted voltage % according to the supply voltage Vcc, where %_LCti(VDD-VT)-VT, V" is CLK and (10) The high level, and the threshold voltage of these _ = body 401-405. The inverter circuit 411 is powered by the boost voltage % to generate the boost signal vBH according to the PWM signal V1.

The high side crystal 3 〇 4 has a gate terminal of Vbh, one of the supply voltage Vcc 汲 extreme, and is coupled to the source terminal of the main side NM 〇s transistor 3〇9 to generate the The high level of the gate control signal Vg. The low side NM〇s transistor 3〇5 system == control signal V. The low level, which has more than the extremes of the gate, is light, to the extreme end of the _ secret crystal Xie source - secret, and a secret to a reference L ^ - source extreme. The high level of the gate control signal Vg can be as high as the supply voltage Vcc, and the side_S transistor 304 has a higher level than the supply voltage difference cc of the boost signal Vbh. The dust drop is close to zero. Thus, the supply voltage - = f level - its adjustment procedure is subject to the low UVL (L0N electrical low UVLQJ) FF voltage of the _ unit 301 - and the supply reliance Vex can be used to produce the match One of the gate control signals required by the minimum gate voltage is still level. The series combination of the dynamic resistor 306 and the holding capacitor 3〇7 is between a main input voltage vIN and the reference ground to provide a starting current path of the hybrid voltage Vcc. In order to meet the requirements of the above-mentioned switching power supply, the mW standby requirement and the requirement of 3 seconds, the resistance of the starting resistor can be greater than the typical value, for example, due to the low UVLQ-QN power of the UVLG unit and The arrangement of the low voltage 'the holding capacitor 3Q7 can still be specified at this typical value V. Under the condition of 4 Ω, the power consumption of the starting resistor 3〇6 is about 35mW when the voltage is 37. Due to the low UVL()J)n voltage, the starting touch can meet the requirement of 3 seconds "201121215". The main circuit 308 is used to store magnetic energy when the main side nm 〇S transistor 309 is turned on, and is provided by the main input voltage Vin. The main side NMOS transistor 309 has the gating signal yG coupled thereto. One of the gate terminals is coupled to one of the main side coils 308 and is coupled to the source terminal of the current sensing resistor 31A to be composed of the main side coil 3〇8 and the current sensing resistor. The main-side current path acts as a switch. The current-sense resistor 310 is coupled between the source terminal of the main-side NM〇s transistor 3〇9 and the reference ground to carry the current of the main-side current. The current sensing signal Vcs is generated. Similarly, since the power consumption of the starting resistor 3〇6 is greatly reduced, the starting period can also meet the requirements. Therefore, the other preferred embodiment of the present invention can solve the switching type. The power supply application is used to reduce the problem of standby power consumption. Moreover, the preferred embodiment of the present invention provides The voltage should be lower than the conventional one, and the miscellaneous controller can also follow

Therefore, through the implementation of the preferred embodiment of the present invention, a switching power supply using a random voltage-to-voltage ratio (4) can be presented. The design of the present invention allows the use of a large starting resistor without violating the requirements during start-up and reducing the voltage level of the master side of its gate control signal, so the present invention does overcome the shortcomings of conventional circuits. It is a preferred embodiment, and the technical idea of the present invention is changed or modified in part, and the person who is familiar with the skill of the fourth (four) skill is expected to pay attention to the case. For example, the 4-level Dickson charge pump circuit can be replaced by a Dixon charge pump circuit or other charge pump circuit, and the standby power consumption is not limited to 100 mW. a in the 3 summary of the case 'this case regardless of the purpose, means and efficacy, is displayed in the technical characteristics of the province, and its first invention is practical, but also in the different patent requirements, please ask your review board to observe, and pray early曰 Granting a patent = society, real feelings.俾嘉惠 i S,] 12 201121215 f Schematic brief description] Figure 1 is a schematic diagram showing a main circuit block diagram containing a conventional power application Λ3 one of the touch controllers A block diagram of a main side circuit of a low-to-control-switching power supply application in accordance with a preferred embodiment of the present invention. The UVLO ptw' ride does not include the low voltage PWM control of the preferred embodiment of the present invention - the main side circuit block diagram of the switched power supply application. Fig. 4 is a diagram showing the boosting circuit of the present invention in accordance with the present invention.

[Main component symbol description] PWM controller 1〇〇UVLO unit ιοί, 2〇1, 3〇1 PWM unit 1G2, 202, 302 NMOS transistor 103, 1〇4, 1〇8, 2〇4, 2〇8 , 3〇4, 3〇5, 3〇9, 4〇14〇5 resistors 105, 1〇9, 205, 209, 306, 310 capacitors 106, 206, 307, 406-410 main side coils 107, 207, 308 Low UVLO voltage pwm controller 2〇〇, 300 PMOS transistor 2〇3 booster circuit 303 inverter circuit 411 13

Claims (1)

201121215 VII. Patent application scope: 1. A low UVLO voltage PWM controller for a switching power supply application, having a power supply terminal coupled to a main input voltage by a dynamic resistor and coupled by a capacitor Connected to a reference ground, and an output terminal coupled to a gate terminal of a main-side transistor, wherein the main-side transistor requires a minimum gate voltage to operate: the low-UV0 voltage PWM controller includes: μ a UVLO unit for performing a hysteresis comparison with a UVL0-0N voltage and a UVL0_0FF voltage on one of the power supply terminals to generate a uniform energy state And a control state of the disable state, wherein the UVL〇_〇FF voltage can be as low as ^=gate voltage; _ a PWM unit is enabled to generate a PWM when the control signal is in the enable state An apostrophe, and the PWM signal is disabled when the control signal is in the disabled state; and a driver stage having a -PMGS transistor to lightly connect the PWM signal by its gate terminal, a source terminal coupling The supply voltage is coupled to the output terminal in an extreme. 2. The low UVLO voltage PWM controller of claim 1, wherein the driver stage further has a _s transistor to couple the pwMf number by a gate terminal thereof, and a source terminal is coupled to the reference Ground, and one is not extremely lightly connected to Q 3. For example, the low-voltage voltage-controlled main-side electro-crystalline system of the item i of the patent scope is an NM0S transistor. ^ 4 · The low UVLO voltage PWM controller of claim 1 of the patent scope, wherein the switching power supply application is AC to DC conversion. 〃 〇Λ 5. A low UVLO voltage PWM controller for a switching power supply application, with a power supply terminal, which is connected to the battery by - electric shock and dream-capacitance_to-reference The ground 'and-output terminal, the chick to the main side of the gate ^ the gate knows 'the main side of the transistor requires - the minimum gate voltage to operate 'the low UVL0 voltage PWM controller includes: $ a UVL0 a unit for performing a hysteresis comparison with a 201121215 UVL0_0N voltage and a UVL0_0FF voltage to supply a voltage to one of the power supply terminals to generate a control signal having a consistent state and a disabled state, wherein the UVL0_0FF voltage can be as low as The minimum gate voltage; a PWM unit is enabled to generate a PWM signal when the control signal is in the enabled state; and is disabled from generating the PWM signal when the control signal is in the disabled state; a voltage circuit for generating an inverted signal of the PWM signal, wherein a south level of the inverted 4s is south of the supply voltage; and a driver stage having an NM0S transistor for a gate terminal thereof Lightly connect the anti-rude signal An output terminal is coupled to the output terminal, and a source terminal is coupled to the output terminal. 6. The low UVL 〇 voltage pWM controller of claim 5, wherein the driver stage further has an NMOS transistor to couple the /pwM^ by a gate terminal thereof, and a source terminal is lightly connected to the Reference ground, and one is not extremely lightly connected to the output. 7. The low UVL0 voltage PWM controller of claim 5, wherein the main side electro-emissive system is an NM0S transistor. . 8. A low UVL0 voltage PWM controller as claimed in item 5 of the patent application, wherein the switching power supply application is an AC to DC conversion. , ^ 9. Low UVL 〇 voltage pWM control as in claim 5 of the patent scope The boost circuit has a charge pump circuit. D ', 中中 ▲ ^ As in the patent scope of the ninth item of the low UVL 〇 voltage pWM controller, 5 Hai charge system is a Dixon charge pump circuit. Eight 15