TW201126535A - 3D memory array with improved SSL and BL contact layout - Google Patents

Abstract

A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. the conductive lines conform to the surfaces of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips and the conductive lines. The memory element are programmable, like the anti-fuses or charge trapping structures. in some embodiments, the 3D memory is made using only two critical masks for multiple layers. Sone embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-density memory device, and more particularly to a memory device having a plurality of planar memory cells to provide a three-dimensional array. [Prior Art] When the critical size of the device in the integrated circuit is reduced to the limit of the usual memory cell technology, the designer turns to the multi-stack plane technology of the memory cell to achieve a more uniform storage density, and each bit Lower cost. For example, thin film transistor technology has been used in charge trapping memory, see for others. A multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory", IEEE Int'l Electron Device Meeting, December 11-13, 2006; and Jung et al.'s paper "Three Dimensionally

Stack NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS structure for Beyond 30nm

Node", IEEE Int'l Electron Device Meeting, December 11~13, 2006. In addition, the 'intersection point array technology has also been applied to anti-fuse memory, see the paper by Johnson et al."512- Mb PROM with a Three Dimensional Array of Diode/Anti-fuse Memory Cells", IEEE J of

Solid-state Circuits, vol. 38, no. 11, November 2003. In the design described by J〇hnson et al., multi-layer word lines and bit lines are used, which have memory elements at the parent point. The § element includes a P+ polycrystalline sunset pole connected to the word line, and an n+ polysilicon cathode connected to the bit line, and the cathode and anode are separated by a reverse soluble filament material. In the process described by Lai, Jung, et al., each memory layer uses 201126535 multiple key lithography steps. Therefore, the number of critical lithography steps required to fabricate this device will be a multiple of the number of memory layers used. Therefore, although higher density can be achieved by using a three-dimensional array, higher manufacturing costs also limit the scope of use of this technology. Another technique for using vertical anti-gate memory cell structures in charge trapping memory has also been published in Tanaka et al. "Bit Cost Scaleable Technology with Punch and Plug Process for Ultra High Density Flash Memory ", 2007 Symposium on VLSI Technology Digest of

Technical Papers, pp. 14~15, June 12-14, 2007, described. Among the structures described by Tanaka et al., include a multi-gate field-effect transistor structure having a vertical channel similar to the anti-gate operation, using a SONOS type charge trapping memory cell structure for each A storage location is created at a gate/vertical channel interface. The memory structure is based on a columnar semiconductor material of a vertical channel to form a multi-open memory cell. The selection gate of the full ^ is close to the substrate, and - the higher selection gate is on the upper = section: the plane electrode layer is not rr, not #2, cost. However, it is still necessary for each vertical memory cell, and the 鼗^(4) multi-layer junction control is limited by the factors such as the vertical channel conductivity, the stylization used, and the erase operation. . The stack used has this three-dimensional _, memory cells and interconnects can be _ high-density mode stacking, 1 bracket; a low manufacturing cost of the three-dimensional integrated circuit memory is sinned very small memory components and occupy a small area of interconnection Line and contact. 201126535 SUMMARY OF THE INVENTION The technique described herein is a three-dimensional plate; a plurality of strips of semiconductor material; 5^^' having a plurality of wires after the integrated circuit substrate; and a memory element. The Changqing stack has a ridge shape and includes at least two positions—the e-sharp stacking and sharing the plurality of plane joints=the strip material is connected by the stepped structure and the φ line is the same position, so Steps: at the middle end. Different from the meaning of the guiding material, connect different layers t _ private =. The intersection area of the three-dimensional array is established by forming a three-dimensional array on the surface of the semiconductor material and the plurality of wires. The component is in the intersection region, and the three-dimensional memory cells are accessible via the elongated semiconductor material and the plurality of wires. The number = also reveals a three-dimensional memory shock 'with an integrated circuit substrate; a complex strip of semiconductor material stack; a plurality of multiple wires; a memory of a plurality of conductive conformal structures. The plurality of stacks have a ridge shape and include at least two elongated semiconductor materials separated by an insulating layer to form different planar locations in the plurality of planar locations. The long strip of semiconductor material sharing the same planar position in a plurality of planar locations is exhausted. The 4 or more plurality of wires include the first, second, and third plurality of wires. The first plurality of wires are arranged orthogonal to the plurality of stacks and are stacked with the 201126535 such that a surface of the strip of rotating material forms a three-dimensional array of intersections with the complex conductor points. Dropping in the intersection region, the memory cells of the three-dimensional array are accessible through the strip of semiconductor material and the plurality of wires. Each conductive conformal structure is on the plurality of stacks. In some embodiments, the tandem select line is disposed on the plurality of stacks via the second plurality of conductors == lines and the conjugated ridge structure and the conductive plurality of conductors, the semiconductor The materials are parallel. Each of the second plurality of conductive strips has a different electrically conductive conformal structure in the electrically conductive conformal structure electrically connected to the first plurality of wires and the third plurality of wires. Above the Wei line] a plurality of wires are parallel to each of the third plurality of wires. The different wires of the first plurality of wires are connected. In some embodiments, the second plurality of wires are The third plurality of wires 'there are a total of the column selection signal electrically connected to the non-stone / nursery rhymes 1 b? * also describes the roots based on the energy gap Wei (four) · oxygen bee nitride chapter 'will be in the next mode [Embodiment] The following embodiments of the present invention are described. 7 201126535 Figure 1 shows a schematic diagram of a 2x2 memory cell of a three-dimensional programmable resistive memory array. The filling material is omitted in the figure to show the long strip of semiconductor material constituting the three-dimensional array. Stacked and orthogonal wires. In this figure, only two planes are shown. However, the plane, the number "I is expanded to a very large number. As shown in the figure, the memory array is formed with one The insulating layer 10 is separated by a column πμ2, 13 ::=: 21, 22, 23, 24 of the integrated circuit substrate above the semiconductor or other structure (not shown) underneath. The stack is ridged: γ in the figure The axial direction extends, so the long strip of semiconductor material (4) 7 is configured as a bit line and extends out of the substrate. The long strip semiconductor of your main lion 13 can be used as the bit line on the first memory plane, and the length: + conductor material 12, 14 can be used as the bit layer memory on the second memory plane (4) 15 'for example, anti-drawing silk (four), in this example ^ 匕 over the long strip of semiconductor material, and in other examples, to 20% Long strip of semiconductor material a plurality of wires 16, 17 a strip of semiconductor material stacked orthogonally. a plurality of wires 16, 17 a plurality of strips of semiconductor (four) stacked lion's surface, and filled into a defined trench (for example, 2G), and In the strip half 3:, 2 4 隹 隹 与 与 复 复 复 16 16 16 16 16 16 • • • • • • • • • • • 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 Shape == Line 16, the upper surface of the crucible. The rice (four) hair guide can contain, for example, an anti-fuse material such as dioxo, oxynitride, or other cerium oxide, which is a thickness of ==. Others can also be used. The opposite semiconductor material of the two-conductivity type (for example, P-type). The wire 16, the force 201126535 is a half having a second conductivity type (for example, n-type), and the long semiconductor material n~14 can be $^ Lines 16, η may use a heavily doped n+ type of multiple turns: 4:: The width of the material 1 must be sufficient to provide the depletion = domain required for diode operation. Therefore, the memory cell includes a PN junction formed between the three-dimensional intersection of the long polycrystalline stone and the wire rectifier, and the PN connection has a -programmable inverse layer in the cathode pole 1 embodiment. _ programmable resistance memory material, package =

, a metal oxide oxide or a long strip of semiconductor material above the oxide field. Such (4) can be (4), the formula is = except for the = operation of the bit in a memory cell. The ~^ figure shows a cross-sectional view of the 6-remembered cell-Χ plane of the conductor 16 and the strip of semiconductor material. The active regions 25, 26; ^ are on both sides of the semiconductor material 14 and between the wires 16 and 14: 14. In the natural state, the anti-drawing memory material is in the sense of resistance. After Cheng Chengqian, this (4) silk memory = = one of the active areas 25, 26 in the memory material 4: = low resistance _. In the implementation described here, each - t ^ '.ml i; ; #, vL - map in the wire 16, 17 and the strip of semiconductor material 〗 4 intersection: at the mouth / mouth 5 忆 χ χ γ γ plane profile Figure. The current path of the conductor material section 14 in the figure. The flow of the sub-flow is shown by the solid line in Figure 3, the self-contained wire Μ 14 (Lu: strip of semiconductor material 14, and along the strip of semiconductor material:;, then, the amplifier, at the sense amplifier The measurement uses a state of about 1 nanosecond: hidden. In a typical embodiment, the oxidized stone is used as an anti-spike material, and the application is carried out by using the in-wafer control circuit of the figure 28 201126535. A 7 volt pulse and a programmed pulse having a pulse width of about 1 microsecond, and the read pulse is applied with a pulse of 1 to 2 volts and a configuration related pulse width using the in-wafer control circuit of Fig. 28. The pulse can be much shorter than the stylized pulse. The two memory cell planes, each with six cells, have an anti-fuse between the cathode and the anode.

The plane is indicated by the diode of the table. The two memory cells 16 know the first and the first _ of the word line WLn and the second word line WLn+ 与 and the bit lines BLn, BLn+1, and BLn+2 54 and 55, 5, respectively. ^, the third strip of semiconductor material stacks 51, 52, 53 and the first level of the memory cell define the first and second layers of the array. The memory cells 30, 31 are supported on the strips of semiconductor material stack 52, 3 to 3, and the memory cells 32 on the strips of semiconductor material stack 54, and the second stack of memory cells. Memory cells 3 4, 3 5. The memory cells 4G, 41 are included on the elongated semiconductor material stack 51, 42, and the memory cells 45 on the county strip semiconductor material stack 53. As shown in the figure, the memory cell 4 4 on the semiconductor material stack 5 5, the vertically extending 6 〇], and the ^6 line are used as the word line WLn, which includes the material in the trench corresponding to 〇-2, 60-3 and An exemplary strip semi-conducting between the stacks in Figure 1 is a stacking of the conductors 6〇 with 3 in each plane as described herein. An array can be implemented as very high megabytes of megabytes to form a close-up or reach-by-wafer. A representation of one of the eight-dimensionally programmable resistive memory arrays of the 2x2 memory cell portion and a stacking of the long strip of semiconductor material constituting the opposite pattern of the conductors having the filling material in the figure In the drawing, only two layers are displayed. However 10 201126535 The number of layers - people can be extended to a very large number. As shown in Fig. 5, the memory array is formed on an integrated circuit substrate having an insulating layer 11 over its lower body or other structure (not shown).

The stack 1U, U2, 丨 114 comprising a plurality of strips of semiconductor material are separated from one another by insulating materials 121, 122, 23, 124. This stack is ridge-shaped and extends along the γ-axis direction in the figure, so the semiconductor materials #111 to 114 can be configured as bit lines, and the board. The long strip of semiconductor material m, 113 can be used as a bit line on the first memory layer, and the long strip of semiconductor material 112, 114 can be used as a bit line on the two memory planes. The insulating material 121 between the elongated semiconductor materials U1 and 112 in the first stack and the insulating material 123 between the elongated semiconductor materials 113 and 114 in the second stack have an equivalent oxidation of about 4 〇 or more The layer thickness (E0T), wherein the equivalent oxide thickness (Ε〇τ) is the thickness of the insulating material multiplied by the thickness of the oxide layer converted by the ratio of the dielectric constant of the tantalum oxide to the insulating layer. The term 'Jonami' as used herein is the result of an order of magnitude change of about 丨〇% in a typical process of such a device. The thickness of this insulating layer has an important influence on reducing interference between adjacent memory cells in this structure. In some real cases, the equivalent oxide thickness (EOT) of the insulating material can be as small as 3 nanometers and still have sufficient isolation between adjacent layers. #层层材料1, for example, a dielectric charge trapping structure Wrapped over the elongated semiconductor material in this example, a plurality of wires 116, 117 are orthogonally stacked with the strips of semiconductor material. The plurality of wires 116, 117 have a stack of thin semiconductor materials. Surface, and filled into the trench defined by these stacks (for example, 120), and define a multilayer array where the intersection of the long semiconductor material m~114 stack and the plurality of wires ι6, Η? Interface area. One layer 11 201126535 Metal halides (such as tungsten telluride, cobalt telluride, titanium telluride) 118, 119 are formed on the upper surface of a plurality of wires 116, 117. 'Nano-line gold oxide half The transistor pattern is also configured in this manner by providing a channel region of the nanowire or nanotube structure over the wires 111~U4, as Paul et al. "Impact 〇fa ΡΐΌα = Variation on Nanowire And Nanotube Device Performance " IEEE Transactions on Electron Device, Vol. 54, No. 9, September 11~13, 2007, which is incorporated herein by reference. Thus, a SONOS type memory cell configured to be a three-dimensional array of anti-gate flash arrays can be formed. The source, the immersion, and the tong are formed in the broken strip of semiconductor material 111-114. The memory material layer 115 includes yttrium oxide (the tunneling dielectric layer 97, the ytterbium nitride (N) charge storage layer%, oxidation矽 (Ο) blocking dielectric layer 99 and polysilicon (s) wires 116, U7. The elongated semiconductor materials 111~114 may be p-type semiconductor materials and the wires 116, 117 may use the same or different semiconductor materials (eg type For example, the elongated semiconductor material lu~114 may be a polycrystalline germanium or a p-type epitaxial single crystal germanium, and the conductive line 116 may be used with a relatively indifference P+ polycrystalline stone. Alternatively, long The strip semiconductor materials 1U to 114 may be n materials and the wires 116, 117 may use the same or different conductive materials (eg, Ρ+type). This n-type semiconductor material arrangement ^ buried-channel depletion charge trapping memory For example, + ί (4) bulk material (1) ~ 114 can be n-type polycrystalline germanium, or: type ^ crystal germanium' and wires 116, 117 can use relatively concentrated doping | crystallization wafer. Typical n-type long strip semiconductor material The sound of the 1019/cm3 eve is around 1〇1 7/cm3 to paste (4) ιϋ/ use n-type long strip of semiconductor material for a good choice of joints, because it can improve the conductivity along the anti-gate core 201126535 and thus allow higher read current Therefore, the field-effect electricity 曰μμ is formed at the intersection of the three i array 4: the medium cell t has a charge semiconductor structure of the length of the semiconductor material and the conductivity; the thickness of the nanometer stack is also about 25 nanometers. The device of the Bode buckle/the ridge-shaped stack) has a capacity of tens (1 〇 12) bits in a single wafer, f, for several tens of layers (for example, thirty layers (four). The memory material layer 115 can be used for whites, and the energy gap engineering_3 storage structure can be used.

Generation, which includes the dielectric through layer 97, and the reed owing to the gate; the storage structure is taken from the penalty. The force of a tube is shielded from the human body. At 0V bias, there is an inverted U. In the case of (4), the multilayer wear layer includes a first layer of tunnel layer, and the second layer is called a band compensation layer and The three layers are said to be in the example, the hole _97 includes dioxin _ formed on the side surface of the long material 'which can be formed by using, for example, on-site steam generation g, ISSG), and selectively utilizes post-deposition nitric oxide annealing Or nitriding by depositing a square of nicotine-nitrogen oxide. The thickness of the cerium oxide in the first layer is less than 20 angstroms, and preferably less than angstroms, and in a representative embodiment is 10 -12 angstroms. In this embodiment, the band compensation layer comprises a tantalum nitride layer on top of the tunnel tunnel layer, and the system utilizes a technique such as low pressure chemical vapor deposition (1: >): Dichlorosilane (DCS) was formed at 680 ° C with an ammonia precursor. In other processes, the bandgap compensation layer includes niobium oxynitride, which is formed using a similar process and a nitrous oxide precursor. The thickness of the tantalum nitride layer in the energy compensation layer is less than 30 angstroms, and preferably 25 angstroms or less. In this embodiment, the 'isolation layer comprises the ruthenium dioxide layer on the band compensation layer' and is formed by means of LPCVD high temperature oxide HTO deposition. The thickness of the ruthenium dioxide layer in the spacer layer is less than 35 angstroms, and preferably 25 angstroms or less. Such a three-layer tunneling dielectric layer produces an "inverted U" shape of the valence band energy 13 201126535 - the first- and semi-conducting so that the electric field is sufficient to induce the hole to pass through the and the conductor body or the strip of semiconductor material a thin region between the interfaces, complex: wear with: =; _ energy level 'to effectively eliminate the valence band of the inverted u shape after the first -, can also achieve the electric field-assisted high-speed electrical memory extracellular electric field does not exist or for Other operational purposes (such as the recording of a neighboring memory cell) or the induction of a small electric field. 'Efficient · Charge loss through the composite electrical ageing layer structure. The memory material layer 115 comprises an energy gap engineering (BE). The thickness of the dioxide layer containing the first layer of the 'I electrical layer' is less than 2, and the thickness of the gas layer is less than 3 nm and a second. The layer of the dioxide dioxide has a dryness of less than 4 nanometers. In the embodiment, the composite wear-through dielectric layer comprises ultra-thin oxidized (tetra) 〇1 (for example, 15 angstroms or less), and the ultra-thin nitriding pin is called, for example. Less than or equal to 30 angstroms) and ultra-thin oxidized stone layer 〇2 (for example, less than or equal to 35, composed) 'And it can be combined with the interface of semi-conducting or long-semiconductor materials - a compensation of 15 angstroms or less 'increased the price of about 26 electron volts U. With low-cost band The region (high hole tunneling) and the high conduction band energy level '02 layer can separate the N1 layer from the charge trapping layer by a second compensation (eg, from about 30 angstroms to 45 angstroms from the interface). Farther, it is enough to induce the hole penetration, and the electric field can increase the valence band energy level after the second place, so that it can effectively eliminate the hole penetration barrier. Therefore, the 02 layer does not rigorously interfere with the electric field-assisted hole penetration. _In addition, the ability of the I-transfer dielectric structure to lose charge in a low electric field can be increased. # 5 The charge trapping layer in the material layer 115 in this embodiment includes a tantalum nitride layer having a thickness greater than 50 angstroms, including examples. In other words, tantalum nitride having a thickness of about 7 angstroms is formed by LPCVD. The invention can also use other electricity 14 201126535 including, for example, Nitrox Oxide (Six〇yNz), high inclusions Chaos w 3 stone eve of the oxide, including the capture layer of embedded nano particles, etc. Shi Xi, memory The barrier dielectric layer in the material layer 115 is yttrium oxide having a thickness greater than 5 angstroms, and is included in the embodiment of the formula 9 〇, 1 is a wet oxidation process for converting nitrogen cuts. The high temperature oxide (HTO) or LPCVD deposition can be used to use other barrier dielectric layers. In a representative embodiment, the hole penetrates the accompanying shot dioxide U ang; The layer of tantalum nitride layer has a thickness of 20 angstroms and the thickness of the lanthanum oxide layer is 25 angstroms; the nitrogen of the charge trapping layer is 270 angstroms; and the resistive dielectric layer can be an oxide of 9 angstroms thick. The inter-electrode material of U7 may be P+ polycrystalline stone (the work function is 5 丨 ^ ^ 116, and the sixth figure is shown on the wire 116 and the strip of semiconductor material). The formed charge traps the memory cell along the memory cell ζ χ χ plane parent meeting. The active regions 125, 126 form a cross-sectional side of the elongated semiconductor material 7 and are implemented by two of the wires 116 and the elongated semiconductor material U4, each of the memory cells being double "曰: having two active regions 125, 126 Forming strips half, 114 on both sides. Conductor material, Figure 7 shows the charge trapping memory cells in the wire 116 and the strip of semiconductor material 114 along the memory cell χ γ 平 人 g / 4 14 to the sense amplifier At the sense amplifier, the conductor can be in the state of the memory cell. “Μ里·· indicates the wire 116 as the word line, 〗 17 asks 128 15 201126535 The miscellaneous state does not need to be connected to the channel under the word line The doping patterns of the regions are different. In this "no junction" embodiment, the charge trapping field effect transistor can have a p-type channel structure. Further, in some embodiments, source/drain doping can be utilized after defining word lines. Automated alignment of the implants is formed. In an alternate embodiment, the elongated semiconductor materials ηι 114 may use a lightly doped n-type semiconductor body in a "jointless" arrangement, resulting in formation that can operate in a depletion mode. Buried channel FET, this charge trap has a natural offset to a lower threshold voltage distribution. Figure 8 shows two memory cell planes, each with 9 charge-carrying memory cells arranged in reverse And m is - the representative of the cube includes a plurality of planes and a plurality of word lines. The two memory cells are made up of 160, 161 and 162 as sub-line WLn, WLn+1 and WLn+2. Chu μ: stacking of bulk materials. The first plane of the first, second and third strips of semi-conductive memory cells includes memory cells 70, 71 and 72 in the string: '7 = above the stack of long strips of semiconductor material , and memory cells: on top of the stack, and memory cells 76, 77, and 78 The == is wide' and is located on the stack of long strips of semiconductor material. The second plane of the memory cell and the bottom plane of the cube are opposite to the gate train. The way of the face is in the Yanchang/pan The wire _ of the wire I includes a vertical material to transfer the 70, 73, and 76 of the trenches of the trench 120 between the stacks. (9) Zhuo Qianzhong Zhongji has arranged the transistor in this arrangement. 85, (10) and 89 are connected between 16 201126535 respective anti-gate sequence and bit line BLn. Similarly, in this arrangement, similar serial selection transistor connections in the bottom plane are between respective anti-gate strings Columns and bit lines BL0. The string selection lines 106, 107, and 1〇8 connect the gates of the tandem selection transistor between the ridges in each of the planes of the cube in a row direction, and provide strings in this example. The column selects the numbers SSLn-1, SSLn, and SSLn+Ι. In this arrangement, the block selection transistors 9〇~95 arrange the other side of the series and are used to select the opposite of the -selection cube.

J is, for example, a reference source coupled to the ground (example shown in item 23). f In this example, the ground selection line GSL is connected to the block selection transistor 9〇~%, and a mode 2 similar to the wires 160, 161, and 162 can be used. In some embodiments, the tandem selection transistor and the block selection 2 crystal can use the same dielectric stack as the gate oxide layer in the memory cell. In other cases, the patch can be used as a typical material without memory material. 2. In addition, the length and width of the channel can be designed to withstand the proper switching function of these transistors. = Figure shows - an alternative structure diagram similar to Figure 5, in [2 structure! 7 uses the same reference numerals, and is not described again"; the difference between the figure and the fifth picture is the insulation layer 110 The surface of the surface and the side surface (4) of the elongated semiconductor material 113, m is then taken out at the gate of the wire (e.g., (10)) as the word line. Therefore, the memory material layer U5 is in the word

St or split etching does not affect the operation. However, the general etch described at a certain junction forms a dielectric charge trapping structure through the memory layer 丨5. ^ 10 shows a memory cell similar to Figure 6 along the ζ_χ平

Surface map. The structure of the illusion 0 and the 6th is completely the same as the structure of the fifth figure 201126535. Fig. 11 is a cross-sectional view showing the memory cell of the i-like figure 7 along the χ γ plane. The different portions of Fig. 11 and Fig. 7 are removed from the sibling material in the regions 128a, 129a and 13a of the side surface (e.g., 114 Α) of the elongated semiconductor material U4. Active regions 125, 126 are formed on both sides of the elongated semiconductor material 114 and between the conductors 116 and the elongated conductor material 114. The figures 12 through 16 show a basic process stage flow diagram for implementing a three-dimensional memory array as described herein, using only two patterned mask steps that are critical to the alignment of the array. In Fig. 12, the structure after interleaving the deposition insulating layers 210, 212, 214 and the semiconductor layers 211, 213 is shown. For example, the semiconductor layer can be formed on the array region of the wafer using the fully deposited doped semiconductor. Depending on the embodiment, the semiconductor layer may use a polycrystalline or insect crystal single crystal having an n-type or P-type doping. The interlayer insulating layers 210, 212, 214 may be, for example, germanium dioxide, other tantalum oxide or tantalum nitride. These layers can be formed in a number of different ways, including techniques well known in the art for low pressure chemical vapor deposition (LPCVD). Figure 13 shows the result of a first lithographic patterning step for defining a plurality of ridge-like strips of elongated semiconductor material 25, wherein the elongated semiconductor material is comprised of semiconductor layers 2U, 213 and is comprised of an insulating layer Separated by 210, 212, and 214. Ditches with deep and very high aspect ratios can be formed between multilayer stacks, which use a lithography-based process and apply a carbon-containing hard mask and reactive ion etching. The A #14B diagram respectively shows a programmable resistive memory structure including, for example, an anti-shock memory cell structure and a programmable charge trap memory structure including, for example, a SONOS type memory cell structure. A cross-sectional view of the next stage in the example. Figure 14A shows the results of a comprehensive deposition of a memory material 215 in an embodiment of a programmable resistive memory structure comprising a single layer of anti-solving filament memory as shown in Figure 1 . Alternatively, an oxidizing process can be performed without the use of a full deposition to form an oxide on the exposed side of the elongated semiconductor material, wherein the oxide is used as a memory material.

Figure 14B shows the result of a comprehensive deposition of a memory 315 embodiment of a programmable resistive memory structure comprising a multilayer charge trapping profile as shown in Figure 4. The multilayer charge trapping structure includes a layer 397, a A charge trapping layer 398 and a blocking layer 399. As shown in Fig. 14B of the second jaw, the memory material layers 235 and 315 are stacked in a ridge-like strip of long semiconductor material (the 25th in the 13th figure). The step of filling the high aspect ratio trench The subsequent junction is ί, for example, having n-type or p-type doping, and the wire 'for the wire' is deposited to form the layer 225. Further, in the case of using polycrystalline eve, the layer-wei 226 Formed on layer 225. Polycrystalline branching such as Low Turbology Vapor Deposition (LPC VD) is used in this embodiment to fill the ridge-like stack: making it very narrow and deep Aspect ratio (four) nanometer number: 16 shows the result of the second lithography patterning step, and the second step is to use a single curtain to define the ridge-like stack in this array. The polycrystalline stone can only pass through the stone or the nitrogen The height selectivity is determined by the pair and the oxidation process will stop at the bottom insulating layer 21 1. 1 member of the strip of semiconductor material in the -decoding structure is connected to the schematic diagram of the way 19 201126535 together, and shows a selective cloth Planting step. The illustration in Figure 17 is rotated 90 degrees on the z-axis so that The Y and z axes fall on the plane of the paper, as opposed to Figures 1 and 16, where the parent and the 2 axis are on the plane of the paper. In addition, the insulating layer between the ridged stacks of the long semiconductor material' Removed from the image to show more structural details.

A multilayer stack is formed over the insulating layer 410, including a plurality of wires 425-1, ... 425-n-1, 425-n ridged ridge-like stacks, and is used as word lines WLn, WLn-1, ... WL1. The plurality of ridge-like stacks include strips of semiconductor material 412, 413, 414 that are coupled to other strips of semiconductor material in the same plane via extensions 412A, 413A, 414A. In other embodiments shown later, the elongated semiconductor material 4 forms an extension of the extension of the stepped structure. The elongated semiconductor material is bonded to a plurality of long semiconductor materials stacked in a plurality of mountains via the extensions 412A, 413A, and 414AS along the X-axis direction. In addition, as shown below, the extensions 412A, 413A, 414A extend beyond the edges of the array and are arranged to interface with decoding circuitry within the array to select a plane. These delays

2:13, ΓΑ can be defined in a number of ridge-like stacks _ temple or it is patterned. In the embodiment shown later, the extension of the structure terminates the edges of the elongated semiconductor material ς array. However, it is necessary to extend the super a singularity from the long semiconductor to the 425_n meeting. In more detail, the transistor of the crystal 450 forms a gate between ^ 412, 413, 414 and the wire 425]. The production, + strip conductors 'long strip semiconductor material (such as 413), the crystal gate structure (such as 429) is in the channel region defining the wire 42 ^: patterned. A layer of telluride 426 is formed along the upper surface of the 1 耆 wire at the beginning of 1 425-n and then 20 201126535 Ϊ:2:. The memory material layer 415 can be used as a gate of the transistor array as a selection gate and a decoding circuit block to select rows along the ridge-like stack. The process of 40--n-select-1 includes forming a hard mask 401] onto a plurality of wires, and a hard mask and a side on the gate άτ. This hard mask can be formed using a relatively thick oxide to block the ion implanted material. After the hard mask is formed, ion implantation can be performed to increase the elongated semiconductor material 412,

The doping concentration in 113b, =14 and extensions 412A, 413A, 414A, and thus = low resistance along the current path of the elongated semiconductor material. By using the control implant energy, the implant can result in a long strip of semiconductor material that passes through the bottom strip of semiconductor material 412' and each of the stacks. Fig. 18 is a diagram showing the next stage of manufacturing the memory array shown in Fig. 17. The same reference numerals are used in the figure, and the description will not be repeated. The structure shown in Fig. 18 shows the result of removing the hard mask to expose the plurality of wires 425-1 to 425-n and the germane 426 over the gate structure 429. After an interlevel dielectric layer (not shown) is formed over the array, the via holes are formed up to the upper surface of the gate structure 429 and, for example, plugs 458, 459 using tungsten are filled therein. The upper metal lines 460n, 460n+1 as the serial selection line SSL are patterned and connected to the row decoding circuit. A three-dimensional decoding circuit is constructed in the manner of a picture, using a word line, a bit line, and a string selection line SSL to access a selected memory cell. See the title "Piane Decoding Method and Device for Three Dimensional"

U.S. Patent No. 690,694 to Memories. To program a selected antifuse type memory cell, the selected word line is biased to -7V in this embodiment, and the unselected word line can be set to 0V. The selected bit line can also be set to 0V, the unselected bit line 21 201126535 can be set to 0V, the selected string selection line can be set to -3.3V, and the unselected string selection line can be set to 0V. Reading a selected memory cell, in this embodiment, the selected word line is biased to -1.5V, the unselected word line can be set to 0V, and the selected bit line can also be set to 0V, and the selected bit is not selected. The line can be set to 0V, the selected string selection line can be set to -3,3V, and the unselected string selection line can be set to 0V. Figure 19 provides a top view of the memory cell layout, including the string selection line. And bit lines 470-472 over a ridged stack comprising strips of semiconductor material 414 and wires 425-n as word lines. These word lines extend to the column decode circuit. A contact plug (eg, 458) is connected to the gate structure to select a length Semiconductor material 414 to the upper series of select lines (eg, 460n). One may be referred to as a twisted layout, wherein the gate structures are shown in an alternately stacked manner such that the alignment boundary of the patterned contact plug 458 process can be Sharing along the row direction, thereby reducing the average spacing of the ridge-like stack layout. These string selection lines extend to the row decoding circuit. Figure 19 also shows the upper view of the memory cell layout, including the extension of the semiconductor material extension Connecting (e.g., 414 turns) to the portion of the bit line. As shown in the figure, the extension connection 414 extends beyond the array to the bit line. The via holes are also opened in an interleaved manner to expose the length in each of the planes of the array. The strip of semiconductor material is extendedly connected. In this example, the junction 481 is formed of a long strip of semiconductor material in a first plane, the junction 482 is formed of a long strip of semiconductor material in a second plane, and the junction 483 is The formation of long strips of semiconductor material in the three planes, and so on. Non-critical alignment can be used to form these contacts with large errors as shown in the figure. The degree of tolerance. The bit lines 470, 471, 472 are connected to the contacts 481, 482, 22 201126535 483 and parallel to the embodiment in which the tandem selection line extends, which has a stepped shape:: junction strip + conductor junction , does not need to extend beyond the array] ^ Figure 2 18 ® decoder layout of the memory cell in the example, the extra patterning step is used for the sunset, the real selection line (such as 491), the array of the month of the month ° $ as 425-D parallel. f mother a plane and wire (for example with a long semiconductor material = in tandem selection line 491 lyrics 40) 1: i 矽 490 can be formed on the string i selection, line 491. tandem selection line 491 Externally connected to the decoding circuit from the array. The upper azimuth element line 498 and the - touch structure state, the view (10) and the ^ connection 'and form in the via hole. Figure 21 shows the second figure in the 鲑民拼-吐田... Schematic diagram of the 121 T旳 decoding state layout, as shown in Fig. 2, the two semiconductors can form a strip of semiconductor material (such as the structure so that the alignment boundary is shared in a plurality of rows.

Ϋ45922 "J -^ ^ ;; V,:;5; 2 Boundary (if Hi into this structure layout can use non-critical alignment = 1: two? In this example, the string selection line extends to the flat I arrangement The line extends to the row decoding circuit and the sense amplifier, and the structure is configured to allow wider and parallel read and write ', and the 乍子凡线 extends to the column decoding circuit. 201126535 Guide] FIG. Displaying the strip of semiconductor material together to a decoding structure and displaying a hard selective implantation step. In Figure 22, it is rotated: in the paper, slightly different from Fig. 5, which is χ#σΖ The insulation between the two ridges (four) 4 towel strips and the body (four) is removed from the figure to show more detail.

The = column is formed over an insulating layer 110, which includes the via guides 655-1..., 625_n and a plurality of ridge-like stacked ciss as the word lines WLn, WLn, ... WL1. The plurality of ridges include strips of semiconductor material 612, sin, 6 丨 4 which are identical to the same plane; parallel other ridge-like stacked strips of semiconductor material are coupled via extensions 612A, 613A, 614A. The extensions 612, 613, and 14 of these elongated semiconductor materials are arranged along the X-axis direction and coupled to a plurality of strips of semiconductor material stacked in a stack. Moreover, as shown below, these extensions 612 A, 613 A, 614A extend beyond the edges of the array and are arranged to interface with decoding circuitry within the array to select a plane. These extensions 612A, 613A, 614A can be defined in a plurality of ridge-like stacks.

At the same time or prior to being patterned when the elongated semiconductor material and the insulating layer are formed. In some embodiments, the elongated semiconductor material extensions 612A, 613A, 614A have a stepped structure extension to terminate the elongated semiconductor material 612, 613, 614. These extensions 612A, 613A, 614A can be patterned while defining a plurality of ridge-like stacks. A layer of memory material 615 separates conductors 625-1 through 625-n from strips of semiconductor material 612-614 as previously described. For example, the transistor of transistor 650 is formed between elongated semiconductor material extensions 612A, 613A, 614 and conductor 025-1. Further, a transistor such as 24 201126535 transistor 651 forms the opposite side of the elongated semiconductor material to control the connection of the segments of the array to a common source line (not shown). In these transistors 650, 651, a long strip of semiconductor material (e.g., 612) acts as a channel for the device. The gate structures (e.g., 629, 649) are simultaneously patterned while defining conductors 625-1 through 625-n. This ground selection line gSL 649 can be arranged in a column direction and through a plurality of ridge-like stacked strips of semiconductor material. A layer of germanide 626 is formed over the upper surface of the wire and over the gate structures 629, 649. The memory material layer 615 can serve as a gate dielectric layer for the transistor. These transistors 650, 651 are connected to the decoding circuit as spring select gates to select segments and rows along the ridge-like stack in the array. < An optional process step includes forming a hard mask 601 - 1 to 601 - n over a plurality of wires, a hard mask 648 over the ground selection line GSL 649, and a hard mask 602 and 603 at the gate structure Above 629. This hard mask can be formed using relatively thick oxides or other materials that block ion implantation. After the hard mask is formed, n-type or p-type ion implantation may be performed 6 根据 according to the applied application to increase the doping concentration in the elongated semiconductor materials 612 to 614 and the extension 6 ΠΑ 6 6 及 and thus reduce The resistance along the current path of the strip of semiconductor material. In addition, if necessary, the doped impurities are opposite to the conductivity type of the bulk strip semiconductor material (eg, when the bulk strip semiconductor material is p-type, n-type ion implantation is performed) 'to follow the strip semiconductor The material forms a doped source/drain junction. By using the control implant energy' implant can result in the passage of the bottom strip of semiconductor material 612, and each of the elongated semiconductor material in the stack. In order to program a selected inverse gate flash SONOS type memory cell, the word line selected in this embodiment is biased to +20V, and the unselected word line can be set to, and the selected bit line is also Set 201126535 to ον, the unselected bit line can be set to ον, the selected string select line can be set to 3.3V, and the unselected string select line and the ground select line GSL can be set to 0V. In order to read a selected memory cell, the selected word line in this embodiment is biased to the read reference voltage, unselected

Take the word 70踝3 to fork the horse 6V, the selected bit line can also be set to IV, the unselected bit line can be set to 0V 'The selected string selection green can be set to 3.3V, but the serial selection is not selected The line can be set to 〇Vc Figure 23 to create a schematic diagram of the next stage of the memory array shown in Figure 22. The same reference numerals are still used in this figure and will not be described again. The structure shown in Fig. 23 shows the result of removing the hard mask to expose the strip conductors 625-1 to 625-n and the smear 626 over the gate structures 629 and 649. After an inter-layer dielectric layer (not shown above the array), the via hole is formed until the upper surface of the interrogation structure and, for example, a plug 665 using tungsten, filled with its dipole line 67g and formed adjacent to The end connection of the electro-optic L ^ material is selected. The upper metal lines 665, 666 are patterned to be connected to the row decoding circuit via the connection plugs 665, % gates and connections.

6M and "words ^" are placed on a ridged stack of wires 625·n including wire semiconductor material ^, spring. ίϊίΐ below = decoding circuit. In addition, the graphic also shows the common source line 670 located in the string and :!= is shown below the tandem selection line, ^ _ and also parallel to the word line. 661). You can use one: ^ earth side string selection line (for example, a twist layout, where the gate structure It is shown in Fig. 26 201126535, so that the patterned contact plug 665 can be made, and the alignment boundary (such as 665 Α) can be shared along the row direction, thereby extending the average spacing of the layout. These series selection lines are extended. Also shown in the upper view of the memory cell layout, the ^ body material extends the connection (eg, 614A) to the portion of the bit line. As shown in the extension connection 6MA extends beyond the array to the bit line. The second hole is also opened in an interleaved manner. Extending the connection of a long strip of semiconductor material exposed to each of the planes of the array. In this example, the long strip of semiconductor material in the first plane is formed by a long strip of semiconductor material in the surface of the junction milk, and the junction疋 苐 苐 苐 平 平The long strip of semiconductor material is composed, and pushed. In forming these junctions, non-alignment can be used to have a large tolerance of tolerance as shown at 680 in the figure. Bit line 6 Sichuan, π Bu junction 68 682, 683 are connected and parallel to the string selection line extension: to the ^ decoding circuit and the sensing release | | |. The embodiment shown later has a stepped structure to terminate the strip of the tantalum conductor, ... to be extended Exceeding the edge of the array. Figure 25 shows the cross-section of the 丫 and z-axis on the paper surface, which will extend the connection 612A~614A and the contact plug 681, 682. The upper orientation line 67G~672 is connected to the connection plug. ^ 68〗 The alignment boundary 68〇a, _ shows that the step is not very important 'it will not affect the density of the array. The reference number is shown in the same reference as before, and will not be shown in Figure 26. In contrast, the image of the flash array is similar to that of Fig. 23, which is slightly different from Fig. 23. In the example of the figure, 'Using an additional patterning step to define the use of 27 201126535 polycrystalline stone Serial select line (eg 691) and ground tandem select line (eg 64 9), in which each plane of the array is parallel to a wire (e.g., 〗, 。). The transistors 700 and 702 are formed as a result of using lines 691 and 649 using a long strip of semiconductor material as a channel region. 692 is applied between the string selection line 691 and the elongated semiconductor material 612 and between the ground selection line 649 and the elongated semiconductor material 612. A layer of lithography 690 is formed between the string selection line 691 and the ground selection line 649. The serial select line 691 extends outwardly from the array as described below to connect with the decode circuit. The upper orientation element line 698, the via hole opening through the structure is in the respective ridge-like stack with the elongated semiconductor material 612, φ 613, 614 are connected 'and form contact structures 695, 702, 693, 703 within the via holes. Figure 27 shows a schematic diagram of the decoder layout in Figure 26, as shown in the figure, a contact (e.g., 705) may be formed between a strip of semiconductor material (e.g., 614) and a bit line (e.g., 698). The joints are still arranged in a stepped structure such that the alignment boundaries are shared in a plurality of rows. A string selection line (e.g., 649) extends from the array to the upper overall array selection line 720, 721, 722. The contact plugs γιο, γη, and 712 are formed in the via holes and extend to the tandem selection lines in the respective planes of the array to the upper overall string select lines 72〇, 721, 722. Again, non-critical alignment boundaries (such as 713, 714) can be used when forming this structural layout. In this example, the serial select line extends to the planar decode circuit. In some embodiments shown later, the elongated semiconductor material extends with an extension of the stepped structure to terminate the elongated semiconductor material 612 and does not need to extend beyond the edges of the array. The bit lines extend to the row decode circuit and the sense amplifier, which are arranged in a page buffer structure to allow for wider, parallel entry and write stagnation. The sub-line extends to the column decoding circuit.

In addition, the ground selection line GSL 28 201126535 649 below the bit line is also shown and extends parallel to the word line to the sector decoder. Also shown is a common source line 670 below the bit line, and also parallel to the word line (e.g., 625n), and to the common source line 725 above the contact plug 68 to the top of the array.

Figure 28 is a simplified pictorial diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit 875 includes the use of a three-dimensional resistive memory (RRAM) array 860 having a three-dimensional resistive memory (RRAM) array 860 as described herein. A list of horses 861 and /. The & recall array 860歹ij direction of the rehearsal text line line 862~ face and electrical communication. The row decoder, 863 is electrically communicated with the complex bit line 864 (or the previously bribed (four) line) arranged along the memory array_row direction to read and program the data from the memory cell of the array 860. . A = plane decoder 858 is coupled to the previously described series selection = 59 on this array plane. Bit (four) her _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The sense amplifier and data bank 1 in row 867 are coupled to row decoder 863. The data is entered into the data in block 866 by the source of the data. The circuit 874 is included in the integrated circuit, such as a processor or a special purpose application circuit, or a module, and is supported by a programmable memory cell array.曰疋,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The data is provided by block 875, 戍^j£ to jiji=bee material output line 872, and is supplied to the integrated circuit in the internal/external data terminal of the circuit milk. The controller used in the actual example uses a biased voltage to be known to those skilled in the art. Applying a processor as is familiar to the logic circuit, it can cause the same-integrated device to include the operation of the general purpose device. In the case of a m-product circuit, which is controlled by a computer program, the controller is composed of a special purpose logic circuit 29 201126535 and a general purpose processor. Figure 29 is a simplified schematic view showing an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit 975 includes the use of a three-dimensional three-dimensional anti-gate flash memory array array 96 as described herein over a semiconductor substrate. A column of decoders 961 is coupled to a plurality of word lines 962 arranged along the direction of the array of memory arrays 96 to couple electrical communication. Row decoder 963 is in electrical communication with a plurality of bit lines 964 (or string select lines as previously described) arranged along the row direction of memory array 960 to read and program data from memory cells of array 960. . A planar decoder 958 is coupled to the previously described string select line 959 on the array 960 plane. The address is provided by bus 965 to row decoder 963, column decoder %1 and plane solution 958. The fine magnification of the square towel (four) and the structure is connected to the row decoder 963 via the data bus 967. The data is supplied to the data input line 971 by the input/output 积 on the integrated circuit 975, or is input to the data input structure in block 966 by other internal/external data sources of the integrated circuit 975. In this exemplary embodiment, other circuits 974 are included in the integrated circuit milk, such as a destination processor or special purpose application, or a system supported by a reverse flash memory array. Single chip work = block 966 _ sense amplifier, via data output line 972, 'money supply to Wei 975 _ other external controller used in this embodiment uses a bias adjustment to adjust the bias The application of the supply voltage 968, such as ', Cheng two special purpose ^ Luo, sigh stylized verification voltage. The controller can be used in conjunction with i = t as is well known to those skilled in the art. In the case of ==circuit's execution-computer program control: Chengzhong: The controller is made of special purpose logic ^ 30 201126535 " Figure 30 is an 8-layer vertical channel thin film transistor energy gap engineering polycrystalline niobium oxide niobium-nitrogen剖面 矽 矽 矽 矽 BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE Schedule decoding. This device was formed using a half pitch of 75 nm. The channel is an approximately 18 nm thick n-type polysilicon. No joint joints were formed to form a jointless joint structure. The insulating material used to isolate the channels between the semiconductor strips is in the z-direction = direction and is a tantalum oxide having a thickness of about 4 nanometers. The gate provided is extremely P+ polysilicon. This serial selection and ground selection device has a longer channel length for the memory cell. The test device has 32 word lines and no junctions and gate ratio columns. Since the trench etch used to form the illustrated structure has an inclined shape with a wide tantalum line at the bottom of the trench and the insulating material between the thin lines is etched more from the polysilicon, the width of the lower thin line in Fig. 30 It is wider than the width of the upper thin line. This device can also be programmed using positive and negative Le Nordheim electron tunneling. This example uses an incremental step-pulse stylization (ISSP) operation of self-pressurization. The stylized bias of the selected memory cell can be understood in conjunction with Figure 8, and the interference of adjacent memory cells will also be discussed. To program memory cells A (74) in BLn, sSLn, and WLn, a stylized potential is applied to WLn, and SSLn is set to

Vcc (about 3.3 V), and the bit line BLn is set to about ov. GSL is also set to approximately 0V. WLn-Ι and WLn+Ι (and other word lines in this string) are set to turn on the voltage. SSLn-Ι and SSLn+l (and other serial selection lines in this cube) are set to approximately 〇V. Other bit lines, such as bit line BL(), are stunned to be about 3.3V to suppress interference. gsL is also set to approximately 〇v. An incremental step pulse stylization (ISSP) program involves applying a stepped stylized pulse to word line ranging from 14V to 2〇v. A turn-on voltage of about 1 〇v is applied to the other word lines. 201126535 The following describes the interference of this stylized bias on adjacent memory cells, respectively, on BLn, SSLn+1 (adjacent ridges in the same layer of the same word line) and memory cells (77), on BL0 , SSLn (the same ridge in different layers of the same word line) and memory cell C of WLn, for BL0, SSLn+Ι (adjacent ridges in different layers of the same word line) and memory cell d of WLn, Memory cell E (73) for BLn, SSLn, and WLn-1 (the same ridge in the same layer of adjacent word lines). The gate of the memory cell receives the stylized potential through WLn, and its channel is floating, which causes self-boosting. Therefore, stylized interference is avoided. The gate of memory cell C receives the stylized potential through WLn, while its channel is floating, which causes self-boosting. Therefore, stylized interference is avoided. However, for adjacent planes, the interference can still occur due to the fringing electric field induced by the voltage change in memory cell A. Therefore, the separation between the planes should be sufficient to suppress the interference in the Z direction. The simulation results suggest that the thickness of the insulating material between the planes should be set to at least 30 nm, and preferably 4 〇 nanometers or more to suppress the interference caused by the z direction. The gate of memory cell D receives the stylized potential and its channel is floating, which causes self-boosting. Therefore, stylized interference is avoided. The gate of the memory cell E receives the turn-on voltage through wLn-i, and its channel is connected to the BLn of about GV via the anti-gate Φ column. This stylized turn-on voltage is on the order of 10V to suppress this memory cell interference. "Right, 隹iff can use the negative gate and the negative Le-Nordehan hole of the electric rush to tunnel into the second erasing. Applying the erase voltage from _16 to _12¥, the sub-wire can be set to receive This erases the voltage, and the V word V-line in the series receives the turn-on voltage and the selected bit line can be set: about

The three-dimensional buried channel of this description is opposite to the size of the gate array which is suitable for the micro-redness, because the channel width A portion is related to the thickness of the elongated semiconductor material and its width. The pitch limit is therefore limited by S 32 201126535 d::, and the groove required to fill the word line. For further steps, = the cost of a memory cell. 7 I Manufacturing' has thus greatly reduced the layout of each of the other diagrams. Compared with the design of the code and memory architecture, the layout is not shown, and the layout is omitted (above the 24th. This character is good, the ridge is stacked, and the serial selection of metal wires is slamming and crying. The word line extends to a section: the second source line 670 extends over the tandem selection line. 31 i. The touch plug (eg, 665) is connected to the gate structure to select the structure. The stepped pattern is such that the average spacing of the patterned conductive 2 ==. This string selects the line segment along the upper region of the character line of the 2nd class == = = the upper region of the character line of the second segment on the side, Then the next segment reaches the upper right (four) three character line upper area, so as to push the two contacts to be placed at the end of the staggered line segment staggered above the spot: the direction of the string selection line connection, which will be Word=Selection, circuit, which can be placed in the decoding area with the word line solution in the layout column. The spacing of this string selection line is greater than the line spacing 'So - each column of the example layout can have 33 201126535 32 character lines (plus a grounding selection line), and 16 8-layer deep ridged piles The result is to use 16 horizontal strings in the column decoding area, selecting lines and 32 word lines. The 8 bit lines are coupled to the 8 channels above the 16 ridges. The line is decoded to select the column, the string select line is decoded to select the row, and the bit line is decoded to select the plane. This provides a cubic structure with 32 χ 16 χ 8 memory cells. Of course, other word lines, tandem select lines And the combination of the bit lines can be used. It is also possible to add a dummy word line, for example, two dummy word lines in each string.

Figure 31 shows a block labeled "bitline step contact structure, which will be implemented as described below to provide planar decoding and to intermix the selected plane with the sense amplifier. The stepwise opening opens to expose the elongated semiconductor material in each of the array planes. Again, a non-critical alignment boundary with a relatively large tolerance can be used in forming the contact structure layout. The array layout shown here can Repeated in mirror symmetry, and adjacent cubes share contact at the end of the stepped bit line, and adjacent cubes share a common source line at the ground select line end.

Figure 32 shows a cross-sectional view of a memory array having a stepped structure termination bit in an alternative embodiment (compared to Figure 23). The same reference numerals are still used in this figure and will not be described again. The structure shown in Fig. 23 shows the result of removing the hard mask to expose the plurality of wires MS to ^25~n and the telluride 626 over the gate structures 629 and 649. An interlayer dielectric layer (not shown) is formed over the array, and via holes are formed up to the upper surface of the gate structure 629 and filled with plugs 665, 666 of tungsten, for example =5. Further, a metal line 670 is formed and adjacent to the end of the elongated semiconductor material of the selective transistor 651.卞 34 201126535 Over the Λ metal line 665, the secret is patterned to connect via the plug 665,

In this =, the twisted closed pole layout is not shown, but it is preferable that the iL long bucket extensions 6i2A, 6i3A, and 6i4A constitute a stepped structure of the terminating conductor materials 612, (1), and 614. These long extensions 612A, 613a, and 614a can be patterned together with a plurality of mountain-like stacks. Figure 10 shows an alternative embodiment with a stepped structure termination

A cross-sectional view of the array of cautions with =, ' and having a staggered contact plug (4) with a clear line connection (compared to Figure 32). The metal wires 661 and 662 above the heart are slaughtered to select the lines between the lines in the short < Λ $ string and connect and decode the lines with the line ί :. ==== 排 = still make : The electric trrr can be used to reduce the average spacing in this ridge-like stack layout along many: the connection. Figure 34 is a line contact for the next stage of the memory array shown in Fig. 33, and the vertical stack is formed and the selection line and the ridge are on the tandem selection line; the bit line is also displayed in the genus layer. Fig. 35 is a circuit diagram showing the implementation of the 3rd flash device. Display = the description of the reverse gate layout and design plan. The detailed and closed flash devices of the same technology node are based on == 35 201126535. Figure 36 shows a plan view of one possible two array embodiment. In one embodiment there is a density of 8 GB (equal to 64 Gbits or 64 Gb): the details are as follows: In both the word line and the DIFF (serial selection line device), the half-pitch of the design criteria is 65 nm. A three-dimensional VGNAND with an 8-layer memory layer. The bit line (third metal layer) pitch is equal to 2xDIFF pitch = 260 nm. The tandem selection line (second metal layer) pitch is equal to 2xWL spacing = 260 nm. φ density is 8Gb (8-layer memory layer, multi-level memory cell (2-bit/memory cell)) The page size is 4kB (2-bit/memory cell), the block size is 2MB=32*16 pages, and the plane size is 4GB (2000 blocks) Grain size ~ 150 square millimeters (array = 107 square millimeters) Another embodiment has 64GB density (equal to 512G bits or 512Gb): the details are as follows: Word line and DIFF (string In the column selection line device), the half-pitch of the design criteria is 32 nm. Three-dimensional VGNAND with 16 memory layers. • The bit line (third metal layer) pitch is equal to 2xDIFF pitch = 128 nm. The tandem selection line (second metal layer) pitch is equal to 2xWL spacing = 128 nm. The density is 512Gb (8-layer memory layer, multi-level memory cell (2-bit/memory cell)) The page size is 8kB (2-bit/memory cell), the block size is 16MB=64*32 page, and the plane size is 32GB. (2000 blocks) Grain size ~ 140 mm 2 (array = 97 mm 2 ) 36 201126535 Because of the additional serial selection line, this XDEC (column decoding) area is 1.5 times that of the conventional multi-level memory cell. XDEC (column decoding) can be located on one or both sides. Other micro-conditions are listed below, which have a 2-bit/memory cell operation: 8 layers of memory, 128 Gb with 45 nm 4F2; 256 Gb with 32 nm 4F2; 256 Gb with 25 nm 5.IF2 ; pc is 32nm half-pitch, Y is 25nm half-pitch) with 16-layer memory layer '512Gb with 32nm 4F2 or 25nm 5.1F2; 32-layer memory layer, 1Tb with 42nm 4F2 or 5nm 5.1F2; in other embodiments 'can be designed as a multi-plane memory for other different technology nodes. The number of memory layers is not limited to 8, 16, or 32. Other embodiments may have other numbers 'e.g., other 2x or a half node such as 12, which is a half node between 8 and 16. The preferred embodiments and examples of the present invention are disclosed in detail above, but it should be understood that the above examples are only used as a secret and are not intended to limit the scope of the patent. As far as the well-known technology is concerned, it can be easily changed according to the following patent scope to the related technology and [simplified description of the drawing] Figure 1 shows a three-dimensional programmable resistance memory, part of the schematic diagram 'including plural number The strips of long strips of semiconductor material are parallel to the gamma axis and arranged in a plurality of ridge-like stacks, the sides of a strip of semi-conductive material, and the plurality of strips having the bottom surface of the ridged stack of the 37 201126535 ridges . : 2 shows the first! The memory cell structure of the graph is in the plane along the ζ_χ plane. Figure 3 shows the memory cell structure of the Fig. diagram along the γ_χ plane. The dry display shows the inverse (four) of the structure of Fig. 1 as the underlying memory. The cell diagram is a three-dimensional anti-gate flash memory structure - memory, can not bear the picture, which includes a plurality of strips of semiconductor material plane 盥 layer of multiple ridge-like stacks, - charge trap memory i mountain two + conductor material The side, and the plurality of wires have a plurality of ridge-like stacked bottom surfaces below the wire. Yes Section: Figure 6 shows the memory cell structure of Figure 5 in section 7 along the z-x plane showing the memory cell structure of Figure 5 along the γ-χ plane. 8 is a schematic diagram showing a reverse-gate flash memory having the structure of FIG. 5, which is similar to the three-dimensional inverse gate flash memory alternative embodiment of FIG. 5, wherein the memory material layer is cut from the wire: FIG. Hey. The figure shows the memory cell structure of Fig. 9 in section S1 along the (four) plane. The figure shows a schematic cross-sectional view of the memory cell structure of Fig. 9 in the first stage of the memory device of Figs. 1, 5, and 9 in the 121st implementation along the Y_x plane. Figure 13 shows a schematic cross-sectional view showing the second stage of the process of manufacturing the device as in Figures H and 9 of 2011. Process of memory device in the drawing Process of memory device in the figure 5, 9 The memory device in Figs. 5 and 9 of the memory device shows a cross-sectional view of the third stage of manufacturing. Fig. 14B shows a schematic cross-sectional view of the implementation of the third stage. The 15th shows the implementation of manufacturing as the first! Schematic diagram of the third stage of the process. Figure 16 shows a schematic cross-sectional view of the fourth stage of the manufacturing process. The diagram of Fig. 17 is a schematic diagram of the Z-axis rotation, which also shows a schematic diagram of the cross-section of == produced in Fig. 1 including a hard mask and selection == to illustrate Fig. 1δ. The figure shows that the reliance on the string of the basic memory (Fig. 19) provides an interconnection line similar to the apparatus in Fig. 18 in which the planar decoding structure is not shown. The second diagram of the brother figure shows that the anti-shock is an alternative to the base memory (iv). A top view similar to the device layout in Figure 20. The series V is rotated by 90 degrees in the Z axis in Fig. 5: =, .. The intention of the structure also shows the schematic diagram of the section of the section which is made as shown in Fig. 5, including the second rr package of the hard mask structure and the layout of the second device _ 39 201126535 Alternative diagrams and closed flashes are used as an alternative to serial selection. Figure 27 provides a top view similar to the second and twenty-eighth diagrams showing the layout according to the invention = (four). It is intended that the integrated circuit includes a simplified square fast sense read only memory array having an integrated circuit of & Three-Dimensional Programmability of Decoding Circuits Figure 29 shows an alternative embodiment of the present invention in which the integrated circuit includes a simplified square fast and gate flash memory array having row and body circuits. 1 and the three-dimensional anti-decoding circuit The third picture shows the three-dimensional anti-gate flash flash relay. A tunneling diagram of a portion of the train column shows a top view of the layout of the tandem selection line. Figure 32 shows a schematic diagram of a memory array with a step structure of the final gentleman _ embodiment. . An alternative to the 疋, '' plane Fig. 33 shows a schematic view of the other side of the step contact plug with the stepped structure terminal 选择 series selection line, the pole connection column. The generation of the memory array is shown in the figure = the level of the memory of the farm in the figure - the difference between the line contact and the step structure is shown in Fig. 35 is a circuit diagram showing the implementation of Fig. 34.咐田述之反 and 快快装装 Figure 36 shows a plan view of two possible examples. 201126535 [Description of main component symbols] 10, 110: insulating layers 11 to 14, 111 to 114: elongated semiconductor materials 15, 115: memory materials 16, 17, 116, 117: wires 18, 19, 118, 119: metal stones夕化20,120: trenches 21~24, 121~124: insulating materials 25, 26, 125, 126 · active area

30 to 35, 40 to 45, 70 to 79, 80, 82, 84: memory cells 51 to 56: long semiconductor material stacks 60 (60-1, 60-2, 60-3), 61, 160-162: Wires 90-95: Block Selecting Cells 97, 397: Tunneling Dielectric Layers 98, 398: Charge Storage Layers 99, 399: Blocking Dielectric Layers 85, 88, 89: Tandem Selective Crystals 106, 107, 108 : series select lines 128, 129, 130: source/drain regions 210, 212, 214: insulating layers 211, 213: semiconductor 215 memory material layer 250 ridge-like stack 315 charge trapping layers 225, 260: wires 226, 426, 490, 626: metal lithology 400: ion implantation 401-1~401-n: hard mask 41 201126535 402, 403: hard mask 410: insulating layer 412 414: long semiconductor material 412A~414A: long Strip semiconductor material extension 415. Memory material 425-1 ~ 425-n, 460-1 ~ 460-n: wire 429: gate structure 450, 500: transistor 458, 459, 510, 511, 512: contact plug 470, 471, 472: bit line 480: contact boundary 481~483: contact 491: tandem select line 492: gate dielectric layer 498, 499: bit line 495, 496, 502, 503: contact structure 52 0, 521, 522: overall serial selection lines 513, 514: alignment boundary 600: ion implantation 601-1~601-n: hard mask 602, 603, 648: hard mask 610: insulating layer 612~614 : strip semiconductor material 612A~614A: strip semiconductor material extension 615. memory material 625-1 ~ 625-n, 460-1 ~ 460-n: wire 629, 649: gate structure 650, 651: transistor 201126535 661 662: tandem select lines 671, 672, 673: bit lines 665, 666, 680: contact structure 665A: contact boundaries 670, 725: common source lines 680a, 680b, 713, 714: alignment boundaries 681~683 710~712: contact plug 691: tandem selection line 692: gate dielectric layer φ 698, 6 ": bit line 695, 696, 702, 703, 705: contact structure 720, 721, 722: overall series Selection lines 875, 975: integrated circuit 860: automatic alignment three-dimensional programmable resistance read-only memory array 960: automatic alignment three-dimensional inverse gate flash memory array 858, 958: plane decoder 859, 959: serial Selection lines 861, 961: column decoders φ 862, 962: word lines 863, 963: row decoders 864, 964: bit lines 865, 965, 867, 96 7: Bus 866, 966: sense amplifier / data input structure 874, 974: other circuits 869, 969: state mechanism 868, 968: bias adjustment supply voltage 871, 971: data input line 872, 972: data output line 43

Claims (1)

201126535 VII. Patent application scope I A memory device, comprising: an integrated circuit substrate; a circuit substrate, sharing the different plane positions of the plurality; the bit line in the "===== is located in the bit line contact The end of the strip of semiconductor material (four)-like structure is placed orthogonal to the plurality of stacks, and intersects the plurality of planes with the plurality of wires. The complex number is as in claim 1. The memory device further includes: a decoding circuit coupled to the plurality of semiconductor materials and the plurality of wires in the plurality of stacks to access the memory cell. 3. The memory device of claim 1 The memory device includes an anti-fuse. 4. The memory device of claim S1, wherein the memory device comprises a charge storage structure. t. The memory device of claim 1, wherein the memory cell comprises Buried channel charge storage transistor 44. The memory device of claim 1, wherein the plurality of stacked semiconductor materials comprise doped semiconductors. 7. The memory device of claim 1, wherein the plurality of semiconductors are doped. I. The memory device of claim 1, wherein the memory component of the memory component-common layer is a plurality of lobes and the ferrule of the present invention, wherein the memory device of claim 1 includes a pass-through layer, a capture layer, and a resistance to the plurality of stacks and the plurality of wires The combination of wearing 阙, charge her layer and layer layer is based on the secret of the seizure. 1—0. The memory device of the i-th item of the application of the patent, including the plurality of female platoons in the fine-numbered fold The strips of semiconductor material are parallel, and the different bits of the plurality of bits (4) are electrically connected to different plane positions in the plurality of stacks by the plurality of meta-frames = ladder-like structure." The memory device comprises: an integrated circuit substrate; two numbers: a long two-way substrate, the complex number = centered not _: set conductor: =:== complex two sides of the side of the if long semiconductor material by a stepped structure connected to the same number of bit line contacts in the number of bit read contacts Thus, the stepped junction 45 201126535 is located at the end of the long strip of semiconductor material; the derivative stack is fine _ above, and a three-material is established with the double line intersection point: Futian Fengzhi ^ sac The structure of each of the conductive conformal structures in the plurality of electrically conductive conformal structures of the plurality of stacked electrical structures is electrically connected to the plurality of conductive conductors and to the first plurality of conductors Each of the different wires and the second 12. The memory of the item n of the patent application includes: a plurality of paths 'and the strip of semiconductor material in the plurality of stacks, the first - A plurality of wires and the third plurality of wires are connected to access the memory cells. In the eleventh item of the coffee, the memory item comprises: wherein the memory element comprises a memory charge storage structure buried in claim 11 of the patent application scope. =·, as in the patent application scope u, the memory device channel charge storage transistor. 46. The device of claim 5, wherein the plurality of elongated semiconductor materials comprise a semiconductor. τ 17. The doped semiconductor is included in the first line of the patent application. The memory device of claim 11, wherein the memory device of claim 11 wherein the memory element comprises a portion of the memory layer of the common layer in the plurality of stacks and the plurality of Between the wires. 19. The memory device of claim U, comprising a pass-through layer, an electrical capture layer, and a germanium layer between the plurality of stacks and the first plurality of wires and the towel (4) layer 1 The combination of the trap layer and the barrier layer constitutes the memory element in the intersection region. 2. The memory device of claim U, further comprising a plurality of bit lines arranged on the plurality of stacks and having no strips of semiconductor material in parallel" wherein the f-number of strips of the strips are different The plurality of bit lines are electrically connected to the different planar positions of the plurality of stacks 4 via the plurality of bit line contacts and the stepped structure. 21 - A method for manufacturing a memory device, comprising: Extending the ridge to touch the peach substrate, the subsequent plurality of stacks comprising at least two strips of semiconducting material, a semi-conducting line, and a step in a phase structure connected to the plurality of bit line contacts The step of the strip material is set to two different plane positions, sharing the complex number two = forming a plurality of material lines into the money _ Wei turn 4 above, and with the complex 47 201126535 stacked, so Forming a three-dimensional array of intersections on the surface of the strip of semiconductor material and the plurality of strips and the father's day point; and detecting the conductor material in the rendezvous area, verifying that the long strip conductor material and the "multiple lines" are established Take the three-shifted memory cell 22. A method of manufacturing a memory device, comprising: «^^long strip material body 4 extending out of the electric shouting board, the plurality of strips of at least two long strips of semiconductor material (four) separated by insulating layer The middle material is in the same plane position, sharing the plurality of plane positions + the plurality of strips of material connected to the plurality of two sides are connected by a stepped structure to the same bit line in the line contact. Stepped,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The plurality of material and the object are visibly disposed on the plurality of first strips other than the first plurality of wires, and the different wires of the second plurality of wires are connected to the parent wire and the wire Forming a second plurality of turns of the plurality of semiconductor materials in parallel, each of the second plurality of lines is electrically connected to a different conductive structure in the conductive conformal structure, and ... Wei 48