201112888 0906005 31963twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路板’且特別是有關於一種整 合高/低佈線密度的線路板結構。 【先前技術】 消費性電子產品的市場需求大，消費者除 a处 • 強大外，更要求輕、薄、短、小，因此市面上電子產 線路越來越細密，而用以安裝電子元件的印刷線路板:朝 多層發展，由二層、四層而變為六層、八層，甚至到十層 以上，以使電子元件可以更密集地裝設於印刷線路板上， 縮小印刷線路板的面積，使電子產品的體積更小。 士然而，隨著印刷線路板的層數越來越多，製造的步驟 也變=極為繁複，使得製造的時間變得报長。為了製作高 佈線密度的線路，印刷線路板的層數常常超過四層，但在 • 製作四層的印刷線路板時，光是將膠片、銅箔與内層線路 板一起壓合所需要的時問’就大約要數小時左右，如果再 加上後續的處理步驟’大概需要約五個小時。若所製作的 印刷線路板為四層以上的多層板，如六層、八層、十層的 印刷線路板’則壓合所需要的時間會更長，因此製作成本 過高。 相對而言’低佈線密度的印刷線路板因層數少、製造 的步驟較少’可以在較短的時間内完成，故產量高、成本 低因而業界無不希望以較少的步驟來製造高佈線密度的 201112888 0906005 31963twf.doc/n 印刷線路板。值得注意的是，在局部高佈線密度的線路板 中，高佈線密度的區域僅佔整個線路板的一部分，其餘區 域為一般佈局（低佈線密度）的線路，但礙於製程上缺乏 創新’習知的製作方法還是需要很長的時間，因此製造成 本並未減少，不符合經濟效益。 【發明内容】 本發明提供一種缘路板結構，用以製作局部高佈線密 度的線路板，並能簡化步驟及減少製造成本。 本發明提出一種線路板結構，包括一内層線路板以及 一線路子板。内層線路板具有第一線路層、第二線路層以 及位於第一及第二線路層之間的一核心層。線路子板内埋 於核心層中，線路子板的佈線密度大於内層線路板的佈線 密度。 、 在本發明之一實施例中，上述之線路板結構更包括二 絕緣膠片以及二圖案化線路層。二絕緣膠片至少包覆於線 路子板的周圍。二圖案化線路層配置於内層線路板與線路 子板的相對兩側，且二絕緣膠片分別隔離於二圖案^匕線 層與第一及第二線路層之間。 在本發明之-實施例中，上述之相對兩側的二圖宰化 線路層、内層線路板以及線路子板彼此電性連接。/、 在本發明之-實施例中，上述之線路子板具有四 四層以上的線路層。線路子板的層數大於⑽線路板二層 數0 201112888 0906005 31963twf.doc/n a在本發明之一實施例令，上述之線路子板的厚度小於 或等於内層線路板的厚度。 本發明提出另一種線路板結構，包括一内層線路板、 一線路子板、二絕緣膠片以及二圖案化線路層。内層線路 板具有第-線路層、第二線路層以及位於第一及第二線路 層之間的一核心層。線路子板内埋於核心層中，線路子板 的佈線密度大於内層線路板的佈線密度。二絕緣膠片至少 φ 包覆於線路子板的周圍。二圖案化線路層配置於内層線路 板與線路子板的相制側，且二絕緣膠#分賴離於二圖 案化線路層與第一及第二線路層之間，其中線路子板之至 少一侧對應顯露於一開口區域中。 在本發明之一實施例_，上述之開口區域是移除覆蓋 於一預定開口區域的一部分絕緣膠片以及一部分圖案化線 路層所形成。 ' 基於上述，本發明之線路板將預先完成的高佈線密度 的線路子板整合至一般佈局（低佈線密度）的内層線路板 _ 中，並與一絕緣膠片以及二圖案化線路層結合為一體，以 簡化步驟及減少製造成本。因此，線路板只需一次壓合所 需要的時間’不需花报長的時間，大幅減少習知多層線路 板的製造成本。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 201112888 uyuouus 31963twf.doc/n 【實施方式】 圖1A〜圖ιέ分別緣示本發明一實施例之線路板的製 作方法的"IL权圖。請參考目1A +具有高佈線密度的線路 子板100 ’是由切割一線路母板10而來。線路母板10分 離為ί個線路子板_之後，這些缘路子板應均具^ 佈線^度的線路，其包括四層或四層以上的線路層102, 例如’、層人層或十層^在本實施例中，先將多層的線路 f 1〇2以及絕緣層104依序層疊於核心基板106上，再以 目孔V及鑛通孔P電性連接線路層1()2的線路，以製作出 多個相同佈局的線路子板觸於-線路母板10上。線路子 ，100的相對兩侧具有多個接墊3，密集地排列於線路子 上’以使線路子板100可電性連接高階處理的電子 凡牛（未繪示）’例如中央處理器或顯示晶片等。 ’請參考圖1B及圖1C的步驟，將完成高佈線密 ^ 子板1〇〇配置於一内層線路板200的開口 C中。 =線，板jGG的開σ c例如以雷射切割成預定的形狀及 肉二Λ以容納尺寸較小的線路子板。在本實施例中， 板細具有第—線路層2G2、第二線路層204以 f 3弟—及第二線路層2°2、204之間的-核心層206， 可知’線路子板_的佈_度大於内層線路 、_線控度’且線路子板100的層數（四層或四層 以上也南於内層線路板200的層數（二層或二層以上）。 200的板100的厚度大致上可小於或等於内層線路板 的居度’依設計的需求而定。當線路子板1〇〇内埋於 201112888 0906005 31963twf doc/n 核心層206時，分別配置—絕緣勝片2l2以及一金屬羯片 2H於線路子板觸與内層線路板的相對兩側，並進 行熱堡合步驟，以使上下兩側的二金屬落片214藉由二 絕緣膠片212 SJ著於線路子板⑽以及内層線路板2〇〇 上，並結合為一體。 ，著，明參5圖1D及圖1E的步驟，當完成熱壓合步 之4更可進行-穿孔製程以及—鑛孔製程，以分別形 ，導電材料於-通孔P1及多個盲孔V1中。穿孔製程例如 疋以雷射燒孔製程或機械鑽孔製程。通孔ρι可貫穿相對 兩側的二金射|片214、二絕緣膠片212以及内層線路板 200。多個盲孔¥1分別顯露出内層線路板上的第一線 ，層搬及第二線路層2G4，並顯露出位於線路子板⑽ β。此外，鍍孔製程例如是魏導電材料 、通孔1中，以電性連接相對兩側的二金屬箱片214至 内層線路板200,以及電錢導電材料於盲孔νι中， 連接相對兩側的二金屬箔片214至飧改本 路板200。 214至線路子板1〇〇及内層線 詳細而言，形成通孔ρ、ρι㈣式有二種 :::柱、⑺形成中空導電柱’該中空導電柱的空腔= 4，、入填充材料，其巾填充材料可201112888 0906005 31963twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a wiring board' and particularly to a wiring board structure for integrating high/low wiring density. [Prior Art] The market demand for consumer electronic products is large. Consumers are more demanding, lighter, thinner, shorter, and smaller. Therefore, the electronic production lines on the market are getting more and more fine, and they are used to install electronic components. Printed circuit board: It develops toward multiple layers, from two layers and four layers to six layers, eight layers, and even ten layers or more, so that electronic components can be densely mounted on a printed circuit board, and the printed circuit board can be reduced. The area makes the electronic product smaller. However, with the increasing number of layers of printed circuit boards, the manufacturing steps have become extremely complicated, making the manufacturing time become longer. In order to make a wiring with a high wiring density, the number of layers of a printed wiring board often exceeds four layers, but in the case of making a four-layer printed wiring board, the time required to press the film, the copper foil and the inner wiring board together is required. 'It takes about a few hours, if you add the subsequent processing steps' it takes about five hours. If the printed wiring board is a multi-layer board of four or more layers, such as a six-, eight-, and ten-layer printed wiring board, the time required for pressing will be longer, and the manufacturing cost is too high. Relatively speaking, 'lower wiring density printed circuit boards have fewer layers and fewer manufacturing steps' can be completed in a shorter period of time, so the output is high and the cost is low, so the industry has no desire to manufacture high in fewer steps. The wiring density of 201112888 0906005 31963twf.doc/n printed circuit board. It is worth noting that in a local high wiring density circuit board, the area of high wiring density only occupies a part of the entire circuit board, and the remaining area is a general layout (low wiring density) line, but it lacks innovation in the process. Knowing the production method still takes a long time, so the manufacturing cost is not reduced, and it is not economical. SUMMARY OF THE INVENTION The present invention provides a edge board structure for fabricating a circuit board having a high degree of wiring density, which simplifies steps and reduces manufacturing costs. The present invention provides a circuit board structure including an inner circuit board and a line sub board. The inner circuit board has a first circuit layer, a second circuit layer, and a core layer between the first and second circuit layers. The wiring sub-board is buried in the core layer, and the wiring density of the wiring sub-board is greater than the wiring density of the inner circuit board. In an embodiment of the invention, the circuit board structure further includes two insulating films and two patterned circuit layers. The two insulating films are covered at least around the line daughter board. The two patterned circuit layers are disposed on opposite sides of the inner circuit board and the circuit board, and the two insulating films are respectively separated between the two pattern lines and the first and second circuit layers. In the embodiment of the present invention, the two opposite-layered circuit layers, the inner layer circuit board, and the line daughter board on the opposite sides are electrically connected to each other. In the embodiment of the invention, the above-mentioned circuit sub-board has four or more wiring layers. The number of layers of the circuit sub-board is greater than (10) the number of layers of the circuit board. 0 201112888 0906005 31963twf.doc/n a In one embodiment of the invention, the thickness of the above-mentioned circuit sub-board is less than or equal to the thickness of the inner circuit board. The invention proposes another circuit board structure comprising an inner circuit board, a circuit sub board, two insulating films and two patterned circuit layers. The inner circuit board has a first circuit layer, a second circuit layer, and a core layer between the first and second circuit layers. The circuit sub-board is buried in the core layer, and the wiring density of the circuit sub-board is greater than the wiring density of the inner circuit board. The two insulating films are at least φ wrapped around the circuit board. The second patterned circuit layer is disposed on the phase side of the inner circuit board and the circuit sub-board, and the two insulating glues are separated from the second patterned circuit layer and the first and second circuit layers, wherein at least the circuit sub-board One side is correspondingly exposed in an open area. In an embodiment of the invention, the open area is formed by removing a portion of the insulating film covering a predetermined opening area and a portion of the patterned wiring layer. Based on the above, the circuit board of the present invention integrates a pre-finished high wiring density wiring sub-board into an inner layout board of a general layout (low wiring density), and is integrated with an insulating film and a two patterned circuit layer. To simplify the steps and reduce manufacturing costs. Therefore, the time required for the board to be pressed at one time is not required to be reported, and the manufacturing cost of the conventional multilayer board is drastically reduced. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] Fig. 1A to Fig. 1A respectively show an <IL right diagram of a method of manufacturing a wiring board according to an embodiment of the present invention. Please refer to the item 1A + the wiring board 100' having a high wiring density is obtained by cutting a wiring mother board 10. After the line mother board 10 is separated into ί line daughter boards _, these edge board slabs should each have a wiring line of 4 degrees or more, including four or more layers of circuit layers 102, such as ', layer layer or ten layers In the present embodiment, the plurality of lines f 1 〇 2 and the insulating layer 104 are sequentially laminated on the core substrate 106, and the lines of the circuit layer 1 () 2 are electrically connected by the mesh hole V and the mine through hole P. To make a plurality of wiring sub-boards of the same layout touch the line mother board 10. The circuit sub-100 has a plurality of pads 3 on opposite sides of the 100, and is densely arranged on the line to enable the circuit sub-board 100 to be electrically connected to a high-order processing electronic (not shown) such as a central processing unit or Display wafers and the like. Referring to the steps of Fig. 1B and Fig. 1C, the high wiring dense board 1 is disposed in the opening C of an inner wiring board 200. = line, the opening σ c of the board jGG is, for example, laser cut into a predetermined shape and a meat chord to accommodate a smaller size circuit board. In this embodiment, the thin plate has a first circuit layer 2G2, a second circuit layer 204, and a second core layer 206 between the second circuit layers 2 and 2, 204. The cloth_degree is greater than the inner layer line, the _way control degree, and the number of layers of the line daughter board 100 (four or more layers are also south than the number of layers of the inner layer circuit board 200 (two or more layers). 200 of the board 100 The thickness can be substantially less than or equal to the occupancy of the inner layer circuit board. Depending on the design requirements. When the line daughter board is buried in the 201112888 0906005 31963twf doc/n core layer 206, respectively, the insulation film 2l2 is configured. And a metal slab 2H on the opposite side of the circuit board contacting the inner circuit board, and performing a hot-spot combination step, so that the two metal falling pieces 214 on the upper and lower sides are placed on the circuit board by the two insulating film 212 SJ (10) and the inner circuit board 2 ,, and combined into one., the steps of Figure 1D and Figure 1E of Mingshen 5, when the hot pressing step 4 is completed, the perforation process and the mine hole process can be performed. Shaped separately, the conductive material is in the through hole P1 and the plurality of blind holes V1. The punching process is, for example, thunder The hole hole process or the mechanical hole drilling process. The through hole ρι can penetrate the opposite sides of the two gold film|strip 214, the two insulating film 212 and the inner layer circuit board 200. The plurality of blind holes ¥1 respectively reveal the inner layer circuit board The first line, the layer is moved and the second circuit layer 2G4, and is exposed in the circuit sub-board (10) β. In addition, the plating process is, for example, a Wei conductive material and a through hole 1 to electrically connect two metal boxes on opposite sides. The sheet 214 to the inner layer circuit board 200, and the electric money conductive material in the blind hole νι, connecting the two metal foils 214 on opposite sides to the tampering of the road board 200. 214 to the line sub-board 1 〇〇 and the inner layer line are detailed In other words, there are two types of through holes ρ and ρι (4)::: column, (7) forms a hollow conductive column 'the cavity of the hollow conductive column = 4, into the filling material, and the towel filling material can be
tj t ^ ^ ^ ^ ^ 5 L =月曰材料，磁材料或具有陶竟材料顆 導熱材料’例如具有金屬顆粒、金屬化 陶磁材料顆粒分布的樹脂材料等。 、/ - 201112888 0906005 31963twf.d〇c/n 成導電柱體的方式通常包括化學沉積法於通孔 ==電電鍍導體層，且/或於該導體層 法形成有電電鍍導體層。 一==導電盲孔V ' V1的方式通常包括：⑴以化 子/儿積法2目孔表面形成無電電錢導體層，且/或於該導體 層上再2仃電鑛法形成有電電料體層，形成具有中空導 電才的g孔，（2)直接以化學沉積法由盲孔表面形成無電電 鑛導體層’並延續沉積至形成具有實體導餘的盲孔。 成於線路子板100的盲孔V及/或内層線路板2〇〇 的埋孔，在本技術領域中，通常會形成中空導電柱，並於 中空導電柱巾填人樹脂材料、具有金卿喊陶磁顆粒分 布的樹脂材料，或金屬膏，例如銅膏或銀膏等。當然也可 以視情況保留中空狀直接進行熱壓合由半固化膠片的含膠 於熱壓過程流動填入該盲孔及/或埋孔中。 之後，圖案化相對兩側的二金屬箔片214，以形成二 圖案化線路層214a。如此，本發明之線路板22〇大致上製 作完成’其包括一線路子板1〇〇、一内層線路板2〇〇、二絕 緣谬片212以及二圖案化線路層214a。線路子板1〇〇内埋 於内層線路板200中，且線路子板1〇〇的佈線密度大於内 層線路板200的佈線密度，以做為線路板220的高佈線密 度的區域。此外’二絕緣膠片212包覆於線路子板100的 周圍，並隔離於二圖案化線路層214a與第一及第二線路層 202、204之間。另外，線路子板1〇〇與内層線路板2〇〇可 藉由外層的圖案化線路層214a與電子元件（未繪示）電性 201112888 0906005 3l963twf.doc/n 連接，以傳遞訊號。 圖2A〜圖2F分別繪示本發明另一實施例之線路板的 製作方法的流程圖。請參考圖2A中具有高佈線密度的線 5子板100，是由切割一線路母板10而來。線路母板10 二離為夕個線路子板100之後，這些線路子板100均具有 1線密度的線路，其包括四層或四層以上的線路層，例 如/、層、八層或十層。相關的描述請參考上述施在 ^ 此不再贅述。 、 接著，巧參考圖2B及圖2C的步驟，將完成高佈線密 又的線路子板100配置於一内層線路板200的開口 C中。 ^路子板100的佈線密度大於内層線路板的佈線密 ^ ’且線路子板100的層數（四層或四層以上）也高於内 層線路板細的層數（二層或二層以上）。與上述實施例 '同的疋進行熱壓合步驟之前，可先形成一離型膜 於線路子板100之-側上，以隔離同樣位於線路子板刚 之一側的絕緣缪片212。離型膜21〇可於後續完成 • &、鑛孔製程以及圖案化線路製程之後，自線路子板議 上掀離而私除，以顯露出線路子板綱於一開口區域中， 如圖2F所示。有關圖2D及圖2E的穿孔製程、鑛孔 以及圖案化線路製程，請參考上述實施例，在此不再贅述。 。、睛參考步驟2E及圖2F，線路板uoa具有—預定 區域A，對應於離型膜21〇所在的位置，預定開口區域a ^可保留-部分外層線路⑽，但亦可不保留此部分 線路2i4b。本發明可藉由雷射切割預定開口區域a並移^ 201112888 uyueuui 31963twf.doc/n 覆蓋於預定開口區域的一部分絕緣膠片212以及一部分金 屬箱片214,以顯露出離型膜210。之後，移除離型膜210, 以顯露出線路子板100於一開口區域C1中。 在另一實施例中，雖未繪示於圖式中，但可想而知， 線路板例如具有二預定開口區域，分別對應於二離型膜所 在的位置，其中二離型膜位於線路子板的相對兩側。同樣 可藉由上述的說明’來移除相對兩側的一部分絕緣膠片以 及一部分金屬箔片，以顯露出二離型膜。之後，再移除離 型膜’以顯露出線路子板的相對兩側於二開口區域中。 —如此，本發明之線路板220a大致上製作完成，其包括 :線路子板100、一内層線路板2〇〇、二絕緣膠片212以及 —圖案化線路層214a。線路子板1〇〇内埋於内層線路板2〇〇 中户且線路子板100的佈線密度大於内層線路板200的佈 線，度，以做為線路板220的高佈線密度的區域。此外， 、巴、'表膠片212包覆於線路子板1〇〇的周圍，並隔離於二 二案化線路層214a與第一及第二線路層202、204之間。 外’線路子板1〇〇之至少一側對應顯露於一開口區域d ^開口區域Cl可容納-個或多個電子元件（未繪示）， 由導電球或導電塊（未繪示）與線路子板⑽的接 墊B電性連接，以傳遞訊號。 幻褛 的線述，本發明之線路板將預先完成的高佈線密度 中:Μ -整合至一般佈局（低佈線密度）的内層線路板 簡化^二絕緣膠片以及二圖案化線路層結合為一體，以 ν驟及減少製造成本。因此，線路板只需-次®合所 201112888 〇y〇6UUi) 31963twf.doc/n 餘長的A幅減少習知多層線路Tj t ^ ^ ^ ^ ^ 5 L = Lunar material, magnetic material or ceramic material. Thermally conductive material 'for example, a resin material having metal particles, metallized ceramic material particle distribution, and the like. / / 201112888 0906005 31963twf.d〇c/n The manner in which the conductive pillars are formed generally includes a chemical deposition method in the via hole == electroplated conductor layer, and/or an electroplated conductor layer is formed in the conductor layer method. A == conductive blind hole V 'V1 generally includes: (1) forming a non-electrical money conductor layer on the surface of the 2 mesh hole by the chemical/child method, and/or forming an electric current on the conductor layer by a further electroporation method The body layer forms a g hole having a hollow conductive state, (2) directly forms an electroless ore conductor layer from the surface of the blind hole by chemical deposition method and continues deposition to form a blind hole having a solid guide. The blind hole V formed in the circuit sub-board 100 and/or the buried hole of the inner circuit board 2〇〇, in the technical field, a hollow conductive column is usually formed, and the hollow conductive column is filled with resin material, and has Jinqing. A resin material that cites the distribution of ceramic particles, or a metal paste such as a copper paste or a silver paste. Of course, it is also possible to directly carry out the thermocompression in a hollow shape as required, and the glue containing the semi-cured film is filled in the blind hole and/or the buried hole in a hot pressing process. Thereafter, the two metal foil sheets 214 on opposite sides are patterned to form a two patterned wiring layer 214a. Thus, the circuit board 22 of the present invention is substantially completed. It includes a wiring sub-board 1 一, an inner wiring board 2 〇〇, two insulating dies 212, and two patterned wiring layers 214a. The wiring sub-board 1 is buried in the inner wiring board 200, and the wiring density of the wiring sub-board 1 is larger than the wiring density of the inner wiring board 200 as the high wiring density area of the wiring board 220. Further, the second insulating film 212 is wrapped around the wiring sub-board 100 and is isolated between the two patterned wiring layers 214a and the first and second wiring layers 202, 204. In addition, the line daughter board 1 〇〇 and the inner layer board 2 连接 can be connected to the electronic component (not shown) by the patterned circuit layer 214a of the outer layer to transmit signals. 2A to 2F are respectively a flow chart showing a method of fabricating a circuit board according to another embodiment of the present invention. Please refer to the line 5 sub-board 100 having a high wiring density in Fig. 2A, which is obtained by cutting a line mother board 10. After the circuit board 10 is separated from the circuit board 100, the line boards 100 each have a 1-line density line including four or more layers, such as /, layer, eight or ten layers. . For related descriptions, please refer to the above application. ^ This is not repeated here. Next, referring to the steps of FIG. 2B and FIG. 2C, the line sub-board 100 which completes the high wiring is disposed in the opening C of the inner wiring board 200. ^The wiring density of the circuit board 100 is greater than the wiring density of the inner circuit board and the number of layers of the circuit board 100 (four or more layers) is also higher than the number of layers of the inner circuit board (two or more layers) . Before the thermal compression bonding step of the above-described embodiment, a release film may be formed on the side of the wiring sub-board 100 to isolate the insulating spacers 212 which are also located on one side of the wiring sub-board. The release film 21〇 can be removed from the line sub-board after the subsequent completion of the &, the mine hole process and the patterned circuit process, to reveal that the line daughter board is in an open area, as shown in the figure 2F is shown. For the perforation process, the mine hole, and the patterned circuit process of FIG. 2D and FIG. 2E, please refer to the above embodiment, and details are not described herein again. . Referring to step 2E and FIG. 2F, the circuit board uoa has a predetermined area A corresponding to the position where the release film 21 is located, and the predetermined opening area a ^ may remain - part of the outer layer line (10), but may not retain the part line 2i4b . According to the present invention, a predetermined opening area a is cut by laser and a portion of the insulating film 212 and a portion of the metal case piece 214 covering the predetermined opening area are covered by the surface to reveal the release film 210. Thereafter, the release film 210 is removed to expose the wiring sub-board 100 in an open area C1. In another embodiment, although not shown in the drawings, it is conceivable that the circuit board has, for example, two predetermined opening areas corresponding to the positions of the two release films, wherein the two release films are located in the circuit. The opposite sides of the board. Similarly, a portion of the insulating film on the opposite sides and a portion of the metal foil can be removed by the above description to reveal the two release film. Thereafter, the release film is removed to expose the opposite sides of the wiring daughter board in the two opening regions. - Thus, the circuit board 220a of the present invention is substantially completed and includes: a wiring sub-board 100, an inner wiring board 2, a second insulating film 212, and a patterned wiring layer 214a. The wiring sub-board 1 is buried in the inner circuit board 2 且 and the wiring density of the wiring sub-board 100 is greater than the wiring width of the inner circuit board 200 as the high wiring density area of the circuit board 220. In addition, the slab, the 'film 214' is wrapped around the wiring board 1 , and is isolated between the multiplexed wiring layer 214a and the first and second wiring layers 202, 204. At least one side of the outer circuit board 1 is correspondingly exposed to an opening area d. The opening area C1 can accommodate one or more electronic components (not shown), and is made of a conductive ball or a conductive block (not shown). The pads B of the line daughter board (10) are electrically connected to transmit signals. In the illusion, the circuit board of the present invention integrates the pre-finished high wiring density: Μ-integrated to the general layout (low wiring density) of the inner layer circuit board to simplify the combination of the two insulating films and the two patterned circuit layers. In order to reduce manufacturing costs. Therefore, the circuit board only needs to be - Times® Co., Ltd. 201112888 〇y〇6UUi) 31963twf.doc/n A-length reduction of the conventional multilayer line
板的衣k成本，付合經濟效盈，實為可供產業上利用之發 明。 X 雖然本發明已以實施例揭露如上，然其並非用以限定 斤屬严術領域中具有通常知識者，在不脫離 本發月之精神和關内，當可作些許之更動與潤飾 發明之保護範圍當視後附之申請專利範_界定者為準。 【圖式簡單說明】 作方分翁林糾—實施狀線路板的製 製分麟林發—實補之線路板的 【主要元件符號說明】 10 ： 線路母板 100 線路子板 102 線路；f 104 絕緣層 106 核心基板 200 内層線路板 202 第一線路層 204 第二線路層 206 核心g 11 201112888 ϋ6ϋϋ5 31963twf.doc/n 210 :離型膜 212 :絕緣膠片 214 :金屬箔片 214a :圖案化線路層 214b :外層線路 220、220a :線路板 A:預定開口區域 B :接墊 C :開口 C1 :開口區域 P、P1 :導電通孔 V、VI :導電盲孔The cost of the board's clothing k is economical and effective, and it is an invention that can be used in the industry. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the ordinary knowledge in the field of rigorous surgery, and it is possible to make some changes and refine the invention without departing from the spirit of the present month. The scope of protection shall be subject to the definition of the patent application. [Simple description of the diagram] As a part of the system, the implementation of the circuit board is divided into two parts: the main component symbol description: 10: line mother board 100 line daughter board 102 line; f 104 Insulation layer 106 Core substrate 200 Inner layer circuit board 202 First circuit layer 204 Second circuit layer 206 Core g 11 201112888 ϋ6ϋϋ5 31963twf.doc/n 210: Release film 212: Insulating film 214: Metal foil 214a: Patterned line Layer 214b: outer layer lines 220, 220a: circuit board A: predetermined opening area B: pad C: opening C1: opening area P, P1: conductive via hole V, VI: conductive blind hole