201110098 六、發明說明： 【發明所屬之技術領域】 本發明係與顯示裝置有關，特別是關於一種液晶顯示 裝置(LCD display)的閘極驅動器(gate driver)及其運作方法。 【先前技術】 近年來，由於影像顯示相關之科技不斷地發展，市面上 出現的各式各樣翻態的齡裝置逐漸取代傳統的陰極射線 管(Cathode Ray Tube，CRT)顯示器。其中，液晶顯示農置 (Liquid Crystal DisPlayer，LCD)由於具有省電及不佔空間等優 點，廣受-般消費者的喜愛，因此已絲顯㈣市場上的主 流。 请參照圖一，圖一係繪示傳統的液晶顯示裝置之電源管 理晶片與閘極驅動器之運作情形的示意圖。如圖一所示，傳 統上用於液晶顯示裝置的電源管理晶片i主要包含兩個部 分H周郎器(boost regulat〇r)10以及削角波產生器(鹏 pulsemcxi祕。nswiteh)12。其中，升_節器ω係用以將低 堅^輸入電源物升壓錄高壓_比主獅AVDD。類比 主电源AVDD係用以提供液晶顯示裝置之源極驅動器⑼職 —、G™參考電壓緩衝器、第-電荷幫浦(charge =mp)2以及第二電荷幫浦3所需之電源。至於第一電荷 2及第—電㈣浦3將會分難生高準位輸出電源 及低準位輪出電源VGL，以提供給各侧極驅動器 201110098 後，二顯示裝置之掃蹈線的傳輸 產生電阻及寄生電麵遲之影響而 不同的波端及末端之問極驅動器5的訊號具有 了改呈此二=日顯示裝置所顯示之晝面閃爍。為 準位i出象’第—電荷幫浦2所輸出的高 是先透過Ξ 並不會直接提供給閘極,_11 5，而 號y^c =官理晶片1的削角波產生器12以削角控制訊 產匕生削準位輸出電源VGH進行削角處理，以 出電源訊號VG簡’再將削角輸出電源訊號 VGHM輸出至各閘極驅動器5。201110098 VI. Description of the Invention: [Technical Field] The present invention relates to a display device, and more particularly to a gate driver of a liquid crystal display device and a method of operating the same. [Prior Art] In recent years, as the technology related to image display has been continuously developed, various types of inverted-age devices appearing on the market have gradually replaced conventional cathode ray tube (CRT) displays. Among them, Liquid Crystal DisPlayer (LCD) has been widely loved by consumers because of its advantages of power saving and no space occupation. Therefore, it has become the mainstay in the market. Referring to FIG. 1, FIG. 1 is a schematic diagram showing the operation of a power management chip and a gate driver of a conventional liquid crystal display device. As shown in Fig. 1, the power management chip i conventionally used for a liquid crystal display device mainly includes two parts of a boost regulater 10 and a chamfer wave generator (nwiteh). Among them, the liter-node ω is used to boost the low-voltage input power to the high voltage _ than the main lion AVDD. Analog The main power supply AVDD is used to supply the source driver (9) of the liquid crystal display device, the GTM reference voltage buffer, the first charge pump (charge = mp) 2, and the second charge pump 3. As for the first charge 2 and the first (four) pu 3, the high-level output power supply and the low-level turn-off power supply VGL will be divided to provide the sweeping line transmission of the two display devices after the 201110098. The signal of the driver and the driver of the terminal of the wave terminal and the terminal end which are different in the influence of the resistance and the parasitic electric surface delay are changed to the surface flashing displayed by the display device. For the level i, the output of the first-charge pump 2 is first transmitted through the Ξ and is not directly supplied to the gate, _11 5, and the number y^c = the chamfer wave generator 12 of the wafer 1 The chamfering control signal is used to output the power supply VGH for the chamfering process, and the power output signal VG is simply outputted to the gate drivers 5 by the chamfered output power signal VGHM.
^照圖二，圖二係繪示傳統的電源管理晶片工之削角 ^產生12的—範例。如圖二所示’削角波產生器η利用 兩個PMOS作為開關並且放電節點紐外接至放電 ，阻R1 §削角控制訊號YVC處於高準位時，削角控制訊 號YVC之反向訊號yyC-N則處於低準位，此時，開關η 將會開啟且關P2將會_，故削缝㈣源訊號^ Figure 2, Figure 2 shows the traditional power management chip worker's chamfering ^ produces 12 examples. As shown in Figure 2, the chamfering wave generator η uses two PMOSs as switches and the discharge node nucleus is externally connected to discharge. When the resistance R1 § chamfering control signal YVC is at a high level, the chamfering control signal YVC reverse signal yyC -N is at a low level. At this time, the switch η will be turned on and the P2 will be turned off, so the slash (4) source signal
VGHM 將會被充電至㊣壓電位VGH ;當肖彳脸制喊YVC處於低 準位時’削角控制訊號YVC之反向訊號YvC—N則處於高準 位，此時開關P1將會關閉且開關P2將會開啟，故削角輸 出電源§fl號VGHM將會透過接地的放電電阻尺丨從高壓電位 VGH開始放電。 雖然上述方法能夠改善液晶顯示裴置所遭遇之晝面閃蝶 現象，然而，卻也導致其他難以克服的問題。請參照圖三， 圖三係繪示傳統的削角波產生器12作動的時序圖。如圖三所 示，假設高壓電位VGH為30伏特(v)，削角底部電壓為 201110098 10V。於第一時間間隔tl期間，開關pi關閉且開關P2開 啟’削角輸出電源訊號VGHM將會對放電節點RE開始放電 而形成削角的波形。 接著’當時間進入第二時間間隔t2後，開關P1由原本 的關閉狀態切換至開啟狀態且開關P2由開啟狀態切換至關閉 狀態’由於一般的開關Pi及？2之阻值約為15歐姆或更小， 因此，於開關P1由關閉切換至開啟的瞬間將會產生一突波電 流，其峰值約為(30伏特-10伏特)/15歐姆=13安培。 值得注意的是，隨著液晶顯示裝置之面板尺寸不斷變 大，閘極驅動器的通道(channei)數目亦會變多，使得削角輪 出電源喊VGHM的負載電容變大，導致開關ρι開啟 所形成=突波電流所維持之時間亦變長。另—方面，間極驅 動器的錢電位VGH亦會隨著面板尺寸狀而提高，在削 角底部電壓不_情況下，亦會觀突波電流的峰值變大， 因而，成閘極驅動器以及其封裝線路之損傷。此外，傳統的 電源官理晶丨1為了要將具有刊龍之製程 10及削角波產生器12整人在一击t + 成本，相當不便。I在起’讀·花費許多設計 顯示裝置之閘極驅動 因此，本發明提出一種應用於液晶 器及其運作方法，以解決上述問題。 【發明内容】 根據本發明之第一且I#眚#如丨 /、體實轭例為一種閘極驅動器。該 閘極驅動窃係應用於—液晶基 狀曰日硝不裝置，該閘極驅動器包含複 201110098 削角控制模組。該複數組通道中之每-扭、i、曾 元，分別雛並對應於該複數f通道二削角控制單 接收到之-移位暫存訊號係對應且二 於該複數組通道中之一紐、、 並且該通道係屬 藉以使 電源訊號開始放 得該削角控制單元輸 電而具有削角之波形 位暫存訊號啟動對應於該組通道之即根據該移 入至該通道之一高電位 溫贫*丨丨& >也丨HH - ΧΛ 月控苹丨單元’無以作 根據本發明之第二且體會 - 一體貫施例亦為—種閘極驅動器 施‘ 率’使其與則控制訊號之卫作週率:致:—㈣工作f 體實施例之此實施例 i #地設計纽的時脈訊號的 故可直接以系統 的時脈訊號取代原本的削角控制訊號， 統之設計 以進一步簡化面板系 根據本發明之第三具體實施例為—種_驅動哭運作 ί係應用於—液晶顯示裝置，該閘極驅截 43複數組通道及-削角控制模組，該複數組通道中之每 -組通道包含減個通道脸倾組包含複數侧角 控制單兀，該魏侧肖控财元分卿應於該複數組通 道。 該閘極驅動器運作方法包含下列步驟：首先，該削角 控制模組接收i位暫存訊號。接著，判斷該移位暫=訊號 所對應之該通道係屬於該複數組通道中之—組通道。之後， 根據上述判斷結果啟動該複數個削角控制單元中之對應於髮 201110098 角控制單元。然後，該削角控制單元根據接收 ί雷單元輪入至該通道之一高電位電源訊號開始 放電而具有削角之波形。 所^=發明之優點與精神可㈣由以下的發明詳述及 所附圖式付到進一步的瞭解。 【實施方式】 根t發明之第—具體實施例為—種閘極驅動器。於 只加歹丨中，該閘極驅動器係應用於液晶顯示裝置，但不以 二為，:與先前技術相同的是，魏晶顯轉訪包含電源 管理4及閘極购[細，值躲意岐，由於本發明 係由閘極驅動誠生輸出至各的則輸㈣源，所以當 晶片設計者設計麵管理晶片時，僅f考慮期於升壓調節 器之製程(例如2GV電壓之製程)即可，故可大幅簡化晶片設 计之流程及成本，亦可增加製程選擇上之彈性。 j外更重要的疋，本發明透過分區控制之概念將閘極 驅動益巾之肖|]肖控繼組分好侧脸鮮元，分別控制 不同組通道，崎低⑽控賴組之貞载電容，並且由於削 角控制模組係内建於·驅動器，故可有效避免傳統面板系 統中由於導線負荷(wire l〇ading)現象所導致的m賴降之缺 請參照圖四，圖四係緣示根據本發明之第一具體實施 例之閘祕動n的功能方塊圖。如圖四所示，職驅動器4 201110098 ο έ移位暫存她4卜輸紐能控纖組42、轉偏移模 的、輸出緩衝模組44、削角控麵組Μ。其中，移位暫存 模組41 _接至輸出致能控制模組42 ;輸出致能控制模组幻 位準偏移模組43 ;位準偏移模組43 _至輸出緩衝 、上於此實_中’閘極驅動器4總共包含n俩道，並且 这η個通驗序齡成m組通道，其巾每—輯道均包含： —組通道包含第—通道〜第^通道；第二組通 第2Γ通道;其餘依此類推。n、m及r均 -、I。牛例而言’若 n=4〇〇 且 m=4，則 1-400/4=100，但 不以此為限。如圖四所示，輸出緩衝模組44包含第一輸^ =早兀44!〜第m輸出緩衝單元44m，分麟應於第一組通 ^ / 道；^控制模組45包含第―削角控制單元 元441 f角^山制单^ 45m ’藉以分別透過第一輸出緩衝單 ^4。1〜弟m輸出緩衝單元4知對應於第-組通道〜第m組 人.八f丨#第削角控制單元451接收到之訊號包 s3⑴〜刀/m通道〜第r通道之第一移位暫存訊號 啟遞二&立&子5孔號s(r)、控制第—削角控制單元451開 刀:帝'1功月匕啟動喊GS-Ctli、削角控制訊號YVC以 ’並且第一削角控制單元451將會透過第 之=-早70 441輸出第—高壓電位VGH1至其相對應 I-:、且^道。至於第二削角控制單元452〜第m削角控制 早70 45m則依此類推，於此不另行贅述。 201110098 模組’由於雕轉11 4所包含之致能控制 組，故不移模組43及輸出緩衝模組44已為習知之模 移位暫存/*述。接下來’將相針對本㈣最主要的 細之ί'ΪΓ 41制__45鞭蚊其魏進行詳 請同時參照圖五、圖六Α另闰丄D ^ 少 制模組45中之第一削角控二：^ 452作動的時序圖;圖六A係_角=角= 一削角控制單元451 M L =控職組45中之第 第一組通道及第二组iii削角立^制單元452分別對應於 於圖六a中之第I組通道;^一通圖增六示對應 圖。 之第一通逼的知作模式示意 胸t圖所Γ，於時間Ή時，削角控繼組衫自移位暫存 啟動音ϋΐ 通道，因此，削角控制模組45即备The VGHM will be charged to the positive piezoelectric position VGH; when the Xiaofu face system calls YVC at the low level, the reverse signal YvC-N of the chamfering control signal YVC is at the high level, and the switch P1 will be turned off. And the switch P2 will be turned on, so the chamfered output power supply §fl VGHM will discharge from the high voltage potential VGH through the grounded discharge resistor 丨. Although the above method can improve the phenomenon of the surface flashing phenomenon encountered by the liquid crystal display device, it also causes other insurmountable problems. Referring to FIG. 3, FIG. 3 is a timing diagram showing the operation of the conventional chamfering wave generator 12. As shown in Figure 3, assume that the high voltage potential VGH is 30 volts (v) and the bottom corner voltage is 201110098 10V. During the first time interval t1, the switch pi is turned off and the switch P2 is turned on. The chamfered output power signal VGHM will begin to discharge the discharge node RE to form a chamfered waveform. Then, when the time enters the second time interval t2, the switch P1 is switched from the original closed state to the open state and the switch P2 is switched from the open state to the closed state. Due to the general switch Pi and ? The resistance of 2 is about 15 ohms or less. Therefore, a surge current is generated at the moment when switch P1 is switched from off to on, and its peak value is about (30 volts - 10 volts) / 15 ohms = 13 amps. It is worth noting that as the panel size of the liquid crystal display device continues to increase, the number of channels (channei) of the gate driver will also increase, so that the load capacitance of the chamfering wheel power supply VGHM becomes larger, causing the switch to open. Formation = The time during which the surge current is maintained also becomes longer. On the other hand, the money potential VGH of the interpole driver will also increase with the size of the panel. When the voltage at the bottom of the chamfer is not ,, the peak value of the surge current will also increase, thus forming a gate driver and its Damage to the package line. In addition, the conventional power supply official crystal 1 is quite inconvenient in order to have the process of the magazine 10 and the chamfering wave generator 12 in one stroke. I have read and spent many gates of design display devices. Therefore, the present invention proposes a method for applying to a liquid crystal cell and its operation to solve the above problems. SUMMARY OF THE INVENTION According to the first aspect of the present invention, an I#眚# such as 丨 /, a solid yoke example is a gate driver. The gate drive is applied to a liquid crystal based device, and the gate driver includes a 201110098 chamfer control module. Each of the complex array channels, each of which is twisted, i, and Zeng Yuan, respectively corresponds to the complex f channel, the two chamfer control commands are received, and the shift temporary storage signal corresponds to one of the complex array channels. The button is used to cause the power signal to start to be output by the chamfering control unit, and the waveform having the chamfered bit temporary signal is activated corresponding to the group of channels, that is, according to the high potential temperature of the channel Poverty*丨丨&> also 丨HH - ΧΛ 控 控 丨 ' ' 无 无 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据The control signal is used as the weekly rate: to: (4) work f body embodiment of this embodiment i can design the clock signal of the new design to replace the original chamfer control signal directly with the system clock signal, Designed to further simplify the panel system according to the third embodiment of the present invention, which is applied to the liquid crystal display device, the gate drive 43 complex array channel and the chamfer control module, the plural Each group channel in the group channel contains minus Pour channel group comprising a plurality of side face angle control unit Wu, Wei-side of the sub-Qing Xiao wealth-membered group corresponding to the plurality of channels. The gate driver operation method comprises the following steps: First, the chamfer control module receives an i-bit temporary storage signal. Then, it is determined that the channel corresponding to the shift temporary signal belongs to the group channel in the complex array channel. Then, according to the above determination result, the angle control unit corresponding to the 201110098 is started in the plurality of chamfering control units. Then, the chamfering control unit has a waveform of chamfering according to the reception of the high-power source signal of one of the channels to be discharged. The advantages and spirit of the invention can be further understood by the following detailed description of the invention and the accompanying drawings. [Embodiment] The first embodiment of the invention is a gate driver. In the twisting only, the gate driver is applied to the liquid crystal display device, but not the second one: the same as the prior art, Wei Jingxian's transfer includes power management 4 and gate purchase [fine, value hiding] Since the present invention is driven by the gate drive to the respective (four) sources, when the chip designer designs the wafer management surface, only f considers the process of the boost regulator (for example, the process of 2GV voltage). Yes, it can greatly simplify the process and cost of wafer design, and increase the flexibility of process selection. More importantly, the invention is based on the concept of zone control to drive the gates of the wipes.] The control of the components is better than the components of the face, and the different groups of channels are controlled separately, and the low-level (10) control group Capacitance, and because the chamfering control module is built in the driver, it can effectively avoid the lack of wire l〇ading phenomenon in the traditional panel system. Please refer to Figure 4, Figure 4 The functional block diagram of the gate lock n according to the first embodiment of the present invention is shown. As shown in Fig. 4, the job drive 4 201110098 ο έ shifts the temporary storage of her 4 输 button, the transfer mode, the output buffer module 44, and the chamfer control group Μ. The shift temporary storage module 41_ is connected to the output enable control module 42; the output enable control module magic level offset module 43; the level shift module 43_ to the output buffer, on The real-medium gate driver 4 comprises a total of n lanes, and the n-test passes into m-group channels, and each of the lanes includes: - the group channel includes the first channel - the ^ channel; the second Group the second channel; the rest and so on. n, m and r are both -, I. For cattle example, if n=4〇〇 and m=4, then 1-400/4=100, but not limited to this. As shown in FIG. 4, the output buffer module 44 includes a first input ^=early 44!~m output buffer unit 44m, and the splitting should be in the first group of channels. The angle control unit element 441 f angle ^ mountain system single ^ 45m 'by respectively through the first output buffer unit ^4. 1 ~ brother m output buffer unit 4 knows corresponding to the first group channel ~ m group of people. eight f丨# The first chamfering control unit 451 receives the signal packet s3(1)~knife/m channel~the rth channel, the first shift temporary signal, the second &&& sub-port 5 hole number s(r), control the first-cut The angle control unit 451 is opened: the emperor '1 power month starts shouting GS-Ctli, the chamfer control signal YVC is 'and the first chamfer control unit 451 will output the first high voltage potential VGH1 through the first =- early 70 441 to It corresponds to I-:, and ^ Road. The second chamfering control unit 452 to the mth chamfering control are 70 45 m early, and so on, and will not be described here. 201110098 Module 'Because of the enabling control group included in the engraving 11 4, the immovable module 43 and the output buffer module 44 have been conventionally shifted. Next, we will focus on the most important details of this (four) ί ΪΓ 制 制 制 制 _ 鞭 鞭 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏Angle control two: ^ 452 actuation timing diagram; Figure 6A system _ angle = angle = a chamfer control unit 451 ML = the first group of channels in the control group 45 and the second group iii chamfering unit 452 corresponds to the group I channel in FIG. 6a, respectively; The first popular mode of knowing is shown in the chest t-picture. At time ,, the chamfered control panel is self-shifting and temporarily suspends the sound channel. Therefore, the chamfering control module 45 is ready.
啟動對應於第_組通道 L 削角控制單元451被啟動後义:當第-一削角邏輯控制5| 4510\ 二早兀51之第 關阳，以透過第-AH分·啟開關PS1且關閉開 vgH1至第-組通^輪心解元441輸出第一高塵電仅 备著L當時間開始進入第三時間間隔t3之瞬間，由於削 訊號YVC正好由高#_•㈣岐 角邏輯控制器4510將會根據削角控制訊號YVC分別關^ 201110098 開關PS1且開啟開關pR1。 -如圖五所示，當開關PR1開啟時’相對應之第一通道閑 "^輸出G1★即會開始透過放電節點RE進行放電而得到具有削 出電源訊號G(l)，直到輸出致能訊號OE由 厭Ϊ變為低準位時，第—輸出電源訊號G(1)即會開始處於 阻技从位。實際上，放電節點肪可減至透過放電電 接，之放電路徑(discharging _)，但不以此為限。同理， 二ί —通道閘極輸出G2〜第^通道閘極輸出Gr亦會分 =於弟二日獨間隔t3 _放電而得到 出電源訊號G(2)〜第r輸出電源訊號G(r)。 弟一輪 電源T2正好處於第， 第r輪出電源訊號G(r)所對應°甬:中 由第-控鮮元451所㈣料組通道而 控制料452所控制，亦即第f =則角 同的削角控鮮謂控制，因此，肖,_^ )通係屬於不 對應於第：通道與第肖糾^ 45將會根據 ㈣移位暫存訊號sUtmrf立暫存訊號物或第 ^關閉第-削角控制料，亦即於時間 452。至於第二削角控制單元= 啟第—削角控制單元 制單元451類似，故不另行費述形亦與第-削角控 移位暫存訊絲控制分區編發明主要是揭露-利用Startup corresponds to the _th group of channels L. The chamfering control unit 451 is activated: when the first chamfering logic controls 5|4510\2, the second 兀51 is turned off, to pass the AH-minute splitting switch PS1 and Close the open vgH1 to the first group pass ^ wheel center solution 441 output the first high dust power only when L starts to enter the third time interval t3, because the clipping number YVC happens to be high by #_•(四) corner logic The controller 4510 will respectively turn off the 201110098 switch PS1 and turn on the switch pR1 according to the chamfer control signal YVC. - As shown in Figure 5, when the switch PR1 is turned on, the corresponding first channel idle "^ output G1★ will begin to discharge through the discharge node RE to obtain the cut-off power signal G(l) until the output is When the signal OE changes from versatile to low level, the first output power signal G(1) will start to be in the slave mode. In fact, the discharge node can be reduced to the discharge path (discharging _), but not limited to this. Similarly, the two-channel gate output G2 ~ the ^ channel gate output Gr will also be divided into two on the second day of the interval t3 _ discharge to get the power signal G (2) ~ r output power signal G (r ). The second round of the power supply T2 is in the first position, and the r-th power supply signal G(r) corresponds to the temperature: the middle control unit 451 (four) the material group channel and the control material 452 is controlled, that is, the f = the angle The same chamfering control is called control, therefore, Xiao, _^) is not corresponding to the first: channel and the first xiao ^ ^ 45 will be based on (four) shift temporary signal sUtmrf stand-up signal or ^ close The first-corner control material, that is, at time 452. As for the second chamfering control unit = the first - chamfering control unit unit 451 is similar, so there is no additional description and the same - the chamfering angle shifting temporary storage signal control section is mainly disclosed - use
再者，雖然圖六A所纟 不之開關PR1係採用PM〇S 角力月匕的方法，但不以此為限 元 201110098 件f而於實際應用中’該放電開關亦可改為NM〇S元In addition, although the switch PR1 of Figure 6A adopts the method of PM〇S yoke, but this is not limited to 201110098 pieces f. In practical applications, the discharge switch can also be changed to NM〇S. yuan
壓^卜m由圖八A可知，閘極驅動器4僅需外部給予一低 ^源士彻，即可透過其内部的第—電荷幫浦46及第二電 =浦47自行升壓形成輪出的高壓電位卿及低壓電位 L，故可達到具有單-電源(single哪办)之晶片設計，對 於面板系統設計而言，相當方便且節省設計成本。It can be seen from Fig. 8A that the gate driver 4 only needs to externally give a low source, and can be self-boosted by its internal first-stage charge pump 46 and second power source-pull 47. The high-voltage potential and low-voltage potential L can achieve a single-power (single) wafer design, which is quite convenient for panel system design and saves design cost.
根據本發明之第二具體實施例亦為—種閘極驅動器。 I照圖人B ’圖八B係繪示該閘極驅動器的功能方塊 圖。比較圖八B與圖四所示之閘極驅動器可知，兩者之不 同，處在於’為了能步祕面板系統之設計及減少 訊娩之種類，圖八B係以系統的時脈訊號CLK來取代圖四 中之削角控制訊號YVC。實際上，只錢當地設計系統的時 脈訊號CLK的工作週率(duty cycle)，使其與削角控制訊號 yvc之工作週率一致，即可直接以系統的時脈訊號CLK作 為削角控制訊號之用。至於圖九則係、纟會示圖八B中之削角 控制模組45作動的時序圖。比較圖九與圖五可知，兩者之 差別亦僅在於圖九係以系統的時脈訊號CLK來取代圖五中之 削角控制訊號YVC，故不另行贅述。 綜上所述’本實施例之閘極题動器除了具有避免突波電 流所造成的損傷以及單一電源之晶片設計等優點之外，還能 夠以糸統原本就有的日守脈訊虎CLK來取代削角控制號 12 201110098 計，一 法 内，該閘極驅動器包含複螯 履日日』不裝置 數組通道中之每角控制模組，該複 包錢數_角控制單元，該複數 === 於該複數組通道。 工刺早兀^刀別對應 請參照圖十，圖十係緣示根據本發明之 例的問極驅動器運作方法之流程圖。如圖十所示了首先= =執行倾S1〇，輔編組接收—移位暫存訊號:: =、酋ΓΓ執行步驟S12，判斷該移位暫存訊號所對應之 該通道係屬於該複數組通道中之一組通道。 於實際應財，只要適#地設計系統㈣脈訊號的工作 週率，使其與削角控制訊號之工作週率一致，即可直接以系 統_脈訊餘代原本_角控制訊號。接著，該方法執行 步驟S14 ’根據上述判斷結果啟動該複數個肖彳肖控制單元中 之對應於該組通道之一削角控制單元。然後，於步驟幻6 中’該削角控制單tg根據接收狀—削角控他號開啟該削 角控制單元之一主動開關。實際上，該主動開關可以是 PMOS元件或NM〇s元件。最後’於步驟S18中，該削角控 制單兀輸入至該通道之一高電位電源訊號開始放電而具有削 角之波形45至於詳細的閘極驅動器運作模式可參照上述第一 具體實施例及其相關圖式之說明，於此不另行贅述。 13 201110098 相較於先前技術，根據本發明之閘極驅動器除了能夠有 效避免傳、、級^;原f理晶#產生肖彳肢時所形成的突波電流 對於閘極驅動狀損傷外，還具有採用單—電源、減少訊號 種類以及簡化原本電源管理“設計之複·㈣點。更重 要的疋’本發明透過分區控歡概念將問極驅動器中之削角 控制模組分成多個削角控制料，以降低·控制模組之負 載電谷，並且由於_控糖組係内建於_驅動器 ，故可 有效避免傳統面板系統中由於導線負荷現象所導致的瓜電塵 降之缺點。因此’本發日月之閘極鶴器可大闕化整體面板 顯不系統之設計流程及成本，以贿應用此—閘極驅動器之 面板顯示糸統於市場上之競爭力。 藉由以上較佳具體實施例之詳述，係希望能更加清楚 =核明之特徵與精神，而並非以上述所揭露的較佳具 體實，例，對本發明之範·加以_。相反地’其目的是 希望硓涵盍各種改變及具相等性的安排於本發明 之專利範圍的範轉内。 【圖式簡單說明】 片與閘極 圖係續'示傳統的液晶顯示裝置之電源管理晶 驅動器之運作情形的示意圖。 圖二係綠轉、⑽電源管理晶片之肖❻波產生器的一範 圖.三係繪示傳統的削角波產生器作動的時序圖。 201110098 具'體實施例的閘極驅動 ； 圖四係繪示根據本發明之第 1 器之功能方塊圖。 圖五係繪示圖四中之削角柝告，丨 單元及第二創角控制單元作動的中之第一肖_制 圖六A躲示圖四中之肖彳角 角Γ單元分別對應於第—組i道= '—組通道之不思圖，圖六B孫絡-π -組通道中之第二通道的操作模Α中之第 圖七Α係^示將放電開關改為nm〇s的間極驅動器 之功能方顧，圖七B鱗示對應 ^ 道中之第二通道的操作模式示意圖广A中之$組通 圖八A係繪示圖四中之間托Βτ_ # _ 閘極驅動器進一步包含第一Φ :幫浦及第二電荷幫浦之功能方塊圖；圖八二:;干; 時脈訊號取代㈣控龍紅祕驅姑的魏方^^乂 圖九係繪示圖八B中之削角控制 控制單元及第二削角控制料作動的時序圖。則角 驅動 器運作圖縣㈣之第三賭實_的閑極 【主要元件符號說明】 S10〜S18 :流程步驟 電源控制晶片 G1〜Gn :通道閘極 10 :升壓調節器 15 201110098 12 :削角波產生器 4:閘極驅動器 PR1、PS1、NR1 :開關 RE :放電節點 t2 :第二時間間隔 t3 :第三時間間隔 43 :位準偏移模組 44 :輸出緩衝模組 441〜44m :輸出緩衝單元 DIO :輸入訊號 452 :主動開關 OE :輸出致能訊號 VGG、VGH1 〜VGHm :请 2、 46 :第一電荷幫浦 3、 47 :第二電荷幫浦 Rl、R :電阻 tl :第一時間間隔 Ή、T2 :時間 41 :移位暫存模組 42 :輸出致能控制模組 45 :削角控制模組 451〜45m :削角控制單元 DOI :輸出訊號 CLK :時脈訊號 YVC :削角控制訊號A second embodiment in accordance with the present invention is also a gate driver. I. Figure B shows the functional block diagram of the gate driver. Comparing the gate drivers shown in Figure 8B and Figure 4, the difference between the two is that 'in order to be able to design the panel system and reduce the type of delivery, Figure 8B is based on the system clock signal CLK. Replace the chamfer control signal YVC in Figure 4. In fact, the duty cycle of the local signal system CLK is designed to match the working cycle rate of the chamfering control signal yvc, and the system clock signal CLK can be directly used as the chamfering control. Signal use. As for the figure 9, the timing diagram of the chamfering control module 45 in Fig. 8B is shown. Comparing Fig. 9 with Fig. 5, the difference between the two is only that the system clock signal CLK replaces the chamfer control signal YVC in Fig. 5, so it will not be described separately. In summary, in addition to the advantages of avoiding the damage caused by the surge current and the design of the chip of a single power supply, the gate actuator of the present embodiment can also be used by the Japanese Guardian CLK. To replace the chamfering control number 12 201110098, in one method, the gate driver includes a re-clawing day. The control module for each corner of the array channel is not installed, the multi-package number _ angular control unit, the complex number = == on the complex array channel. Please refer to Fig. 10, which is a flow chart showing the operation method of the pole driver according to the example of the present invention. As shown in FIG. 10, first == execution tilt S1〇, auxiliary group receiving-shift temporary storage signal::=, the emirate performs step S12, and determines that the channel corresponding to the shift temporary storage signal belongs to the complex array. One of the channels in the channel. In the actual financial situation, as long as the working cycle rate of the pulse design signal is the same as that of the chamfer control signal, the system can directly control the signal. Next, the method performs step S14' to start a chamfering control unit corresponding to one of the set of channels in the plurality of control units according to the determination result. Then, in step F6, the chamfer control unit tg turns on one of the chamfer control units to activate the switch according to the receiving state. In fact, the active switch can be a PMOS element or an NM 〇 s element. Finally, in step S18, the chamfer control unit is input to one of the channels, and the high-potential power signal starts to discharge and has a waveform 45 for chamfering. For the detailed gate driver operation mode, reference may be made to the first embodiment described above. The description of the related drawings is not described here. 13 201110098 Compared with the prior art, the gate driver according to the present invention can effectively avoid the transmission, the level, and the surge current formed by the original 理 晶 产生 对于 对于 对于 对于 对于 对于It has a single-power supply, reduces the type of signal, and simplifies the original power management. "Design Complex (4). More importantly, the present invention divides the chamfer control module in the polarity driver into multiple chamfers through the partition control concept. Control material to reduce the load grid of the control module, and because the _ sugar control system is built in the _ drive, it can effectively avoid the shortcomings of the electric dust drop caused by the wire load phenomenon in the traditional panel system. 'The gates of this month and the moon can greatly improve the design process and cost of the overall panel display system, and use the panel of the gate driver to show the competitiveness of the system in the market. DETAILED DESCRIPTION OF THE INVENTION The detailed description of the present invention is intended to provide a clearer understanding of the features and spirit of the invention, and is not to be construed as a preferred embodiment of the invention. It is hoped that the various changes and equal arrangements are within the scope of the patent scope of the present invention. [Simple diagram of the diagram] The slice and gate diagrams continue to show the power management crystal driver of the conventional liquid crystal display device. Schematic diagram of the operation situation. Figure 2 is a schematic diagram of the green-turning, (10) power supply management chip of the Xiaobo wave generator. The three series show the timing diagram of the conventional chamfer wave generator actuation. 201110098 with the 'body embodiment Figure 4 is a functional block diagram of the first device according to the present invention. Figure 5 is a diagram showing the chamfering notice in Figure 4, the first of which is the operation of the unit and the second angle control unit. Xiao _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the operation mode of the channel, the seventh figure of the channel shows the function of changing the discharge switch to the interpole driver of nm〇s, and the figure of Fig. 7B shows the operation mode of the second channel corresponding to the channel. $ group diagram 8A is shown between Figure 4 between the tray τ_ # _ gate driver further Contains the first Φ: the functional block diagram of the pump and the second charge pump; Figure 82: dry; the clock signal replaces (4) the control of the dragon red secret drive Wei Fang ^ ^ 乂 Figure 9 shows the figure eight B The timing diagram of the chamfering control unit and the second chamfering control material in the middle. The angle driver operates the third gambling of the county (4) _ the idle pole [main component symbol description] S10~S18: process step power control chip G1~Gn: channel gate 10: boost regulator 15 201110098 12: chamfer wave generator 4: gate driver PR1, PS1, NR1: switch RE: discharge node t2: second time interval t3: third time interval 43: level shift module 44: output buffer module 441~44m: output buffer unit DIO: input signal 452: active switch OE: output enable signal VGG, VGH1 ~ VGHm: please 2, 46: first charge help Pu 3, 47: second charge pump Rl, R: resistance tl: first time interval Ή, T2: time 41: shift temporary storage module 42: output enable control module 45: chamfer control module 451 ~45m: chamfering control unit DOI: output signal CLK: clock signal YVC: chamfering control signal
VGL :低壓電位 VDD :低壓電源 G(l)〜G(n):輸出電源訊號 S(l)〜S⑻：移位暫存訊號 4510、4520 :削角控制邏輯器 16VGL: Low-voltage potential VDD: Low-voltage power supply G(l)~G(n): Output power signal S(l)~S(8): Shift temporary signal 4510, 4520: Chamfer control logic 16