201118950 32806twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種功率金氧半導體場效電晶體（p〇wer metal-oxide-semiconductor field effect transistor ； p〇wer MOSFET)的製造方法。 【先前技術】 功率金氧半導體場效電晶體被廣泛地應用在切換 (power switch)元件上，例如是電源供應器、整流器 壓馬達控湘料。言’功率金氧半導體場效電晶 體多採取垂直結構的設計，以提升元件密度。其利用晶片 之背面作為祕，而於晶片之正面製作多個電晶體之源極 以及閘極。由於多個電晶體线極是並聯在—祕，因此 其所耐受之電流大小可以相當大。 隨著功率金氧半導體場效電晶體之積集度的日益提 升’功率金氧半導體場效電晶體之尺寸亦隨之縮小。因 此’功率金氧半導料效電晶體之接觸崎溝渠的對準偏 差（misalignment)容易產生，進而影響元件的效能。 舉例來說，接觸洞對溝渠的對準偏差會影響通道開啟 !阻（Ron) A臨界電壓（vth)的變異，進而限制 單元間之間距（cell pitch )的縮小。 此外，功率金氧半導體場效電晶體的工作損失可分成 切換損失（SwitChingk>ss)及導通損失（c〇nduc'tingl〇ss) 201118950 32806twf.doc/n 兩大類，財’因輸人電纟Cissm造成的i刀換損失會因操 =頻率的提高增加。輪人電容Qss包括祕對源極之電 容Cgs以t閘極對汲極之電容Cgd。因此，如何降低間極對 汲極之電容cgd以有效地降低切換損失，已成為業者亟 重視的議題之一。 【發明内容】 有鑑於此，本發明提出—種功率金氧半導體場效電晶 體的製^方法’其利用削減製程及自對準製程，可以避免 功率金^半導體場效電晶體之接觸洞對溝渠的對準偏 差’並製作出具有低的閘極對汲極之電容C 功率金氧 半導體場效電晶體。 、本發明提出一種功率金氧半導體場效電晶體的製造 方，。^先，於具有第一導電型之基底上形成具有第一導 電型之遙晶層。然後’於蠢晶層中形成具有第二導電塑的 主體層。接著，於基底上形成多數個罩幕圖案。之後，於 罩幕圖案，間社_及部分Μ層中形舒數個溝渠。. ，之:於溝渠的表面形成第—氧化物層。然後，於溝渠中 ❿成第。接著，對罩幕贿進行誠製程，以縮 小各罩幕圖㈣線寬。之後’以經誠的罩幕随為罩幕， =各，渠的兩側的主體層中形成具有第—導電型的二源極 ，。繼之’於第—導體層上及經肖憤的罩幕圖案之間形成 夕數個；|電®案H移除經削減的罩幕圖案。 在本發明之一實施例中，於形成第一氧化物層的步驟 201118950 32806twf.doc/n 之後以及形成第=導體層的步驟之前，上述方法更包括於 溝渠的底部及罩幕圖案的頂部形成第二氧化物層。 在本發明之-實施例中，上述第二氧化物層的材料包 括介電常數低於4的氧化物。 在本發明之-實施例中，形成上述第二氧化物層的步 驟描述如下。首先，於聽上依序形縣幕層及氧化物材 料層。然後，以科層驗擋層’猶位赠渠及罩幕圖 ，之侧壁上的氧化物材料層。接著，移除未被第二氧化物 層覆蓋的罩幕層。此外’罩幕層的㈣包減化石夕。 在本發明之-實施例中，於溝渠中形成第一導體層的 =描述如下。首先，於基底上形成導體㈣層以填入溝 =触,然後，對導體材料層進行全面勤⑶程，以移除部 刀V體材料層。此外，全面钱刻製程包括乾钱刻製程。 於主實施财，上述第—導體層的表面不高 步發實施财，於移除經削減的罩幕圖案的 ^驟^，上述方法更包括於基底上形成第二導體層，且 ^^ 源極區電性連接。此外，第二導體層的_ 步驟2發明之一實施例中’於移除經削減的罩幕圖宰的 步驟之後以及形成第二導體層的步驟之前^ =介電圖案為罩幕’於主體層中形成 返2 多數個摻雜區，且第二導體層與摻雜區電性型的 在本發明之一實施例中’上述削減製程包括祕刻 201118950 32806twf.doc/n 程。 在本發明之一實施例中，形 述如下。首先，於基底上形成介步驟描 後’移除部分介電層，直到曝露Atm幕圖案°然 移除部分介電層的步驟包括、卜罩幕圖案的表面。此外， 製程。f層的步驟包括進仃⑽刻法或化學機械研磨 化石夕。 在本發明之—實施例中，上述罩幕 圖案的材料包括氮 在本發批-實施财，上 多層的堆疊結構。 夢口系匕祜早一層或 在本發明之—實施例中， 摻雜多晶發。、 “體層的材料包括 及狀—實關+，鄉成Μ層財驟之後以 =層的步驟之前’上述方法更包括於基底上形成 f本發狄—實施财，形成上述第 物 騍包括進行熱氧化製程。201118950 32806twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a semiconductor device, and more particularly to a power MOS field effect transistor (p〇wer metal- Oxide-semiconductor field effect transistor ; manufacturing method of p〇wer MOSFET). [Prior Art] Power MOS field effect transistors are widely used in power switch components such as power supplies and rectifier voltage control devices. The 'power MOS field effect electric crystals are mostly designed with vertical structures to increase the density of components. It uses the back side of the wafer as a secret, and the source and gate of a plurality of transistors are fabricated on the front side of the wafer. Since the plurality of transistor lines are connected in parallel, the current they can withstand can be quite large. With the increasing integration of power MOS field effect transistors, the size of power MOS field effect transistors has also shrunk. Therefore, the misalignment of the contact sag of the power MOS transistor is easy to occur, which in turn affects the performance of the device. For example, the misalignment of the contact hole to the trench affects the variation of the channel opening resistance (Ron) A threshold voltage (vth), which in turn limits the cell pitch reduction. In addition, the operating loss of the power MOS field effect transistor can be divided into switching loss (SwitChingk > ss) and conduction loss (c〇nduc'tingl 〇 ss) 201118950 32806twf.doc / n two categories, the wealth of the loss of electricity The i-knife change loss caused by Cissm will increase due to the increase of the frequency of operation. The wheel capacitance Qss includes the capacitance Cgs of the source-to-source and the capacitance Cgd of the gate-to-drain. Therefore, how to reduce the capacitance cgd of the pole-to-pole to effectively reduce the switching loss has become one of the topics that the industry has paid attention to. SUMMARY OF THE INVENTION In view of the above, the present invention proposes a method for fabricating a power MOS field effect transistor, which can avoid contact hole pairs of power gold semiconductor field effect transistors by using a process and a self-aligned process. The alignment deviation of the trenches' and the fabrication of a capacitor C-power MOSFET with a low gate-to-drain. The invention provides a method for manufacturing a power MOS field effect transistor. First, a crystal layer having a first conductivity type is formed on a substrate having a first conductivity type. A body layer having a second conductive plastic is then formed in the stray layer. Next, a plurality of mask patterns are formed on the substrate. After that, a number of ditches were formed in the mask pattern, the inter-community _ and the part Μ layer. . . : forming a first oxide layer on the surface of the trench. Then, in the ditch, it becomes the first. Next, make a process of making a bribe to reduce the line width of each mask (4). After that, the mask is used as a mask, and each has a second source having a first conductivity type in the main layer on both sides of the channel. Subsequent to the first conductor layer and the whispering mask pattern are formed; the electric meter H removes the reduced mask pattern. In an embodiment of the present invention, after the step of forming the first oxide layer 201188850 32806twf.doc/n and before the step of forming the second conductor layer, the method further comprises forming at the bottom of the trench and at the top of the mask pattern. a second oxide layer. In an embodiment of the invention, the material of the second oxide layer comprises an oxide having a dielectric constant of less than 4. In the embodiment of the present invention, the steps of forming the above second oxide layer are described below. First of all, it sounds like a sequence of county curtains and oxide material layers. Then, the layer of oxide material on the side wall of the barrier layer and the mask is attached. Next, the mask layer not covered by the second oxide layer is removed. In addition, the (four) package of the cover layer reduces the stone eve. In the embodiment of the invention, the formation of the first conductor layer in the trench is described as follows. First, a conductor (four) layer is formed on the substrate to fill the trench = touch, and then the conductor material layer is subjected to a full-scale (3) process to remove the V-body material layer. In addition, the comprehensive money engraving process includes a dry money engraving process. In the main implementation, the surface of the first conductor layer is not high, and the method for removing the reduced mask pattern further comprises forming a second conductor layer on the substrate, and the source region is Electrical connection. In addition, in the second embodiment of the second conductor layer, in the embodiment of the invention, after the step of removing the reduced mask pattern and before the step of forming the second conductor layer, the dielectric pattern is a mask In the layer, a plurality of doped regions are formed, and the second conductor layer and the doped region are electrically typed. In one embodiment of the present invention, the above-described reduction process includes a secret engraving 201118950 32806 twf.doc/n. In an embodiment of the invention, the description is as follows. First, forming a dielectric layer on the substrate to remove a portion of the dielectric layer until the Atm curtain pattern is exposed. The step of removing a portion of the dielectric layer includes the surface of the mask pattern. In addition, the process. The steps of the f layer include enthalpy (10) engraving or chemical mechanical polishing fossil eve. In an embodiment of the invention, the material of the mask pattern comprises nitrogen in the present invention. The dream mouth is one layer earlier or in the embodiment of the invention, doped polycrystalline hair. "The material of the body layer includes the shape---------------------------------------------------------------------------------------------------------------------------- Thermal oxidation process.
電型為P型，第二導電型為N 在本發明之—實施例中，上述第—導電型為㈣，第 一導電型為p型；或第一導 型。 基於上述，本發明的方法利用削減製程及自對準製程 由形《渠料幕圖案_成功率金氧半導體場效電 曰曰體的接觸窗’因此接觸窗與溝渠之間不會發生對準偏 所以，可以大幅縮小單元間的間距，提高元件的集積 201118950 32806twf.doc/n 度。此外，本發明的方法相當簡單，不 利用自對準製程即可而曰加額外的先罩’ 作，大幅節省成本觸窗㈣ (" gp ^ ,. 另外，本發明的閘氧化 物層（即弟-乳化物層）為經由熱 = 不連續之接面而丄= ,,β 本發明於溝渠之底部形成的底氧化 :層（㈣二氧化物層）的材料為介電常數低於4的氧化 :二：此可以降低間極對汲極之電容。，有效地減少切 換才貝失。 為讓本發明之上述待徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 圖1A至1H為依據本發明一實施例所繪示的一種功 率金氧半導體場效電晶體的製造方法之剖面示意圖。 首先，請參照圖1A，於作為汲極之具有第一導電型 之基底102上形成具有第一導電型之磊晶層1〇4。基底1〇2 例如是具有N型重摻雜之矽基底。磊晶層1〇4例如是具有 N型輕摻雜之磊晶層，且其形成方法包括進行選擇性磊晶 生長（selective epitaxy growth ; SEG)製程。接著，於磊晶層 104中形成具有第一導電型的主體層1〇6。主體層例如 疋P型主體層，且其形成方法包括進行離子植入製程與後 續的驅入（drive-in)製程。在一實施例中，於形成磊晶層 104的步驟之後以及形成主體層1〇6的步驟之前，也可以 201118950 32806twfdoc/n 選擇性地於基底102上形成墊氧化物層105。墊氧化物層 • 105可以避免進行離子植入製程以形成主體層ι06時造成 ‘ 的穿隧效應（tunnelingeffect)。墊氧化物層1〇5的材料例 如是氧化矽，且其形成方法例如是進行熱氧化製程。 然後，於基底102上依序形成罩幕層log及圖案化光 阻層110。罩幕層108的材料包括氮化矽，且其形成方法 包括進行化學氣相沉積（CVD)製程。在一實施例中，罩 幕層1〇8例如是厚度約5000〜6000埃的單一氮化矽層，如 圖1所示。在另一實施例中（未繪示），依製程需要，罩 幕層108也可以為多層結構，例如包括底氮化石夕層及頂氧 化矽層之雙層結構。 、 之後，請參照圖1B，以圖案化光阻層11〇為罩幕， 對罩幕層108及墊氧化物層105依序進行圖案化，以於基 底1〇2上形成墊氧化物圖案105a及罩幕圖案1〇8&。繼之 移除圖案化光阻層110。接下來，以罩幕圖案1〇如為罩幕， 進，乾蝕刻製程，以於罩幕圖案1〇8a之間的主體層1〇6 • 及部分蠢晶層1〇4中形成多數個溝渠112。在一實施例中， 於形成溝渠112的步驟之後，也可以選擇性地對溝渠112 表面進行等向性蝕刻製程，以移除溝渠112的表面損傷。 =後，也可以選擇性地於基底1()2上形成犧牲氧化物層（未 • ^不^再移除之，以修補溝渠112的表面晶格破壞。特別 ’主思的是，當上述的罩幕層1〇8為包括底氮化矽層及頂 化矽層之雙層結構時，在移除犧牲氧化物層的步驟中， 也會將頂氧化矽層一併移除之。 201118950 32806twf.doc/n 接著’請參照圖ic，於、、盖泪110 一 層114。氧化物層114的材料的表面形成氣化物 法例如是進行熱氧化動 ’且其形成方 刚〜麵埃。在一實施心魏物層114的厚度例如是约 約500埃。然後，於基底ω =度例如是 化物材料層118。形成罩幕声成罩幕層116及氧 _ _ t 取卓綦層116及氧化物材料層^ 方法υ括進行化學氣相沉積製程。罩幕層u ， =〇〇埃的氮化料。氧化物材料層118的材料包 吊數低於4的氧化物。氧化物材料層118例如是厚卢： :氧化购而，由於化學氣相沉積Ϊ=Ϊ 制，乳化物材料層118於罩幕圖案刚㈣頂部及溝渠山 之底部的厚度通常大於氧化物材料層118於溝渠112及罩 幕圖案l〇8a之側壁的厚度。在一實施例中，氧化物材料層 m於罩幕圖案驗的頂部及溝渠m的底部的厚度約^ 4〇〇〇埃，但其於溝渠112及罩幕圖案1〇8a之側壁的厚; 約為2000埃。 又 之後，請參照圖1D ’以罩幕層116為阻擋層（stop layer) ’進行全面蝕刻（bianketetching)製程，以移除位 於溝、112及罩幕圖案i〇ga之側壁上的氧化物材料層 118 ’並留下位於罩幕圖案1〇8a的頂部及溝渠112之底部 的氧化物層120。在一實施例中，氧化物層120的厚度約 為2000埃。全面蝕刻製程例如是濕蝕刻製程，其使用的蝕 刻液例如為姓刻氧化緩衝液（buffer oxide etchant ’ BOE)或 稀釋之氫氟酸（diluted hydrofluoric acid，DHF)。繼之，移 201118950 32806twf.doc/n ' 除未被氧=物層120覆蓋的罩幕層116。移除未被氧化物 .I 12G覆蓋的罩幕層116的方法例如是進行祕刻製程， 其使用的姓刻液例如為鱗酸（ph〇sph〇ric ，氏p〇4)。特 别要說明的疋，於溝渠112之底部形成氧化物層m的目 =是為了降低閘極對汲極之電容Cgd，以有效地減少切換 知失。在不考慮間極對祕之電容Cgd的情況下，也可以 不形成溝渠112之底部的氧化物層12〇。也就是說，可以 • 痛'略下列步驟：形成罩幕層116及氧化物材料層118的步 驟、移除部分氧化物材料層118㈣成氧化物層12〇的步 驟、以及移除未被氧化物層12G覆蓋的罩幕層π6的步驟。 然後’請參照圖1E，於各溝渠112中形成導體層122。 形成導體層m的步驟包括於基底102上形成導體材料層 121 (如圖1D所示）以填入溝渠112中。導體材料層ΐ2ι =材料例如是摻雜多晶，接著，對導體材料層⑵進行 全面蝕刻製程，以移除部分導體材料層121。在一實施例 中，全面蝕刻製程例如是以氧化物層12〇為阻擋層的乾蝕 藝難程’如圖1E所示。在另—實施例中，當未形成上述 的氧化物層120時，全面钱刻製程例如.是利用時間模式 (time m〇de)來決定蝕刻終點的乾蝕刻製程。在一實施例中， 於形成導體層122的步驟之後，也可以選擇性地對導體層 進行熱氧化製程，以提高導體層122的耐電壓程度。 - 導體層122的表面不高於主體層106的表面，也就 是°兑，導體層122的表面實質上等於或低於主體層106的 表面。之後，移除罩幕圖案108a上的氧化物層12〇。 釦之，凊參照圖1F ’對罩幕圖案i〇ga進行削減製程， 201118950 32806twf.doc/n 以縮小各罩幕圖案1〇如的 (如圖1E所示)縮小為％ (如罩的線寬由 例如為濕蝕刻製程，其使用的蝕刻‘例如為：酿削減製程 於罩幕圖_a上的 =幕^6步=會同時移除位 圖案職為罩幕，於各漢泪曰 …、、後’以，_減的罩幕 成且右笛一道帝別、各溝木U2的兩側的主體層忉6中形 有^型重_^^源極區124。源極區124例如是具 是磷或是坤。形成 程，W 括進離子植入製程與後續的驅入製 :下Γ=分源極區124會延伸到罩幕圖案應a 幕圖荦1G1H區124的離子植人製程是以經削減的罩 S案108a為罩幕，因此為—種自對準製程（祕 process)。 接著，請參照圖1G，於導體層122上及經削減的罩幕 圖案108a之間形成多數個介電圖案126。形成介電圖案126 的步驟包括於基底1〇2上形成介電層125 (如圖ip所示） ，覆盍經削減的罩幕圖案108a。介電層125的材料例如是 氧化矽、硼磷矽玻璃（BPSG)、磷矽玻璃（PSG)、氟矽玻 璃（FSG)或未摻雜之矽玻璃（USG)，且其形成方法包 括進行化學氣相沉積製程。然後，移除部分介電層125， 直到曝露出經削減的罩幕圖案丨〇 8 a的表面。移除部分介電 層125的方法包括進行回钱刻法或化學機械研磨（cmp) ‘程。特別要注意的是，在此步驟中，介電圖案126與罩 幕圖案108a實質上為互補圖案。 12 201118950 32806twf.doc/n 繼之之圖1H ’移除經削減的罩幕圖案隐。 ::觸物圖案咖，以形成介電圖案126之間 刻制程除塾氧化物圖案1G5a的方法例如是濕餘 二钱刻液例如為钱刻氧化緩衝液（B0E)或 幸105里的牛驟由酌。在一實施例中，於移除塾氧化物圖 =5a的步驟中，也會同時移除部分的介電圖案12 :來1 =電圖案126為罩幕，於主體層1〇6+形成具有 數個摻雜區128。形成摻雜區128的目的 成的接觸窗與主體層106之間的電阻。 具有ρ型重摻雜之摻雜區。ρ型雜質例 程是以介電圖_ 马車泰’因此為一種自斜車製采 成導體層13。，導體声13=，考，於基底102上形 性連接。# 區124及換雜區128電 進行化㈣如妓’且其形成方法包括 化學氧相沉積製程。至此，完成本發明之功率金氧丰 導體場效電晶體100的製造。 之力早金氧+ ^以上的實施例中，是以第一導電 =Γ例來說明之，但本發明並不以此為限= 應了解，第-導電型也可以為。型，而第二導電 ,綜上所述’本發明之功率金氧半導體場效 的形成方法包括對形成溝渠112的罩幕圖安1〇8 =7小其線寬。然後’以罩幕圖案1〇:為:幕仃 木兩側的主體層106巾形成源極區124。接著，形成 13 201118950 32806twfdoc/n 經削減之轉_驗的補伽案（即 之後’移除經削減之罩幕圖案驗以形成接^26)。 知後績形成的導體層130與源極區124電性連 使 也就是說，本發明的方法藉由 而形成功率金氧半導體場效電晶體10二=;，製私 觸窗與溝渠U2之間不會發，觸固’因此接 ΛΑ „ θ1χ生對準偏差。所以，可以最小 微马機°換言之’溝渠職渠的距離可以縮小至 二：對而經由形成溝渠的罩幕圖案_來形成接 ^ ’所㈣以大幅縮小單元間關距，提高元件的集積 光罩，利用當簡單’不需增加額外的 及接觸窗的製作，：畐節源極區124、摻雜區128 <丨f人ΐ田即嗜成本，提升競爭力。 由熱氧化製ί發=氡:物層(即氧化物層114)為經 有不^之接面叫似件效能的情形發生。 氧化物心明於溝渠112之底部形成的底氧化物層（即 =:z=r容rr—^ 電谷cgd ’有效地減少切換損失。 太旅日日、'日月已以貫拖例揭露如上，然其並非用以限定 本i明之精;中具有通常知識者’在不脫離 靶圍内，§可作些許之更動與潤飾，故本 " …㉚15當錢社申請專娜賴界定者為準。 201118950 32»uotwf.doc/n 【圖式簡單說明】 圖1A至1H為依據本發明一實施例所繪示的一種功 1 率金氧半導體場效電晶體的製造方法之剖面示意圖。 【主要元件符號說明】 100 :功率金氧半導體場效電晶體 102 :基底 104 ·蟲晶層 • 105 :墊氧化物層 105a :墊氧化物圖案 106 :主體層 108、116 :罩幕層 108a :罩幕圖案 110 :圖案化光阻層 112 :溝渠 114、120 :氧化物層 118 :氧化物#料層 121 :導體材料層 122、130 :導體層 124 :源極區 ' 125 :介電層 126 :介電圖案 ‘ 127:接觸洞 128 :摻雜區 Wl、W2 :線寬 15The electric type is P type, and the second conductivity type is N. In the embodiment of the invention, the first conductivity type is (4), the first conductivity type is p type; or the first type. Based on the above, the method of the present invention utilizes the process of reducing the process and the self-aligned process by the shape of the "drain screen pattern _ success rate of the metal oxide semiconductor field effect contact body window" so that no alignment occurs between the contact window and the trench Therefore, it is possible to greatly reduce the spacing between cells and increase the accumulation of components 201118950 32806twf.doc/n degrees. In addition, the method of the present invention is relatively simple, without the use of a self-aligned process, but with the addition of an additional hood, a substantial cost-saving window (4) (" gp ^ ,. In addition, the gate oxide layer of the present invention ( That is, the emulsion-emulsion layer is 经由= via the heat=discontinuous junction, β, the bottom oxidation of the present invention formed at the bottom of the trench: the material of the layer ((four) dioxide layer) has a dielectric constant of less than 4 Oxidation: 2: This can reduce the capacitance of the interpole to the drain. Effectively reduce the switching loss. In order to make the above described advantages and advantages of the present invention more obvious, the following specific embodiments and cooperation BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1H are schematic cross-sectional views showing a method of fabricating a power MOS field effect transistor according to an embodiment of the invention. First, please refer to FIG. 1A. An epitaxial layer 1〇4 having a first conductivity type is formed on the substrate 102 having the first conductivity type as a drain. The substrate 1〇2 is, for example, a germanium substrate having an N-type heavily doped. The epitaxial layer 1〇4 For example, an N-type lightly doped epitaxial layer is formed The method includes a selective epitaxy growth (SEG) process. Next, a body layer 1〇6 having a first conductivity type is formed in the epitaxial layer 104. The body layer is, for example, a p-type body layer, and the method of forming the same Including an ion implantation process and a subsequent drive-in process. In an embodiment, after the step of forming the epitaxial layer 104 and before the step of forming the body layer 1〇6, it may also be 201118950 32806twfdoc/n A pad oxide layer 105 is selectively formed on the substrate 102. The pad oxide layer 105 can avoid the tunneling effect caused by the ion implantation process to form the bulk layer ι06. The pad oxide layer 1〇5 The material is, for example, yttrium oxide, and is formed by, for example, performing a thermal oxidation process. Then, a mask layer log and a patterned photoresist layer 110 are sequentially formed on the substrate 102. The material of the mask layer 108 includes tantalum nitride. And the forming method comprises performing a chemical vapor deposition (CVD) process. In an embodiment, the mask layer 1〇8 is, for example, a single layer of tantalum nitride having a thickness of about 5000 to 6000 angstroms, as shown in FIG. One In the embodiment (not shown), the mask layer 108 may also have a multi-layer structure, for example, a two-layer structure including a bottom nitride layer and a top yttrium oxide layer, as required by the process. The photoresist layer 11 is a mask, and the mask layer 108 and the pad oxide layer 105 are sequentially patterned to form a pad oxide pattern 105a and a mask pattern 1〇8& on the substrate 1〇2. The patterned photoresist layer 110 is removed. Next, the mask pattern 1 is used as a mask, and the dry etching process is performed to cover the main layer 1〇6 between the mask patterns 1〇8a and a part of the stupid A plurality of trenches 112 are formed in the crystal layer 1〇4. In an embodiment, after the step of forming the trench 112, the surface of the trench 112 may be selectively subjected to an isotropic etching process to remove surface damage of the trench 112. After =, a sacrificial oxide layer may also be selectively formed on the substrate 1 () 2 (not removed) to repair the surface lattice damage of the trench 112. In particular, the main idea is that when When the mask layer 1〇8 is a two-layer structure including a bottom tantalum nitride layer and a topped tantalum layer, in the step of removing the sacrificial oxide layer, the top tantalum oxide layer is also removed. 201118950 32806twf.doc/n Then, please refer to Figure ic, and cover the tear 110 layer 114. The surface of the material of the oxide layer 114 forms a vaporization method, for example, thermal oxidation, and the formation of the square just ~ face. The thickness of the core layer 114 is, for example, about 500 angstroms. Then, the substrate ω = degree is, for example, the material layer 118. The mask is formed into a mask layer 116 and the oxygen layer _ _ _ The material layer method includes a chemical vapor deposition process, a mask layer u, a nitride material, and an oxide material layer 118 having an oxide number lower than 4. The oxide material layer 118 For example, thick lum:: oxidized, due to chemical vapor deposition Ϊ = ,, the emulsifier material layer 118 is covered The thickness of the top of the pattern (4) and the bottom of the trench mountain is generally greater than the thickness of the oxide material layer 118 on the sidewalls of the trench 112 and the mask pattern 10a. In one embodiment, the oxide material layer m is inspected by the mask pattern. The thickness of the bottom of the top and the trench m is about 4 angstroms, but the thickness of the sidewalls of the trench 112 and the mask pattern 1 〇 8a is about 2000 angstroms. After that, please refer to FIG. 1D for the mask layer. 116 is a stop layer' bianketetching process to remove the oxide material layer 118' on the sidewalls of the trenches 112 and the mask pattern i〇ga and leave the mask pattern 1〇 The top of 8a and the oxide layer 120 at the bottom of the trench 112. In one embodiment, the oxide layer 120 has a thickness of about 2000 angstroms. The full etch process is, for example, a wet etch process using an etchant such as a last name oxidized Buffer oxide etchant 'BOE' or diluted hydrofluoric acid (DHF). Next, move 201118950 32806twf.doc/n ' except for the mask layer 116 that is not covered by the oxygen layer 120. A cover that is not covered by an oxide.I 12G The method of layer 116 is, for example, a secret engraving process, and the surname used is, for example, scaly acid (ph〇sph〇ric, p〇4). In particular, an oxide layer m is formed at the bottom of the trench 112. The purpose of the purpose is to reduce the capacitance of the gate to the drain Cgd to effectively reduce the switching loss. The oxide layer 12 at the bottom of the trench 112 may not be formed without considering the capacitance Cgd of the interpole. Hey. That is, the following steps can be performed: the steps of forming the mask layer 116 and the oxide material layer 118, removing the portion of the oxide material layer 118 (4) into the oxide layer 12, and removing the oxide. The step of covering the mask layer π6 by the layer 12G. Then, referring to FIG. 1E, a conductor layer 122 is formed in each of the trenches 112. The step of forming the conductor layer m includes forming a conductive material layer 121 (shown in FIG. 1D) on the substrate 102 to fill the trench 112. The conductor material layer =2ι = the material is, for example, doped polycrystal, and then the conductor material layer (2) is subjected to a comprehensive etching process to remove a portion of the conductor material layer 121. In one embodiment, the full etch process is, for example, a dry etch process with the oxide layer 12 〇 as a barrier layer as shown in Figure 1E. In another embodiment, when the oxide layer 120 described above is not formed, the full etching process is, for example, a dry etching process that uses a time mode to determine the end point of the etch. In one embodiment, after the step of forming the conductor layer 122, the conductor layer may be selectively subjected to a thermal oxidation process to increase the withstand voltage of the conductor layer 122. The surface of the conductor layer 122 is not higher than the surface of the body layer 106, that is, the surface of the conductor layer 122 is substantially equal to or lower than the surface of the body layer 106. Thereafter, the oxide layer 12A on the mask pattern 108a is removed. According to FIG. 1F', the mask pattern i〇ga is cut, 201118950 32806twf.doc/n to reduce the size of each mask pattern 1 (as shown in FIG. 1E) to % (such as the line of the cover) The width is, for example, a wet etching process, and the etching used is, for example, the brewing reduction process on the mask screen _a = screen ^ 6 steps = will simultaneously remove the bit pattern as a mask, in each Han tears... After the ', _ minus the mask is formed and the right flute is a different part, and the main layer 忉6 on both sides of each trench U2 is shaped with a ^-type source region 124. The source region 124 is for example Is a phosphorus or Kun. Formation process, W enrollment ion implantation process and subsequent drive-in system: Γ = sub-source region 124 will extend to the mask pattern should be a screen map 荦 1G1H area 124 ion implant The human process is based on the reduced mask S case 108a, so it is a self-aligned process. Next, please refer to FIG. 1G, between the conductor layer 122 and the cut mask pattern 108a. A plurality of dielectric patterns 126 are formed. The step of forming the dielectric pattern 126 includes forming a dielectric layer 125 on the substrate 1 ( 2 (as shown in ip), covering the reduced mask pattern 108a. The material of the dielectric layer 125 is, for example, yttrium oxide, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), fluorocarbon glass (FSG) or undoped bismuth glass (USG), and the method of forming the same includes A chemical vapor deposition process is performed. Then, a portion of the dielectric layer 125 is removed until the surface of the reduced mask pattern 丨〇 8 a is exposed. The method of removing a portion of the dielectric layer 125 includes performing a money engraving or chemistry Mechanical Grinding (cmp) 'Cycle. It is important to note that in this step, the dielectric pattern 126 and the mask pattern 108a are substantially complementary patterns. 12 201118950 32806twf.doc/n Figure 1H The reduced mask pattern is hidden. The method of forming the photoresist pattern 1G5a between the dielectric pattern 126 and the engraving process is, for example, a wet residue etching solution such as a money etching buffer (B0E). Or fortunately, the boil of 105 is considered. In an embodiment, in the step of removing the niobium oxide pattern = 5a, part of the dielectric pattern 12 is also removed at the same time: 1 = the electric pattern 126 is a mask Forming a plurality of doping regions 128 in the body layer 1〇6+. The purpose of forming the doping region 128 The resistance between the contact window and the body layer 106. There is a doped region of p-type heavily doped. The p-type impurity routine is based on the dielectric diagram _ Ma Chetai', so it is a self-slanting vehicle to produce a conductor layer. 13. The conductor sound 13=, test, is formed on the substrate 102. The #124 and the impurity-changing region 128 are electrically converted (4), such as 妓', and the formation method thereof includes a chemical oxygen phase deposition process. Up to this point, the present invention is completed. The manufacture of the power metal oxide conductor field effect transistor 100. The embodiment of the force of the early gold oxide + ^ is described by the first conductivity = example, but the invention is not limited thereto. The first conductivity type can also be. And the second conductive, in summary, the method of forming the power MOS field effect of the present invention includes forming a mask of the trench 112 with a line width of 1 〇 8 = 7 small. Then, the source region 124 is formed by the mask pattern 1 〇: the main layer 106 on both sides of the curtain. Next, a compensated gamma case of 13 201118950 32806 twfdoc/n is formed (i.e., the cut mask pattern is removed to form a joint). The conductor layer 130 formed by the prior art is electrically connected to the source region 124. That is to say, the method of the present invention forms a power MOS field effect transistor 10=;, the private contact window and the trench U2 There will be no hair, and the contact will be ' 因此 θ θ1 对准 对准 对准 。 。 。 。 。 。 。 。 。 。 。 θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ Connected to '4' to greatly reduce the distance between the units, improve the component's accumulation mask, using the simple 'no need to add additional and contact window production:: 源 source region 124, doped area 128 < f people squatting is cost-effective and enhances competitiveness. From thermal oxidation to 发: 氡: the layer of matter (ie, oxide layer 114) occurs in the case of a device that has a similar effect. The bottom oxide layer formed at the bottom of the trench 112 (ie, =: z = r rong rr - ^ electric valley cgd ' effectively reduces the switching loss. The day of the tour, the 'day and the moon have been exposed as above, but it is not Used to define the essence of the present; those with the usual knowledge 'without leaving the target, § can be made Xu Zhichang and retouching, so this " ... 3015 when the money agency applied for the definition of the general. The 201118950 32»uotwf.doc / n [Simple diagram of the drawings] Figures 1A to 1H in accordance with an embodiment of the present invention A schematic cross-sectional view of a method for fabricating a work-rate MOSFET. [Main component symbol description] 100: Power MOS field effect transistor 102: substrate 104 · worm layer • 105: pad oxidation Material layer 105a: pad oxide pattern 106: body layer 108, 116: mask layer 108a: mask pattern 110: patterned photoresist layer 112: trenches 114, 120: oxide layer 118: oxide # layer 121: Conductor material layer 122, 130: conductor layer 124: source region '125: dielectric layer 126: dielectric pattern '127: contact hole 128: doped region W1, W2: line width 15