201103091 六、發明說明： 【發明所屬之技術領域】 本發明浦:種料體元件及作綠歧善綠，特別是有 關-種金氧半導體電晶_製作方法與改通道效應及汲極 引發能帶降減應的金氧半_電晶體結構。 【先前技術】 隨著半導體製程之線寬的不斷縮小，金氧半電晶體 (MOSFET)之尺寸亦精地朝向微型化發展，㈣目前半導 體製程之線寬已發展至_的情況下，如何提升載子遷移率 以增加MOS f晶體之速紅成為目前半導體技術領域中之 一大課題。 在目則已知的技術中’已有使用應變石夕(strained siiic〇n) 作為基底的MOS電晶體’其利用矽鍺^沿幻的晶格常數與單 晶矽（single crystal Si)不同的特性，使矽鍺磊晶層產生結構上 應反而形成應變石夕。由於梦錯層的晶格常數(lattiCe constant) 比石夕大’這使得矽的帶結構(band structure)發生改變，而造 成载子移動性增加，因此可增加PMOS電晶體的速度。201103091 VI. Description of the invention: [Technical field to which the invention pertains] The invention relates to a seed material component and a green hybrid, in particular to a related metal oxide semiconductor electro-crystal _ fabrication method and channel effect and buckling initiation energy The metal oxide half-electrode structure with the reduction and reduction. [Prior Art] With the shrinking of the line width of the semiconductor process, the size of the metal oxide semi-transistor (MOSFET) is also finely oriented toward miniaturization. (4) How to improve the line width of the current semiconductor process has been developed to _ The carrier mobility to increase the speed of the MOS f crystal has become one of the major issues in the field of semiconductor technology. In the technique known from the prior art, 'the MOS transistor which has strained siiic〇n as a substrate' has a lattice constant different from that of single crystal Si. The characteristics of the bismuth layer of the bismuth layer should be structurally formed instead of strained. Since the lattice constant of the dream layer (lattiCe constant) is larger than that of the stone, the band structure of the germanium is changed, and the mobility of the carrier is increased, so that the speed of the PMOS transistor can be increased.
另外，亦有使用選擇性磊晶成長方法，於閘極形成之後，在源極 /¾極預定區域中嵌入摻雜鍺，形成受壓擠的應變矽膜，以增進 PM0S的電洞遷移率。一般而言，在進行選擇性磊晶成長製程 時’填入源極/汲極預定區域之鍺化矽雖能增進應變矽PMOS 5 201103091 的電洞遷移率，但亦會同時折損NM〇s的電子遷移率，進而 影響電晶體的效能。因此，在形成PM〇s和NM〇s的整合 製程中，於進行磊晶成長鍺化矽時，通常會使用氮化矽作為 遮罩，將NMOS的區域完全覆蓋住，並於鍺化矽磊晶完成之 後，再使用熱磷將覆蓋NMOS的氮化石夕移除。.但是在移除氮 化矽時，熱磷酸亦會侵蝕位於_08源極/汲極預定區域的矽基 底表面’使其相對於NMOS的閘極介電層和基底之間的介面向下 移，因此，後續在植入NMOS的源極/汲極摻質時，會使得p/n接面 較預先設^:的紐絲，最後會導致輯道效應和祕服的能帶 降低(Drain Induced Barrier Lowering，DIBL)效應。 因此，仍需要一種金氧半電晶體元件及其製造方法，以 改善上述問題。 【發明内容】 有鑑於此，本發明之主要目的在於提供一種製作金氧半電晶體 的方法，以改善習知在移除NM〇s上的遮罩時，所造成的介面下 移問題。 根據本發明之申請專利範圍，係揭露一種金氧半電晶體之製程， 該等金氧半電晶體係形成於一基底包含一第一型井和一第二型井 上，該製程包含有下列步驟：首先，形成—第一間極於該第一型井 以及-第二閘極於該第二型井，接著，形成—第三側壁子於該第一 間極上’然後’分別形成一蟲晶層於該第—閘極之兩侧的該基底中， 之後，形成-第四側壁子於該第二閘極上，接著，分卿成一石夕覆 201103091 蓋層^亥遙晶層之表面和該第四側壁子之兩側的該基底表面，然 後，分^形成-第-源極/沒極摻雜區於該第一問極之兩侧的該基底 中以及刀別形成-第二源極/没極摻雜區於該第二閘極之兩側的該 基底中。根據本發明之申請專利侧，其中縣晶層為雜遙晶層。 根據本發明之中請專概圍，在形成縣晶料係彻—遮罩層覆 蓋。玄第5^井以及該第一閘極，於形成該蠢晶層之後，移除至少部 分之該遮罩層。 • 根據本發明之申請專利範圍’另揭露-種改善短通道效應及沒極 引發的能帶降低效應的金氧半電晶體結構，該金氧半電晶體結構包 含下列結構：-基底包含—P型井、一閘極設於該卩型井之該基底 上側壁子5又於該閘極之兩側、一 N型源極/沒極摻雜區設於該閘 極兩側之該基底内、一矽覆蓋層覆蓋於該N型源極/汲極摻雜區上以 及一金屬石夕化物設於該石夕覆蓋層上。 本發明的特徵在於在完成上述蟲晶層之後，同時分別在pM〇s Φ 和见108的閘極二側’也就是PMOS和NMOS的源極/汲極摻雜區 上形成一矽覆蓋層，此矽覆蓋層對於_〇8來說，可以填補在移除 月ij述遮罩層時，對NMOS閘極附近的基底表面造成的表面下移部 分，維持p/n接面在預先設定的深度，避免_〇8發生短通道效應 和汲極引發的能帶降低效應。除此之外，在完成上述磊晶層後，該 遮罩層亦可以形成NMOS閘極的侧壁子。 【實施方式】 第1圖至第9圖為本發明製作金氧半電晶體之製程示意圖。如第 201103091 1圖所不’首先提供—基底1G包含—第—型井12和—第二型井 其^第—斷12可叫_或卩型，而第二邮4則可以相對為 PMN型’於下列實施例中，係以第—型井以㈣井而第= =井Η為P型井為例說明，也狀說於下列實施射，於第一: ^ 12上最終將會形成一 pM〇s，而於第二型井μ最終將會 :。此外，第-型井12和第二型井14之間與所在之外圍之 土底10内另環繞一淺溝隔離（STI)15。 接著，分卿成-第-閘極16於第—型井12之上以及—第 ，18於第一型井14之上’其中第—間極％包含有一第一介電層 %設於基底H)上、—第―導電層22設於第—介電㈣上、—^ =蓋層24位於第—導電層22上以及—第—側壁子26設於第— W 22 _ —賤層Μ樣。而第二間極 18入匕3 -第二介電層28設於基底1〇上、一第二導電層3〇設於第 一層28上、-第二頂蓋層32以及一第二側壁子34設於第二 :::28、第二導電層30和第二頂蓋層％之側壁。舉例而言， 電屬2G和第—介電層28可為—利用熱氧化或沈積等製程所 ^成之氧化石夕層所構成，或者是介電常數大於4的高介電常數材料 導電層22及第二導電層3G可為多晶料導電材料，或可 為具有特定功函數的金屬材料，而第_頂蓋層Μ和第二頂蓋層 32則可由氮化㈣所組成’並且第—職層％和第二頂蓋層s 32可以選擇性的形成。第—側壁子糾第二側壁子料則是為了 後續形成源極娜延伸區域(sou_rainextensi〇n)等的低捧雜區， 之後，可留存於結構中，或是移除。接著，以第一閘極16為遮罩， 201103091 刀別形成一第一低摻雜區36於第一閘極16之兩側的基底1〇争。 之後’如第2圖所示、再形成一第三侧壁子38於第一閉極π 之側壁，在形成第三側壁子38的同時，亦形成一遮罩層4〇覆蓋第 -型井14以及第二閘極18。其中，形成第三側壁子％和遮軍層如 的方式可以為，例如’形成_氮化销全面覆蓋第—型井12、第二 型井Μ、第一閘極16和第二閘極18，之後形成一圖案化光阻(圖未 不）覆蓋第二型井14和第二閘極18，再利用餘刻方式去除未受光 籲阻覆蓋之氮化石夕層’形成第三側壁子38，最後再移除光阻，而原本 位於光阻下的氮化矽層則成為遮罩層4〇。 接著分別形成一蟲晶層42於第一閘極16之兩側的基底1〇中。 根據本發明之較佳實施例，PM0S之蟲晶層42可只包含錯蟲晶 層44 ’如第2圖所示；而根據本發明之另一較佳實施例，如第3圖 所不’磊晶層42亦可以包含一矽鍺磊晶層44和一單晶矽層46位於 矽錯蟲晶層44上。-般而言，石夕錯遙晶層44的形成方式可以利用 •嵌入式矽鍺(embedded Silicon Germanium, e-SiGe)製程，例如，先藉 由遮罩層40、第-閘極16與第三侧壁子38的保護，以於第一間極 16兩側的基底10中侧出兩凹槽(圖未示），再於反應室中通入矽 源材料氣體和鍺源材料氣體而於此兩凹槽内選擇性形成矽鍺 磊晶層44，或者是在矽鍺磊晶層44成長到一預定厚度後， 將鍺源材料氣體關閉，便可於矽鍺磊晶層44上再形成單晶矽 層46。亦即於本發明中，單晶矽層46可視製程而調整其厚度， 亦可喊擇不製作單祕層46 ’甚至判^晶層44巾的錯漢度也 . 可依調整而呈一梯度變化。 201103091 在完成嵌入式矽鍺(e-SiGe)製程之後，如第4圖所示，以一圖案 化光阻(圖未示)覆蓋第一型井12和第一閘極16以及第三侧壁子 38。接著’糊部分遮罩層4〇，以形成一第四側壁子48於第二閘 極18 «則壁’接著將光阻移除。根據本發明之另-較佳實施例，第 :側壁子48的製作方式亦可以為，將第三侧壁子38和遮罩層40 凡全移除’接著’如第5圖所示，接著形成一材料層5〇順應地覆蓋 第-型井14、第—型井12、第—閘極16和第二閘極18之後，如第 6圖所不’移除部分之材料層5〇，以分別在第一閑極^和第二閑極 18上形'-第七側壁子52和前述之第四麵子48。上述側壁子的 製程僅疋本發明之較佳實施例，凡依本發明巾請補範圍所做之 句等隻化與彳；飾’ 0應屬本發明之涵蓋範圍。後續製程將接續第4 圖進行說明。 曰如第7圖所示’分鄉成—魏蓋層54於第-_ 16兩側之遙 b曰層42表面和第二閘極18兩側的基底1()表面，也可以說魏蓋層 541成在第-型井12和第二型井14中預定形成雜/汲極推雜區的 ^置。梦覆蓋層Μ可以為單祕，其形成方式舉_言，可以利用 則述形成蠢晶層42之方式製作，甚至可以使用和前述形成蟲晶層 2相同的反應室，再度將發源材料氣體開啓而形成。根據本發 明之一較佳實施例，石夕覆蓋層54之厚度為50至15〇埃。 如第8圖所不利用一圖案化光阻(圖未示)覆蓋第一型井並 以此光阻、第四側壁子48和第二閘極18為遮罩進行摻雜，分卿 成:第二低摻雜區56於第二閘極18之兩側的基底川中。然後，分 卿成-第五麵子58和—第六_子60於第三側壁㈣和第四 201103091 側壁子48之側壁，並將第一頂蓋層24和第二頂蓋層32移除， 曝露出第一導電層22和第二導電層30。接著，形成一 P型之第一 源極/沒極摻雜區62於第一閘極16之兩側的基底10中以及形成一 N型之第二源極/汲極摻雜區64於第二閘極18之兩側的基底1〇中， 此時，本發明之PMOS66和NMOS68業已完成。當然，形成第一 源極/汲極摻雜區62和第二源極/汲極掺雜區64的先後順序可依產品 製程變換。另外，第一源極/淡極摻雜區62形成的位置係和磊晶層 • 42部分重疊。 如第9圖所示，進行一金屬矽化製程，使曝露之第一導電層22 和第二導電層30、石夕覆蓋層54至少一部分變成金屬石夕化層55。之 後可選擇性再整合其他如接觸蝕刻停止層(CESL)、雙應力層(〇11&1 Stress Liner，DSL)等之應變記憶技術(Stress Mem〇rizati〇n technQbgy， SMT) ’以更提升MOS的性能。後續可以進行内部電連結線路的製 作，例如形成層間介電層覆蓋PM0S 66和NM0S 68，並且在層間 • 介電層中製作接觸插塞以分別電連接第一閘極16、第二閘極18、第 一源極/汲極摻雜區62和第二源極/汲極摻雜區64等，即不多贅言。 此外，本發明也可應用於嵌入式SiC製程，以改善顧〇§電流驅動。 例如，於進行第2圖或第3圖的步驟時，將石夕錯蟲晶層以碳化砂 蟲晶層取代。 由於上述實施例在形成磊晶層42時，會在第二型井Μ上形成一 遮罩層4〇，且在完成蠢晶層42後，至少一部分的遮罩層4〇會被移 除，故在移除時，會_到第二閘極18兩側的基底iq表面此將 •無可避免的使第二閘極18兩侧的基底1〇表面，相對於第二介電層 201103091 28和基底iG的介面下降。因此本發明之—特徵即在於部分移除遮 罩層40之後，同時在PM0S 66和顧〇s 68的閉極兩側也就是 PMOS 66和NMOS 68的源極/汲極摻雜區上分別形成一石夕覆蓋層 54。此石夕覆蓋層54對於nM〇S 68來說，可以填補前述顧〇^極 附近的基底表面下移部分，維持p/n接面在一預定深度，避免丽〇8 發生短通道效胁;雄f丨發的能舞低錢。雜pMQs的來說， 矽覆蓋層54主要係用來形成金屬石夕化物％。除此之外在完成上 述蟲晶I 42後，原本用於保護第二型井14和第二閑極18的遮罩層 40，’亦可以形成NMOS 68之閘極的側壁子。 除此之外’本發明亦提供了 -種改善短通道效應及汲極引發的能 帶降低效應的N型金氧半電晶體結構，第1〇圖情示了根據本發 明之較佳實施例之N型金氧半電晶體之侧視示意圖。如第1〇圖所 示，本發明之NMOS 168之結構，包含：一基底丨⑻包含一 p型井 114、一閘極118設於P型井114之基底1〇上、一侧壁子15〇設於 閘極118上、一淺掺雜區156設於側壁子150下方之基底1〇〇内、 一 N型源極/及極換雜區164設於閘極15〇兩側之基底1⑻内、一石夕 覆蓋層154覆蓋於N型源極/汲極摻雜區164上以及一金屬矽化物 155設於石夕覆蓋層154上。另外，一 p型井114所在之外圍之基 底100内另環繞一淺溝隔離(STI)115。其中閘極118包含一介 電層128設於基底100上和一導電層130設於介電層128上，此外， 侧壁子150為一複合式側壁子包含一側壁子134、側壁子148、側壁 子160 ’設於閘極118之側壁。另外，矽覆蓋層154之厚度為5〇至 150埃並且由單晶矽構成。再者，金屬石夕化物155之外表面較介電 12 201103091 層128和基底100之間的介面提升。 綜上所述，本發明之—特徵在於_08168的源極/汲極摻雜區 I64處有一矽覆蓋層154，其可以避免NMOS發生短通道效應和汲 極引發的能帶降低效應。 以上所述僅為本發明之較佳實補，凡依本發明申請專利範圍所 做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第9圖為本發明製作金氧半電晶體之製程示意圖。 第10圖中繪示了根據本發日月之較佳實施例之金氧半^晶體之側視 【主要元件符號說明】 10 ' 1〇〇 基底 14 第二型井 16 第一閘極 20 第一介電層 24 第一頂蓋層 28 第二介電層 32 第二頂蓋層 36 第一低摻雜區 40 遮罩層 12 第一型井 15 、 115 淺溝隔離 18 第二閘極 22 第一導電層 26 第一側壁子 30 第二導電層 34 第二側壁子 38 第三侧壁子 42 蟲晶層 201103091 44 珍錯蟲晶層 46 48 第四側壁子 50 52 第七侧壁子 54 55 金屬矽化層 56 58 第五側壁子 60 62 第一源極/汲極摻雜 64 區 66 PMOS 68、168 114 P型井 118 156 淺摻雜區 128 134、 侧壁子 154 148、 150 > 160 金屬矽化物 164 155 單晶矽層 材料層 碎覆蓋層 第二低摻雜區 第六侧壁子 第二源極/汲極摻雜 區In addition, a selective epitaxial growth method is also used. After the gate is formed, a doped germanium is embedded in a predetermined region of the source/3⁄4 pole to form a strained tantalum film to improve the hole mobility of the PM0S. In general, during the selective epitaxial growth process, the enthalpy of filling the source/drain region can increase the hole mobility of the strain 矽 PMOS 5 201103091, but it will also damage the NM〇s. Electron mobility, which in turn affects the performance of the transistor. Therefore, in the integrated process of forming PM〇s and NM〇s, when epitaxial growth and deuteration is performed, tantalum nitride is usually used as a mask to completely cover the NMOS region, and After the crystallization is completed, the Zn nitride covering the NMOS is removed using hot phosphor. However, when removing tantalum nitride, hot phosphoric acid also erodes the surface of the germanium substrate in the _08 source/drain region to be shifted downward relative to the dielectric between the gate dielectric layer and the substrate of the NMOS. Therefore, in the subsequent implantation of the source/drain dopant of the NMOS, the p/n junction is made to be larger than the pre-set:, and finally the band effect and the energy band of the secret service are reduced (Drain Induced) Barrier Lowering, DIBL) effect. Accordingly, there is still a need for a MOS semi-transistor element and a method of fabricating the same to improve the above problems. SUMMARY OF THE INVENTION In view of the above, it is a primary object of the present invention to provide a method of fabricating a metal oxide semi-transistor to improve the interface down-conversion caused by the conventional mask removal on NM〇s. According to the patent application scope of the present invention, a process of a metal oxide semi-electrode crystal formed on a substrate comprising a first type well and a second type well is disclosed, the process comprising the following steps First, forming - a first pole in the first well and a second gate in the second well, and then forming - a third sidewall on the first pole - and then forming a crystal Layered on the substrate on both sides of the first gate, and then forming a fourth sidewall on the second gate, and then, splitting into a surface of the 201103091 cover layer and the remote layer The surface of the substrate on both sides of the fourth sidewall, and then forming a -first source/dot-doped region in the substrate on both sides of the first gate and forming a second source / immersed in the substrate on both sides of the second gate. According to the patent application side of the invention, the county layer is a heteroporous layer. According to the present invention, it is necessary to cover the entire area of the crystal film to form a cover layer. The mysterious 5th well and the first gate remove at least a portion of the mask layer after forming the stray layer. • The scope of the patent application according to the invention 'further discloses a metal oxide semi-transistor structure which improves the short channel effect and the infinitely induced energy band reduction effect, the metal oxide semi-transistor structure comprising the following structure: - substrate comprising - P a well and a gate are disposed on the substrate upper side wall 5 of the 井-type well and on both sides of the gate, and an N-type source/dot-doped region is disposed in the substrate on both sides of the gate A cover layer covers the N-type source/drain-doped region and a metal-lithium compound is disposed on the Shishi cover layer. The invention is characterized in that after completing the above-mentioned worm layer, a ruthenium layer is formed on the source/drain-doped regions of the PMOS and NMOS, respectively, on the two sides of the gates of pM〇s Φ and 108, respectively. The 矽 矽 layer can fill the surface down portion of the substrate surface near the NMOS gate when removing the mask layer, and maintain the p/n junction at a predetermined depth. To avoid the short channel effect of _〇8 and the energy band reduction effect caused by the bungee. In addition, after the epitaxial layer is completed, the mask layer may also form sidewalls of the NMOS gate. [Embodiment] Figs. 1 to 9 are schematic views showing a process for fabricating a gold oxide semi-electrode according to the present invention. As shown in the figure 201103091 1 does not first provide - the base 1G contains - the first type well 12 and the second type well - the first - break 12 can be called _ or 卩 type, while the second post 4 can be relatively PMN type 'In the following examples, the first type of well is the (4) well and the == well is the P-type well as an example. It is also described in the following implementation. On the first: ^ 12 will eventually form a pM〇s, while the second type μ will eventually:. In addition, the first well 12 and the second well 14 are surrounded by a shallow trench isolation (STI) 15 between the soil well 10 at the periphery thereof. Next, the division-first-gate 16 is above the first well 12 and - the first 18 is above the first well 14 'where the first-most pole % comprises a first dielectric layer % disposed on the substrate H) upper, first conductive layer 22 is disposed on the first dielectric (four), -^ = cap layer 24 is located on the first conductive layer 22, and - the first sidewall member 26 is disposed on the first - W 22 _ - layer kind. The second electrode 18 is disposed on the substrate 1 , a second conductive layer 3 is disposed on the first layer 28 , and the second cap layer 32 and the second sidewall are disposed on the first layer 28 . The sub-34 is disposed on the sidewalls of the second:::28, the second conductive layer 30, and the second cap layer %. For example, the electrothermal 2G and the first dielectric layer 28 may be formed by a layer of oxidized stone formed by a process such as thermal oxidation or deposition, or a conductive layer of a high dielectric constant material having a dielectric constant greater than 4. 22 and the second conductive layer 3G may be a polycrystalline conductive material, or may be a metal material having a specific work function, and the first cap layer and the second cap layer 32 may be composed of nitride (four) 'and The job layer % and the second cap layer s 32 may be selectively formed. The first side wall corrects the second side wall sub-material for the subsequent formation of a low-noise area of the source extension region (sou_rainextensi〇n), etc., which may then remain in the structure or be removed. Then, with the first gate 16 as a mask, the 201103091 knife forms a first low doped region 36 on the substrate 1 on both sides of the first gate 16. Then, as shown in FIG. 2, a third sidewall 38 is formed on the sidewall of the first closed pole π. At the same time as the third sidewall 38 is formed, a mask layer 4 is formed to cover the first well. 14 and a second gate 18. Wherein, the third sidewall % and the barrier layer may be formed, for example, a 'formation_nitriding pin comprehensively covers the first well 12, the second well, the first gate 16 and the second gate 18 Forming a patterned photoresist (not shown) to cover the second well 14 and the second gate 18, and then removing the uncoated nitride-coated nitride layer to form the third sidewall 38. Finally, the photoresist is removed, and the tantalum nitride layer originally under the photoresist becomes the mask layer. A worm layer 42 is then formed in the substrate 1 两侧 on both sides of the first gate 16 respectively. According to a preferred embodiment of the present invention, the worm layer 42 of the PMOS may comprise only the worm layer 44' as shown in FIG. 2; and according to another preferred embodiment of the present invention, as shown in FIG. The epitaxial layer 42 may also include a germanium epitaxial layer 44 and a single crystal germanium layer 46 on the germanium fault layer 44. In general, the formation of the Shixia wrong crystal layer 44 can be performed by using an embedded silicon Germanium (e-SiGe) process, for example, by using the mask layer 40, the first gate 16 and the first The three side walls 38 are protected so that two grooves (not shown) are formed in the substrate 10 on both sides of the first interpole 16 , and then the source material and the source material gas are introduced into the reaction chamber. The germanium epitaxial layer 44 is selectively formed in the two recesses, or after the germanium epitaxial layer 44 is grown to a predetermined thickness, the germanium source material gas is turned off, and the tantalum epitaxial layer 44 is formed again. Single crystal germanium layer 46. That is, in the present invention, the single crystal germanium layer 46 can be adjusted in thickness according to the process, and it is also possible to choose not to make the single secret layer 46' or even to judge the wrongness of the crystal layer 44. It can be adjusted according to the gradient. Variety. 201103091 After completing the embedded germanium (e-SiGe) process, as shown in FIG. 4, the first well 12 and the first gate 16 and the third sidewall are covered by a patterned photoresist (not shown). Sub 38. Next, the paste portion of the mask layer 4 is formed to form a fourth sidewall portion 48 on the second gate 18 «the wall" and then the photoresist is removed. According to another preferred embodiment of the present invention, the first side wall 48 can be formed by removing the third side wall sub-38 and the mask layer 40 as shown in FIG. 5, and then After forming a material layer 5 〇 compliantly covering the first well 14 , the first well 12 , the first gate 16 and the second gate 18 , as shown in FIG. 6 , the material layer 5 部分 is not removed. The seventh side wall 52 and the fourth surface 48 are formed on the first idler and the second idler 18, respectively. The process of the above-mentioned side wall is only a preferred embodiment of the present invention, and the sentences and the like according to the scope of the invention are only included in the scope of the present invention. Subsequent processes will be described in Figure 4. For example, as shown in Fig. 7, the surface of the b-layer 42 on both sides of the first-- 16 and the surface of the base 1 on the two sides of the second gate 18 can also be said to be Wei Gai. Layer 541 is formed in the first well 12 and the second well 14 to form a miscellaneous/deuterium doping region. The dream cover layer can be a single secret, and the manner of formation thereof can be made by using the method of forming the stupid layer 42. Even the same reaction chamber as the aforementioned crystal layer 2 can be used, and the source material gas can be turned on again. And formed. In accordance with a preferred embodiment of the present invention, the thickness of the stone cover layer 54 is 50 to 15 angstroms. As shown in FIG. 8, a patterned photoresist (not shown) is used to cover the first well and the photoresist, the fourth sidewall 48 and the second gate 18 are doped as a mask. The second low doped region 56 is in the base of both sides of the second gate 18. Then, the first cap layer 24 and the second cap layer 32 are removed, and the first cap layer 24 and the second cap layer 32 are removed, and the second cap layer 58 and the sixth cap 60 are on the side walls of the third side wall (four) and the fourth 201103091 side wall 48. The first conductive layer 22 and the second conductive layer 30 are exposed. Next, a P-type first source/depolarization doped region 62 is formed in the substrate 10 on both sides of the first gate 16 and an N-type second source/drain doping region 64 is formed. In the substrate 1 on both sides of the two gates 18, at this time, the PMOS 66 and NMOS 68 of the present invention have been completed. Of course, the order in which the first source/drain doping region 62 and the second source/drain doping region 64 are formed may be changed according to the product process. In addition, the position formed by the first source/light-polar doping region 62 and the epitaxial layer 42 partially overlap. As shown in FIG. 9, a metal deuteration process is performed to cause at least a portion of the exposed first conductive layer 22, the second conductive layer 30, and the lithographic cover layer 54 to become the metal slab layer 55. Afterwards, other strain memory technologies such as contact etch stop layer (CESL) and double stress layer (Stress Mem〇rizati〇n technQbgy, SMT) can be selectively integrated to enhance MOS. Performance. Subsequent fabrication of the internal electrical connection lines may be performed, for example, forming an interlayer dielectric layer covering the PMOS 66 and the NMOS 68, and forming contact plugs in the interlayer/dielectric layer to electrically connect the first gate 16 and the second gate 18, respectively. The first source/drain doping region 62 and the second source/drain doping region 64 are not so much. In addition, the present invention can also be applied to an embedded SiC process to improve the current drive. For example, when the steps of Fig. 2 or Fig. 3 are carried out, the crystal layer of the stone worm is replaced by a layer of carbonized sand worm. Since the above embodiment forms a mask layer 4 on the second type well after the epitaxial layer 42 is formed, at least a part of the mask layer 4 is removed after the stray layer 42 is completed. Therefore, when removed, the surface of the substrate iq on both sides of the second gate 18 will inevitably cause the surface of the substrate 1 on both sides of the second gate 18 to be opposite to the second dielectric layer 201103091 28 The interface with the substrate iG drops. Therefore, the present invention is characterized in that after the mask layer 40 is partially removed, the source/drain doping regions of the PMOS 66 and the NMOS 68 are formed on both sides of the closed ends of the PM0S 66 and the Gu s 68, respectively. A stone cover layer 54. For the nM〇S 68, the diarrhea layer 54 can fill the lower surface of the substrate surface near the pole, and maintain the p/n junction at a predetermined depth to avoid the short channel effect of the 〇8; The male f’s can dance low. For the case of the hetero-pMQs, the ruthenium cover layer 54 is mainly used to form the metal lithium %. In addition to this, after the above-described insect crystal I 42 is completed, the mask layer 40, which was originally used to protect the second well 14 and the second idler 18, may also form the sidewall of the gate of the NMOS 68. In addition to the above, the present invention also provides an N-type oxy-oxygen semi-transistor structure for improving the short-channel effect and the drain-induced energy band-reducing effect, and the first preferred embodiment of the present invention is shown in accordance with the present invention. A side view of an N-type gold oxide semi-electrode. As shown in FIG. 1 , the structure of the NMOS 168 of the present invention comprises: a substrate (8) comprising a p-well 114, a gate 118 disposed on the substrate 1 of the P-well 114, and a sidewall 15 〇 is disposed on the gate 118, a shallow doped region 156 is disposed in the substrate 1 下方 below the sidewall sub-150, and an N-type source/pole-changing region 164 is disposed on the substrate 1 (8) on both sides of the gate 15〇 An inner, a lithographic overlay 154 overlies the N-type source/drain doping region 164 and a metal telluride 155 is disposed over the lithographic overlay 154. In addition, a shallow trench isolation (STI) 115 surrounds the substrate 100 on the periphery of a p-well 114. The gate 118 includes a dielectric layer 128 disposed on the substrate 100 and a conductive layer 130 disposed on the dielectric layer 128. Further, the sidewall spacer 150 includes a sidewall 134 and a sidewall spacer 148. The sidewalls 160' are disposed on the sidewalls of the gate 118. Further, the ruthenium cover layer 154 has a thickness of 5 Å to 150 Å and is composed of a single crystal yttrium. Furthermore, the outer surface of the metal lithium 155 is dielectrically 12 201103091 The interface between the layer 128 and the substrate 100 is elevated. In summary, the present invention is characterized in that the source/drain doping region I64 of _08168 has a germanium cap layer 154 which can avoid the short channel effect of the NMOS and the band-reduction effect induced by the drain. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 9 are schematic views showing the process of fabricating a gold oxide semi-electrode according to the present invention. FIG. 10 is a side view of a gold oxide half crystal according to a preferred embodiment of the present invention. [Main component symbol description] 10 '1〇〇 substrate 14 second well 16 first gate 20 A dielectric layer 24 first cap layer 28 second dielectric layer 32 second cap layer 36 first low doped region 40 mask layer 12 first well 15 , 115 shallow trench isolation 18 second gate 22 First conductive layer 26 first side wall 30 second conductive layer 34 second side wall 38 third side wall 42 worm layer 201103091 44 worm layer 46 48 fourth side wall 50 52 seventh side wall 54 55 metal deuteration layer 56 58 fifth side wall 60 62 first source/drain doping 64 region 66 PMOS 68, 168 114 P-well 118 156 shallow doped region 128 134, sidewall sub-154 148, 150 > 160 metal telluride 164 155 single crystal germanium layer material layer cover second low doped region sixth side wall second source/drain doped region
NMOS 閘極 介電層 矽覆蓋層 N型源極/汲極摻雜NMOS gate dielectric layer germanium overlay N-type source/drain doping