TW201103006A - Display and shift register device - Google Patents

Abstract

A display and a shift register device thereof are provided. The display includes a display panel and a first and a second shift register devices (SRDs). The display panel includes a plurality of pixels arranged in an array, and both of the first and the second SRDs are directly disposed on the glass substrate of the display panel. Only one of the first and the second SRDs is normally in operation at one time. When the first SRD is normally in operation, the first SRD sequentially outputs a scan signal to one-by-one turn on all of the pixel rows from the 1st pixel row to the last pixel row. In addition, when the second SRD is normally in operation, the second SRD sequentially outputs the scan signal to one-by-one turn on all of the pixel rows from the last pixel row to the 1st pixel row.

Description

201103006 473i2l2twfd〇c/n VI. Description of the Invention: [Technical Field] The present invention relates to a flat display technology, and more particularly to a liquid crystal display and a shift register thereof. [Prior Art] In recent years, with the rapid development of semiconductor technology, portable electronic products and flat display products have also emerged. Among the many types of flat panel displays, liquid crystal displays (LCDs) have become the mainstream of display products based on their low voltage operation, no radiation scattering, light weight and small size. Because of this, all of the manufacturers' development technologies for liquid crystal displays are moving toward more miniaturization and lower production costs. In order to reduce the manufacturing cost of the liquid crystal display, some manufacturers have developed the original solar panel display panel using the amorphous stone eve (am〇rph〇us siiic〇n,). A shift register inside the scan driver IC used on the scanning side of the liquid crystal display panel is directly placed on a glass substrate of the liquid crystal display panel. Therefore, the scanning drive 1C originally disposed on the scanning side of the liquid crystal display panel can be omitted, thereby connecting the purpose of reducing the manufacturing cost of the liquid crystal display. However, the multi-stage shifting temporary state directly disposed on the glass substrate of the liquid crystal display panel can only be outputted from top to bottom by a scan signal to be turned on by the first column of the liquid crystal display panel to the last column of pixels. And can not be down to the output of J47 3I2l2twf.doc/n 201103006 'a know the 乱田乱乱" 5 tiger to the end of the liquid crystal display panel - the key to the first column. In other words, the current multi-stage shift register that is directly disposed on the glass substrate of the liquid crystal display panel has only a forward scan function' without a reverse scan function. SUMMARY OF THE INVENTION In view of this, the present invention provides a display including a display panel

And first and second shift register devices. The display panel has a plurality of pixels arranged in a matrix, and both the first and second shift register devices are directly disposed on the glass substrate of the display panel. Wherein, the first and second shift register devices operate normally at the same time - and when the first shift register device is in normal operation, the sequence outputs a scan signal to be turned on one by one from the first column. To the last-column, and when the second shift register is operating normally: The sequence outputs the scan signal to open from the last column to the first column of pixels. The structure provides - the county-age temporary county, its package-level circuit frame, the shells are the same and are connected to each other in series to temporarily cry. The 移位-level shift register includes first to fifth transistors, "; and ^ early 兀, ! is a positive integer. The first - transistor (four) pole receives the - start signal. The second transistor __ 彳 ^ ^一^ ' No. ^, and the source of the second transistor is connected to the source and source of the second electric (4) by the ^ wheel pole off. ^ " »υ47 31212twf.doc/n 201103006 The unit consumes the first fish and the second crystal eccentricity, and the first fish _time disjointed U is used to respectively receive the chorus music, the music and the pulse signal, or simultaneously receive the said, and close the ^ No., and in the i-th stage shift register, the scan nickname is not taken out, and the source of the first transistor is coupled to the gate of a reference three-band 曰- for receiving the fourth level The wheel of the shift register = 曰曰曰 = is connected to the source of the second transistor - the body is connected to the reference voltage. The source of the C body is coupled to the gate of the fourth transistor and the gate of the second transistor of the third transistor, and the pole of the fourth transistor is reduced to the voltage. The fifth transistor is configured to receive a two-pole turn-on signal or the gate turn-off signal, and a fifth power: two voltages. * "_Source_to the reference" The present invention further provides a shift temporary storage device which is substantially identical and is connected in series with each other; = more; = the next day gk also, % points, Μ汉卜The gate and the drain of the 狃 are coupled to the first transistor of the second transistor of the second transistor; the source: the drain of the S body is used to receive the first clock signal and the second brother: The source of the crystal is used to output the scanning shout. Lei if ' and the second between the transistor between the pole and the source. ~ Connected to the dipole off the W device === ^ level shift register Including the first to the eighth transistor, "; and the next f early. When the first Thunder crystal ΑΛ k A. and the pull-down 31212 twf.doc/n 201103006, the source of the second transistor is coupled to the inter-electrode of Yuan Di for receiving the (i+1)-stage shift register ^ The source of the crystal, and the third transistor is connected to the cup. (4) The gate of the transistor is reduced by = body ==_ is connected to the gate of the second transistor, and the source of the fourth private day is coupled to the reference voltage. The gate is substantially pure: the gate and the drain are purely received to receive the gate 1 'tiger' or receive one of the pole signal and the gate off signal during every N sides of the display. The gate of the sixth transistor is the source of the electric shock crystal, the electrode of the sixth transistor is depleted of the second electrode 'the source of the sixth transistor is _ to the source of the seventh transistor of the reference electrode 2 The poles are consuming together to receive the interpole or receive the signal and the interpole off signal during every N sides of the display. The gate of the eighth transistor, the source of the seven transistors, the drain of the eighth transistor is coupled to the gate of the second transistor, and the source of the first transistor touches the reference voltage. Is a positive integer. Soil - It should be understood that the above-mentioned general description and the following specific embodiments are merely exemplary and reversible, and are purely within the scope of the invention. [Embodiment] Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the same reference number of elements/components/symbols in the drawings and the embodiments are used to represent the same or a class of ^47 312I2twf.doc/n 201103006. FIG. 1 is a system block diagram of a liquid crystal display 1A according to an exemplary embodiment of the present invention. Referring to FIG. 1, the liquid crystal display 1 includes a display panel 10 source driver 103, a timing control unit 1〇5, and a backlight module 1〇7 for providing a backlight required for the display panel 101. The display area AA of the display panel 101 has a plurality of pixels arranged in a matrix (indicated by, for example, 1024*768, and ^^ and ^ are positive integers). In addition, the left and right sides of the glass substrate (not shown) of the display panel 101 are directly disposed with the shift register devices SRD1 and SRD2, respectively, and the operations of the two shift register devices SRD1 and SRD2 are controlled by Timing control unit 105. In the present exemplary embodiment, only one of the shift register devices SRD1 and SRD2 operates normally at the same time, and when the shift register device SRD1 operates normally, the sequence outputs a scan signal SS1 SSSN to the display area AA. The first column of pixels is turned on one by one to the last column, and when the shift register SRD2 is operating normally, the sequence outputs a scan signal to open one by one from the last column in the display area AA to the first column. Prime. In other words, the shift register SRD1 has a forward scan function, and the shift register SRD2 has a reverse scan function. More clearly, FIG. 2A and FIG. 2B are respectively block diagrams showing shift register devices SRD1 and SRD2 according to an exemplary embodiment of the present invention. Referring to FIG. 1 , FIG. 2A and FIG. 2B , the shift register device SRD1 includes a shift register of the N-level circuit architecture which is substantially identical in series and connected in series with each other, 201103006 ^47 3l212twf.doc/n wide SRN, The shift register SRD2 also includes the shift registers SR, ~sw which are identical on the same circuit board and are connected in series with each other, in the present exemplary embodiment, due to the shift register The circuit architecture of SI^~srN fish SRVSR'n is substantially the same, so only the i-th bit register SRi/SR'i will be described here. Sand Figure 3 depicts a circuit diagram of a shift 斩 SRi/SR,i that is not an exemplary embodiment of the present invention. Please merge reference heads 1 to II 3, shift ^ in: SR/SR'i includes transistor T1 ~ TS, capacitor c, and pull-down unit ^, transistor Π closed and no _ connected, use To pick up. Dynamic wave AS. In the present exemplary embodiment, except for the opening 2: i_sR received between the poles of the transistor T1 in the ninth stage = Na, "the closed pole of the transistor T1 in the i side; = the starting signal AS is the upper level Shift temporary memory crying, tracing SSWSSYr 9 memory Ub output sweep, for example, shift register SR2 / SR, 2 in the mail: the received start signal AS is the shift temporary two = knowledge signal SSl /SSV and shift temporary memory crying / 1 output of the gate received by the start signal AS; two R 3 in the transistor T1 out of the scan signal ss === (four) round SR / ς ρ5 λα and this Push to the shift register to cry the transistor T1 in the SRN/SRN SR / ς;?, ± The received start signal AS is (4) S b siwsrvm output broom Please continue to refer to Figure 3, transistor T2 '叫Ν -1 ° source, fa # M4 m 3 pole lightly connected to the T1 electric armor 2 and the pole is used to receive the timing control unit milk U47 31212t\vf.doc/n 201103006 clock signal CK Or the gate close signal Vgl (for example, tearing, not limited to this), and the source of the transistor T2 is used for the input signal ss^/ss. The capacitor C_ is connected to the interpole and source of the transistor Τ2. Drop down single 7C The sources of the 301 crystals T1 and Τ2 are used to respectively receive the phase difference (10) degrees of the clock provided by the timing control unit U) 5 or simultaneously receive the idle pole off signal vGL provided by the timing control unit milk. The pull-down unit 3G1 couples the source of the transistor T2 to the reference voltage VSS when the scan register SSi/SS'i is outputted by the shift register SR, and is not limited to the ground potential. The gate of the transistor Τ3 is used to receive the scan signal SSi+1/SS'i+1 outputted by the shift register SRM/sR, i, and the drain of the transistor T3 is coupled to the source of the transistor T2 The source of the transistor T3 is connected to the reference voltage VSS. The gate of the transistor Τ4 is coupled to the gate of the transistor Τ3, and the drain of the transistor τ4 is coupled to the gate of the transistor Τ2, and the transistor Τ4 The source is the reference voltage VSS. The gate of the transistor Τ5 is used to receive the gate turn-on signal Vgh (for example, 25 ν) or the gate turn-off signal VGL provided by the timing control unit 105, and the drain of the transistor T5. The gate of the transistor T2 is coupled to the source of the transistor T2 to the reference voltage vss. In the present exemplary embodiment, When the gate of the transistor 接收5 receives the gate-off signal vGL provided by the timing control unit 105, the drain of the T2 receives the clock signal CK, and the pull-down unit 3〇1 receives the clock with a phase difference of 180 degrees. Signals CK and XCK. However, when the gate of transistor T5 receives the gate turn-on signal vGH, the drain of transistor T2 receives the gate turn-off signal VGL' and the pull-down unit 301 receives the gate at the same time 201103006 31212twl:.doc /n Turns off the signal vGL. v Soil order control unit 兀1〇5 *For the gate closing signal vGL, the 4-level shifting device SRD1 every time the stage shifting transistor (1) spoon idle pole, indicating the timing control unit ι〇; want to control ^, temporarily The storage device srD1 operates. Therefore, the timing control unit iG5 provides the closing of the transistor T1 that calls the STV to the first stage shift register 11 SR1 and provides the clock signal CK to all the shift registers; the phase difference (10) pull unit 3〇 The nucleus shift register is also the same as this, all shift register in the shift register SRm::j column output sweep signal is called ~^, from the display area aa to the last - Lennon, and the source driver Kai Jin I sub-speaks not to the poor material to be opened by the shift register SRD1: 2: = 匕 来 再 再 再 背光 背光 背光 背光 背光 背光 背光 背光 背光 背光 背光 背光 背光 背光The image will be displayed on the panel 1〇1. The shouting is not affected by the second =::=:, timing control list... I:t^fSRD2-^ register SR,: the closed signal VGL Give all the shifting signals vGL "Yes; 曰2, 极极, and at the same time provide the gate close 30 Buru / Γ register, SR, wide SR, pull-down unit - this, shift register device 2 It will stop working, so 201103006 312l2tvvf.doc/n will not affect the operation of the shift register SRD1. W provides the gate turn-off signal to the ^^ surface memory element 1〇5. A ^ T5 * The gate of the daily body T5 of each stage shift register SITcSITn indicates that the time register SRD2 operates. Therefore, the H system early element 105 wants to control the shift start signal STV to the i-th stage shift temporary storage: unit 曰 = SRVSR, N of the transistor T2 of the second f = jin has the shift register of the clock signal CK and XCK gives all shifts; = destination bit t: pull unit 301. 5 plagiarism i ~ SRN under

Also because of this, the 'shift register device SRD ss^^ssv AA in the last - 昼 昼 逐 — = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = The backlight provided by SRD2 is displayed on the panel 1. 1 will be: 2 = 107 However, due to the desire to shift the temporary storage shift register SRD1 plastic operation day can not be difficult to control the shift register When, "“1 〇5 will SRD1 bit register TM = OFF: the pure temporary storage device SRD1 will stop working, so it will not affect 12 201103006 ^ ^vuu^u_>vJ47 3J212twf.doc/n The operation of the shift register SRD2. The second embodiment of the present invention - the shift of the exemplary embodiment can be clearly seen in Fig. 4. Please refer to Fig. 3 and Fig. 4 together to improve the transistor Τ5; Body Τ 5', ~ Τ 8, will replace the transistor Τ 5, the problem of insufficient sin in the -17 degree.

Crystal display; (10) 4: = turn off the signal V- 'or during the liquid every 100 昼 surface, 、 Ν is a positive integer ' and for example, the pole: crystal gate closure and pole will be coupled In order to connect the pole to open the signal Vgh and the side close ^ face = = = the source of the crystal Jr, the transistor two or two vss. The source of the crystal T8' is coupled to the reference voltage. The gate of the transistor (10) Τ7, while receiving the gate-off signal 4 provided by M2 ^ early Γ 1〇5, , the pole " receives the clock signal CK, and the pull-down unit 301 will be connected to the M-bit difference of 18 (3 degrees of the clock signal CK and XCK. However, when the gate of the transistor Γ: and T7' is on the liquid crystal display Every n paintings of 100: During the period of the gate opening signal VGH and the gate closing signal Vgl, the drain of the transistor T2 will receive the gate closing signal VGL, and the pull-down unit 1〇〇13 201103006 -- -----1) 47 31212twf.doc/n will receive the gate off signal VGL at the same time. Based on the above, when the timing control unit 105 simultaneously supplies the gate turn-off signal VGL to the transistor T5 of each stage of the shift register SRD1, and the gate of T7, the timing control list & 105 wants to control the operation of the shift register SRD1. Therefore, the timing control = element 1〇5 will provide the start signal STV to the gate and drain of the transistor τι of the third stage shift register, and provide the clock signal CK to all the bit registers SR] The drain of the transistor T2 of ~SRn, and simultaneously providing the clock signals CK and xck with a phase difference of 18 给 to all the shift registers SRi~sr pull-down unit 301. 'Also: In this case, all the shift register i~SRn g sequences in the shift register SRDi output the scan signals 珥~SSn to open from the fr column of the display area 1 to the last-lister. The source driver will provide the corresponding display data to the listed temporary storage device ^^. In this way, plus the backlight module 1〇7 provides = the source, the display panel 101 will display the image plane. Since it is desirable to shift the scratchpad s in operation, it is not affected by SRD2. Therefore, the 'timing control unit 105 will operate every two registers! Rm, and between the closed signal 5 i of the liquid crystal display 100, the parent provides a gate turn-on signal Vgh and a gate shift SRD2 for each stage of the shift. The memory number Vgl is given to the center; the gate of f T7, and the gate is turned off, and the gate of the transistor τ2 of the gate mR'N is provided at the same time,] the number VGL is given to all the shift registers 14 201103006 j47 31212twf.d〇c/n Pull-down unit 3G1. In this way, the shift register SRJD2 is made P. The operation is not affected, so that the shift register is not affected. On the other hand, when the timing control unit 1〇s provides SRD2 at the same time

SR wide SR N pen crystal T5, and T7, the gate when 'represents the timing control list = 105 to control the shift register device 2 operation. Because the timing control unit 1051 provides the start signal STV to the interpole and drain of the transistor τι of the i-th stage shift register, and provides the clock signal CK to the power of the 1-bit register SRVSR'N. The crystal T2 is infinitely poled, and at the same time, the clock signals CK and XCK with a phase difference of 180 degrees are provided to all the shifts to temporarily store the pull-down unit 3〇1 of the SR' wide SR'N.曰°°, also because all the shift registers SRVSR'N in the shift register SRD2 will output the scan signals SSVSS, N in sequence to open the first column from the display ^ = one by one to the first The column driver, and the source driver benefit 103 will also provide corresponding display data to the listed elements that are turned on by the shift register SR=2. In this way, plus the backlight provided by the backlight module (10), the display panel 1〇1 will display the image plane. However, since it is desired that the shift register 3 is not affected by the private register SRD1 during operation. Therefore, the timing control unit is combined to control the operation of the shift register SRD2, and alternately provide the gate open signal vgh to each stage of the shift register SRD1 during the period of the liquid (four) display (10) Bit register SRi~SRn transistor 丁5曰, with T7, the gate, and provides gate off signal Vgl to all shifts temporary storage 15 201103006 Vv~〇47 31212twf, doc/n ^ SURn transistor The drain of T2, and at the same time, provides a gate turn-off signal VGL to the pull-down unit 3〇1 of all shift registers SR1 SRSRn. As a result, the shift register device S will stop operating, so that the operation of the shift register SRD2 will not be affected. As described above, the present invention mainly arranges two independent shift register devices directly on the left and right sides of the glass substrate of the display panel, and controls the two shift temporary storage by the timing control unit. The operation of the device is to operate the two shift temporary storage devices in the same time-time. In addition, because one of the two shift register devices can sequentially output a seedling «signal, from the first column of the display panel to the last column of pixels, and then - can be sequenced output - scan The signal is turned on from the last-column of the display panel to the first column of pixels. Therefore, the two shift register devices can perform a forward scan or a reverse scan on the display panel, thereby improving the current situation in which the #-level shifter directly disposed on the substrate of the display panel does not have the function of reverse scan. Although the present invention has been disclosed above in the above-described exemplary embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art may be modified without departing from the spirit and scope of the invention. And the scope of protection of the invention is defined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a liquid crystal display of an exemplary embodiment of the present invention. 16 201103006 31212tvvf.c3oc/n FIG. 2A and FIG. 2B are block diagrams respectively showing the shift register devices SRD1 and SRD2 according to an exemplary embodiment of the present invention. FIG. 3 is a circuit diagram of a shift register SRi/SR'i according to an exemplary embodiment of the present invention. FIG. 4 is a circuit diagram of a shift register SRi/SR'i according to another exemplary embodiment of the present invention. [Main component symbol description] 100 LCD display 101 Display panel 103 Source driver 105 Timing control unit 107 Backlight module 301 Pull-down unit AA Display area SRD1, SRD2: Shift register • T1~T5: Transistor C: Capacitor STV: Start signal AS: Start signal CK, XCK: Clock signal Vgh: Gate turn-on signal VGL: Gate turn-off signal SR wide SRN, SR' wide SR, n: Shift register SSi~SSn, SS 'i~SS'n. Scan signal 17

Claims (1)

201103006u47312l2iwM〇c/n VII. Patent application scope: 1. A display comprising: a first and a display panel on a glass substrate, a display panel: having a plurality of pixels arranged in a matrix; and a first shift temporary The storage device, both of which are directly configured in the 'the first-and the second shift register device at the same time--the normal operation, and when the first-shift (four) is purely normal operation, the column output = scan The signal is turned on one by one from the first column of pixels to the last column, and when the second shift is temporarily stored, the signal is normally operated to start from the last column of pixels to the first column of the book. Such as the scope of patent application! The display device of the present invention, wherein the plurality of stages of the circuit structure are the same on the real f and are turned to each other in the shift register, wherein the i-th stage first shift register includes ·· ^ 1 -f crystal 'it's difficult to connect with it_ to start-receive-start signal; no sigh μ^ second transistor, its gate is connected to the source of the first-transistor, 1 decay to receive a first The clock signal or the closed-close signal, and the source of the basin is used to output the scan signal; the ',' and the second capacitor are connected between the pole and the source between the second transistors; Receiving the first and the first, the first disc receiving the phase difference (10) degrees respectively receives the inter-pole turn-off signal, and at the first stage, the first core: the signal, the source of the second transistor _ 々18 201103006 /Λ.υυ川31.212t.\vi..(j〇c/ii a third transistor whose gate is used to receive the (i+1)th first shift register The output is connected to the source of the second transistor, and the source thereof is coupled to the reference voltage; and a fourth transistor having a gate coupled to the third transistor a pole, the drain of which is coupled to the gate of the second transistor, and the source of which is coupled to the reference voltage, wherein i is a positive integer. 3. The display of claim 2, The first stage shift register further includes: a fifth transistor, wherein the gate is configured to receive a gate turn-on signal or the gate turn-off signal, and the drain is coupled to the gate of the second transistor, The display device is coupled to the reference voltage. The display of claim 3, wherein when the gate of the fifth transistor receives the gate turn-off signal, the second transistor The drain is configured to receive the first clock signal, and the pull-down unit is configured to respectively receive the first and second clock signals with a phase difference of 180 degrees. 5. The display of claim 3 When the gate of the fifth transistor receives the gate turn-on signal, the drain of the second transistor is configured to receive the gate turn-off signal, and the pull-down unit is configured to receive the gate turn-off signal simultaneously 6. The display of claim 2, wherein the i-th level The first shift register further includes: a fifth transistor having a gate coupled to the drain thereof for receiving the gate turn-off signal, or receiving the 19 J47 31212 twf during every N sides of the display .doc/n 201103006 One of the gate turn-on signal and the gate turn-off signal; - a sixth transistor with a pole (4) the source of the fifth transistor and = a gate of the second transistor, and The secret_connected to the reference-seventh transistor's pole is so close to receive the gate off (4), or every N gates of the display are turned on and the gate is turned off. In addition, the eighth transistor is received, the gate of the eighth transistor is coupled to the gate of the second transistor, and the source is connected to the reference voltage, wherein N is a positive integer. 7. In the case of the display of claim 6, the seven-electrode is simultaneously received by the cabinet. The second::: the bottom of the transistor is used to receive the first-clock signal. And do not receive the phase difference (10) degrees of the first and the second 8. The display of the sixth aspect of the patent application, the fifth transistor and the seventh transistor gate field S S:=::r signal And the gate is turned off by the second element for receiving the gate off signal at the same time and the pull-down list is 9. The fourth bit register from the patent application scope item, wherein the second stage shift is temporarily stored. The device includes 20 201103006 (4) 3 〖2] 2 twf.d 〇 c / n its gate is coupled with its drain to receive a transistor - a start signal, a second transistor, the gate is coupled to the first The source of the transistor is used to receive the -first clock signal or the gate signal, and the source is used to output the scan signal; the valley is connected to the gate of the second transistor Between the source and the source; the first and the second transistor are coupled to each other by an eight-down pull-down, and the first phase of the phase difference is 180* The second clock signal or the same ϊ 3 Γ signal, and the second shift register in the i-th stage does not lose Μ, the source of the second transistor is consumed to - the reference memory is crying ^ three The transistor 'closed pole is for receiving the fourth (fourth) second shift temporary coupling: two = coupling = the source of the second transistor and the source 2 gate is lower than the gate of the third transistor, Its voltage is the gate of the heart, and its secret is connected to the reference, i is a positive integer. For example, in the display of the scope of claim 9, the Hidden Private Register further includes: ', the pole is closed to receive the 1 pole turn-on signal or the board 2 = the second transistor Opening the pole, and the source U is as shown in the application of the patent item (4), wherein when the gate of the 21 D47 31212 twf_doc/n 201103006 is received by the gate of the SB body, the second The crystal is configured to receive the first clock signal, and the pull-down unit is configured to receive the first and second clock signals with a phase difference of 180 degrees, respectively. 12. The display of claim 1, wherein a drain of the second transistor receives the gate turn-off signal when the gate of the fifth transistor receives the gate turn-on signal And the pull-down unit is configured to receive the gate off signal at the same time. 13. The display of claim 9, wherein the i-th second shift register further comprises: ', the fifth transistor/the inter-corrosion wave pole are coupled together to receive, the gate The pole is turned off or receives one of the gate opening indicator and the gate off signal during every N sides of the display; and a sixth transistor is connected to the fifth transistor The source, ^; and the lightly connected to the gate of the second transistor, and the source thereof to; voltage; ° > - the seventh transistor 'the gate is connected to the __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ m~ 'th gate turns to the source of the seventh transistor, ^ voltage, connected to the gate of the second transistor' and its source_ is connected to the parameter, where N is a positive integer. If the material of the fifth transistor and the gate of the seventh transistor are simultaneously received by the gate of the seventh material, the gate is closed at the same time. 22 201103006 ^ J v_/u 47 31212twf.doc/n The drain of the second transistor is configured to receive the first clock signal, and the pull-down unit is configured to receive the first and second clock signals with a phase difference of 18 degrees. 15. The display of claim 13, wherein the gate opening signal and the gate are alternately received during a gate of the fifth transistor and the seventh transistor during every N sides of the display When the signal is turned off, the drain of the second transistor is used to receive the gate turn-off signal, and the pull-down unit is configured to receive the gate turn-off signal at the same time. 16. The display of claim 3, further comprising a timing control unit coupling and controlling operation of the first and second shift register devices. The display of claim 1, wherein the display is a liquid crystal display. 18. A shift register device comprising: a shift register register having substantially the same multi-level circuit architecture and being serially connected to each other, wherein the i-th shift register comprises: - a first transistor, The gate is connected to the drain pole thereof to receive an activation signal; a second transistor has a gate connected to the source of the first transistor, and a pole for receiving a first clock a signal or a gate is turned off, and a source is used to output the scan signal; a capacitor is coupled between the gate and the source of the second transistor; and a pull-down unit is coupled to the first The source of the second transistor is configured to receive the first and a second clock signal with a phase difference of 180 degrees or 23 201103006 047 31212 twf.d〇c/n, respectively, to receive the gate off signal, and The first stage of the i-th shift temporarily transmits the source of the second transistor to one; the fourth transistor, the gate of which is used to receive the fourth (fourth) level: The source of the second transistor, "source _ two ==:==_, its voltage; and the source is coupled to the reference-fifth transistor, The gate is used to connect the gate to close the signal, and the second electrode is coupled to the reference voltage, 3 poles, and the source thereof, i is a positive integer. 4^^!_第18韵Pure temporary storage device, which is used for: the other = the difference of the position (10) degrees; the =; =: the displacement of the temporary storage device as described in item 19 of the patent patent in May. When the gate of the transistor receives the closed-cell turn-on signal, the second terminal is used to receive the gate-off signal, and the second is used to receive the gate-off signal. 21. a shift register device, comprising: a multi-level circuit architecture substantially (four) and connected to each other in a register, wherein the i-th shift register comprises: 夕24 2〇11〇3〇06j473__ a first electric a crystal whose gate is coupled to its drain to receive a start signal; a second transistor having a gate coupled to the source of the first transistor and a drain for receiving a first clock a signal or a pole off signal, and a source for outputting the scan signal; a valley, lightly connected between the gate and the source of the second transistor; And coupling the first and the second transistor to receive the first and second clock signals with a phase difference of 180 degrees or receiving the gate off signal simultaneously, and When the first shift register is not output = the scan signal, the source of the second transistor is coupled to a reference ^. A third transistor is used to receive the (i+i) The first stage shifts the output of the 軿子益, the source of the second transistor is coupled to the reference voltage; /, the source, the fourth transistor, and the third wheel of the gate wheel The gate of the crystal, the gate of the second transistor, and the source is secret to the reference - the fifth transistor 'its gate and its bungee _ in the beginning to receive the second: the closed signal' or The display is received every N picture periods; one of the gate turn-on signal and the gate turn-off signal; μ - the first, the crystal, the gate is lightly connected to the source of the fifth transistor, and the cell is connected to the cell a gate of the second transistor, the source of which is input to the material - the seventh transistor, the gate and the junction of which are connected to receive the 047 31212twf.doc / n 201103006 1 \ ^ ^ \J -/ 极 关闭 讯 二 二 二 ... ... ... ... 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场 场a crystal whose opening is coupled to the junction between the second transistor and the source thereof, wherein i and Ν are positive integers. 22, in the middle of the patent scope, in the 21st paragraph, when the transistor and the j-th memory-turn-off signal, the gate of the electric-electrode receives the gate signal, and the lower electrode is used to delete ^ with the second time pulse; the knife receives the phase difference (10) degrees of the first - 23. As in the patent application scope 21 when the fifth transistor and the seventh, the stand-up temporary attack, the other one蚩面湘Μ & The sun and the body of the gate are extremely stunned by the Λ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . When the mother is used, the second transistor is not used. = she turns off the signal. For example, _ is used to receive the gate off, and the first to close the signal. Oh, and 26