201101655 六、發明說明： 【發明所屬之技術領域】 本發明係有關於切換式電源轉換，特別是關於可調整主 器二次側電流路徑關閉時間之切換式電源轉換。 【先前技術】 在電子設備之供電中，切換式電源轉換器因其具有高 率及小型零件尺寸之優勢而廣被採用。 。、 以返馳式交流轉直流電源轉換器為例，圖13展示一返馳式交 流轉直流電源轉換器之主變壓器充電週期，圖比展示—返馳式交 Ο 流轉直流電源轉換器之主變壓器放電週期。如圖ia及圖比所示 之架構包含有一 N型金氧半(NM0S)電晶體101、一主變壓器1〇2T 一二極體103及一電容1〇4。 在該架構中，該NM〇S電晶體ιοί係用以反應於一脈衝寬度調 變(PWM)信號yG1以控制該主變壓器1〇2之電能轉換。 該主變壓器1〇2係用以將輸入直流電源y1N轉換成一直流輪 電壓Vcc。 ^ 該二極體103係耦接至該主變壓器102之二次側，用以在該 q NM〇sS電晶體101開啟時截斷該二次側之電流路徑，及在該NMOS 電晶體ιοί關閉時釋放磁通能量至該電容104。當該NM〇s電晶體 開啟時’ 5亥一>極體1〇3之陰極電壓為Vin/N+Vcc，其大於該二極 體103之陽極電壓GND，致使該二極體1〇3逆偏而截斷該二次側之 電流路後；當該NMOS電晶體101關閉時，該主變壓器102二次側 之電壓極性會正、負互換，致使該二極體103之陽極電壓大於其 陰極電壓而使該二次侧之電流路徑開啟。 ，電容104係用以承載該直流輸出電壓vcc。 曰藉由一PWM控制器（未示於圖中）之PWM信號Vgi使該NM0S電 a曰體101週期性地開啟、關閉，輸入電源即可經由該主變壓器1〇2 轉換至輪出端。 201101655 然而’當磁通能量經由該二極體103釋放時，該二極體i〇3 之開啟電壓0· 7V會消耗相當多之能量而使轉換效率劣化，特別是 當該直流輸出電壓V(X額定在一低電壓時。 習知電源轉換器所採用之一解決方案係以具低開啟電壓之一 開關電路取代該二極體103以增進轉換效率。 請參照圖2，其繪示一習知電路，用以開關一返馳式AC轉DC 電源轉換器之變壓器二次側。如圖2所示，該習知電路包含有一 二極體2(Π、一比較器202及一 NMOS電晶體203。 該二極體201係用以在該比較器202及該NMOS電晶體203之 〇 切換速度慢於輸入信號之切換速度時開、關一電源轉換器之變壓 器二次侧。 該比較器202及該NMOS電晶體203係用以模擬一二極體之功 能。該比較器202反應該二極體201之陽極電壓及陰極電壓以控 制该NMOS電晶體203之開啟。當該陽極電壓比該陰極電壓高且其 壓差大於一臨界電壓時’該比較器202會將該NMOS電晶體203開 啟，且該NMOS電晶體203之開啟電壓遠小於該二極體2〇1之開啟 電壓，若否，該比較器202會將該NMOS電晶體203關閉。圖2電 路中之開啟電流I與開啟電壓VF之關係示於圖3。如圖3所示，201101655 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to switched mode power conversion, and more particularly to switched mode power conversion that can adjust the secondary side current path turn-off time of the main unit. [Prior Art] In the power supply of electronic equipment, the switching power converter is widely used because of its high rate and small component size. . Taking the flyback AC to DC power converter as an example, Figure 13 shows the main transformer charging cycle of a flyback AC to DC power converter. Figure shows the main transformer of the flyback DC power converter. Discharge cycle. The structure shown in Fig. ia and Fig. includes an N-type metal oxide half (NM0S) transistor 101, a main transformer 1〇2T-diode 103, and a capacitor 1〇4. In this architecture, the NM〇S transistor ιοί is used to react to a pulse width modulation (PWM) signal yG1 to control the power conversion of the main transformer 1〇2. The main transformer 1〇2 is for converting the input DC power source y1N into a DC current voltage Vcc. The diode 103 is coupled to the secondary side of the main transformer 102 for cutting off the current path of the secondary side when the q NM〇sS transistor 101 is turned on, and when the NMOS transistor ιοί is turned off. Magnetic flux energy is released to the capacitor 104. When the NM〇s transistor is turned on, the cathode voltage of the pole body 1〇3 is Vin/N+Vcc, which is greater than the anode voltage GND of the diode 103, so that the diode 1〇3 After the NMOS transistor 101 is turned off, the voltage polarity of the secondary side of the main transformer 102 is positively and negatively interchanged, so that the anode voltage of the diode 103 is greater than the cathode thereof. The voltage causes the current path of the secondary side to turn on. The capacitor 104 is used to carry the DC output voltage vcc.该 The PWM signal Vgi of a PWM controller (not shown) causes the NM0S to be periodically turned on and off, and the input power can be switched to the wheel terminal via the main transformer 1〇2. 201101655 However, when the magnetic flux energy is released via the diode 103, the opening voltage of the diode i〇3 will consume a considerable amount of energy, which deteriorates the conversion efficiency, especially when the DC output voltage V ( X is rated at a low voltage. One of the solutions adopted by the conventional power converter is to replace the diode 103 with a switching circuit having a low turn-on voltage to improve the conversion efficiency. Referring to FIG. 2, a drawing is shown. The circuit is used to switch the secondary side of the transformer of a flyback AC to DC power converter. As shown in FIG. 2, the conventional circuit includes a diode 2 (Π, a comparator 202, and an NMOS battery). The diode 203 is configured to turn on and off a transformer secondary side of a power converter when the switching speed between the comparator 202 and the NMOS transistor 203 is slower than the switching speed of the input signal. 202 and the NMOS transistor 203 are used to simulate the function of a diode. The comparator 202 reflects the anode voltage and the cathode voltage of the diode 201 to control the opening of the NMOS transistor 203. When the anode voltage is higher than the The cathode voltage is high and its differential pressure is greater than one When the voltage is 'the comparator 202, the NMOS transistor 203 is turned on, and the turn-on voltage of the NMOS transistor 203 is much smaller than the turn-on voltage of the diode 2〇1. If not, the comparator 202 will turn the NMOS The crystal 203 is turned off. The relationship between the turn-on current I and the turn-on voltage VF in the circuit of Fig. 2 is shown in Fig. 3. As shown in Fig. 3,
當VF超過〇· 25mv時，該開啟電流I會以1/R腦之斜率增加；當Vf 低於0. 25mv時’該開啟電流I會縮減至〇。 雖然該習知電路可降低開啟電壓，其仍然有二主要缺點。首 先，該0. 25mv之臨界電壓需要一具較佳解析度之比較器方能匹配 而使該習知轉料實施。再者，在連續賴模式⑹nti_s Current Mode ; CCM)中該臨界賴之數鎌誠定。請參照圖4， 當電源轉儲工作於αΜ時，若貞餘況由低貞載魏高負載， =該尚負載所需之二次側戴斷電流高於—臨界電流，其中該臨 界電流對應於-預定之臨界電壓（該臨界電壓=該臨界電流χ R_) ’則制關電路將永遠得不到觸發以 二次 路 201101655 徑，而可能導致系統災難。 為解決CCM下之二次側電流路徑截斷相關問題，美國專利 6T71059B1提出在二次侧量測該二極體陰極電壓之週期，其係藉由 债測對應於主側開啟時之一高電壓Vin/N+Vcc而完成（示於圖la)， 然後依該週期定出截斷該二次側之時間。然而’此方案無法適用 於不連續電流模式(Discontinuous Current Mode ; DCM)，因為在 DCM下’主變壓器中之能量在主側開啟之前早已放光了，其結果 是’該二次側電流路徑之輸出電容會提供一逆向電流，而該逆向 電流會在該主侧開啟時干擾該主變壓器之充電。因此，亟需提供 一解決方案，其可妥適截斷CCM下之二次側電流路徑及DCM下之 二次側電流路徑。 有鑒於此瓶頸，本發明提出一新穎的架構，用以產生一關閉 預測信號，以妥適截斷CCM下之二次側電流路徑及DCM下之二次 側電流路徑、避免在二次側電流路徑產生逆向電流。 【發明内容】 本發明之一目的在於提供一二次側關閉時間調整方法，使一 切換式電源轉換器能妥適地截斷CCM下之二次侧電流路徑及DCM 下之二次側電流路徑，以避免在二次側電流路徑產生逆向電流。 本發明另一目的在於提供一二次側關閉時間調整裝置，使一 切換式電源轉換器能妥適地截斷CCM下之二次側電流路徑及DCM 下之二次側電流路徑，以避免在二次側電流路徑產生逆向電流。 本發明又一目的在於提供利用一二次側關閉時間調整裝置之 一系統’使一切換式電源轉換器能妥適地截斷CCM下之二次侧電 流路徑及DCM下之二次側電流路徑，以避免在二次側電流路徑產 生逆向電流。 為達到本發明前述之目的，一適用於切換式電源轉換之二次 側關閉時間調整方法乃被提出，該方法包含以下步驟：依一第一 參考電壓偵測一二次側電晶體跨電壓之下降緣以產生一第一重置 201101655 化號’依一第二參考電壓偵測該二次侧電晶體跨電壓之上升緣以 產士一第一設置信號；依該第一重置信號及該第一設置信號驅動 一第一閃鎖操作以產生一二次侧放電結束信號；以及依該二次側 放電結束信號之週期產生一關閉預測信號。 為達到前述之目的’本發明進一步提出一種二次側關閉時間 調整裝置，其適用於一切換式電源轉換，該裝置具有：一第一比 較器，用以依一第一參考電壓及一二次側電晶體跨電壓之電壓比 較而產生一第一重置信號；一第二比較器，用以依一第二參考電 壓及該二次側電晶體跨電壓之電壓比較而產生一第一設置信號； 一第一閂鎖器，用以依該第一重置信號及該第一設置信號產生一 二次侧放電結束信號；以及一關閉預測信號產生單元，用以依該 二次侧放電結束信號之週期產生一關閉預測信號。 為達到前述之目的，本發明進一步提出一種利用一二次側關 閉時間調整裝置之系統，其適用於一切換式電源轉換，該系統具 有：一第一比較器，用以依一第一參考電壓及一二次側電晶體跨 電壓之電壓比較而產生一第一重置信號；一第二比較器，用以依 一第二參考電壓及該二次側電晶體跨電壓之電壓比較而產生一第 一設置信號；一閂鎖器，用以依該第一重置信號及該第一設置信 號產生一二次側放電結束信號；一關閉預測信號產生單元，用以 依該二次側放電結束信號之週期產生一關閉預測信號以關閉該二 次側電晶體；以及一脈衝寬度調變控制器，用以產生一脈衝寬度 調變信號以控制該切換式電源轉換。 為使貴審查委員能進一步瞭解本發明之結構、特徵及其目 的，茲附以圖式及較佳具體實施例之詳細說明如后。 【實施方式】 請參照圖5，其繪示一二次側電晶體壓降VDS於CCM及DCM之 工作波形，以說明本發明關閉二次側電晶體之主要原理。如圖5 所示，DCM及CCM下之壓降^其波形差異在於DCM下之VDS波形在 201101655 ° 異’本發明乃在放電 』曰》又〇至2V〇間之臨界電壓，以偵測放電結 發明由放電結束咖量耻電結束職，再依 門曰 設_及晶體。本發明之 s W祐贸咖都發揮功效，因為在放電期間所設介於〇 壓’繼轉換處糊編，都能捕捉 ,〇 、s。又，2v°之值夠大，使相關偵測電路易於實施 且侧結果較不受雜響。 料⑽貫苑 Ο ο 请參照圖6 ’其％示本發明關二次側電晶體—較佳實之 流程圖。如® 6所示’該方法包含以下步驟：依—第—參考電壓 偵測一二次侧電晶體跨電壓之下降緣以產生一第一重置信號（步 驟a)，依-第二參考電壓_該二次侧電晶體跨電壓之上升緣以 產生-第-設置信號(步驟b);依該第一重置信號及該第一設置信 號驅動-第-閃鎖操作以產生—二次侧放電結束信號(步驟c);以 及依該-次側放電結束信號之週期產生一關閉預測信號(步驟d)。 在步驟a中，該第一參考電壓可設於加至_〇/^之間而二 次側電晶體跨電壓之下降緣代表一放電期間之開始。 在步驟b中，該第二參考電壓可設於〇v至2Vg之間，而二次 側電晶體跨電壓之上升緣代表一放電期間之結束。 在步驟c中，該二次侧放電結束信號乃一脈衝信號，其上升 緣或下降緣之位準變換係由該第一重置信號及該第一設置信號促 成，而該位準變換可用以代表放電期間之結束。 在步驟d中，該關閉預測信號係一脈衝信號，其由該二次側 放電結束js號及該一次側放電結束信號週期之一比值決定，以關 閉該二次側電晶體。該關閉預測信號之脈衝產生時間乃可妥適地 定在距主側開啟前一短時間處以避免系統災難發生。 請參照圖7 ’其緣示本發明開關一二次側電晶體一較佳實施例 之方塊圖。如圖7所示，本發明該較佳實施例至少包含一 NM〇s電 201101655 晶體701、一主變壓器702、一 NM0S電晶體703、一電容704及一 二次側開關控制器705。 在該架構中’該NM0S電晶體701係用以反應於一 pWM信號I 以控制該主變壓器702之電源轉換。 ° 7 G1 該主變壓器702係用以將輸入直流電源yIN轉至一直流輪 壓 Vcc。 ' 該NM0S電晶體703係耦接至該主變壓器702之二次側，用以 在該二次側開關控制器705 —閘控信號i之控制下，於該nm〇s 電晶體701開啟時截斷該二次側之電流路徑，及於該NM〇S電晶體 〇 7〇1關閉時釋放磁通能量至該電容704。 。该電容704係用以承載該直流輸出電壓ycc。藉由一 ρψΜ控制 器（未示於圖中）之PWM信號Vgi使該NM〇s電晶體7〇1週期性地開 啟、關閉’輸入電源即可經由該主變壓器7〇2轉換至輸出端。 該二次側開關控制器705係用以依該NM0S電晶體703之汲極 電壓Vd產生該閘控信號V(；^相關的操作包括：依一第一參考電壓 偵測該NM0S電晶體703之汲極電壓VD之下降緣以產生一第一重 置信號(步驟a);依一第二參考電壓偵測該NM〇s電晶體7〇3之汲 Q 極=壓VD之上升緣以產生一第一設置信號（步驟b);依該第一重 置信號及該第一設置信號產生一二次侧放電結束信號，其中該二 -人側放電結束信號為一脈衝信號，其上升緣或下降緣之位準轉換 乃由該第一重置信號及該第一設置信號促成，且該位準轉換係用 以代表該放電期間之結束(步驟C);以及依該二次側放電結束信號 ，週期產生一關閉預測信號，其中該關閉預測信號係一脈衝信 號，其由該二次側放電結束信號及該二次侧放電結束信號週期之 一比值決定，以關閉該二次側電晶體。該關閉預測信號之脈衝產 生時間乃可妥適地定在距主側開啟前一短時間處以避免系統災難 發生（步驟d)。 圖8綠示了圖7中該二次側開關控制器7〇5之一細部方塊圖。 201101655 如圖8所不’ 5亥一次側開關控制器705包令—比較器801、一比較 器802、一問鎖器803、一反相1§ 804、一遮蔽時間模組8〇5、一 或閘806、一 SR閂鎖器807、一緩衝器808及一關閉預測信號產 生單元809。 該比較器801係用以依該汲極電壓vD及一第一參考電壓 Vth，〇n/。》產生一第一重置信號Vreseh，而該比較器8〇2係用以依該汲 極電壓Vd及一第二參考電壓Vth’rising產生一第一設置信號ysETi，其 中該第二參考電壓Vth,rising大於該第一參考電壓Vth<j_。 該閂鎖器803及反相器804係用以依該第一重置信號Vreseti& Ο該第一設置信號Vsm產生一二次側放電結束信號V2nddischend，其中該 二次側放電結束信號V 2nddischend 為一脈衝信號，其上升緣或下降緣之 位準轉換乃由該第一重置信號Vreseti及該第一設置信號Vsm促成， 且該位準轉換係用以代表該放電期間之結束。 該遮蔽時間模組805係用以依該第一重置信號VreSET1產生一第 二設置信號VsET2及一關閉信號V〇FF ’其中該第二設置信號VsET2係用 以開啟該二次側電晶體703，而該關閉信號V〇FF則用以強迫該二次 側電晶體703關閉。 該或閘806係用以依該關閉信號Vqff及一關閉預測信號v〇ffpred Ο 產生一第二重置信號VRESET2。 該SR閃鎖807及緩衝器808係用以依Vset2及Vreset2產生該 閘控信號Vg2，其中VSET2用以使該閘控信號Vg2輸出開啟狀態以開啟 該二次側電晶體70 3，而VRESET2用以使該閘控信號VG2輸出關閉狀態 以關閉該二次側電晶體703。 該關閉預測信號產生單元809係用以依該二次侧放電結束信 號V2nddischend產生該關閉預測信號VoFFPRED ’其中S亥關閉預測信號VoFppRg]) 係一脈衝信號，其由該二次側放電結束信號V2nddisc；hend及該二次侧放 電結束信號V2nddiSChend其週期之一比值決定，以關閉該二次側電晶體 703 〇 201101655 圖9繪示圖8中該關閉預測信號產生單元809之一細部方塊 圖。如圖9所示，該關閉預測信號產生單元8〇9包括一 D型正反 器901、一單發脈波產生器9〇2、一開關9〇3、一電流源9〇4、一 電容905、一運算放大器906、一電阻907、一電阻908、一比較 器909、一單發脈波產生器910、一開關911、一電流源912、〆 電容913、一運算放大器914、一電阻915、一電阻91Θ、一比較 器917及一開關單元918。 該D型正反器901係用以依Vhddischend產生一第一選擇信號Vsela 及一第二選擇號Vselb。該D型正反器901乃充當一除頻器以使vsela Ο 之脈衝與Vselb之脈衝可交替呈現。 該單發脈波產生器902係用以依Vsela產生一第一放電脈衝 RESETA 〇 該開關903係用以反應於RESETA而對該電容9〇5實施放電。 該電流源904及該電容905係用以產生一斜波信號v_。 該運算放大器906、電阻907及電阻908係用以產生該第一斜 波"is 號 Vrampa 之一分壓 Vrefa。 該比較器909係用以依該Vrampa及一分壓Vrefb產生一第一關閉 0 預測彳自號VoFFPREDICTA 0 該單發脈波產生器910係用以依Vselb產生一第二放電脈衝 RESETB ° 該開關911係用以反應於RESETB而對該電容913實施放電。 該電流源912及該電容913係用以產生一斜波信號Vrampb。 該運算放大器914、電阻915及電阻916係用以產生該第二斜 波k就Vrampb之一分壓VrEFB。 該比較器917係用以依該Vrampb及Vrefa產生一第二關閉預測信 VoFFPREDICTB 0 該開關单元918係用以在Vsela之控制下’使WmEDICTA與VoFFPREDICTB 乂替呈現以產生VoFFPRH)。 201101655 及圖T 工H9之CCM工作波形示於圖10，而圖7、圖8 於®u。如圓ig及圖11所示，V。· ㈣_上升緣之-小段時_出現，a_CTA 興V〇™mB係交替呈現以產生Vqf_。 利用如圖8簡9所示本發明—較佳實施例之 間調=裝置實現圖7中該二次側關控制器7{)5，—可調整二二侧 關閉時間之AC轉DC電轉換n乃得呈現。另 | 用於AC轉AC，DC轉AC，。说轉DC之切換式電源轉=發胁了應 2案所揭林，乃較佳實_，舉凡局部之變更或 源 為熟習該項技藝之人所易於推知者，例如引 5二緩衝器尺寸之變更、平 範嘴。 月化處理方式之變更等，俱不脫本案之專利權 綜上所陳’杨無錄目的、手段與 於習知之技術特徵，且其首先發人 =顯不其町異 2 Li，貝審查委員明察，並祈早曰賜予專利，俾嘉氧 社會，實感德便。 π丁号π伴彔思 Ο 【圖式簡單說明】 壓器=期^_ ’躲示—返赋Α⑽_換器之變 壓器:ib:期。不意圖’其繪示-返馳式’队電源轉換器之變 鏟it圖雷哭意圖’其緣示一習知電路’用以開關一返馳式AC 轉dc電麟換器之麵器二蝴。 Ξ ’其繪補2 f知電路之卜Vf特性曲線。 之-圖’錄示不連續電流模式及連續電流模式下 之一:人側電流相對於時間之變化曲線。When the VF exceeds 〇·25mv, the turn-on current I increases with a slope of 1/R brain; when Vf is lower than 0.25mv, the turn-on current I is reduced to 〇. Although this conventional circuit can reduce the turn-on voltage, it still has two major drawbacks. First, the threshold voltage of 0.25 mv requires a comparator of better resolution to match the conventional transfer. Furthermore, in the continuous mode (6) nti_s Current Mode; CCM), the critical value is determined. Referring to FIG. 4, when the power dump is operated at αΜ, if the residual condition is lower than the load of the Wei high load, the secondary side wear current required for the load is higher than the critical current, wherein the critical current corresponds to At the predetermined threshold voltage (the threshold voltage = the critical current χ R_) 'the circuit will never be triggered to the secondary road 201101655 diameter, which may cause system disaster. In order to solve the problem of secondary current path truncation under CCM, U.S. Patent No. 6T71059B1 proposes to measure the period of the diode voltage of the diode on the secondary side, which is determined by the debt measurement corresponding to one of the high voltage Vin when the main side is turned on. /N+Vcc is completed (shown in Figure la), and then the time to cut off the secondary side is determined according to the period. However, 'this scheme cannot be applied to Discontinuous Current Mode (DCM) because the energy in the main transformer has already been discharged before the main side is turned on under DCM. The result is 'the secondary current path The output capacitor provides a reverse current that interferes with the charging of the main transformer when the primary side is turned on. Therefore, there is a need to provide a solution that properly intercepts the secondary current path under the CCM and the secondary current path under the DCM. In view of this bottleneck, the present invention proposes a novel architecture for generating a turn-off prediction signal to properly cut off the secondary side current path under the CCM and the secondary side current path under the DCM to avoid the secondary side current path. A reverse current is generated. SUMMARY OF THE INVENTION One object of the present invention is to provide a secondary side turn-off time adjustment method, such that a switching power converter can properly cut off the secondary side current path under the CCM and the secondary side current path under the DCM. Avoid reverse currents in the secondary side current path. Another object of the present invention is to provide a secondary side closing time adjusting device for enabling a switching power converter to properly cut off the secondary side current path under the CCM and the secondary side current path under the DCM to avoid The side current path produces a reverse current. Another object of the present invention is to provide a switching power converter capable of properly cutting off the secondary current path under the CCM and the secondary current path under the DCM by using a system of a secondary side closing time adjustment device. Avoid reverse currents in the secondary side current path. In order to achieve the foregoing object of the present invention, a secondary side turn-off time adjustment method suitable for switching power conversion is proposed, the method comprising the steps of: detecting a secondary side transistor cross voltage according to a first reference voltage Decreasing the edge to generate a first reset 201101655 chemical number 'detecting the rising edge of the secondary side transistor across the voltage according to a second reference voltage to the first setting signal of the maternal; according to the first reset signal and the The first setting signal drives a first flash lock operation to generate a secondary side discharge end signal; and generates a close prediction signal according to a period of the secondary side discharge end signal. In order to achieve the foregoing objectives, the present invention further provides a secondary side turn-off time adjusting device, which is suitable for a switched power conversion, the device having: a first comparator for accommodating a first reference voltage and a second Comparing the voltage of the side transistor across the voltage to generate a first reset signal; a second comparator for generating a first set signal according to a second reference voltage and a voltage comparison of the secondary side transistor across the voltage a first latch for generating a secondary side discharge end signal according to the first reset signal and the first setting signal; and a turn-off prediction signal generating unit for outputting the secondary side discharge end signal The cycle produces a closed prediction signal. In order to achieve the foregoing object, the present invention further provides a system using a secondary side off time adjustment device, which is suitable for a switched power conversion, the system having: a first comparator for accommodating a first reference voltage And comparing the voltage of the secondary side transistor across the voltage to generate a first reset signal; a second comparator for generating a voltage according to a second reference voltage and a voltage comparison of the secondary side transistor across the voltage a first setting signal; a latch for generating a secondary side discharge end signal according to the first reset signal and the first setting signal; and a closing prediction signal generating unit for ending according to the secondary side discharge The period of the signal generates a turn-off prediction signal to turn off the secondary side transistor; and a pulse width modulation controller for generating a pulse width modulation signal to control the switched mode power conversion. The detailed description of the drawings and preferred embodiments is set forth in the accompanying drawings. [Embodiment] Please refer to Fig. 5, which shows the working waveform of a secondary side transistor voltage drop VDS in CCM and DCM to illustrate the main principle of the invention for closing the secondary side transistor. As shown in Figure 5, the voltage drop under DCM and CCM is different in waveform. The VDS waveform under DCM is at 201101655 °. The present invention is in the discharge state and then reaches the threshold voltage of 2V to detect the discharge. The invention was terminated by the end of the discharge of the shame, and then set the _ and the crystal according to the threshold. The s W You Trade Café of the present invention functions as a buffer, which can be captured during the discharge, and can be captured, 〇, s. Moreover, the value of 2v is large enough to make the correlation detection circuit easy to implement and the side results are less susceptible to noise. (10) Guanyuan Ο ο Please refer to Fig. 6 '% shows the secondary side transistor of the present invention - a preferred flow chart. As shown in FIG. 6 'the method includes the following steps: detecting the falling edge of the secondary side transistor across the voltage to generate a first reset signal (step a), according to the second reference voltage _ the secondary side transistor crosses the rising edge of the voltage to generate a -first-set signal (step b); according to the first reset signal and the first set signal to drive the -th-flash lock operation to generate - secondary side a discharge end signal (step c); and a turn-off prediction signal is generated according to the period of the -side side discharge end signal (step d). In the step a, the first reference voltage may be set to be added between _〇/^ and the falling edge of the secondary side transistor across the voltage represents the beginning of a discharge period. In step b, the second reference voltage may be set between 〇v and 2Vg, and the rising edge of the secondary side transistor across the voltage represents the end of a discharge period. In the step c, the secondary side discharge end signal is a pulse signal, and the level change of the rising edge or the falling edge is caused by the first reset signal and the first setting signal, and the level conversion can be used. Represents the end of the discharge period. In step d, the off prediction signal is a pulse signal determined by a ratio of the secondary side discharge end js number and the primary side discharge end signal period to turn off the secondary side transistor. The pulse generation time of the off prediction signal can be properly set a short time before the main side is turned on to avoid a system disaster. Referring to Figure 7', there is shown a block diagram of a preferred embodiment of the switch-secondary transistor of the present invention. As shown in FIG. 7, the preferred embodiment of the present invention includes at least one NM〇s electric 201101655 crystal 701, a main transformer 702, an NM0S transistor 703, a capacitor 704, and a secondary side switch controller 705. In the architecture, the NMOS transistor 701 is responsive to a pWM signal I to control the power conversion of the main transformer 702. ° 7 G1 This main transformer 702 is used to switch the input DC power supply yIN to the DC current Vcc. The NM0S transistor 703 is coupled to the secondary side of the main transformer 702 for intercepting the nm〇s transistor 701 when the secondary side switch controller 705 is controlled by the gate signal i. The secondary side current path, and the magnetic flux energy is released to the capacitor 704 when the NM〇S transistor 〇7〇1 is turned off. . The capacitor 704 is configured to carry the DC output voltage ycc. The NM〇s transistor 7〇1 is periodically turned on and off by a PWM signal Vgi of a ρψΜ controller (not shown) to be switched on to the output via the main transformer 7〇2. The secondary side switch controller 705 is configured to generate the gate control signal V according to the drain voltage Vd of the NMOS transistor 703. The operation includes: detecting the NMOS transistor 703 according to a first reference voltage. a falling edge of the drain voltage VD to generate a first reset signal (step a); detecting a rising edge of the Q pole of the NM〇s transistor 7〇3=voltage VD according to a second reference voltage to generate a a first setting signal (step b); generating a secondary side discharge end signal according to the first reset signal and the first setting signal, wherein the two-person side discharge end signal is a pulse signal, and its rising edge or falling The level transition is caused by the first reset signal and the first set signal, and the level transition is used to represent the end of the discharge period (step C); and according to the secondary side discharge end signal, The cycle generates a shutdown prediction signal, wherein the shutdown prediction signal is a pulse signal determined by a ratio of the secondary side discharge end signal and the secondary side discharge end signal period to turn off the secondary side transistor. Turn off the pulse generation time of the prediction signal. Suitably set a short time before opening from the main side to avoid system disaster (step d). Figure 8 shows a detailed block diagram of the secondary side switch controller 7〇5 in Figure 7. 201101655 Not 5 hai primary side switch controller 705 package order - comparator 801, a comparator 802, a lock 803, an inversion 1 § 804, a occlusion time module 8 〇 5, a or gate 806, a The SR latch 807, a buffer 808 and a turn-off prediction signal generating unit 809. The comparator 801 is configured to generate a first weight according to the drain voltage vD and a first reference voltage Vth, 〇n/. The signal Vreseh is set, and the comparator 8〇2 is configured to generate a first setting signal ysETi according to the threshold voltage Vd and a second reference voltage Vth'rising, wherein the second reference voltage Vth,rising is greater than the first The reference voltage Vth<j_. The latch 803 and the inverter 804 are configured to generate a secondary side discharge end signal V2nddischend according to the first reset signal Vreseti&, the first set signal Vsm, wherein the secondary side The discharge end signal V 2nddischend is a pulse signal whose rising edge or falling edge The level conversion is caused by the first reset signal Vreseti and the first set signal Vsm, and the level conversion is used to represent the end of the discharge period. The mask time module 805 is used according to the first weight. The signal VreSET1 generates a second setting signal VsET2 and a closing signal V〇FF', wherein the second setting signal VsET2 is used to turn on the secondary side transistor 703, and the closing signal V〇FF is used to force the second The secondary side transistor 703 is turned off. The OR gate 806 is configured to generate a second reset signal VRESET2 according to the turn-off signal Vqff and a turn-off prediction signal v〇ffpred Ο. The SR flash lock 807 and the buffer 808 are configured to generate the gating signal Vg2 according to Vset2 and Vreset2, wherein VSET2 is used to enable the gating signal Vg2 to be turned on to turn on the secondary side transistor 70 3, and VRESET2 is used. The gate signal VG2 is turned off to turn off the secondary side transistor 703. The off prediction signal generating unit 809 is configured to generate the off prediction signal VoFFPRED 'where the Shai off prediction signal VoFppRg is generated according to the secondary side discharge end signal V2nddischend), and the second side discharge end signal V2nddisc ;hend and the secondary side discharge end signal V2nddiSChend are determined by a ratio of one of the periods to close the secondary side transistor 703 〇 201101655. FIG. 9 is a detailed block diagram of the off prediction signal generating unit 809 of FIG. As shown in FIG. 9, the shutdown prediction signal generating unit 8〇9 includes a D-type flip-flop 901, a single-shot pulse generator 9〇2, a switch 9〇3, a current source 9〇4, and a capacitor. 905, an operational amplifier 906, a resistor 907, a resistor 908, a comparator 909, a single pulse generator 910, a switch 911, a current source 912, a tantalum capacitor 913, an operational amplifier 914, a resistor 915 A resistor 91 Θ, a comparator 917 and a switching unit 918. The D-type flip-flop 901 is configured to generate a first selection signal Vsela and a second selection number Vselb according to Vhddischend. The D-type flip-flop 901 acts as a frequency divider such that the pulses of vsela 与 and the pulses of Vselb are alternately presented. The single pulse generator 902 is configured to generate a first discharge pulse RESETA according to Vsela. The switch 903 is configured to discharge the capacitor 9〇5 in response to RESETA. The current source 904 and the capacitor 905 are used to generate a ramp signal v_. The operational amplifier 906, the resistor 907 and the resistor 908 are used to generate a partial voltage Vrefa of the first ramp wave "is Vrampa. The comparator 909 is configured to generate a first off 0 prediction according to the Vrampa and a divided voltage Vrefb. The single pulse generator 910 is configured to generate a second discharge pulse RESETB according to Vselb. The 911 is used to discharge the capacitor 913 in response to RESETB. The current source 912 and the capacitor 913 are used to generate a ramp signal Vrampb. The operational amplifier 914, the resistor 915 and the resistor 916 are used to generate the second ramp k to divide VrEFB in one of Vrampb. The comparator 917 is configured to generate a second shutdown prediction signal VoFFPREDICTB 0 according to the Vrampb and the Vrefa. The switch unit 918 is configured to "present WmEDICTA and VoFFPREDICTB to generate VoFFPRH" under the control of Vsela. The CCM working waveforms of 201101655 and Figure H9 are shown in Figure 10, while Figures 7 and 8 are in ®u. As shown in circle ig and Figure 11, V. · (4) _ rising edge - small segment _ appears, a_CTA 兴 V〇TM mB is alternately presented to produce Vqf_. The secondary side off controller 7{)5 of FIG. 7 is realized by using the apparatus of the present invention as shown in FIG. 8 and the adjustment between the preferred embodiments, and the AC to DC conversion of the second and second side closing times can be adjusted. n is to be presented. Another | For AC to AC, DC to AC,. It is said that the switch-type power supply to DC is not threatened. It is better to use it. It is easy to infer that the local change or source is familiar to those skilled in the art, such as the size of the buffer. Change, Ping Fan mouth. The change of the monthly processing method, etc., does not deviate from the patent right of the case. In summary, Yang did not record, the means and the technical characteristics of the well-known, and the first to send people = show the difference between the two 2 Li, the shell review committee clearly, And praying for the patents, the 俾jia oxygen society, the real sense of virtue. π丁号 π伴彔思 Ο [Simple diagram description] Pressurer = period ^_ ‘Double-return Α(10)_Changer transformer: ib: period. I don’t intend to 'show-return-type' team power converter's change shovel it's tears intentions 'there is a familiar circuit' to switch a return-to-back AC to dc electric converter butterfly. Ξ ‘There is a picture of the Vf characteristic curve of the circuit. - Figure 'records one of the discontinuous current mode and continuous current mode: the curve of the human side current versus time.
圖5為7F意圖’其緣示一二次側電晶體壓降VDS於CCM及DCM 11 201101655 之工作波形，以說明本發明關閉二次側電晶體之主要原理。 圖6為一示意圖，其繪示本發明關閉二次側電晶體一較佳實 施例之流程圖。 圖7為一示意圖，其繪示本發明開關一二次側電晶體一較佳 實施例之方塊圖。 圖8為一示意圖，其繪示圖7中二次側開關控制器之一細部 方塊圖。 圖9為一示意圖，其繪示圖8中關閉預測信號產生單元之一 細部方塊圖。Fig. 5 is a view showing the operation of a secondary side transistor voltage drop VDS at CCM and DCM 11 201101655 to illustrate the main principle of the present invention for closing the secondary side transistor. Figure 6 is a schematic view showing a flow chart of a preferred embodiment of the invention for closing the secondary side transistor. Fig. 7 is a schematic view showing a block diagram of a preferred embodiment of the switch-secondary transistor of the present invention. Figure 8 is a schematic view showing a detailed block diagram of the secondary side switch controller of Figure 7. Fig. 9 is a schematic view showing a detailed block diagram of the closed prediction signal generating unit of Fig. 8.
圖10為一示意圖，其繪示圖7,圖8及圖9之CCM工作波形。 圖11為一示意圖，其繪示圖7,圖8及圖9之DCM工作波形。 【主要元件符號說明】 變壓器102、702 電容 104、704 二次側開關控制器705 閂鎖器803 遮蔽時間模組805 SR閂鎖器807 關閉預測信號產生單元809 單發脈波產生器902、910 電流源904、912 運算放大器906、914 比較器909、917 NM0S 電晶體 101、203、701、703 二極體 103、201 比較器202 比較器801、802 反相器804 或閘806 緩衝器808 D型正反器901 開關 903、911 電容 905、913 電阻 907、908、915、916 開關單元918 12FIG. 10 is a schematic diagram showing the CCM working waveforms of FIG. 7, FIG. 8 and FIG. Figure 11 is a schematic view showing the DCM operating waveforms of Figures 7, 8 and 9. [Main component symbol description] Transformer 102, 702 Capacitor 104, 704 Secondary side switch controller 705 Latch 803 Mask time module 805 SR latch 807 Close prediction signal generation unit 809 Single pulse generator 902, 910 Current source 904, 912 operational amplifier 906, 914 comparator 909, 917 NM0S transistor 101, 203, 701, 703 diode 103, 201 comparator 202 comparator 801, 802 inverter 804 or gate 806 buffer 808 D Type flip-flop 901 switch 903, 911 capacitor 905, 913 resistor 907, 908, 915, 916 switch unit 918 12