201109691 六、發明說明： 【發明所屬之技術領域】 本發明係關於半導體積體電路之電氣測試用測試晶 片，特別是關於做為積體電路形成於晶圓並被切斷為電路 晶片之測試晶片。 【先前技術】 做為以一次或分複數次測試形成於晶圓之未切斷之多 數積體電路之裝置之一種，有使用實行積體電路之電氣測 S式之測試晶片者（專利文獻1及2)。 於此等習知技術中係使用將複數測試晶片配置於晶片 支持體之上側之晶片單元、從該晶片單元往下方隔有=隔 且具備探冑支持體與配置於該探針支持體之下側之複數個 接觸子之探針單元、配置於前述晶片單元及前述探針單元 之間且具備銷支持體與於上下方向貫通該銷支持體而上端 及下端可分別往前述銷支持體之上方及下方突 連接銷之連接單元。 数根 ^測試晶片產生用於積體電路即被檢查體之電氣測試 之電5虎並具有接受來自被檢查體之回應信號並處理 之機能。因Λ ’利用習知技術，由於不需要具備測 °" 之機能之配置有複數電路之複數配線基板，故在 :技術前被認為必要之測試頭顯著小型化，測試裝置變廉 之具體機能及電路 因此，無法減少對 然而，上述習知技術針對測試晶片 除上述事項以外完全未記載亦未隱含。 201109691 如電腦之外部之裝罟夕、s > ^ 之通彳§用頻道’亦無法進行正確且迅 速之測試。 [專利文獻1].曰本特表平10-510682公報 [專利文獻2]:日本特開平1 1 -25 1 383號公報 【發明内容】 [發明欲解決之課題] 本發月係以電路構成雖簡略化但對外部之裝置之通信 用頻道數減少，可$ #苗τ λ J進仃更正確及迅速之測試為目的。 [解決課題之手段] …本發明之測5式晶片係產生用於被檢查體之電氣測試之 測。式U並接受來自被檢查體之回應信號。此種測試晶片 包含產生前述測試信號並接受前述回應信號加以處理之至 夕1個k號處理電路、進行對該信號處理電路及外部之電 氣信號之收發之收發電路。 該信號處理f路包含基於從外部被供給之圖案資訊產 生真值1及〇之脈衝信號之格式器、基於前述脈衝信號產 生驅動被檢查體之驅動信號之複數驅動器、接受來自被檢 查體之回應信號並對前述收發電路輸出表示被檢查體之中 之單元為不良之不良信號之複數比較電路。 前述收發電路具備產生基準測試頻率信號之時率產生 器、基於前述不良信號特定出不良單元並對外部輪出之失 效擷取控制 '基於前述基準測試頻率信號產生對應於該基 準測試頻率信號之定時信號之定時信號產生器、對外部輸 出為了從外部讀出前述圖案資訊之位址信號之圖案產生 6 201109691 則述4號處理電路及前述收發電路可連接於外部之電 腦，且可從外部接受電力而作動。 <刖述k號處理電路可進一步具備保護該信號處理電路 免受從被檢查體輸入該信號處理電路之過電壓之箝位/負 載電路。 ' 别述仏號處理電路可進一步具備測定被檢查體之輸出 輸入端子之電壓、電流之定電壓及定電流測定電路。 前述比較電路可具備將前述回應信號與Η側之基準信 號加以比較之第1類比比較器、將前述回應信號與L側之 基準信號加以比較之第2類比比較器、基於兩類比比較器 之輸出信號輸出前述不良信號之不良信號產生電路。 前述不良信號可包含特定前述被檢查體中之不良單元 之座標位置之資訊。 [發明之效果] 利用本發明，由於將測試機能分為具備如上述之各種 電路之信號處理電路及收發電路，故即使具備複數信號處 理電路且使收發電路為此等信號處理電路共通之電路，測 5式晶片之電路構成雖簡略化但對外部之裝置之通信用頻道 數減少’可進行更正確及迅速之測試。 【實施方式】 [關於用語] 於以下之說明中，於圖1及圖4將上下方向稱為上下 方向或Ζ方向，將左右方向稱為左右方向或X方向，將紙 201109691 奇方向稱為前後方向或y 元、探針單元及連接單元。於、旦此等方向會隨將晶片單 之此等單元之姿勢而變。…則试裝置之支架之狀態中 因此，使用本發明之測 單元被安裝於支架之狀態下二片本=試裝置於此等3個 際上可於成為上下方向之狀 所谓之上下方向實 為斜方向之狀態等成為任二為上下相反之狀態、成 [測… 之狀態下使用。 L J式裝置之一實施例] 參照圖1，測試裝置10係 圓12之未切斷容把 ’、成於圓板狀之半導體晶 次或分複數 體電路（未圖示）為被檢查體，以一 進行之電查即測試此積體電路。以測試裝置1。 狀電㈣即各積體電路係於上面具有如墊 狀電極般之複數電極(未圖示)且具有複數單元。 測試裝置1 〇包含去拉留_ m 承載圓板狀之半導體曰圓二0、受支持單元20支持並 2〇支持為位於檢杳載122之上之載台22、被支持單元 曰圓丨）,—戟〇 22之上方並進行對圓板狀之半導體 ΘΒ 之電氣信號之收發之卡式組裝體24 ' .星備各種雷a :路之外《置聯照圖……控制測試 路及機益並進行信號之處理之電腦28(參照圖4及。 ^單元2G具備往χγ方向延伸之基座板3 為從該基座板女裝 …… 方向隔間隔之複數處分別往上方 態之支柱32、安裝於各支柱32之上端部且平行： 基座板30之板狀之支持基座34。 、 支持基座34具有承接卡式組裝冑24之圓形之開口 立於開口 36之周圍限定開σ 36之緣部係承接並支持 201109691 卡式、、且裴體24之向上段部38(參照圖i、4、12)。 檢查載台22係使可解除地真空吸附圓板狀之半導體晶 圓1 2之夹碩40支持於載台移動機構42之上部，藉由載台 移動機構42使夾頭4G於χγζ方向三維移動並於繞往上下 方向延伸之Ζ軸線（例如於圖4顯示之假想軸線94)角度性 旋轉之公知之機構。 因此，圓板狀之半導體晶圓丨2在電氣測試之前以可解 除地被真空吸附於檢查載台22之狀態於前後、左右及上下 方向被二維移動，且繞ζ軸線被角度性旋轉，積體電路之 各電極被定位為可接觸板狀之接觸子44之針尖。 卡式組裝體24包含呈圓板狀之零件單元即晶片單元 46、具備複數前述接觸子44之探針單元48、將此兩單元 46、48之内部配線電氣連接之連接單元5〇、將晶片單元私 及連接單元50可分離地結合之上結合單元52(參照圖2至 15)、將探針單元48及連接單元5〇可分離地結合之下結合 單元54(參照圖2至15)，且全體具有圓板狀之形狀。 關於上述卡式組裝體24之細節，參照圖2至17進一 步說明。 如圖12詳細顯示，晶片單元46係將分別做為電子零 件作用之複數（Μ)測試晶片56配置於圓板狀之晶片支持體 58之上側。各測試晶片56係對應於複數（Ν)被檢查體（積體 電路）。 各測試晶片56亦為切斷形成於半導體晶圓之積體電路 而被形成之積體電路晶片以產生用於對應之各被檢查體之 電氣測s式之電氣信號並接受來自對應之各被檢查體之回應 <!； 9 201109691 k號加以處理，實仃對應之各被檢查體之電氣測試。 晶片支持體58具備於上面配置有複數測試晶片56之 圓板狀之晶片基板6〇、繞晶片基板60延伸之環62。此外， 環㈣將晶片基板60於該晶片基板6〇之上下面分別往上 下露出之狀態收容於環62之開口 62a(參照圖6及12)β 此種晶片基板60係以如含玻璃環氧樹脂或聚醯胺等樹 脂，'其積層體等電氣絕緣材料形成為圓板狀之多屏 配線基板，具有多數内部配線64且於上面具有連接於測言;; ΒΒ片56之電極之多數連接島(未圖示），進而於下面具有多 數其他連接島66,進而於上面具有複數連接器68。 多數内部配線64之中，複數内部配線64之上端部係 連接於連接於測試晶片56之電極之未㈣之前述連接島， 其餘複數内部配線64之上端部係連接於連接H 68之端 子。各内部配線64之下端部係連接於連接島66。各連接器 68係如圖4所示結合於電氣連接於外部裝4 %、電腦μ 等之其他連接器70。 矛2係板狀之環，於上端内側具有從上端部往内方突 出之向内凸緣部62b’且於於周方向隔間隔之複數處分別具 有於上下方向貫通之定位孔62c。 晶片基板60與環62係藉由從上方往下方貫通凸緣部 ㈣並螺合於晶片基板6G之複數固定螺絲76(參照圖9)可 :離地結合為晶片基板60被按壓於凸緣部02b之下面之狀 心及％ 62繞晶片基板6〇同軸延伸之狀態。 於％ 62繞於圖4顯示之假想軸線94隔間隔設有複數 凸輪從動件72。環62之凸輪從動件72係從環62之外周部 10 201109691 往半徑方向外方延伸，並做為上接合裝置52中之變位機構 74(參照圖2、3、4、14)之一部分發揮作用。 如圖12詳細顯示，探針單元48具備複數接一子料、 圓板狀之探針支持體78,於該探針支持體78之下側配置有 接觸子44。探針支㈣78 #備於下面配置有複數接觸子 44之圓板狀之探針基板8〇、繞探針基板肋延伸之環Μ。 此外’壤82係將探針基板8G於該探針基板8()之上下面分 別往上下露出之狀態收容於環82之開口仏(參照圖6 : 凡裡休对基板80係與晶片基板6〇同樣以如含玻璃環 氧樹脂或聚酿胺等樹脂、陶究、其積層體等電氣絕緣材料 具有與晶片基板60大致相同直徑尺寸之圓板狀之配 具有多數内部配線84 1於上面具有複數連接島 進而於下面具有複數探針島87。 =子44係記載於曰本特開2_-337_號公報、 I::::. 1 13946號公報、曰本特開跡_號公 下端…下方向延伸之座部(安裝區域)、從該座部之 前端H 或Y方向延伸之臂區域、及從該臂區域之 月丨J端部往下方Φ 大出之針尖區域之公知者。 各接觸子44係於臂區域往χ 區域往下方突出之狀態於:之上，方向延伸且針尖 當之手法呈懸臂樑狀固定二二上二部以軟焊、焊接等適 端部及下”係分別連接^^ 7°各内部配線84之上 環82係與…樣為=;τ島87。 下端部往内方突出之向“ &狀之環，於下端内側具有從 °凸緣部82b，且於於周方向隔間隔 201109691 之複數處分別具有於上下方向貫通之定位孔8 2 c。 探針基板80與環82係與晶片基板6〇與環^之結合 ==從下方往上方貫通凸緣部_並螺合於探針基板 固疋螺絲（未圖示）可分離地結合為探針基板8〇被 轴延伸之狀態。面之㈣及壤仏繞探針基板80同 與王衣6 2同樣地，於援δ 1 „ „ 七 、、2、，堯於圖4顯示之假想軸線94 “1隔設有複數凸輪從動件72。環82 從環82之外周部往半和 勒仵72係 工方向外方延伸，並做為下接合裝置 54中之變位機構74之-部分發揮作用。 如圖12詳細顯示，速垃 φ ^ M 早兀50具備將連接島66及85 電乳連接之多數連接銷8 6 ,RS ^ $ 86支持该連接銷86之圓板狀之銷 支持體88。銷支持體88呈 具…狀之環92。銷伴持:=寺具9〇、收容該銷保持 下古A骨、均保持具90係於該等達接銷86於上 方向貫通圓板狀之銷保持 92 ^ ^ ^ ^ ^ ”刈之狀態支持連接銷86。環 92係將劫保持具9〇收容於開σ 92a。201109691 VI. Description of the Invention: [Technical Field] The present invention relates to a test wafer for electrical testing of a semiconductor integrated circuit, and more particularly to a test wafer formed as an integrated circuit formed on a wafer and cut into a circuit wafer . [Prior Art] As one of the devices for testing an uncut main integrated circuit formed on a wafer in one or several times, there is a test wafer using an electrical measurement type S which implements an integrated circuit (Patent Document 1) And 2). In the prior art, a wafer unit in which a plurality of test wafers are disposed on the upper side of the wafer support is used, and the wafer unit is spaced apart from the wafer unit and has a probe support and is disposed under the probe support. a probe unit of a plurality of contacts on the side, disposed between the wafer unit and the probe unit, and having a pin support and penetrating the pin support in a vertical direction, and the upper end and the lower end are respectively above the pin support And the connecting unit of the lower connecting pin. A plurality of test wafers generate an electric function for the integrated circuit, that is, the electrical test of the object to be inspected, and have a function of accepting a response signal from the object to be inspected and processing it. Because of the use of the conventional technology, it is not necessary to have a plurality of wiring boards with a plurality of circuits, and the test heads that are considered necessary before the technology are significantly miniaturized, and the specific functions of the test apparatus become cheaper. Therefore, the circuit cannot be reduced. However, the above-mentioned prior art is not described or implied in addition to the above matters for the test wafer. 201109691 If the computer is installed outside, the s > ^ 彳 § channel ‘ can’t be tested correctly and quickly. [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. Although it is simplified, the number of communication channels for external devices is reduced, and it is possible to use $ #苗τ λ J for more accurate and rapid testing. [Means for Solving the Problem] The test type 5 wafer of the present invention generates an electrical test for the object to be inspected. Equation U and accepts a response signal from the subject. The test chip includes a transmission/reception circuit that generates the aforementioned test signal and receives the response signal for processing, and processes the signal processing circuit and the external electrical signal. The signal processing f-channel includes a formatter that generates a true value of 1 and a pulse signal based on the pattern information supplied from the outside, a complex driver that generates a driving signal for driving the object to be inspected based on the pulse signal, and receives a response from the object to be inspected. The signal and the transmission/reception circuit output a complex comparison circuit indicating that the cell in the object to be inspected is defective. The transceiver circuit includes a time rate generator for generating a reference test frequency signal, and a failure capture control that specifies a defective unit based on the bad signal and externally rotates, and generates a timing corresponding to the reference test frequency signal based on the reference test frequency signal. Signal timing signal generator, pattern output for external output to read the address information of the pattern information from the outside 6 201109691 The processing circuit No. 4 and the above-mentioned transceiver circuit can be connected to an external computer and can receive power from the outside. And act. <The k-processing circuit can further include a clamp/load circuit that protects the signal processing circuit from an overvoltage input from the object to be inspected. The nickname processing circuit may further include a constant voltage and a constant current measuring circuit for measuring the voltage and current of the output terminal of the object to be inspected. The comparison circuit may include a first analog comparator that compares the response signal with a reference signal on the side of the first side, a second analog comparator that compares the response signal with a reference signal on the L side, and an output based on two analog comparators. The signal outputs a bad signal generating circuit of the aforementioned bad signal. The aforementioned bad signal may include information on the coordinate position of the defective unit in the specific object to be inspected. [Effects of the Invention] According to the present invention, since the test function can be divided into a signal processing circuit and a transmission/reception circuit including the above-described various circuits, even if the signal processing circuit is provided and the transmission/reception circuit is common to the signal processing circuits, Although the circuit configuration of the type 5 chip is simplified, but the number of channels for communication of the external device is reduced, a more accurate and rapid test can be performed. [Embodiment] In the following description, the vertical direction is referred to as the vertical direction or the Ζ direction in FIGS. 1 and 4, and the left and right direction is referred to as the left-right direction or the X-direction, and the odd direction of the paper 201109691 is referred to as the front and rear directions. Direction or y element, probe unit and connection unit. These directions will change with the orientation of the units of the wafer. In the state of the bracket of the test apparatus, the two units of the test unit are mounted on the support, and the test apparatus can be in the up and down direction in the three directions. The state in the oblique direction is the state in which the upper and lower sides are opposite to each other, and is used in the state of [measured]. One embodiment of the LJ type device] Referring to Fig. 1, the test device 10 is an uncut device of the circle 12, and a semiconductor crystal or a sub-complex circuit (not shown) formed in a disk shape is a test object. The integrated circuit is tested by a check. To test the device 1. The electric circuit (4), that is, each integrated circuit has a plurality of electrodes (not shown) having a pad electrode as above and having a plurality of cells. The test apparatus 1 〇 includes a semiconductor 曰 circle 208 that is loaded with a circular plate shape, supported by the support unit 20, and supported by the stage 22 located above the inspection load 122, and the supported unit 曰 round 丨) , above the 戟〇 22 and carrying out the card assembly 24 ' for the transmission and reception of the electrical signals of the disk-shaped semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The computer 28 that handles the signal processing (refer to Fig. 4 and . ^ unit 2G has a base plate 3 extending in the direction of χ γ, which is a struts from the pedestal plate... 32. Mounted on the upper end of each of the pillars 32 and in parallel: a plate-shaped support base 34 of the base plate 30. The support base 34 has a circular opening that receives the card-type assembly 24 and is defined around the opening 36. The edge portion of the opening σ 36 receives and supports the 201109691 card type, and the upper portion 38 of the body 24 (see FIGS. i, 4, and 12). The inspection stage 22 is a vacuum-adsorbing vacuum-shaped semiconductor. The wafer 12 is supported on the upper portion of the stage moving mechanism 42 by the stage moving machine 42. A known mechanism for angularly rotating the collet 4G in the direction of χγζ and angularly about a Ζ axis extending in the up and down direction (for example, the imaginary axis 94 shown in Fig. 4). Therefore, the disk-shaped semiconductor wafer 丨 2 Before being electrically tested, the vacuum is adsorbed to the inspection stage 22 in a reversible manner, and is moved two-dimensionally in the front-rear, left-right, and up-and-down directions, and angularly rotated about the axis of the winding, and the electrodes of the integrated circuit are positioned to be contacted. The tip of the plate-shaped contact 44. The card assembly 24 includes a wafer unit 46 which is a disk-shaped component unit, a probe unit 48 having a plurality of the contact members 44, and an internal wiring of the two units 46 and 48. The connecting unit 5 is connected, the wafer unit private and connecting unit 50 is detachably coupled to the upper unit 52 (refer to FIGS. 2 to 15), and the probe unit 48 and the connecting unit 5 are detachably coupled to the unit. 54 (refer to Figs. 2 to 15), and the entire shape has a disk shape. Details of the above-described card assembly 24 will be further described with reference to Figs. 2 to 17. As shown in detail in Fig. 12, the wafer unit 46 will be used as Electricity The plurality of test wafers 56 are disposed on the upper side of the disk-shaped wafer support 58. Each of the test wafers 56 corresponds to a plurality of test objects (integrated circuits). Each test wafer 56 is also cut. The integrated circuit wafer formed on the integrated circuit of the semiconductor wafer is formed to generate an electrical signal for the electrical measurement of each of the objects to be inspected and to receive a response from the corresponding object to be inspected <! 9 201109691 k is processed to perform electrical test of each object to be inspected. The wafer support 58 is provided with a disk-shaped wafer substrate 6 on which a plurality of test wafers 56 are disposed, and a ring extending around the wafer substrate 60. 62. In addition, the ring (4) accommodates the wafer substrate 60 on the upper and lower sides of the wafer substrate 6 in the upper and lower directions, respectively, in the opening 62a of the ring 62 (refer to FIGS. 6 and 12). The wafer substrate 60 is made of glass epoxy. A resin such as a resin or a polyamide, or a multi-screen wiring substrate in which an electrical insulating material such as a laminate is formed into a disk shape, and has a plurality of internal wirings 64 and is connected to the upper surface of the test; The island (not shown) further has a plurality of other connecting islands 66 on the lower side, and further has a plurality of connectors 68 on the upper side. Among the plurality of internal wirings 64, the upper end portions of the plurality of internal wirings 64 are connected to the aforementioned connection islands of the electrodes (four) connected to the electrodes of the test wafer 56, and the upper ends of the remaining plurality of internal wirings 64 are connected to the terminals of the connection H 68. The lower end of each internal wiring 64 is connected to the connection island 66. As shown in Fig. 4, each of the connectors 68 is coupled to another connector 70 that is electrically connected to an external device, such as a computer, or the like. The spear 2 is a plate-shaped ring having an inward flange portion 62b' projecting inward from the upper end portion on the inner side of the upper end, and a positioning hole 62c penetrating in the vertical direction at a plurality of intervals in the circumferential direction. The wafer substrate 60 and the ring 62 are connected to the plurality of fixing screws 76 (see FIG. 9) which are screwed to the wafer substrate 6G from above through the flange portion (four), and can be joined to the ground so that the wafer substrate 60 is pressed against the flange portion. The state of the lower side of 02b and the state of 62 are coaxially extended around the wafer substrate 6〇. A plurality of cam followers 72 are provided at intervals of % 62 around the imaginary axis 94 shown in FIG. The cam follower 72 of the ring 62 extends radially outward from the outer peripheral portion 10 201109691 of the ring 62 and serves as a part of the displacement mechanism 74 (refer to Figs. 2, 3, 4, 14) in the upper engaging device 52. Play a role. As shown in detail in Fig. 12, the probe unit 48 includes a probe holder 78 having a plurality of sub-materials and a disk shape, and a contact member 44 is disposed on the lower side of the probe holder 78. The probe branch (four) 78# is provided with a disc-shaped probe substrate 8A having a plurality of contact arms 44 disposed below, and a loop extending around the probe substrate rib. In addition, the "earth 82" accommodates the probe substrate 8G on the upper and lower sides of the probe substrate 8 (upper and lower) in the opening and closing direction of the ring 82 (refer to FIG. 6: the ririsius pair substrate 80 and the wafer substrate 6) The electric insulating material such as a resin containing a glass epoxy resin or a polyamide, a laminate, or the like has a disk shape having substantially the same diameter as that of the wafer substrate 60, and has a plurality of internal wirings 84 1 on the upper surface. The plurality of connected islands further have a plurality of probe islands 87 below. The sub-44 is described in 曰本特开2_-337_, I::::. 1 13946, 曰本特示__公公端... a seat portion (mounting region) extending in the downward direction, an arm region extending from the front end H or Y direction of the seat portion, and a known needle tip region extending from the end of the arm portion J of the arm region to the lower portion. Each of the contact members 44 is in a state in which the arm region protrudes downward toward the χ region on the upper side, and the direction is extended, and the needle tip is fixed in a cantilever beam shape, and the second and second portions are welded to the appropriate end portion and the lower portion. Connected to ^^ 7° each internal wiring 84 above the ring 82 series and... = τ island 87 The ring having the lower end portion projecting inwardly has a positioning hole 8 2 c penetrating in the vertical direction from the flange portion 82b on the inner side of the lower end and at a plurality of intervals in the circumferential direction 201109691. The probe substrate 80 and the ring 82 are bonded to the wafer substrate 6 and the ring ^=the flange portion is penetrated upward from the bottom _ and is screwed to the probe substrate fixing screw (not shown) to be separably coupled. The needle substrate 8 is extended by the axis. The surface (4) and the tissue probe 80 are the same as the Wangyi 6 2, and the imaginary axis shown in Fig. 4 is applied to δ 1 „ „ 七94 "1 is provided with a plurality of cam followers 72. The ring 82 extends outwardly from the outer circumference of the ring 82 to the outer side of the half and the collar 72, and serves as a part of the displacement mechanism 74 in the lower engagement means 54. As shown in detail in Fig. 12, the speed φ ^ M early 兀 50 has a plurality of connecting pins 8 6 connecting the islands 66 and 85, and RS ^ $ 86 supports the circular pin support of the connecting pin 86. Body 88. The pin support 88 is in the shape of a ring 92. The pin is held: = the temple is 9 inches, the pin is held to keep the ancient A bone, and both are kept. 90 based on those of the joints of the pin 86 through a disk-shaped holding pin 92 in a direction ^ ^ ^ ^ ^ "state mow the support pin 86. The ring 92 is connected to system housed in robbery holder 9〇 opening σ 92a.
銷保持具9 〇及環9 2八I 向下段部，77別於外周緣部具有向上段部及 x p藉由複數固定螺綷r去固-、 段部被相互按壓之狀能二(未圖不)可分離地結合為此等 同轴位置之^ 及環92於銷保持具90之周圍位於 各連接銷86係以導電性 有於厚度方向貫通銷保接罝。製作為細線狀或板狀，具 部…之上部之橫υ字^之G之主部恤一體連接於主 心之下部之橫u字狀之 十尖部86b、一體連接於主部 針尖部嶋之上端部及=叫參照圖12、η)。上 大。I 86c之下端部分別從銷保持 12 201109691 具90往上方及下方突出。 晶片支持體58、探針支持體78及銷支持體88係藉由 結合單元52及54,以往上下方向延伸之假想軸線94(參照 圖4)為共軸同轴地被結合。 如圖12詳細顯示，連接單元5〇係藉由在環％之周緣 部載置於支持基座34之向上段部38之狀態下使複數螺絲 構件95通過環92之貫通孔似螺合於支持基座34而被可 分離地結合於支持基座34。藉此，卡式組裝體以被支持單 元2 〇支持。 如圖12、13詳細顯示，結合單元52及54分別除前述 之複數變位機構74外’還包含配置於晶片支持體Μ或探 針支持體78與銷支持體88之間之止推軸承裝置％、配置 於銷支持體88與止推軸承裝置96之間並從外周側結合於 止推軸承裝置9 6之旋轉環9 8。 止推軸承裝置96具備繞假想軸線94延伸之環狀之轴 承保持具100、繞假想軸線94延伸之環狀之止推軸承、 定位銷104。軸承保持具⑽係配置於晶片支持體58或探 針支持體78與銷支持體88(特別是環92)之間，止推轴承 係配置於旋轉㈣與軸承保持具ι⑼之間，定位鎖刚 :設於軸承保持具⑽±面或下面之周方向隔間隔之複數 處0 #相持具⑽係於環92之上面或下面被安裝為不 二^移動。定位銷]〇4係從各軸承保持具⑽往上方或 =出，收容於定位孔62c或仏。藉此，晶片支持體Μ 衣％、探針支持體78及環92被結合為可於上下方向相The pin holder 9 〇 and the ring 9 2 八 I are the lower section, 77 has the upper section and the xp is fixed by the plurality of fixing screws r, and the segments are pressed against each other (not shown) The coupling pin 86 is detachably coupled to the coaxial position and is located around the pin holder 90 so as to be electrically conductive and penetrate the pin in the thickness direction. It is made into a thin line or a plate shape, and the main part of the G of the upper part of the upper part is connected to the ten-pointed part 86b of the horizontal u-shaped lower part of the center of the main body, and is integrally connected to the main needle tip part. The upper end and the reference are shown in Fig. 12 and η). Up. The lower end of I 86c is respectively protruded from the pin 12 201109691 with 90 upward and downward. The wafer support body 58, the probe holder 78, and the pin holder 88 are coaxially coaxially coupled by the coupling units 52 and 54 in a virtual axis 94 (see Fig. 4) extending in the vertical direction. As shown in detail in Fig. 12, the connecting unit 5 is screwed to the support through the through hole of the ring 92 in a state where the peripheral portion of the ring % is placed on the upper portion 38 of the support base 34. The base 34 is detachably coupled to the support base 34. Thereby, the card assembly is supported by the supported unit 2 〇. As shown in detail in FIGS. 12 and 13, the combining units 52 and 54 respectively include a thrust bearing device disposed between the wafer support body or the probe holder 78 and the pin holder 88 in addition to the above-described plurality of indexing mechanisms 74. %, disposed between the pin support 88 and the thrust bearing device 96 and coupled to the rotating ring 98 of the thrust bearing device 96 from the outer peripheral side. The thrust bearing device 96 includes an annular bearing holder 100 extending around the imaginary axis 94, an annular thrust bearing extending around the imaginary axis 94, and a positioning pin 104. The bearing holder (10) is disposed between the wafer support 58 or the probe support 78 and the pin support 88 (particularly the ring 92), and the thrust bearing is disposed between the rotation (4) and the bearing holder ι (9). : The plurality of 0 #phase holders (10) provided on the bearing holder (10) ± face or the circumferential direction interval are mounted on the upper or lower side of the ring 92 to be moved. The locating pin 〇4 is received from the respective bearing holders (10) upwards or out, and is accommodated in the positioning holes 62c or 仏. Thereby, the wafer support body %, the probe holder 78 and the ring 92 are combined to be vertically movable.
S 13 201109691 對變位、$ 不％繞假想軸線94相對變位。 各車由承保持具1 〇 〇辟由 下方延伸並W 或下面往上方或 ：未圖示之如螺絲構件等適當之手段於環92被 ==移動之短筒狀部、從該筒狀部之上端往外 推轴承1〇2係ΛΥ/字狀或逆W狀之剖面形狀。止 於軸承保持具_之相下側之環狀軌道盤（止推環）安裝 之板環部之下側或上側。 各旋轉環9 8 M -k 部、從該環部之外:缘:部分結合於止推…2之板環 具有L字狀或逆/字狀 方或下方延伸之短筒狀部而 轴承⑽”側或上：::㈣狀，於板環部安裝於止推 轉環98被組裝為 二狀軌:盤(止推環)。藉此，各旋 J 1固早 το 46、48、SfU 夯 μ m , 6)繞於圖4顯示之假想軸線94旋轉。......2、 為了使相對於環9) 之滑動片咖传配置：之旋轉環98之移動較順利，環狀 …/Π ;環92與旋轉環98之間。 之實施例…Ρ(晶片(探針單元48之側)之變位機構 成各變位機構之圆14 之側)之變位機構74具有使構 凸輪槽輪從料72、複數 如圖14、15詳細^ 12等之上下倒置之形狀及構造。 110繞於圖4顯示之假！：’於各變位機構74,複數凸輪槽 收容凸輪從動件72, ：*線94隔間隔形成於旋轉環98以 假想軸線94隔間隔且備驅動機構1丨2係繞於圖4顯示之 假想轴線94變位/，以使旋轉環⑽對銷支持體88繞 各凸輪槽110且古 /、有收容凸輪從動件72之承接口部 14 201109691 U 0a連it於承接σ部丨i Ga並從承接。部m繞假想輪線 94延伸之凸輪部丨1〇b。 承接口部11 〇a係於上方或下方開放，以使從探針支持 體78(或晶片支持豸58)之側(即上方或下方之側)收容對應 之凸輪從動件72。 ^ 凸輪部ii〇b具有對探針支持體78(或晶片支持體叫 傾斜角度Θ以使越從承接口部UQa遠離便越接近晶片支持 體58或探針支持體78(即上方或下方之側）之凸輪面n〇c。 凸輪面1 10c係限制凸輪部i 1〇b之面之中，與銷支持體 88之側相反側之面，且具有往與銷支持體88之側相反之側 凹入之複數凹部。凹部114a、"4bii4c 係於假想軸線94之周圍隔有間隔。 在於圖丨4顯示之例各驅動機構112係使用活塞部藉由 扣環m被連結於旋轉環98且汽缸部藉由扣環"6被連結 於支持基座34之複數汽缸機構。 對此等驅動機構1 12(即汽紅機構）係如壓縮空氣或㈣ 油之壓力流體經壓力流體源12〇、壓力調整_ 122及閥 124同時被供應。壓力流體源12〇、壓力調整機構122及閥 1 24係受於圖4顯示之電腦28控制。 各驅動機構112係在壓力流體對活塞被供給至關於活 塞之-方之汽缸活塞被往伸長方向移動，使旋轉環 % L想軸線94 H向旋轉移動’壓力流體對活塞被 供給至另一方之汽缸室|，活塞被往收縮方向移動，使旋 轉環98往繞假想軸線94之另一方向旋轉移動。 藉此，晶片單元46、探針單元48及連接單元5〇結合 15 201109691 2互相及對轴承保持具100變位，凸輪部⑽ 動件72移動於假想軸線94之周圍。 輪從 上述之結果，晶片單元46或探針單元 接單元50彼此接近遠離之方向（即上下方向）， 於對連 85與連接銷86之間之相對按壓力變化。 66或 藉由旋轉環98甚至凸輪部u〇b對凸輪從動件72如上 述般被旋轉移動’旋轉環98甚至凸輪部_被驅動機構 112維持於凸輪從動件72被收容於凹部U4a.. ll4b、U4c 之-之狀態。藉此，連接島66或85與連接銷％之間之相C 對按壓力被維持於對應於收容有凸輪從動# Η之凹部 114a、1 14b、1 14c 之值。 從晶片單元46或探針單元48至凹部114a、i i 4b、i i 4c 之距離尺寸係依凹部114a、U4b、U4c之順序變小。因此 若凸輪從動件72被收容於凹部U4a，連接島“或85與連 接銷86之間之相對按壓力最小。反之若凸輪從動件u 被收容於凹部1 14c，违姐t G a·· t 4c運接島66或85與連接銷86之間之相 對按壓力最大。 上述之結果’藉由利用結合單元52及54使凸輪從動 件72往/輪# 11G之適當之位置變位，不使連接單元50 對晶片早7L 46及探針單元48旋轉便可變更或調整連接島 66或85與連接銷86之間之相對按壓力。 此外，藉由使凸輪從動件72位於凹部丨丨4a、丨丨处、η乜 其中之一’可防止於測試時連接島66或85與連接銷％之 間之相對按壓力變化。 然而，在凸輪槽110與凸輪從動件72之間之摩擦力、 16 201109691 驅動機構1 1 2之驅動力或維持 寻力較大時、將凸輪從動件72 變更至凸輪槽11〇内之適合 <田之位置並使用維持之其他妒 時等場合，省略凹部1 1 4 a 1 1 /1 u ' ί 叫 u 外 H4a、114b、1 14c 亦可。 J式夺接觸子44之針尖被按壓於被檢查體之對應之 電極，在該狀態下測試信號從各測試晶片56被供給至⑽ 查體’發自各被檢查體之回應信號被輸出至對應之測試晶 片56。各測試晶片56係基於發自對應之被檢查體之回應信 號來判疋該被檢查體中之單元之良否。 如上述，若可變更或調整連接島66及85與連接銷86 之間之相對按壓力，具有如下之優點。 可將連接島66與連接銷86之間之相對按壓力、連接 島85與連接銷86之間之相對按壓力對應於被檢查體之種 類變更或5周整為不同或相同值。此外，可將連接島66及85 與連接銷8 6之間之相對按壓力對應於被檢查體之電極與接 觸子44之間之相對按壓力變更或調整。 其結果’於如積體電路使用微弱電流、微弱電壓之高 頻信號之被檢查體之測試，可將此等接觸部中之接觸抵抗 值設定為最佳之值。 [測試晶片之實施例] 關於測試晶片56，參照圖1 6及1 7進一步說明。 各測試晶片56係分別對應於可以測試晶片56同時測 試之複數被檢查體（積體電路）之1個，包含產生對應之被檢 查體之電氣測試用之測試信號即驅動信號S3並接受發自對 應之被檢查體之回應信號（S4)後處理之複數信號處理電路 1 30、進行對此等信號處理電路1 30及外部之電氣信號之收 17 !1； 201109691 發之收發電路132。 此等電路1 30、1 32係受電腦28控制且從外部裝置26 接受各種資料及電力後作動。各信號處理電路1 30以—對 一之形式被對應於被檢查體，產生對應之被檢查體之電氣 測試用之驅動信號S 3並接受發自對應之被檢查體之回應作 號（S4)後處理。收發電路1 32係測試晶片56内之所有信號 處理電路130共通之電路。 各信號處理電路130具備基於從圖案記憶體156被輸 出且成為測s式Is號之基本之圖案資訊s ]及從定時信號產生 器（TG)148被輸出之定時信號S12來產生脈衝信號S2之格 式器（FMA) 1 34、基於脈衝信號S2產生驅動被檢查體之驅動 信號S3之複數（N)驅動器136、接受來自被檢查體之回應作 號S4並對收發電路132輸出表示被檢查體之中之單元為不 良之不良信號S5之複數（N)比較電路138、產生用於以定電 壓及定電流進行之被檢查體之測試之特殊測試用之特殊測 試信號S6之定電壓及定電流產生電路（PMU) 1 4〇、保護传號 處理電路1 30免受從被檢查體輸入信號處理電路丨3〇之過 電壓之箝位/負載電路142。 驅動器136、比較電路138、之後說明之輸出輸入端子 I/O皆設有與可以各信號處理電路13〇同時測試之被檢查體 之端子數同數（N) ’且對被檢查體之1個單元被對應為一對 一之關係。 共通電路即收發電路132具備產生在測試晶片％使用 之表示基準測試頻率之基準測試頻率信號sl〇之時率產生 器(RG)144、基於從各信號處理電路13〇被輸出之不良信號 18 201109691 S5特定出被檢查體之不良單亓夕也从贴〜^ 个民早7L之失效擷取控制（FCC)146、S 13 201109691 The displacement, $ not around the imaginary axis 94 relative displacement. Each of the vehicles is supported by a holder 1 which extends from below and W or below to the top or: a suitable means such as a screw member (not shown) is looped by the ring 92 == from the cylindrical portion The upper end pushes the cross-sectional shape of the bearing 1〇2 ΛΥ/shaped or inverted W shape. The lower side or the upper side of the plate ring portion to which the annular track disk (thrust ring) on the lower side of the bearing holder is mounted. Each of the rotating rings 9 8 M -k, from the outside of the ring: the edge: a plate ring partially coupled to the thrust ... 2 has an L-shaped or reverse/shaped or short cylindrical portion extending downward and the bearing (10) "Side or upper::: (four) shape, installed in the ring ring portion of the thrust ring 98 is assembled into a two-track: disc (thrust ring). Thereby, each rotation J 1 solid early το 46, 48, SfU夯μ m , 6) rotate around the imaginary axis 94 shown in Fig. 4... 2, in order to make the sliding piece configuration relative to the ring 9): the rotation of the rotating ring 98 is smooth, ring-shaped .../Π; between the ring 92 and the rotating ring 98. The embodiment Ρ (the position of the wafer (the side of the probe unit 48) constituting the side of the circle 14 of each displacement mechanism) has a displacement mechanism 74 The shape and structure of the cam groove wheel from the material 72, the plural number is as shown in Fig. 14, 15 and the like. 110 is turned around the dummy shown in Fig. 4: 'in each of the displacement mechanisms 74, the plurality of cam grooves accommodate the cam from The movable member 72, :* line 94 is formed at intervals between the rotating ring 98 at an imaginary axis 94 and the drive mechanism 1丨2 is displaced around the imaginary axis 94 shown in FIG. 4 to cause the rotating ring (10) to be pinned. Support body 88 around each cam 110 and the old/there is a socket portion 14 for accommodating the cam follower 72. 201109691 U 0a is connected to the ZZ portion 丨i Ga and receives the cam portion 丨1〇b extending from the imaginary wheel line 94. The mouth portion 11A is open above or below so as to accommodate the corresponding cam follower 72 from the side of the probe holder 78 (or the wafer support weir 58) (i.e., the upper or lower side). ^ Cam portion ii 〇b has a cam for the probe support 78 (or the wafer support is called an oblique angle Θ such that the closer it is from the interface portion UQa, the closer it is to the wafer support 58 or the probe support 78 (i.e., the upper or lower side) The surface of the cam surface 1 10c is a surface on the side opposite to the side of the pin support 88 among the faces of the restricting cam portion i 1b, and has a concave side opposite to the side of the pin support 88. The recesses 114a and 4bii4c are spaced apart from each other around the imaginary axis 94. In the example shown in Fig. 4, each of the driving mechanisms 112 is coupled to the rotating ring 98 by the retaining ring m using the piston portion, and the cylinder portion is borrowed. The buckle ring "6 is connected to a plurality of cylinder mechanisms supporting the base 34. These drive mechanisms 1 12 (ie steam The pressure fluid, such as compressed air or (iv) oil, is supplied simultaneously through the pressure fluid source 12, the pressure adjustment _122, and the valve 124. The pressure fluid source 12, the pressure adjustment mechanism 122, and the valve 1 24 are shown in FIG. The computer 28 is controlled. Each of the driving mechanisms 112 is driven by the pressure fluid to the piston to the cylinder of the piston, and the piston is moved in the direction of elongation, so that the rotating ring % L wants the axis 94 H to move in a rotational direction. The piston chamber is supplied to the other side, and the piston is moved in the contracting direction to rotate the rotating ring 98 in the other direction around the imaginary axis 94. Thereby, the wafer unit 46, the probe unit 48, and the connecting unit 5 are coupled to each other and to the bearing holder 100, and the cam portion (10) moves 72 around the imaginary axis 94. From the above result, the wafer unit 46 or the probe unit 50 is moved away from each other (i.e., the up and down direction), and the relative pressing force between the pair 85 and the connecting pin 86 changes. 66 or by the rotating ring 98 or even the cam portion u 〇 b to the cam follower 72 as described above is rotated [the rotating ring 98 or even the cam portion _ driven by the drive mechanism 112 is maintained in the cam follower 72 is received in the recess U4a. The status of ll4b, U4c -. Thereby, the phase C pair pressing force between the connection island 66 or 85 and the joint pin % is maintained at a value corresponding to the recesses 114a, 14b, and 14c in which the cam follower # 收容 is accommodated. The distance dimension from the wafer unit 46 or the probe unit 48 to the recesses 114a, i i 4b, i i 4c becomes smaller in the order of the recesses 114a, U4b, U4c. Therefore, if the cam follower 72 is housed in the recess U4a, the relative pressing force between the connecting island "or 85 and the connecting pin 86 is minimized. Otherwise, if the cam follower u is received in the recess 1 14c, the contraband t G a· • The relative pressing force between the t 4c transport island 66 or 85 and the connecting pin 86 is the largest. The above result 'displaces the cam follower 72 to the appropriate position of the wheel 11 11 by using the combining units 52 and 54. The relative pressing force between the connecting island 66 or 85 and the connecting pin 86 can be changed or adjusted without causing the connecting unit 50 to rotate the wafer 7L 46 and the probe unit 48. Further, by positioning the cam follower 72 in the recess丨丨4a, 丨丨, η乜' can prevent relative pressing force change between the connecting island 66 or 85 and the connecting pin % during the test. However, between the cam groove 110 and the cam follower 72 Friction force, 16 201109691 When the driving force of the driving mechanism 1 1 2 is large or the seek force is large, the cam follower 72 is changed to the position of the field in the cam groove 11 并 and the other 妒 is maintained. Occasionally, the recess 1 1 4 a 1 1 /1 u ' ί is called u outside H4a, 114b, 1 14c The needle tip of the J-type contactor 44 is pressed against the corresponding electrode of the object to be inspected, and in this state, the test signal is supplied from each test wafer 56 to (10) the body's response signal from each object to be inspected is output to the corresponding Test wafer 56. Each test wafer 56 determines the quality of the unit in the object to be inspected based on the response signal from the corresponding object to be inspected. As described above, if the connection islands 66 and 85 and the connection pins can be changed or adjusted The relative pressing force between 86 has the following advantages: The relative pressing force between the connecting island 66 and the connecting pin 86, and the relative pressing force between the connecting island 85 and the connecting pin 86 can be changed corresponding to the type of the object to be inspected. Or different values or the same value for 5 weeks. In addition, the relative pressing force between the connecting islands 66 and 85 and the connecting pin 86 can be changed or adjusted corresponding to the relative pressing force between the electrode of the test object and the contact 44. As a result, the contact resistance value in the contact portion can be set to an optimum value in the case where the integrated circuit uses a low-current, low-voltage high-frequency signal test object. [Example of Test Wafer ] The test wafer 56 is further described with reference to FIGS. 16 and 17. Each of the test wafers 56 corresponds to one of a plurality of test objects (integrated circuits) that can be tested simultaneously for testing the wafer 56, and includes corresponding test objects. The test signal for the electrical test is the drive signal S3 and receives the response signal (S4) sent from the corresponding object to be processed, and the signal processing circuit 1 30 performs the signal processing circuit 1 30 and the external electrical signal. Receiving 17!1; 201109691 Transmitted circuit 132. These circuits 1 30, 1 32 are controlled by computer 28 and are operated after receiving various data and power from external device 26. Each of the signal processing circuits 1 30 is corresponding to the object to be inspected in a one-to-one manner, generates a drive signal S 3 for electrical test of the corresponding object to be inspected, and receives a response number (S4) from the corresponding object to be inspected. Post processing. The transceiver circuit 1 32 is a circuit common to all of the signal processing circuits 130 in the test wafer 56. Each of the signal processing circuits 130 includes a basic pattern information s which is output from the pattern memory 156 and which is a s-type Is number, and a timing signal S12 which is output from the timing signal generator (TG) 148 to generate a pulse signal S2. The formatter (FMA) 1 34 generates a complex (N) driver 136 that drives the driving signal S3 of the object to be inspected based on the pulse signal S2, receives the response number S4 from the object to be inspected, and outputs a representative object indicating the object to be inspected by the transmitting and receiving circuit 132. The unit is a complex (N) comparison circuit 138 of the defective bad signal S5, and a constant voltage and constant current are generated for the special test signal S6 for the special test for testing the test object with constant voltage and constant current. The circuit (PMU) 1 4 〇, the protection mark processing circuit 1 30 is protected from the overvoltage of the input signal processing circuit 被3 from the object to be inspected. The driver 136, the comparison circuit 138, and the output input terminal I/O described later are provided with the same number (N) of the number of terminals of the object to be inspected which can be simultaneously tested by each signal processing circuit 13 and one for the object to be inspected Units are mapped to a one-to-one relationship. The common circuit, that is, the transceiver circuit 132, is provided with a time rate generator (RG) 144 that generates a reference test frequency signal s1 representing a reference test frequency used in the test wafer, and a bad signal 18 based on the output from each signal processing circuit 13 201111691 S5 specifies the unsatisfactory singles of the inspected body, and also from the stickers ~^, the early 7L failure control control (FCC) 146,
基於基準測試頻率作·骑· Q ! Λ I °戒S10及來自電腦28之指令產生對應 於基準測試頻率作·骑^ 。1 0之疋時信號S7之定時信號產生器 (TG)148 &於來自電腦28之指令對圖案記憶體⑼輸出 為了使圖案m 1輪出(讀出)之位址信號之圖案產生器 (PG)150。 外部裝置26 I備對所有測試晶片56 t信號處理電路 1 30及收發電路！ 32供給電力之電力源152、記錄基於從所 有測试晶片56之失效擷取控制（FCC)146被輸出之不良信號 S11特疋不良單;之資料並記錄為可於電腦28讀出之複數 (M)失效記憶體154、記錄有測試器之機能測試用之多數測 試圖案即圖案資訊之圖案記憶體丨56。 電腦2 8係基於被設定於其中之各種資料及程式控制外 部裝置26、各信號處理電路13〇及收發電路132，容許對 應於被檢查體之測試之種類之信號頻率及信號等級之設 疋’對失效榻取控制（FCC) 146輸出從該失效榻取控制 (FCC) 146取得關於不良單元之資料之命令，將此種關於不 良單元之資料置於電腦2 8之内部記憶體並保存。 以下，為了使說明及其理解較容易，假設發自電腦28 之指令包含於圖1 7(D)顯示之波形。因此，被檢查體係被具 有於圖1 7(D)顯示之波形之驅動信號（測試信號）S3驅動。 圖案產生器（PG) 150係基於來自電腦28之指令對圖案 記憶體1 56輸出為了使對應於該指令之圖案資訊s 1輸出之 位址信號S 8。 圖案記憶體156產生對應於從圖案產生器（PG) 150被供 201109691 給之位址信號S8之圖案資訊S1，對各信號處理電路⑽之 格式器134輸出。 時率產生器（RG)144係對測試晶片％内之各電路輸出 表不從電腦28被供仏之俨妹相.右 ^ 、、。唬頻率之產生期間之基準測試頻 ;;二S10。將此種基準測試頻率信號si〇之―例顯示於圖 17(A) 〇 另-方面’定時信號產生器(TG)丨48係產生在該測試晶 使用之做為基本時脈之定時信號s 1 2。 ^格式器⑽A)134係基於圖案及定時信號⑴ 信號S2,對對應之驅動器136輸出。將此種脈 衝仏唬S2之一例顯示於圖！ 7(D)。 對二！動器136係基於脈衝信號S2產生驅動被檢查體之Based on the benchmark test frequency, riding, Q! Λ I ° or S10 and the command from the computer 28 are generated corresponding to the reference test frequency. At 10 o'clock, the timing signal generator (TG) 148 of the signal S7 outputs a pattern generator for the address signal for the pattern m 1 to be rotated (read) from the pattern memory (9) at an instruction from the computer 28. PG) 150. The external device 26 I is equipped with all test chips 56 t signal processing circuit 1 30 and transceiver circuit! 32. The power source 152 for supplying power, recording the bad signal S11 based on the failure fetch control (FCC) 146 outputted from all the test chips 56, and recording the data as a plurality of data that can be read by the computer 28 ( M) The failed memory 154 is recorded with a pattern memory 丨 56 of a plurality of test patterns, that is, pattern information, for the functional test of the tester. The computer 28 controls the external device 26, the signal processing circuit 13A, and the transceiver circuit 132 based on various data and programs set therein, and allows the setting of the signal frequency and the signal level corresponding to the type of the test of the object to be inspected. The Fail Control (FCC) 146 outputs an order for obtaining information about the defective unit from the Invalid Control (FCC) 146, and the information about the defective unit is placed in the internal memory of the computer 28 and stored. Hereinafter, in order to make the explanation and the understanding easier, it is assumed that the command sent from the computer 28 is included in the waveform shown in Fig. 17 (D). Therefore, the system to be inspected is driven by a drive signal (test signal) S3 having a waveform shown in Fig. 17(D). The pattern generator (PG) 150 outputs a address signal S 8 for outputting the pattern information s 1 corresponding to the instruction to the pattern memory 1 56 based on an instruction from the computer 28. The pattern memory 156 generates pattern information S1 corresponding to the address signal S8 supplied from the pattern generator (PG) 150 to 201109691, and outputs to the formatter 134 of each signal processing circuit (10). The time rate generator (RG) 144 is the sister output of the circuit output in the test chip %, which is not supplied from the computer 28. Right ^, . The benchmark test frequency during the generation of the frequency; 2 S10. An example of such a reference test frequency signal si 显示 is shown in FIG. 17(A) 〇 another aspect' timing signal generator (TG) 丨 48 is used to generate a timing signal s used as a basic clock in the test crystal. 1 2. The formatter (10) A) 134 is output to the corresponding driver 136 based on the pattern and timing signal (1) signal S2. An example of such a pulse 仏唬 S2 is shown in the figure! 7 (D). Right two! The actuator 136 generates a driven object to be inspected based on the pulse signal S2.
之驅動信號S3’透過對應之各輸出輸人端子I/O 對應之輸出輸入端子輸出。將此種驅動信號 之。一例顯示於圖17(E)。輸出輸入端子ι/〇係備有與可以 各“號處理電路1 3〇同時測 攸饱置體之早兀數同數 (J\)。 來自被檢查體，特別是+ 之㈣” u &各早X之回應信號S4係在對應 ^ ^ 136不作動時以脈衝信號之形態透過對應之輪出 承入知子I/O輸入各信號處理電路13〇 138接收。 ㈣應之比較電路 =較電路138具備將來自制之單元之⑽信號^ /、側U位準側）之具有基準信號位準之h基準信號咖 t 乂之複數第1類比比較器16〇、將來自對應之單元之回應 W S4與負側（低位準側）之具有基準信號位準之l基準^ 20 201109691 號VOL比較之複數第2類比比較器162、基於第1類比比 較器160及第2類比比較器162之輸出信號輸出關於對應 之單元之不良信號S5之不良信號產生電路164。 各第1類比比較器160係若對應之回應信號S4超過η 基準信號VOH便於每一單元對不良信號產生電路ι64輪出 表示來自對應之單元之Η側之信號為異常，該單元為不良 之異常信號。 各第2類比比較器162係若對應之回應信號S4未達l 基準信號VOL便對不良信號產生電路164輸出表示來自對 應之單元之L側之信號為異常，該單元為不良之異常信號。 各不良信號產生電路164係基於對應之第1類比比較 器160及第2類比比較器162之異常信號輸入，對收發電 路132之失效擷取控制（FCC)146輸出關於對應之單元之不 良#號S5。因此，不良信號S5包含特定被檢查體中之不良 單元與其座標位置之資訊。 在此實施例中，由於以各信號處理電路13〇同時測試 複數（N)單元，故第1類比比較器16〇及第2類比比較器^2 在特定之時機判定來自對應之單元之回應信號S4之良否， 產生上述之表示Η側及L側.之異常之信號。因此，不良俨 號產生電路164係根據表示前述異常之信號從第i類比比 較器160或第2類比比較器162輸入之時機來判定不良單 元與其座標位置。 良信號S5從各信號 ’對外部裝置26輸 失效擷取控制（FCC)146係於每次不 處理電路130被輸出時便判定不良單元 出0 21 201109691 如上述’各信號處理電路1 30係以來自驅動器1 36之 驅動彳έ號S3使對應之被檢查體之各單元驅動，於比較電路 1 38接文對應於各單元之驅動狀態之回應信號S4後判定各 單元之良否。 疋電壓及定電流產生電路（PMU) 140係使用高精度之直 a L號（DC)之為了特殊測試之測試單元，於進行被檢查體 之此種特殊測試之場合，產生高精度之定電壓及定電流之 特殊測<4 4唬S6後對輸出輸入端子j/o輸出，進行被檢查 體之電壓電流測試。定電壓及定電流產生電路（PMU) 140在 輸出電流時測定來自被檢查體之電壓，輸出電壓時測定來 自被檢查體之電流。 箝位/負載電路142係於從被檢查體輸入信號處理電 路1 30之回應仏號S4之電壓位準超過基準值之過電壓之場 合保4在k號處理電@ 13G之回應信㉟S4《輪人之所謂限 高及限低之電路。藉此’信號處理電@ 130受保護免於過 電壓之回應信號S4。 [連接單元之其他實施例] 參…、圖18至23,連接單元17〇之板狀之環172具有與 銷支持體88之環92同樣繞假想軸線％延伸之環部I”、 從環部1 74向環部1 74之曲率车 、 β I曲羊+徑之中心延伸且於環部174 之中心部被互相結合之複數直線部〖76。 m m88具備配置於由環部174及相鄰之直線部 空間180之扇形之呈板狀之複數鎖支持片 178。於各銷主梏^ Λ 合均克持片m於貫通銷支持片178之 複數連接銷86。此箄飿Φ垃y · 〜你将有 此4鈉支持片互相共同形成銷保持具。 22 201109691 於環部1 74之内側及各直線部丨76之兩側部形成有承 載銷支持片178之段部。銷支持片178係以複數螺絲構件（未 圖示）安裝於環部174之前述段部。 利用上述之連接單元170,由於銷支持體172從環部 1 74往假想軸線94延伸且藉由於中心部被互相結合之複數 直線部176而被補強，故即使於高溫測試中探針單元48(特 別是探針基板80)之中央部因熱膨脹而欲往下方或上方變 形，此種熱變形亦受抑制。其結$，防止伴隨熱變形之接 觸子44之針尖位置變化。 [連接銷之其他實施例] 參照圖24,銷支持體19〇係使用跳躍銷做為連接銷 各跳躍銷即各連接銷192具備筒狀構件194、於筒狀構 件194之一端部被配置為可往筒狀構件194之長产方向移 =1銷構件196、於筒狀構件194之另一端部：配置為 可U狀構件m之長度方向移動之第2銷構件198、㈣ 狀構件194内配置於第1銷構 ° „ . ^ ^ t 丹,卞1 及弟2銷構件1 98之 曰並將第1銷構件196及第2銷構件丨98 # & Λ ίο, 鲫構件198彺別端部分別從 ° 之一端部及另—端部突出之方向（即第1 Μ Μ 件196及第2銷構件19 (尸第1鋼構 彈簧2〇〇。 相刀離之方向）彈壓之壓縮線圈 筒狀構件194、第1銷構件196及第2銷構件丨9 縮線圈彈f 200皆係以導電 ：198、壓 ^ % 2 ι〇〇 ^ i作第1銷構件196 及弟2銷構件198係於筒 各連接钝/ y4被保持為不能脫落。 各連接銷192係於筒狀構 被維持為不能脫落。 23 201109691 以電氣絕緣性材 2銷構件1 9 8係 於銷保持具202之上下兩面之各面固定有 料製作之保持片204。第1銷構件ι96及第 分別貫通上側及下側之片構件2〇4。 然而，筒狀構件194係不貫通兩片構件2〇4而使盆上 端及下端抵接於片構件204。藉此，各連接銷Μ係筒狀構 件194被定位於銷保持具2〇2，被防止從銷保持具2〇2之脫 落。 [產業上之可利用性] 於上述各實施例中，各接觸+ 44可為如已記載於日本 特開2〇G8_ 145224號公報般使用金屬細線者、使用具有如於 圖24顯示之形狀及構造之跳躍銷等公知之具有其他構造及 此外’本發明不只如上述以凸輪槽n〇形成凸輪面1丨 之裝置，亦可適用於例如使用於圖15中於旋轉環98之上 面形成為往上方開放之凸輪面之使用其他凸輪面之裝置。 本發明亦可進一步適用於使用如上述之結合單元、 變位機構74、驅動機構} 12以外之結合單元、變位機 驅動機構之裝置。 54 構 二本發明並不受限於上述實施例，只要不脫離記載於申 3月專利範圍之主旨，可為各種變更。 【圖式簡單說明】 圖1係顯示使用本發明之測試晶片之測試裝置之一實 施例之前視圖。 圖2係從斜上方觀察在於圖1顯示之測試裝置使用之 24 201109691 卡 式組裝體及其附近之立體圖。 體圖 圖3係從斜下方觀察卡式組裝體及其附近之立 圖4係卡式組裝體及其附近之縱剖面圖。 圖 圖5係從斜下方觀察卡式組裝體之立體圖。 圖6係分解顯示卡式組裝體之主要構成要素 之縱剖 面 組裝L7:::去“單元之狀態下，上方觀察卡式 圖8係分解顯示在卡式 單元之前視圖。 圖9係從斜上方觀察在卡式 之立體圖。 組裝體使用之連接單元及結合 組裝體使用之晶片支持 體 圖1〇係從斜下方觀察晶片支持體之立體圖。 圖 圖11係除去晶片單元顯示連接單元與其附近之俯視 圖12係將卡式組裝體之結合部及其附近之構件擴大之 圖U係將圖12中 一 中之連接早兀及上下之結合單元與其 附近之構件—起顯示之擴大剖面圖。 :4係將變位機構之-實施例以展開狀態與流體電路 一起顯示之前視圖。 圖1 5係於圖14 ,^ . 顯不之變位機構之按壓力調整部之擴 大刖視圖。 圖1 6係為了說明士 & Θ本發明之測試晶片之一實施例之電路 25 201109691 圖 圖18係顯不連接單元之其他實施例之俯視圖》 係於圖1 8顯示之連接單元之縱剖面圖。 ::〇係除去銷支持片後之狀態之於圖18顯 單兀之俯視圖。 恢 圖21係於圖19顯示之連接單元之縱剖面圖。 圖2 2係顯示在於圖1 8翻一 片之一圖18顯不之連接單元使用之銷支持 片之實轭例之俯視圖。 又将 圖23係於圖22顯示之雜± 4士 u 圓玲 劫支持片之前視圖。 圖係顯示使用其他連接 -部分之縱剖面圖。 角之連接早凡之-實施例之 【主要 元件符號說明】 S1 圖案資訊 S2 脈衝信號 S3 驅動信號 S4 回應信號 S5 不良信號 S6 特殊測試信號 S8 位址信號 S10 基準測試頻率 S12 定時信號 V0H Η基準信號 V0L L基準信號 26 201109691 10 測試裝置 12 形成有多數被檢查體之半導體晶圓 20 支持單元 22 檢查載台 24 卡式組裝體 26 外部裝置 28 電腦 34 支持基座 40 夾頭 42 載台移動機構 44 接觸子 46 晶片單元 48 探針單元 50 ' 170 連接單元 52、54 上下之結合單元 56 測試晶片 58 晶片支持體 66、70 連接器 78 探針支持體 88 銷支持體 94 假想軸線 27The drive signal S3' is output through an output input terminal corresponding to each of the output input terminals I/O. This kind of drive signal will be used. An example is shown in Fig. 17(E). The output input terminal ι/〇 is equipped with the same number of early turns (J\) that can be used to measure the full body at the same time. From the object to be inspected, especially + (4) u & Each of the early X response signals S4 is received in the form of a pulse signal in the form of a pulse signal through the corresponding wheel I/O input I/O input signal processing circuits 13 〇 138 when the corresponding ^ ^ 136 is not activated. (4) The comparison circuit = the comparison circuit 138 has the (10) signal ^ /, side U level side of the unit that is to be self-made in the future, and the reference signal level has the reference signal level, the reference signal level, the first analogy, the comparator 16 The second type analog comparator 162, the first analog comparator 160, and the second analog comparator 162, which are compared with the VOL of the corresponding unit, having the reference signal level, the reference signal level from the corresponding unit W S4 and the negative side (low level side) The output signal of the analog comparator 162 outputs a bad signal generating circuit 164 for the defective signal S5 of the corresponding unit. Each of the first type comparators 160 is such that the corresponding response signal S4 exceeds the η reference signal VOH, so that each unit sends a signal indicating that the signal from the side of the corresponding unit is abnormal to the bad signal generating circuit ι64, and the unit is a bad abnormality. signal. Each of the second analog comparators 162 outputs a signal indicating that the signal from the L side of the corresponding unit is abnormal and the unit is a defective abnormal signal if the corresponding response signal S4 does not reach the reference signal VOL. Each of the defective signal generating circuits 164 is based on the abnormal signal input of the corresponding first analog comparator 160 and the second analog comparator 162, and the fail control (FCC) 146 of the transmitting and receiving circuit 132 outputs the defective ## of the corresponding unit. S5. Therefore, the bad signal S5 contains information on the defective unit and its coordinate position in a specific object to be inspected. In this embodiment, since the complex (N) cells are simultaneously tested by the respective signal processing circuits 13, the first analog comparator 16 and the second analog comparator 2 determine the response signal from the corresponding cell at a specific timing. Whether the S4 is good or not, the above-mentioned signal indicating the abnormality of the side and the L side is generated. Therefore, the defective number generating circuit 164 determines the defective unit and its coordinate position based on the timing at which the signal indicating the abnormality is input from the i-th analog comparator 160 or the second analog comparator 162. The good signal S5 is determined from the respective signals 'transmission failure control (FCC) 146 to the external device 26, and each time the non-processing circuit 130 is outputted, it is determined that the defective unit is out 0 21 201109691 as described above, 'each signal processing circuit 1 30 The driving signal S3 from the driver 136 drives the respective units of the corresponding object to be inspected, and determines whether the units are good or not after the comparison circuit 138 receives the response signal S4 corresponding to the driving state of each unit.疋Voltage and constant current generation circuit (PMU) The 140 series uses a high-precision straight a L (DC) test unit for special tests to generate a high-precision constant voltage for the special test of the object to be inspected. And the special measurement of the constant current < 4 4 唬 S6 output to the output input terminal j / o, the voltage and current test of the object to be inspected. The constant voltage and constant current generating circuit (PMU) 140 measures the voltage from the object to be inspected when the current is output, and measures the current from the object to be inspected when the voltage is output. The clamp/load circuit 142 is connected to the over-voltage of the voltage level of the response signal S10 from the object to be inspected, and the voltage level of the response signal S10 exceeds the reference value. The so-called high limit and low limit circuit. Thereby, the signal processing power @130 is protected from the overvoltage response signal S4. [Other Embodiments of Connection Units] Referring to Figs. 18 to 23, the plate-like ring 172 of the connection unit 17 has a ring portion I" extending from the imaginary axis % like the ring 92 of the pin support 88, and the ring portion 1 74 is a plurality of linear portions extending to the center of the curvature of the ring portion 1 74 and the center of the β-curved sheep + the radial portion and joined to each other at the center portion of the ring portion 174. The m m88 is disposed in the ring portion 174 and adjacent thereto. The plurality of lock support pieces 178 having a fan shape in a sector shape of the linear portion space 180. The plurality of connection pins 86 of the penetrating pin supporting pieces 178 are respectively held by the pin main bodies 。. ~ You will have the 4 sodium support sheets together to form the pin holders. 22 201109691 A portion of the inner side of each of the ring portions 1 74 and the respective straight portions 76 is formed with a portion supporting the pin support piece 178. The pin support piece 178 A plurality of screw members (not shown) are attached to the aforementioned portion of the ring portion 174. With the above-described connecting unit 170, since the pin support 172 extends from the ring portion 1 74 toward the imaginary axis 94 and is joined to each other by the center portion The plurality of linear portions 176 are reinforced, so even in the high temperature test probe unit 48 (special The central portion of the probe substrate 80) is deformed downward or upward due to thermal expansion, and such thermal deformation is also suppressed. The knot is prevented from changing the position of the tip of the contact 44 with thermal deformation. [Other implementation of the connecting pin For example, referring to Fig. 24, the pin support 19 is a jump pin, and each of the jump pins 224 has a tubular member 194, and one end of the tubular member 194 is disposed as a cylindrical member 194. The long-term direction shift = pin member 196, the other end portion of the tubular member 194: the second pin member 198 that is disposed to be movable in the longitudinal direction of the U-shaped member m, and the (four) member 194 that is disposed in the first pin structure ° „ . ^ ^ t 丹, 卞 1 and 2 pin members 1 98 and the first pin member 196 and the second pin member 丨 98 # & Λ ίο, 鲫 member 198 screening end from ° ° a compression coil cylindrical member 194 which is biased in a direction in which one end portion and the other end portion protrude (i.e., the first Μ 196 196 and the second pin member 19 (the first steel splicing spring 2 〇〇. the phase cutter is away from the direction) The first pin member 196 and the second pin member 丨9 are both crimped and f 200 are electrically conductive: 198, pressing ^ 2 2 ι〇〇 ^ i as the first The pin member 196 and the pin member 198 are held in the tube blunt/y4 so as not to fall off. Each of the connecting pins 192 is maintained in a tubular configuration so as not to fall off. 23 201109691 Electrically insulating material 2 pin member 1 9 8 is a holding piece 204 which is fixed to each of the upper and lower surfaces of the pin holder 202. The first pin member ι96 and the sheet member 2〇4 which penetrate the upper side and the lower side, respectively. However, the tubular member 194 does not penetrate the two members 2〇4 so that the upper end and the lower end of the bowl abut against the sheet member 204. Thereby, each of the connecting pin-and-cylinder-shaped tubular members 194 is positioned at the pin holder 2〇2 to be prevented from falling off from the pin holder 2〇2. [Industrial Applicability] In each of the above embodiments, each of the contacts + 44 may be a metal thin wire as described in Japanese Patent Laid-Open Publication No. H8-145224, and has a shape as shown in FIG. The structure of the jump pin or the like is known to have other structures and the present invention is not limited to the above-described apparatus for forming the cam surface 1 凸轮 by the cam groove n ,, and may be applied to, for example, the upper surface of the rotating ring 98 as shown in FIG. The cam surface on the top is open to the other cam surface. The present invention is also applicable to a device using the combination unit, the displacement mechanism 74, the combination unit other than the drive mechanism, and the positioner drive mechanism as described above. The invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a front view showing an embodiment of a test apparatus using a test wafer of the present invention. Fig. 2 is a perspective view of the 24 201109691 card assembly used in the test apparatus shown in Fig. 1 as viewed obliquely from above. Figure 3 is a longitudinal sectional view of the card assembly and its vicinity, as viewed from obliquely below, and the vicinity of the card assembly. Figure 5 is a perspective view of the card assembly viewed obliquely from below. Fig. 6 is an exploded perspective view showing the main components of the main assembly of the card type assembly L7::: "In the state of the unit, the upper observation card is shown in the front view of the card unit. Fig. 9 is from the oblique upper side. A perspective view of the card type is used. The connection unit used in the assembly and the wafer support used in the assembly are shown in Fig. 1. The perspective view of the wafer support is viewed obliquely from below. Fig. 11 is a plan view showing the connection unit and the vicinity of the wafer unit. Fig. 12 is an enlarged cross-sectional view showing the joint of the card assembly and the members in the vicinity thereof. The system is an enlarged sectional view showing the connection of the early and upper joints of the first and second members in Fig. 12 together with the members in the vicinity. The embodiment of the displacement mechanism is shown in an unfolded state together with the fluid circuit. Figure 1-5 is an enlarged view of the pressing force adjustment portion of the displacement mechanism shown in Fig. 14. Fig. Illustrator & 电路 Circuit 25 of one embodiment of the test wafer of the present invention 201109691 FIG. 18 is a top view of another embodiment of the unconnected unit. Fig. 2 is a top view of the connecting unit shown in Fig. 18. Fig. 2 is a vertical sectional view of the connecting unit shown in Fig. 19. Fig. 2 shows the Fig. Figure 18 shows a top view of the yoke example of the pin support piece used in the connection unit. Figure 23 is also attached to the front view of the miscellaneous ± 4 士 u round robber support piece shown in Figure 22. Longitudinal section of the connection-section. The connection of the corners is as early as possible - the main component symbol description S1 pattern information S2 pulse signal S3 drive signal S4 response signal S5 bad signal S6 special test signal S8 address signal S10 benchmark test Frequency S12 Timing signal V0H Η Reference signal V0L L Reference signal 26 201109691 10 Test device 12 Semiconductor wafer 20 with a large number of objects to be inspected Support unit 22 Inspection stage 24 Cartridge assembly 26 External device 28 Computer 34 Support base 40 Chuck 42 Stage moving mechanism 44 Contact sub 46 Wafer unit 48 Probe unit 50 ' 170 Connection unit 52, 54 Upper and lower joint unit 56 Wafer support 66, 70 of the wafer 58 an imaginary axis 94 probe connector 78 pin 88 support 27 support