201108370 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種覆晶封裝結構及其對位方法，尤係關於一 種利用對位焊墊及對位凸塊之覆晶封裝結構及其對位方法。 【先前技術】 隨著對電子裝置輕、薄、短、小的要求，以及多功能性與速度的 要求，使得晶片的封裝結構也日趨複雜與縮小。有鑑於此，傳統的打 線接合封裝技術對於要求高1/0數、速度快、體積小之電子產品來說 • 已經不敷使用’因此，近年來對於晶片的封裝大多採取具有高I/O數、 速度快、體積小等優點的覆晶封裝技術，以符合現今對電子裝置的要 求。 一般而言’覆晶封裝需先在晶片上形成導電凸塊，再利用自動化 的選取與安放裝置將覆晶晶片精確地放置於基板上預先設定與其接合 的位置以利進行覆晶接合，最後，經一焊接製程，使導電凸塊形成一 連接而電性連接與固定晶片與基板而完成覆晶接合與封裝。 _晶片凸塊製程目前可主要分為兩種類別：第一是使用表面黏著技 術（Surface Mount Technology，SMT)的貼片機(mounter)，其優點為機 成本較低，鼓生產速度較快，通常可大於每小時聊0片‘社。然 而其缺點為可容許的誤差為大約為5〇微米，因此無法運用於具細密節 距之覆晶製程。而第二，則是使用覆晶機(flip ehipbQnder)設備，其精 度為大2 '。微^，以運用於具細密節距之置件製程，然而，覆晶機的 成本通吊*較昂貝，並且生產速度約為每小時【，咖片因此產量較低。 舉例而5，如圖1a及1b所示，晶片2上複數個導電凸塊21及基 板丄上之複數個焊塾11之節距為50微米，而烊墊11及導電凸塊21 m微米’當置放誤差值3大於1/2寬度=12 5微糊如㈣ 入.焊接劑的表面張力無法將導電凸塊21拉回焊墊中央，因此 201108370 ㈣情形’進而造錢障，在精 差值⑷、於12·5微米，因此無法使用精度大約為= 微米之表面㈣技術貼賴，㉞須制較 可達10微米的覆晶機。 虿罕-1褙厪為201108370 VI. Description of the Invention: [Technical Field] The present invention relates to a flip chip package structure and a aligning method thereof, and more particularly to a flip chip package structure using a para-position pad and a para-bump and a pair thereof Bit method. [Prior Art] With the requirements for light, thin, short, and small electronic devices, as well as the versatility and speed requirements, the package structure of the wafer has become increasingly complicated and reduced. In view of this, the traditional wire bonding technology is inconvenient for electronic products requiring high speeds of 1/0, high speed, and small size. Therefore, in recent years, most of the packages for wafers have adopted high I/O numbers. The flip chip packaging technology with the advantages of high speed and small size meets the requirements of today's electronic devices. In general, 'the flip chip package needs to form conductive bumps on the wafer first, and then the flip chip is accurately placed on the substrate by an automatic selection and placement device to pre-set the bonding position to facilitate the flip chip bonding. Finally, Through a soldering process, the conductive bumps form a connection and electrically connect and fix the wafer and the substrate to complete the flip chip bonding and packaging. The wafer bump process can be divided into two main categories at present: the first is a mounter using Surface Mount Technology (SMT), which has the advantages of lower machine cost and faster drum production speed. Usually it can be more than 0 tablets per hour. However, the disadvantage is that the allowable error is about 5 μm, so it cannot be applied to the flip chip process with fine pitch. The second is the use of a flip-chip machine (flip ehipbQnder) with a precision of 2'. Micro-^, used for the process of placing parts with fine pitch, however, the cost of the flip-chip machine is higher than that of the Angbei, and the production speed is about hourly. For example, as shown in FIG. 1a and FIG. 1b, the plurality of conductive bumps 21 on the wafer 2 and the plurality of solder bumps 11 on the substrate have a pitch of 50 micrometers, and the germanium pads 11 and the conductive bumps are 21 micrometers. When the placement error value 3 is greater than 1/2 width = 12 5 micro paste as (four) into. The surface tension of the solder can not pull the conductive bump 21 back to the center of the pad, so 201108370 (four) situation 'and then make money barrier, in the fine The value (4) is at 12. 5 microns, so it is impossible to use a surface with an accuracy of about = micron. (4) Technically, 34 is required to make a flip chip machine up to 10 microns.虿罕-1褙厪
Α此外t顯le，晶片2與基板丨之間可能會梭轉位移之誤差， 虽晶片2與基板丨之間具有旋轉位移_而言，旋㈣度㊀大於或等 於0.2度)時，會造成焊㈣與導電凸塊21無法對位，並使得焊塾^ 與導電凸塊21之間的表面張力無法將焊塾丨丨與導電凸塊^拉回正確 位置，也就是無法正確對位，因此造成故障。 綜合上述，如何運用表面點著技術於具細密節距之覆晶製程之 ^以降低機器成本並達成較向產量是目前所需解決的問題。 本發明之目的之一為提供一種覆晶封裝結構及其對位方法以 容許較大的置放誤差值5，並進而達成較低的生產成本及更高的生產 速度及良率。 依據本發明之-實施例，-種覆晶封裝結構，包括—基板及一晶 片。基板具有複數個導電焊墊與複數個對位焊墊設置於基板上。晶片 具有複數個導電凸塊與複數個對位凸塊設置於晶片之主動面上。導電 焊塾與對位係分職應連接導電凸塊與對位凸塊設置。每-對位 凸塊截面之尺寸形狀與每一對位焊墊相同。對位焊墊之面積總合大於 導電焊墊之面積總合，而每一對位焊墊之尺寸大於每一導電焊墊之尺 寸，以藉由加強對位焊墊與對位凸塊之間之表面張力，達成回焊時之 自我對位作用。 本發明之另一實施例’一種依據上述覆晶封裝結構的覆晶封裝 之對位方法，係包含下列步驟：提供晶片；設置一焊接劑於晶片 之導電凸塊與對位凸塊上；提供基板；將晶片對位設置於基板上，使 導電焊塾與對位焊墊係分別對應連接導電凸塊與對位凸塊；以及進行 201108370 -回谭步觀糊對位凸塊與對鱗制吸引力校正對位偏移。 【實施方式】ΑIn addition, there may be an error in the shuttle displacement between the wafer 2 and the substrate ,. Although the rotational displacement between the wafer 2 and the substrate _, the degree of rotation (four degrees is greater than or equal to 0.2 degrees), The solder (4) and the conductive bump 21 cannot be aligned, and the surface tension between the solder bump and the conductive bump 21 cannot pull the solder bump and the conductive bump back to the correct position, that is, the alignment cannot be correctly performed. Caused a malfunction. In summary, how to use the surface-based technology to reduce the machine cost and achieve a higher yield is a problem that needs to be solved at present. One of the objects of the present invention is to provide a flip chip package structure and its alignment method to allow for a large placement error value of 5, and thereby achieve lower production costs and higher production speeds and yields. According to an embodiment of the present invention, a flip chip package structure includes a substrate and a wafer. The substrate has a plurality of conductive pads and a plurality of alignment pads disposed on the substrate. The wafer has a plurality of conductive bumps and a plurality of alignment bumps disposed on the active surface of the wafer. The conductive pad and the alignment system should be connected to the conductive bump and the alignment bump. The cross-sectional shape of each-paragraph bump is the same as that of each pair of pads. The total area of the alignment pads is larger than the area of the conductive pads, and the size of each of the pads is larger than the size of each of the conductive pads to enhance the between the alignment pads and the alignment bumps. The surface tension reaches the self-alignment effect during reflow. Another embodiment of the present invention is a method for aligning a flip chip package according to the above flip chip package structure, comprising the steps of: providing a wafer; and disposing a solder on the conductive bumps and the alignment bumps of the wafer; Substrate; aligning the wafer on the substrate, respectively connecting the conductive pad and the alignment pad to the conductive bump and the alignment bump; and performing 201108370 - returning to the Tan step to observe the alignment bump and the scale attraction Correct the registration offset. [Embodiment]
如圖2a所示，本發明之覆晶封裝結構包括基板3及晶片4。基板 3具有複數個導電焊墊31與複數個對位焊墊32設置於基板3上。晶 片4具有複數個導電凸塊41與複數個對位凸塊42設置於晶片4之= 動面上。導電焊塾31與對位焊塾32係分別對應連接導電凸塊4】與對 位凸塊42設置。每-對位凸塊42截面之尺寸形狀與每—對位焊塾^ 相同。對位㈣32之面積總合大於導電料之面積總合，而每一 ^位焊塾32之尺寸大於每一導電焊墊31之尺寸，以藉由加強對位焊 32與對位&塊42之間之表面張力，達成回焊時之自我對位作用， 並容許較大的置放誤差值占。 +私π j〜用立凸塊42與對位焊墊32間的^ 面張力校正導電谭墊31及導電凸塊4丨之對位偏移，其對位方法拉 设置-焊接劑5於；4之導f凸塊41與對位凸塊&上，其中焊去 =5可使用於晶片4之導電凸塊41與對位凸塊42上、及/或基板3 ^ 導電塾31與對位焊塾32。將晶片情位設置於基板3上，使導灣 焊墊31與對位焊塾32係分別對應連接導電凸塊41與對位凸塊幻， 以便在進彳頂焊轉之過程巾，湘對位凸塊π與對位焊塾 弓丨力校正對位偏移。 、在此更加詳述本發明達成校正對位偏移之方法。如前所述，置教 誤，值5之計算方式為1/2焊墊寬度。因為每一對位焊墊&之尺寸大 ^每-導電焊墊31之尺寸，因此對位_32之置放誤差值會大於 飞焊墊31的置放誤差值’由於對位焊塾32之面積總合大於導電焊塾 之面積總合，因此焊接劑5在對位焊墊32與對位凸塊似之間的 :張力會大於焊鋪5在導電料31與導電凸塊41之間的表面張 乃，因此在焊接劑5固化時，可將導電焊墊W拉回正確位置 助導電焊塾31的正猶位。換句話說，當對位焊塾32之置放^ 小於1/2對位焊塾32寬度時為正確置放，因此導電料3ι部分的置 201108370 放誤f值5可因為對位焊塾32與對位凸塊42之存在與作用而可忽 略，藉此可以增加置放誤差值(5之容忍度。 舉例而1·，導電焊塾31寬度為2s微米因此在先前技術(如圖 )中置放誤差值占為12.5微米，因此無法適用於表面黏著技術貼 機。，在本發明之實施例中，對位焊墊32寬度舉例而言為120微来， 對位焊墊32的置放誤差值6為位焊独寬度的1/2，也就是⑼微米， 經由前述機制可藉由對位焊塾32的表面張力將導電焊塾Μ拉回正確 f置，因此可忽略導電« Μ部分的置放誤差偏。因此在本發明 《對位焊备32部分的置放誤差值6為6〇微米，故可運用於精度大 為50微米之表轉著技術貼片機，藉以達到降低生產成本及增加生 產速度之目的。 •在較佳實施例之中，對位焊塾32為對稱設置於基板3上，以使 對位焊墊32麵位凸塊42之f摘表面張力均勻以增加對位偏移之校 21。每_對位 32之尺柯視生產之機台及所需大小等參數進 其t，在—貫施例中，每一對位焊墊32之尺寸係大於每一導 。4墊31之尺寸之兩倍以上以達到較佳之對位偏移之校正效果。 取b ά如甘圖所不’在—實施例中，基板3之對位焊墊32之形狀為L 3之一x轴與一 γ轴方向設置，而晶片4之對位凸塊42 /、，知墊32為相對設置，藉以減少在X軸及γ軸部分之置放誤差。 狀日2 3所示，在一實施例中，基板3之對位焊墊32之形狀為條 月土板3之一 X轴與_γ轴方向設置，而晶片4之對位凸塊幻 ”對位焊1*32為相對設置，藉以減少在χ^γ細分之置放誤差。 對位焊塾32在紐3上位置並不錄，如圖4所示，對位焊塾 位於基板3中央，而晶片4之對位凸塊42與對位焊塾Μ為相 對设置。 對位轉32及對位凸塊42之材f絲何用以製備導電凸塊的合 適金屬’例如但不限於銅、錯、錫、金、銀、或其合金等。 此外，本發明亦可用以校正晶片與基板之間的旋轉位移。如圖 5a所不’在1關中’對位· &麟位凸塊為條狀且傾斜設置， 此如圖5b所示’ s s曰片4與基板3之間具有較大的旋轉角度(舉例 201108370 而言’旋轉角度Θ大約等於2度)時，在對位焊墊η存在之下，焊接 =對位轉32麟位凸塊42之_表祕力會大於焊接劑在導電 31與導電凸塊41之間的表面張力，藉此可將晶片4與基板3拉 回正確位置以藉此達餅電焊墊31與導電凸塊41之_正確對位， 以達更高的產品良率。 曰在—實施例中，對位焊墊32較佳者為45度傾斜設置，以使對位 焊墊32與對位凸塊42之間的表面張力均扣增加對位偏移之校正效 果。 當完成對位偏移校正之後，此覆晶封裝結構可進行後續製程，舉 例而言，包括烘烤、封膠、固化等製程，以完成封裝程序。 綜合上述’本發明藉由在基板設置對位焊墊以及在晶片之主動面 s又置對位凸塊，以使焊接劑在對位焊墊與對位凸塊之間的表面張力會 大於焊接劑在導電焊墊與導電凸塊之間的表面張力，藉此可將導電凸 塊拉回正確位置以幫助導電焊墊與導電凸塊的對位，因此可以接受較 面的置放誤差值’並進而達成較低的生產成本及更高的生產速度及良 率。 以上所述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内容 並據以實施，當不能以之限定本發明之專利範圍，即大凡依 本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本 發明之專利範圍内。 201108370 【圖式簡單說明】 圖la為一不意圖說明先前技術之覆晶封晶結構。 圖lb為一示意圖說明先前技術之覆晶封晶結構。 圖lc為一剖面圖說明先前技術之覆晶封晶結構。 圖2a為一示意圖說明本發明一實施例之覆晶封晶結構。 圖2b為一剖面圖說明本發明一實施例之覆晶封晶結構。 圖3為一示意圖說明本發明一實施例之覆晶封晶結構。 • 圖4為一示意圖說明本發明一實施例之覆晶封晶結構。 圖5a為一示意圖說明本發明一實施例之覆晶封晶結構。 圖5b為一示意圖說明本發明一實施例之覆晶封晶結構。 【主要元件符號說明】 1 基板 11 焊墊 2 晶片 21 導電凸塊 3 基板 31 導電焊墊 32 對位焊墊 4 晶片 41 導電凸塊 201108370 42 對位凸塊 5 焊接劑As shown in FIG. 2a, the flip chip package structure of the present invention comprises a substrate 3 and a wafer 4. The substrate 3 has a plurality of conductive pads 31 and a plurality of alignment pads 32 disposed on the substrate 3. The wafer 4 has a plurality of conductive bumps 41 and a plurality of alignment bumps 42 disposed on the moving surface of the wafer 4. The conductive pad 31 and the alignment pad 32 are respectively connected to the conductive bump 4 and the alignment bump 42. The cross-sectional shape of each of the para-bumps 42 is the same as that of the per-parallel soldering pad ^. The total area of the alignment (four) 32 is greater than the total area of the conductive material, and the size of each of the solder pads 32 is larger than the size of each of the conductive pads 31 to enhance the alignment welding 32 and the alignment & The surface tension between them achieves the self-alignment effect during reflow and allows for a large placement error value. + private π j~ with the surface tension between the vertical bump 42 and the alignment pad 32 to correct the alignment offset of the conductive pad 31 and the conductive bump 4 ,, the alignment method pulls the setting - solder 5; 4 leads f bumps 41 and alignment bumps &, wherein soldering = 5 can be used for the conductive bumps 41 and the alignment bumps 42 of the wafer 4, and / or the substrate 3 ^ conductive 塾 31 and Solder 32. The wafer condition is set on the substrate 3, so that the guide bay pad 31 and the alignment pad 32 are respectively connected to the conductive bump 41 and the alignment bump, so as to be in the process of welding into the dome, Xiang Xiang The bit bump π and the para-weld bow force correct the alignment offset. The method of the present invention to achieve a corrected alignment offset is described in more detail herein. As mentioned earlier, the teach-in error, the value 5 is calculated as 1/2 pad width. Since the size of each of the pair of pads is larger than that of the conductive pads 31, the placement error value of the alignment_32 is greater than the placement error value of the flying pad 31 due to the alignment pad 32 The sum of the areas is larger than the total area of the conductive pads, so the solder 5 is between the alignment pad 32 and the alignment bumps: the tension is greater than the solder 5 between the conductive material 31 and the conductive bumps 41 The surface is stretched, so that when the solder 5 is cured, the conductive pad W can be pulled back to the correct position to assist the positive solder tab 31. In other words, when the placement of the matching pad 32 is less than the width of the 1/2-parallel pad 32, the placement of the conductive material 3i portion is 201108370. The f value of 5 is due to the alignment of the bonding pad 32. The presence and effect of the alignment bump 42 can be neglected, thereby increasing the tolerance of the placement error (5 tolerance. For example, the width of the conductive pad 31 is 2 s micrometers, so in the prior art (pictured) The placement error value is 12.5 micrometers, so it cannot be applied to the surface adhesion technology. In the embodiment of the present invention, the width of the alignment pad 32 is, for example, 120 micrometers, and the alignment pad 32 is placed. The error value 6 is 1/2 of the width of the tack weld, that is, (9) micrometer. Through the foregoing mechanism, the conductive weld can be pulled back to the correct f by the surface tension of the butt weld 32, so that the conductive « Μ portion can be ignored. The placement error is biased. Therefore, in the present invention, the placement error value of the matching portion 32 is 6 〇 micron, so it can be applied to a precision-mounted 50 micron-spinning technology placement machine, thereby reducing production. Cost and purpose of increasing production speed. • In the preferred embodiment, the alignment pad 32 is It is disposed on the substrate 3 so that the surface tension of the surface of the alignment pad 32 of the alignment pad 32 is uniform to increase the alignment offset 21. Each _ alignment is 32 feet of the Keshi production machine and the required The size and other parameters are entered into t. In the embodiment, the size of each of the pair of pads 32 is greater than twice the size of each of the pads 4 to achieve a better alignment offset correction effect. For example, the shape of the alignment pad 32 of the substrate 3 is one of the L 3 and the γ axis direction, and the alignment bump 42 of the wafer 4 is. The mats 32 are disposed oppositely to reduce the placement errors in the X-axis and the γ-axis portions. As shown in FIG. 23, in one embodiment, the shape of the alignment pads 32 of the substrate 3 is a moon-shaped earth plate. 3 One of the X-axis and the _γ-axis direction is set, and the alignment bump of the wafer 4 is symmetrical, and the alignment welding 1*32 is set relative to reduce the placement error in the χ^γ subdivision. The position on the button 3 is not recorded. As shown in Fig. 4, the alignment pad is located in the center of the substrate 3, and the alignment bump 42 of the wafer 4 is opposite to the alignment pad. The alignment 32 and the alignment convex Block 42 The appropriate metal used to prepare the conductive bumps is, for example, but not limited to, copper, erbium, tin, gold, silver, alloys thereof, etc. Further, the present invention can also be used to correct the rotational displacement between the wafer and the substrate. Figure 5a does not 'in 1 off' alignment and & ridge bumps are strip-shaped and slanted, as shown in Figure 5b 'ss 曰 曰 4 and the substrate 3 have a larger rotation angle (for example 201108370 When the 'rotation angle Θ is approximately equal to 2 degrees'), in the presence of the alignment pad η, the welding=parallel to 32-bit bump 42 will be greater than the soldering agent in the conductive 31 and the conductive bump. The surface tension between 41 can thereby pull the wafer 4 and the substrate 3 back to the correct position to thereby achieve the correct alignment of the cake pads 31 with the conductive bumps 41 for higher product yield. In the embodiment, the alignment pad 32 is preferably disposed at a 45 degree tilt so that the surface tension between the alignment pad 32 and the alignment bump 42 is increased to increase the alignment offset correction effect. After the alignment offset correction is completed, the flip chip package structure can be subjected to subsequent processes, including, for example, baking, encapsulation, curing, etc., to complete the packaging process. In combination with the above, the present invention provides a surface tension between the alignment pad and the alignment bump by soldering the alignment pad on the substrate and the alignment bump on the active surface of the wafer. The surface tension between the conductive pad and the conductive bumps, whereby the conductive bumps can be pulled back to the correct position to help the conductive pads and the conductive bumps align, so that a relatively flat placement error value can be accepted. And then achieve lower production costs and higher production speed and yield. The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention. 201108370 [Simple Description of the Drawings] Figure la is a flip-chip crystal sealing structure which is not intended to illustrate the prior art. Figure lb is a schematic diagram illustrating a prior art flip chip sealing structure. Figure lc is a cross-sectional view illustrating a prior art flip chip crystal sealing structure. 2a is a schematic view showing a flip chip crystal sealing structure according to an embodiment of the present invention. Fig. 2b is a cross-sectional view showing a flip chip crystal sealing structure according to an embodiment of the present invention. 3 is a schematic view showing a flip chip crystal sealing structure according to an embodiment of the present invention. Figure 4 is a schematic view showing a flip chip crystal sealing structure according to an embodiment of the present invention. Fig. 5a is a schematic view showing a flip chip crystal sealing structure according to an embodiment of the present invention. Fig. 5b is a schematic view showing a flip chip crystal sealing structure according to an embodiment of the present invention. [Main component symbol description] 1 substrate 11 pad 2 wafer 21 conductive bump 3 substrate 31 conductive pad 32 alignment pad 4 wafer 41 conductive bump 201108370 42 alignment bump 5 solder