201107228 六、發明說明： 【發明所屬之技術領域^ 本揭不内容是有關於_種半導體結構與製造方 特別是有關於一種用以製造微機電之結構及方法。且 【先前技術】 微機電系統包含各種不同之微結構，將不同之 φ與相關之電路整合連接，並利用不同之加工技術，即可^ 成不同之應用。例如，將微結構與互補型金氧半電晶 路結合，再利用濕式蝕刻使微結構形成懸浮式結構，a可應 用於感測晶片。然而，在微結構的形成過程中，容易有微 結構中金屬層被掏空與氧化物殘留之問題。 如第1圖所示，其繪示微結構與電路之剖面圖。其中 微結構110兩旁具有由金屬層122與各層導孔層124交替 堆疊形成之蝕刻道120。然而由於導孔層124違反一般晶 φ 圓廠的寬度設計原則，而將導孔層124設計為將整層鋪 滿。因此於一開始沉積導孔層124時，沉積材料容易只沉 積在通道侧邊，形成中央凹陷之通道層，而無法如預期把 整個通道填滿，導致沉積出表面不平整之通道層。由於一 開始之沉積製程所沉積出的導孔層表面就已不平整’導致 後續所有製程皆受不平整之影響，使得各層金屬層122與 各層導孔層124皆具有不平整之表面，甚至使蝕刻道120 與微結構110接觸之表面不平整。因此在製造懸浮之微結 構的過程中，容易產生氧化矽等殘留物，也使得形成之微 201107228 結構外表不平整。 此外，如第1圖所示，微結構110外圍以氧化矽116 保護，氧化矽頂端並無阻擋層保護，且氧化矽116頂端與 蝕刻道120頂端位於同一平面。因此，在晶圓廠進行製程 時會由於過蝕刻，在去除覆蓋於蝕刻道上之氧化矽130的 同時，也易一併去除微結構頂端之氧化矽116,不僅裸露 蝕刻道中之金屬層122,也同時造成微結構中之金屬層112 裸露。所以利用濕式蝕刻法去除蝕刻道120中之金屬層122 • 的同時，也容易意外移除微結構110中的金屬層112,造成 微結構的掏空，形成如第2圖所示之結果。 綜上所述，需要一種製造微機電之新的結構及方法， 可於微機電形成過程中，保護微結構内之金屬層不被掏 空，且形成壁面平整之微機電結構。 【發明内容】 因此本揭示内容之一態樣就是在提供於製造懸浮之微 * 結構的過程中，可保護微結構内之金屬層不被掏空，並可 形成壁面平整之微機電的一種微機電結構。 根據本揭示内容一實施例，提出一種微機電結構。其 於基板上具有微結構與蝕刻道。微結構為利用金屬層及導 電層相連而形成，且以氧化矽包覆在微結構周圍，並在氧 化矽頂端具有阻擋層。蝕刻道為金屬層與氧化層交互堆疊 而成。其中，氧化層兩邊具有通道，且微結構的阻擋層與 蝕刻道最上層的金屬層非同一平面。 201107228 本揭示内容的另一態樣是在提供一種可形成壁面平 整’且去除蝕刻道中殘留氧化層的一種微機電製造方法。 依照本揭不内容之上述態樣’提出一種微機電製造方 法。其步驟為以濕式蝕刻法移除蝕刻道中的金屬層，其中，201107228 VI. Description of the invention: [Technical field to which the invention pertains] This disclosure is not related to a semiconductor structure and a manufacturing method, and particularly relates to a structure and method for manufacturing a microelectromechanical device. [Prior Art] The MEMS system contains a variety of different microstructures, and the different φ are integrated with the related circuits, and different processing techniques can be used to make different applications. For example, the microstructure is combined with a complementary gold-oxide half-electrode, and the wet structure is used to form the microstructure into a suspended structure, a which can be applied to sense wafers. However, in the formation of the microstructure, there is a problem that the metal layer in the microstructure is hollowed out and oxide remains. As shown in Figure 1, a cross-sectional view of the microstructure and circuitry is shown. The microstructures 110 have etched tracks 120 formed by alternately stacking metal layers 122 and respective via holes 124. However, since the via layer 124 violates the width design principle of the general crystal φ circle factory, the via layer 124 is designed to fill the entire layer. Therefore, when depositing the via layer 124 at the beginning, the deposited material is liable to be deposited only on the side of the channel to form a channel layer of the central recess, and the entire channel cannot be filled as expected, resulting in deposition of a channel layer having an uneven surface. Since the surface of the via layer deposited by the initial deposition process is not flattened, all the subsequent processes are affected by the unevenness, so that each of the metal layer 122 and each layer of the via layer 124 has an uneven surface, or even The surface of the etched track 120 in contact with the microstructures 110 is not flat. Therefore, in the process of manufacturing the suspended microstructure, residues such as ruthenium oxide are easily generated, and the microstructure of the formed 201107228 is uneven. Further, as shown in Fig. 1, the periphery of the microstructure 110 is protected by the ruthenium oxide 116, and the top end of the ruthenium oxide layer is not protected by the barrier layer, and the top end of the ruthenium oxide 116 is in the same plane as the top end of the etch channel 120. Therefore, during the fab process, the yttrium oxide 130 covering the top of the microstructure is easily removed by removing the yttrium oxide 130 covering the etched land, and the metal layer 122 in the etched track is not exposed. At the same time, the metal layer 112 in the microstructure is exposed. Therefore, while the metal layer 122 in the etching track 120 is removed by wet etching, it is also easy to accidentally remove the metal layer 112 in the microstructure 110, causing the hollow of the microstructure to form a result as shown in Fig. 2. In summary, there is a need for a new structure and method for fabricating microelectromechanics that protects the metal layer within the microstructure from being hollowed out during the formation of the microelectromechanical and forms a planar microelectromechanical structure. SUMMARY OF THE INVENTION Therefore, in one aspect of the present disclosure, in the process of fabricating a suspended micro* structure, a metal layer in the microstructure can be protected from being hollowed out, and a micro-electromechanical layer having a flat surface can be formed. Electromechanical structure. In accordance with an embodiment of the present disclosure, a microelectromechanical structure is presented. It has a microstructure and a etched track on the substrate. The microstructure is formed by the connection of the metal layer and the conductive layer, and is surrounded by the ruthenium oxide around the microstructure and has a barrier layer at the top of the ruthenium oxide. The etching track is formed by stacking metal layers and oxide layers. Wherein, the oxide layer has channels on both sides, and the microstructured barrier layer is not in the same plane as the uppermost layer of the etching track. 201107228 Another aspect of the present disclosure is to provide a microelectromechanical manufacturing method that can form a wall surface and remove residual oxide layers in the etched track. A microelectromechanical manufacturing method is proposed in accordance with the above aspect of the present disclosure. The step of removing the metal layer in the etching track by wet etching, wherein
钱刻道中之金屬層與氧化層交互堆疊，而氧化層兩邊具有 通道。接著，以超音波振盪將蝕刻道中殘餘的氧化層移除❶ 之後利用深反應離子钱刻及背敍刻懸浮微結構。於深反應 離子蝕刻後，背蝕刻前，可加上覆蓋層於微結構上方，以 保護微結構。且於背蝕刻前，於基板下沉積一層光阻層， ^定義背射]區域，並保冑其它不須㈣之區_。上述覆 蓋層可為氧化矽、金屬、玻璃或矽基。 ,f照本揭示内容另—實施例，提出-種微機電製造方 法。其步驟為以濕式㈣法移除㈣道中的金屬層，其中， =道：之：屬層與氧化層交互堆疊，而氧化層兩邊具有 殘：的氣層支撐金屬層。接著，以蝕刻將钱刻道中 浮微社構纟除’最後彻深反應離子⑽及背银刻懸 構=反應離子敍刻後，背钱刻前，可加上覆蓋 保護微結構。且於背刪，於基板 之區域。上述覆蓋層區域’並保護其它不須蝕刻 m . 為氣化矽、金屬、玻璃或矽基。 因此’應用本揭示內六 層兩邊，且通道之之微機電 結構》通道位於氧化 因此在沉手合一般晶圓廠之寬度設計原則。 因此在l積通道層時’可 持餘刻道表面以及钱刻道出卜表千整之通道層以保 ^壁面平整。且於濕式蝕刻移除蝕 201107228 刻道之金的同時，並不會掏空微 應用本揭示内容之微機電製造方法，^ 濁層此外’ 殘留之氧化層，且形成壁面平整之移除餘刻道中 用來製造許多低成本的感測器和致動^㈣電°進而可 【實施方式】 請參照第3圖，其繪示依照本揭 -種微機電結構之剖面圖。微機電結構為於基=2 有微結構210與蝕刻道220。 π、丞极ζυυ上具 微結構210為多層金屬層212間 形成。微結構210外圍以氧化 守連接而 須端具有_218。其中^=62 ==氧切216 用來連接金屬層212。而阻擋層^ &可為導孔（Vla)， 抵擋離子_以保護底下之;結構，‘、=:=刻： 時，不會同時將包覆於微結構外的 "^ 微結構210中的金屬層212 夕移除’造成 ± 稞露。進而避免於濕式蝕刻移 除姓刻道㈣的同時，意外移除微結構2U)中之金屬層212。 蝕刻道220位於以氧化石夕 钕刻道220為金屬層222與 j 210旁。 且氧化層224兩旁具有通=層3 乂互堆曼而形成， 孔（⑺獻0。或者是=通道226可為導孔或觸 其上具有金屬層氧化2道220底部具有整層觸孔， 堆疊，且氧化層二;導孔’以金屬層與氧化層交互 可懸浮導孔，以形成㈣道，使氧化層 … s除可為氧切外，也可為其他氧化物。 201107228 由於本揭示内容之微機電結構中之通道226的寬度設 計符合一般晶圓廠的設計原則，因此通道226於沉積製程 時可以確實被沉積材料填滿，而不會產生表面不平整之通 道226。此外，在標準的互補型金氧半導體（Complementary Metal-Oxide-Semiconductor，CMOS)的製程中，沒有通道 226或金屬層222的位置，會被氧化矽填滿，因此通道226 間會被氧化矽填滿形成氧化層224。 上述微結構210外之氧化矽216頂端的阻擋層218， 以及蝕刻道220中最上層之金屬層222非同一平面。根據 一實施例，蝕刻道220之頂端金屬層較微結構210頂端之 阻擋層218為低，以減少移除蝕刻道後，氧化矽等氧化層 的殘留。此外，如果接續步驟有需要再次移除氧化物，以 露出餘刻金屬孔，蝕刻道220之頂端金屬層較微結構210 頂端之阻擋層218為低可降低後續蝕刻製程内外圈所產生 的蝕刻速度誤差。 再者，基板200之微機電結構旁，具有互補型金氧半 導體電路230，用來控制整個微機電系統。此處所指之互 補型金氧半導體電路為一般習知所瞭解之立補型金氧半導 體電路，因此不在此詳細描述。 由上述可知，應用本揭示内容之微機電結構具有下列 優點： 第一，於微結構外圍具有氧化矽包覆，且氧化矽頂端 具有阻擋層，因此，以濕式蝕刻移除蝕刻道之金屬層時， 並不會將微結構中之金屬層掏空。 201107228 通二=藉=:成於導孔或觸孔間，由於 =可以確實填滿其，進，心表=: 低ini道之_金屬層^結構頂端之阻擋舞為 低：Γ減少移除㈣道後，氧化㈣氧化㈣朗層為The metal layer in the money track is stacked with the oxide layer, and the oxide layer has channels on both sides. Next, the residual oxide layer in the etching track is removed by ultrasonic oscillation, and then the suspended microstructure is engraved and back-stacked by deep reaction ions. After deep reactive ion etching, a blanket layer may be applied over the microstructure to protect the microstructure prior to back etching. Before the back etching, a photoresist layer is deposited under the substrate, and the area of the back-reflection region is defined, and the other regions (4) are not required. The cover layer may be ruthenium oxide, metal, glass or ruthenium. In accordance with another embodiment of the present disclosure, a microelectromechanical manufacturing method is proposed. The step is to remove the metal layer in the (four) track by the wet (four) method, wherein = channel: the genus layer and the oxide layer are alternately stacked, and the oxide layer has a gas layer supporting metal layer on both sides. Then, by etching, the money is removed from the micro-structure. After the final deep reaction ion (10) and the back silver engraving suspension = reactive ion narration, the cover protection microstructure can be added before the money is cut. And deleted in the back, in the area of the substrate. The above-mentioned cover layer region ′ and protects other from etching m. It is a vaporized ruthenium, metal, glass or ruthenium base. Therefore, the application of the six layers on both sides of the disclosure, and the channel of the micro-electromechanical structure" channel is located in the oxidation and therefore the principle of width design in the hands of the general fab. Therefore, when the channel layer is accumulated, the surface of the track can be held and the channel layer of the money can be engraved to ensure that the wall surface is flat. And while the wet etching removes the gold of the etching 201107228, it does not hollow out the micro-electromechanical manufacturing method of the micro-application of the disclosure, the turbid layer further includes the residual oxide layer, and the wall surface is removed. In the engraving, a plurality of low-cost sensors and actuators are used to manufacture a plurality of low-voltage sensors. Further, an embodiment is shown. Referring to FIG. 3, a cross-sectional view of a microelectromechanical structure according to the present invention is shown. The MEMS structure has a microstructure 210 and a etch channel 220 at base = 2. The π, the ζυυ ζυυ has a microstructure 210 formed between the plurality of metal layers 212. The periphery of the microstructure 210 is oxidized and has a _218 end. Wherein ^=62 == oxygen cut 216 is used to connect the metal layer 212. The barrier layer ^ & can be a via hole (Vla), resisting ions _ to protect the underlying; structure, ', =: = engraved: when it will not cover the microstructure outside the "^ microstructure 210 The metal layer 212 in the eve removed 'causes ± 稞 dew. Further, the metal layer 212 in the microstructure 2U) is accidentally removed while the wet etching removes the last trace (4). The etched track 220 is located next to the metal oxide layer 222 and j 210 with the oxidized stone etched track 220. And the oxide layer 224 is formed on both sides of the pass layer 3 乂 mutual stack, the hole ((7) is 0. Or the channel 226 can be a via hole or a metal layer is oxidized on the bottom of the channel 220 has a whole layer of contact holes, Stacking, and the oxide layer is two; the via hole 'interacts with the metal layer and the oxide layer to suspend the via hole to form the (four) track, so that the oxide layer ... can be oxygen cut, or other oxides. 201107228 The width of the channel 226 in the MEMS structure of the content is designed in accordance with the general fab design principles, so that the channel 226 can be filled with the deposited material during the deposition process without creating a channel 226 with surface irregularities. In the standard Complementary Metal-Oxide-Semiconductor (CMOS) process, the position of the channel 226 or the metal layer 222 is not filled by the yttrium oxide, so that the channel 226 is filled with yttrium oxide to form oxidation. The layer 224. The barrier layer 218 at the top of the ruthenium oxide 216 outside the microstructure 210 is not the same plane as the uppermost layer 222 of the etch channel 220. According to an embodiment, the top metal layer of the etch channel 220 is The barrier layer 218 at the top of the structure 210 is low to reduce the residual of the oxide layer such as ruthenium oxide after the etching pass is removed. Further, if it is necessary to remove the oxide again in the subsequent step to expose the remaining metal hole, the top of the etched track 220 The metal layer is lower than the barrier layer 218 at the top of the microstructure 210 to reduce the etching speed error caused by the inner and outer rings of the subsequent etching process. Further, next to the microelectromechanical structure of the substrate 200, there is a complementary MOS circuit 230 for controlling The entire MEMS circuit. The complementary MOS circuit referred to herein is a conventionally known MOS transistor circuit and is therefore not described in detail herein. From the above, the MEMS structure to which the present disclosure is applied has the following Advantages: First, there is yttrium oxide coating on the periphery of the microstructure, and the yttrium oxide top has a barrier layer. Therefore, when the metal layer of the etched track is removed by wet etching, the metal layer in the microstructure is not hollowed out. 201107228 通二 = borrowing =: formed between the guide hole or the contact hole, because = can indeed fill it, enter, the heart table =: low ini road _ metal layer ^ structure top Low barrier dance: Γ (iv) reducing the channel after removal of oxide layer (iv) oxide (iv) Long
凊參照第4圖，係繪示依照本揭示内容另 的一種微機電製造方法的流程圖。首先， 方式 餘刻法移除侧道的金屬層（步驟術）。接著 2 = =之氧化層(步驟404)。再利用深反應離子： ，刻基板至-輯度（步驟槪）。最後，進行背钱刻 成微結構懸浮（步驟4〇8)。 & 進行上述步驟4G2前，可於基板上形成微結構外氧化 =頂端之阻擋層與㈣道頂料在同—平面之結構，造成 同低差，以防止後續濕式蝕刻移除蝕刻道金屬層時（步驟 4〇2)，同時意外移除微結構中之金屬層❶此外，如果後續 步驟有而要再次移除氧化物以露出钮刻金屬孔，氧化石夕頂 之阻擋層與餘刻道頂端不在同一平面之結構也可降低後 續餘刻製程内外圈所產生的蝕刻速度誤差。 另外，進行背飯刻（步驟408)前，可於晶片上方形 成一覆蓋層，以保護微結構。也可在步驟4〇8前，於基板 下方形成光阻層，以定義背蝕刻區域。 凊參照第5圖至第1〇圖，係繪示利用第4圖之微機電 製造方法步驟的剖面圖。首先，形成如前述第3圖之微機 201107228 電結構。其中’微結構210外之氧化矽216頂端的阻擋層 218 ’與钱刻道220中最上層之金屬層222非同一平面，形 成高低差’以防止於後續步驟中，意外移除微結構中之金 屬層212 °再者，接續步驟需再次移除氧化物以露出敍刻 金屬孔時’此高低差結構也可降低後續蝕刻製程内 產生的蝕刻速度誤差。 圈所 接著’以濕式蝕刻法移除蝕刻道的金屬層（步驟4〇2)<> 如第5圖所示，此時，蝕刻道中之氧化層224也會因金屬 層的移除而一併去除，僅剩下最底層與基板連接之氧化層 224。此外，於步驟402中，也會一併移除微結構外圍氧化 矽216頂端之阻擋層，以及打線區域24〇上之部分保護層 242。 '° 如第6圖所示’進行濕式蝕刻後，於打線區域24〇上 仍留有一層保護層242,以確保後續步驟不會對打線區域 造成傷害。接著，藉由濕式蝕刻法去除蝕刻道之金屬層後， 利用乾式钱刻移除餘刻道中殘留之氧化層（步驟406 )。 5月參照第7圖’利用深反應離子钱刻法餘刻基板2〇〇 至一定深度（步驟406)，以益於後續對基板進行背蝕刻。 並且’可選擇性的在整個晶片上方加上覆蓋層25〇，以在 後續製程中保護微結構210。覆蓋層250可為氧化石夕、金 屬、玻璃或矽基。 請參照第8圖’於基板下方沉積一層光阻層260，以 定義背蝕刻之區域’並保護其他不需蝕刻之區域。 請參照第9圖’對基板進行背餘刻（步驟208 )，移除 201107228 微結構210底下之部份基板200，再移除基板200下方之 光阻層260，造成懸浮式微結構3〇〇。同時，為避免覆蓋層 25〇厚度太薄，而出現翹曲現象，因此可將覆蓋層25〇切 割為單一晶粒大小。並且此舉可使打線區 4〇 最後’如第1〇圖所示’以触刻去除打線區域24〇之保 濩層242，以供後續進行封裝打線，傳輪訊號。 此種懸浮式微結構300於微機電系統中，當搖動或晃 镛^整個微機電糸統時’懸浮式微結構3〇〇便觸動旁邊之電 =0。因此’可用來製造感測器或致動器，例如壓力計、 加速計（aCCderometer)、生化感測器等等。 實施容之微機電製造料㈣—㈣方式與上述 了同之處在於’以濕式餘刻法去除餘刻道 =金屬層後，改用超音波㈣移除_道中殘留之氧化 g ’同樣可完全移除氧化層，形成外壁 之微機電結構。其中，超音波震盈器内需具有心殘= •㈣移除，會用氣超:波震_餘 =烘烤或者是旋乾，以去除晶片L:水:此 燥。並於後續對基板進行深反應離；：虱/呆持曰曰片乾 刻二成二壁平整、無殘留物之懸浮微機刻與背餘 移冗揭示内容 震盪或，然式蝕刻移除之後，再進行 深完全移除殘留之氣化層。並以後 反應離子钱刻法與背姓刻形成外壁平整、無殘留物= 201107228 浮式微機電結構。進而可用來製造感測器和致動器。 雖然本揭示内容已以實施方式揭露如上，然其並非用 以限定本揭示内容，任何熟習此技藝者，在不脫離本揭示 内容之精神和範圍内，當可作各種之更動與潤飾，因此本 揭示内容之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】 為讓本揭示内容之上述和其他目的、特徵、優點與實 施例能更明顯易懂，所附圖式之說明如下： 第1圖為先前技術之微結構與電路之結構剖面圖。 第2圖係繪示先前技術之微結構經過濕式蝕刻後之剖 面圖。 第3圖係繪示依照本揭示内容一實施方式的一種微機 電結構剖面圖。 第4圖係繪示依照本揭示内容另一實施方式的一種微 機電製造方法流程圖。 第5圖至第10圖係繪示依照第4圖步驟的一種微機電 製造方法步驟剖面圖。 【主要元件符號說明】 110 :微結構 112 :金屬層 114 :導電層 116 :氧化矽 120 :蝕刻道 122 :金屬層 12 201107228 124 :導電層 130 : 140 :電路 200 : 210 :微結構 212 ： 214 :導電層 216 ： 218 :阻擋層 220 ： 222 :金屬層 224 ： 226 :通道 230 ： 240 :打線區域 242 ： • 250 :覆蓋層 260 : 300 :懸浮式微結構 400 ： 402 、 404 、 406 、 408 :步 氧化矽 基板 金屬層 氧化矽 蝕刻道 氧化層 電路 保護層 光阻層 方法Referring to Figure 4, there is shown a flow chart of another method of fabricating a microelectromechanical device in accordance with the present disclosure. First, the way to remove the metal layer of the sidewalk (step). Next 2 = = oxide layer (step 404). Reuse deep reactive ions: , engrave the substrate to the degree (step 槪). Finally, the money is engraved into a microstructure suspension (steps 4〇8). & Before proceeding to the above step 4G2, a microstructure-external oxidation = top barrier layer and a (four) pass-through material may be formed on the substrate in the same plane to cause the same low difference to prevent subsequent wet etching to remove the etching track metal. At the time of the layer (step 4〇2), the metal layer in the microstructure is accidentally removed. In addition, if the subsequent step has to remove the oxide again to expose the metal hole of the button, the barrier layer and the residual of the oxidized stone roof The structure in which the top ends of the tracks are not in the same plane can also reduce the etching speed error generated by the inner and outer rings of the subsequent remnant process. Alternatively, a cover layer may be formed on the wafer to protect the microstructure prior to the meal (step 408). A photoresist layer may also be formed under the substrate to define a back etched region prior to step 4-8. Referring to Figures 5 through 1 , a cross-sectional view showing the steps of the MEMS manufacturing method of Figure 4 is shown. First, the microcomputer 201107228 electrical structure as shown in the above FIG. 3 is formed. The barrier layer 218 ′ at the top of the yttrium oxide 216 outside the microstructure 210 is not in the same plane as the uppermost metal layer 222 of the money track 220, forming a height difference ′ to prevent accidental removal of the microstructure in the subsequent steps. The metal layer is 212 °. In addition, the subsequent steps need to remove the oxide again to expose the metal hole. This high and low structure can also reduce the etching speed error generated in the subsequent etching process. The circle is then followed by 'wet etching to remove the metal layer of the etching track (step 4〇2)<> as shown in Fig. 5, at this time, the oxide layer 224 in the etching track is also removed by the metal layer. And removed together, leaving only the bottom layer of the oxide layer 224 connected to the substrate. In addition, in step 402, the barrier layer at the top of the microstructured outer ruthenium oxide 216 and the portion of the protective layer 242 on the wire bonding region 24 are also removed. '° As shown in Fig. 6' After the wet etching, a protective layer 242 remains on the wire bonding area 24 to ensure that the subsequent steps do not cause damage to the wire bonding area. Next, after the metal layer of the etching track is removed by wet etching, the oxide layer remaining in the remaining track is removed by dry etching (step 406). In May, the substrate 2' is re-etched to a certain depth (step 406) by means of deep reaction ion scrutiny in accordance with Fig. 7 to facilitate subsequent back etching of the substrate. And a capping layer 25 can be selectively applied over the entire wafer to protect the microstructures 210 in subsequent processes. The cover layer 250 can be a oxidized stone, a metal, a glass or a ruthenium. Referring to Figure 8, a photoresist layer 260 is deposited under the substrate to define the area of the back etch and to protect other areas that do not require etching. Referring to FIG. 9 ', the substrate is back-cut (step 208), part of the substrate 200 under the 201107228 microstructure 210 is removed, and the photoresist layer 260 under the substrate 200 is removed, resulting in a suspended microstructure. At the same time, in order to prevent the cover layer 25 from being too thin and warping, the cover layer 25 can be cut into a single grain size. And this will enable the wire-punching area to be finally removed as shown in Figure 1 to remove the security layer 242 of the wire-bonding area 24 for subsequent encapsulation and routing. Such a suspended microstructure 300 is in a microelectromechanical system. When the entire micro-electromechanical system is shaken or shaken, the suspended micro-structure 3 slams the electric =0. Thus, it can be used to manufacture sensors or actuators such as pressure gauges, aCCderometers, biochemical sensors, and the like. The implementation of Rongzhi MEMS manufacturing materials (4)-(4) is the same as the above. After removing the residual track = metal layer by wet residual method, the ultrasonic wave (4) is used to remove the residual oxidized g in the channel. The oxide layer is completely removed to form a microelectromechanical structure of the outer wall. Among them, the ultrasonic shock absorber needs to have a heart failure = • (4) removal, it will use gas super: wave shock _ residual = baking or spin dry to remove the wafer L: water: this dry. And after the subsequent deep reaction of the substrate;: 虱 / 曰曰 曰曰 干 干 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 微 微 微 微 微The deep and complete removal of the remaining gasification layer is carried out. And then the reaction ion money engraving method and the back surname form a smooth outer wall, no residue = 201107228 floating micro-electromechanical structure. It can in turn be used to make sensors and actuators. The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood. Sectional view. Figure 2 is a cross-sectional view showing the prior art microstructure after wet etching. 3 is a cross-sectional view showing a microcomputer electrical structure in accordance with an embodiment of the present disclosure. 4 is a flow chart showing a method of fabricating a microelectromechanical device in accordance with another embodiment of the present disclosure. Figures 5 through 10 are cross-sectional views showing the steps of a microelectromechanical manufacturing method in accordance with the steps of Fig. 4. [Description of main component symbols] 110: microstructure 112: metal layer 114: conductive layer 116: yttrium oxide 120: etching channel 122: metal layer 12 201107228 124: conductive layer 130: 140: circuit 200: 210: microstructure 212: 214 : Conductive layer 216: 218: barrier layer 220: 222: metal layer 224: 226: channel 230: 240: wire bonding area 242: • 250: cover layer 260: 300: floating microstructure 400: 402, 404, 406, 408: Step yttria substrate metal layer ruthenium oxide etched oxide layer circuit protective layer photoresist layer method
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