TW201106332A - Data signal wiring driving circuit, liquid crystal display device, and driving method for liquid crystal display device - Google Patents

Abstract

A data signal-line driver (30) that outputs, to source lines (22) of a liquid-crystal panel (20), data signals that are in accordance with gradation data, as adjacent outputs with opposite polarities; wherein the data signal-line driver (30) is provided with a polarity-switching control circuit (44) that reverses the polarities of adjacent outputs of polarity-reversal switching circuits (33, 41), based on a control signal (Ctrl_REV); an output short-circuiting control circuit (45) that short-circuits adjacent outputs of short-circuit switching circuits (40), based on a control signal (Ctrl_CS); and an assessing circuit (43) that successively obtains gradation data, and selectively outputs the control signal (Ctrl_REV) and the control signal (Ctrl_CS), based on a display pattern, consisting of penetrating-states and non-penetrating-states at adjacent outputs, of the majority of the one-line's worth of gradation data that was obtained the last time, and a display pattern of the majority of the one-line's worth of gradation data that was obtained currently. In such a way, current consumption is reduced, and heating due to this current consumption is reduced, when displaying a peculiar image upon source-block reversal driving.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data signal line driving circuit, a liquid crystal display device, and a driving method of a liquid crystal display device, and more particularly to a data signal line for each In the source block inversion driving in which the scanning signal line changes polarity and performs dot inversion driving of the display, and further divides the section to be scanned and performs interleave scanning in the section, the data signal line is driven in addition to the control of the liquid crystal display device. The circuit recognizes the pattern of the image, and separately performs control of polarity inversion and control of charge sharing. [Prior Art] Previously, an active matrix type liquid crystal panel was widely used. The active matrix type liquid crystal panel is configured to form a plurality of data signal lines (hereinafter referred to as "data lines") on the transparent substrate in the two transparent substrates sandwiching the liquid crystal layer, and the plural The data lines are intersected by a plurality of scanning signal lines, and the pixel electrodes formed corresponding to the respective intersections are arranged in a matrix (array). Each of the pixel electrodes is connected to a data line passing through a corresponding intersection thereof via a Dinger Film Transistor as a switching element, and a gate terminal of the TFT is connected to a scanning signal line passing through the intersection . Further, on the other transparent substrate, a counter electrode shared by a plurality of pixel electrodes is formed as a common electrode.

The liquid crystal display device having the liquid a & B „ liquid 曰 panel of the above configuration includes a gate driver and a source driver as driving circuits for displaying images on the 叩乂 叩乂 迤 and the day panel. The scanning signal line driving circuit is a driving circuit for sequentially selecting a plurality of scanning signal lines to be applied to a plurality of scanning circuits of the 138936.doc 201106332. The source driver is also called a data signal line driver. a circuit or video signal line driving circuit for applying a data signal for writing data to each pixel forming portion of the liquid crystal panel to a plurality of data lines. The common electrode is opposed to the pixel electrode The common voltage Vc〇m is applied to the pixel electrode selected by the gate driver from the source driver, and the transmittance of the liquid crystal layer is changed according to the voltage applied between each pixel electrode and the common electrode. Thereby, an image can be displayed on the liquid crystal panel. At this time, the liquid crystal panel is AC-driven in order to prevent deterioration of the liquid crystal material constituting the liquid crystal layer. The polar driver outputs a data signal in such a manner that the positive and negative polarities of the voltage applied between the respective pixel electrodes and the common electrode are, for example, inverted every time the frame is inverted. However, the liquid crystal panel of the active matrix type corresponds to each pixel. However, the characteristics of the switching elements such as TFTs are uneven, so even if the data signals output from the driver (the applied voltage based on the potential of the common electrode) are symmetric, the transmittance of the liquid crystal layer is not positive or negative. The data signal is completely symmetrical. Therefore, in the driving mode (inversion frame driving method) in which the positive and negative polarities of the applied voltage on the liquid crystal layer are reversed once every time, the display of the liquid crystal panel is flashed. As a countermeasure against such flashing, it is known that the positive and negative polarities of the applied electric power are reversed for every horizontal scanning signal line, and the driving method of inverting the positive and negative polarities for each frame is i. To form a pixel, the positive and negative polarities of the application (4) on the crystal layer are reversed for each signal line and every 1 data line, and are also reversed for each frame. Driving 148936.doc 201106332 mode (dot inversion driving mode) Fig. 20 shows the output waveform of the source driver when the liquid crystal panel is driven by the dot inversion driving method. As shown in Fig. 20, the 'source driver for each scanning signal The output of the positive polarity data signal Vpdata having a voltage higher than the common voltage Vcom applied to the common electrode and the negative polarity data signal vndata having a lower voltage than the common voltage Vcom are repeated. However, the source driver is provided with a plurality of output buffers, wherein each of the output buffers is connected to each of the data lines to drive the load of each of the data lines and the liquid crystal cells. Therefore, when the source driver outputs the shape of the positive polarity data signal Vpdata, the load is applied to the load. The charging current from the high-potential electric dust flows. On the other hand, in the case where the source driver outputs the negative polarity data signal Vndata, a discharge current that flows toward the low potential voltage Vss flows. The charge current and discharge current pass through the internal resistance in the output buffer provided in the source driver, so the heat is increased. The heat generated from the inside of the source driver is mainly generated by the output buffer. Therefore, in order to reduce the amount of heat generated by the source driver, it is necessary to minimize the heat generated from the output buffer, particularly the output from the output buffer. However, as shown in Fig. 20, if the electric power of the data signal is swung between the positive polarity information signal Vpdata and the negative polarity data signal Vndata, the heat generated by the internal resistance in the output buffer becomes larger as the amplitude of the wobble is increased. Moreover, since the number of charge and discharge times increases, power consumption also increases. Therefore, as one method for preventing the increase in power consumption, a driving method using interlaced scanning (interleaved driving method) has been proposed (for example, see Patent Document 1). In the interleave scanning described in Patent Document 1, first, scanning signal lines of all odd 148936.doc 201106332 series (or even teaching columns) are scanned, and then scanning signal lines of the remaining even columns (or odd columns) are scanned. Figure 21 shows the output waveform of the source driver when interleaved scanning is performed. Since the interlaced scanning film is scanned for the same polarity of pixels, the polarity is reversed by the timing of switching from the scanning of the odd line to the scanning of the even line. Fig. 22 is a view showing the output waveform of the 'source driver' when the output state shown in Fig. 21 is corresponding to Fig. 20 and the scanning signal lines are sequentially replaced by Ί19 Ί ^ t ^ , . Fig. 22 shows the round-out waveform of the source driver at the end of the scan of the i-frame, i.e., the odd-numbered line and the even-numbered line at the end of the interleaving scan (4). The output waveform of the source driver can be obtained in the same state as the output waveform of the source driver of the dot inversion driving mode shown in Fig. 2A. Thus, in the interlaced scanning, the polarity inversion driving for each scanning signal line can be performed, and the number of polarity inversions can be suppressed. As a result, the number of charge and discharge cycles is reduced, so that an increase in power consumption can be suppressed. However, if the interleaved scanning is performed as described in the patent document W and the entire surface of the liquid crystal panel, a method of driving the interleaved scanning by dividing the display portion into a plurality of regions in the row direction is proposed. (For example, refer to Patent Document 2). FIG. 23 shows the scanning sequence of the drive material described in Patent Document 2. The display portion having the pixel electrode of eight lines is divided into a region i and a region 2. Then, interlaced scanning is performed in the order of odd 2 lines to even 2 lines for each area. This scanning is based on the data signals of the area and region 2 of each selection period, so that the flicker can be suppressed. Furthermore, this driving method is called 148936.doc 201106332 source block inversion driving method. Further, as a method of reducing the power consumption of liquid crystal charge and discharge by the above-described dot inversion driving, there is a method described in Patent Document 3 called charge sharing. This method is to cut off the digital analog conversion mechanism and the output terminal by cutting off the switch during the blanking period, and short-circuit the output terminals by the short-circuit switch. Thereby, when the drive signal applied to the same output terminal is inverted, power consumption during the period until the short circuit between the output terminals and the same potential is eliminated can be eliminated. Further, the power consumption is generated during a period in which the output terminals are short-circuited and become the same potential until the inversion, and the potential of the output terminal having the same potential is close to the potential of the driving signal of the opposite phase by the short-circuit between the output terminals. Therefore, the power consumption when the driving signal is reversed can be reduced. , , , , and : 'In the original source block inversion driving method, which is a driving method with less power consumption and less heat generation, it can be seen that if a special image called a killer pattern is displayed, Tea consumes more electricity and produces fever without a problem. Figure 24 shows the source block anti-strength type broken into the killer pattern, Figure 24 (a) shows the pattern, the surrounding _ system 24 (b) The pattern of the odd line is not shown, and the pattern of 1 24(c) is not the even line. As shown in Figure 24(a), the killer pattern is connected to the winter hex. 彔 彔 每 于 于 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每乂 For the black and white pattern. Interlace the pattern of the money hand® 24 (b^ - 匮 shape, the display of the odd line is like Baxiang) Fine-cut private port 4 (the magic is not. Therefore, the output of a scanning signal line M ^ ^ r- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In order to constantly apply the voltage to the liquid crystal pixel, the driving voltage of the white is equal to the voltage of the common electrode of the liquid crystal panel. The driving voltage of the black is the voltage of the state in which the voltage is applied to the liquid crystal pixel. There is a report of applying a positive voltage (positive polarity) and a negative voltage (negative polarity) to the common electrode. Also, the shape of n ^ ) is, for example, the driving voltage of white is 6 v, and the driving voltage of black is 0 v. And Xi Xishan Health & , u, when the source driver output is the parent for black and white output, The output voltage varies for each Μ signal line, so power consumption increases and heat becomes a problem. In the source block inversion driving method.. ^ _ (4) is interlaced in the block, so the mother-person The polarity does not change during scanning, so charge sharing is usually not performed. However, in order to reduce the power consumption, when the display is in the source-region block inversion driving, the J-document 3 performs the output between the two. For example, as shown in Fig. 24(b), the output is black, and the line 1 of the output 2 is the pole. Fig. 25(a) and (b) show the potential state. 1 and output 2 of the coffee ^ potential change: two output 1 potential change, Figure 25 (8) shows the output 2 source block inversion drive between I and line 3 to electrically "output! and output 2 short circuit, The power of the transmission becomes the middle of the black and white - "out of the wheel 2, after the short circuit is removed, it is the object: β§" electric house. Moreover, m, spring into the award, output 1 output + white lightning pressure, turn out 2 output - black voltage. ^White Book I. If the output 2 changes the potential in the opposite direction at one end, the money should be output. The black output is _ black, so in the output _ black <, the line of charge sharing, ·, electricity, and not clear More, more current needs to flow. Similarly, when the line 3 is scanned to the "I48936.doc 201106332 line 5, the voltage between the white and the black is the voltage of "b", which is the short-circuit between the output 1 and the output 2, so that the output 1 is output + Black time ' needs more current. Thus, when the source block inversion driving is performed and the killer pattern is displayed, the charge sharing between outputs is reduced in power consumption and is ineffective. Therefore, for example, Patent Document 4 describes a technique for determining the gray scale of an image to perform charge sharing. In the technique described in Patent Document 4, in the dot inversion driving performed every two lines in the vertical direction, charge sharing is not performed according to the data, but (1) charge sharing is performed every time the polarity of the data voltage is changed. And (2) the polarity is not changed, and the gray scale displayed and the gray scale system to be displayed next turn into white (in the case where the gray scale turns into a gray scale). Further, in the technique described in Patent Document 4, 'the dot inversion drive is generally performed every 1 line in the horizontal direction. However, when the fragile pattern is detected, the dot is reversed every 2 lines in the horizontal direction. Turn, so that it does not bow the display of the fragile pattern. [PRIOR ART DOCUMENT] [Patent Document 1] [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei 8-320674 (published on Dec. 3, 1996). [Patent Document 3] Japanese Laid-Open Patent Publication No. Japanese Patent Laid-Open No. Hei 9-212137 (published on August 15, 1997) 148936.doc -10· 201106332 [Patent Document 4] Japanese Laid-Open Patent Publication No. 9088 (published on Jan. 15, 2011) H 2009- [Summary of the Invention] [Problems to be Solved by the Invention] However, in the technique described in Patent Document 4 When there is a case where charge sharing is applied when a specific pattern such as _ is not applied, power consumption is adversely affected, and effective charge sharing cannot be applied to all patterns. 3 Fig. 27 shows the potential change when M1 is shared with the output in the pattern shown in Fig. 26, and Fig. 27(4) shows the output! The potential changes, and two 27(b) indicate the potential change of the output 2. Between output 1 and output 2: :: In the case of sharing, as shown in Fig. 27 (4), (b), ... point to "... voltage. Thus, especially the output 2 shown in Figure 27 (b) In the case of the power consumption, the charge is increased in the case of changing from white to black, and it is not possible to correspond to the case of changing from black to white, or from black and white to black and white, from black and white to (four). Further, in the patent document, although the fragile pattern is detected, the countermeasure is not to perform charge sharing as described above, so the power consumption is not sufficiently reduced. The present invention has been developed based on the above problems, and its purpose is to provide In the source block inversion driving, even when the display is called a killer pattern: a special image, the data signal line driving circuit, which reduces the power consumption and reduces the heat generated by the power consumption, can be reduced. The electric sputum daily display device and the liquid crystal display device driving method. [Technical means for solving the problem] 148936.doc 201106332 In order to solve the above problem, the data signal line drive circuit of the present invention is characterized in that it has a matrix Match a plurality of pixel electrodes, a plurality of scanning signal lines for supplying a scanning signal to the pixel electrodes in the same row, and a liquid crystal display for supplying a plurality of data signal lines for respectively supplying data signals to the pixel electrodes of the same row a data signal that is generated according to the gray scale data and outputted to the data signal lines of the liquid crystal display unit in a manner opposite to the polarity of the adjacent output, wherein the data signal line driving circuit includes a polarity inversion mechanism. The polarity of the adjacent output is reversed; the link mechanism short-circuits between the adjacent outputs; and the first control unit controls the polarity inversion mechanism to make the polarity of the adjacent output according to the first control signal a second control unit that controls the short-circuiting mechanism to short-circuit the adjacent outputs according to the second control signal; and a determining unit that outputs the first control signal to the second control unit and The second control signal is output to the second control unit; and the liquid crystal display unit is divided into a plurality of regions in the row direction, After sequentially scanning the scanning signal lines of the odd-numbered columns or the even-numbered columns, the gray-scale data is sequentially supplied to the interlaced scanning of the scanning signal lines of the even-numbered columns or the odd-numbered columns in sequence, and the determining mechanism sequentially obtains the gray-scale data. And according to the previous display of the first-order gray-scale data, the display pattern including the display of the adjacent output is a transmission pattern of the transmitted state and a non-transmissive non-transmissive display pattern and the acquisition of the image And displaying, in the column gray scale data, a plurality of display patterns of the display state of the adjacent output and the display pattern of the non-transmissive state, and selectively outputting the second control signal and the second control signal. Doc 201106332 According to the above configuration, the judging means displays a display pattern of a majority of one line corresponding to the scanning signal line of the previous scanning in the interlaced scanning, and a display pattern of the majority of the scanning line corresponding to the scanning scanning signal line. , can determine whether the polarity of the adjacent output is reversed, and whether charge sharing between adjacent outputs is effective, and can be judged The above-described polarity reversal is effective for carrying out charge sharing between adjacent output. That is, the judging means can recognize the pattern of the image to be displayed and perform the above determination. When it is judged that the polarity of the adjacent output is inverted and the electric=share is valid between adjacent outputs, the first control mechanism is controlled to output the polarity by outputting both the i-th control signal and the second (four) apostrophe. The rotation mechanism reverses the polarity of the adjacent output, and the second control mechanism controls the short-circuit mechanism to short-circuit the adjacent outputs. Further, when it is judged that the charge sharing is not performed between the adjacent outputs without performing the polarity inversion, the second control means controls the short-circuiting means to short-circuit the adjacent outputs by outputting the second control signal. - In this way, the charge sharing can be performed efficiently, so that even when a special image called a killer pattern is displayed, the liquid crystal display unit is cut into a plurality of regions in the binding direction to perform interlaced scanning. It can also reduce power consumption and reduce heat generation caused by power consumption. The liquid crystal display device of the present invention includes a liquid crystal display unit having a plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes of the same column, and the same The plurality of data signal lines for respectively supplying the data electrodes to the data electrodes; and the data signal line driving circuit for the above-mentioned data electrodes, which make the above-mentioned data made according to the material of the gray scale I48936.doc -13-201106332 a lack of eight mountains.唬, according to the above configuration, the method of outputting the opposite polarity of the adjacent output to the liquid crystal β a 分别 according to the above configuration, can effectively perform the electric distribution in the data. It is possible to realize a kind of returning m ...., for the liquid day and day display part is divided into a plurality of areas in the row direction, and the feed is shaken and the drive is displayed, even if the display is broken The special pattern of the pattern and the 尨 can also reduce the power consumption and reduce the output of the liquid crystal display device. The liquid crystal display device of the present invention is characterized in that it is a driving method of a liquid crystal display device as described below, and the liquid crystal display device includes: liquid crystal, :, · page no.卩 'There are a plurality of pixel electrodes arranged in a matrix, for respectively supplying the pixel electrodes of the same column, and σ knowing the plurality of scanning signal lines of the 唬, and for the same-if L /A * a plurality of data signal lines for respectively feeding the data electrodes; and a line driving circuit for making the above-mentioned data signals according to the gray scale data, in a manner opposite to the polarity of the adjacent outputs And outputting to each of the data signal lines of the liquid crystal display unit; the driving method includes: in the first step, the scanning signal lines of the odd-numbered columns or the even-numbered columns are sequentially scanned for the plurality of regions in the row direction of the liquid crystal display portion Thereafter, the gray-scale data is sequentially supplied by sequentially scanning the interlaced scans of the scanning signal lines of the even-numbered columns or the odd-numbered columns in sequence, and sequentially obtaining the gray-scale data according to the previous acquisition of the gray-scale data. The display of the adjacent output is a display pattern of a majority of the display patterns of the transmitted transparent state and the non-transmissive non-transmissive state, and one column obtained this time And a display pattern of the majority of the display patterns of the adjacent output and the display pattern of the non-transmissive state, and the polarity of the adjacent output of the data signal line driver circuit is hereinafter referred to as 148936.doc 201106332 A short circuit between adjacent turns of the Becke signal line drive circuit; the width is determined to require the polarity of the adjacent output of the polarity reverse signal line drive circuit to be reversed; and the:::: a short circuit between adjacent outputs. According to the above-mentioned configuration of the n-line driving circuit, according to the front line of the interlaced scanning, the majority of the lines of the line of the sensation number line correspond to the 丨 line multi-quot; The display pattern of the number of factions can be judged whether the adjacent input of the data line driving circuit and the charge sharing are effective, and whether it is effective to charge the adjacent output between adjacent outputs is effective. The above-mentioned judgment is made by changing the pattern of the image. The other side of the data signal line drive circuit is reversed when the polarity of the adjacent wheel is reversed and the adjacent = drought is effective. The polarity of the output is anti-Korean, shooting day, warehouse > - short circuit between adjacent ones. Also, judging:: material: adjacent line drive circuit, adjacent transmission, 隹-+ break-in 仃 polarity reversal When the neighboring output == sharing is valid, the short circuit between the adjacent outputs of the data message is performed. The electric bath = the charge sharing can be effectively performed, so the interlaced scanning is performed for each region divided into a plurality of regions. Drive power, == for the killer pattern When the image is different, the power consumption can be reduced and the heat generated by the power consumption can be reduced. [Effect of the Invention] 148936.doc 15 201106332 As described above, the data signal line drive circuit of the present invention is configured to have a matrix configuration. a plurality of pixel electrodes, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes of the same column, and a liquid crystal display for respectively supplying the data signals to the pixel electrodes of the same row: a plurality of data lines And outputting the data signal according to the gray scale data to the liquid crystal in the opposite manner to the polarity of the adjacent output: the data signal line of the display portion, wherein the data signal line driving circuit comprises: a polarity reversing mechanism Inverting the polarity of the adjacent output; short-circuiting mechanism: short-circuiting the adjacent outputs; and a second mechanism for controlling the polarity inversion mechanism to reverse the polarity of the adjacent output according to the ith control signal a second control unit that controls the short-circuiting mechanism to short-circuit the adjacent outputs according to the second control signal; and a determining mechanism And outputting the second control signal to the second control unit, and outputting the second control signal to the second control unit; and scanning the plurality of regions in the row direction with respect to the liquid crystal display unit, sequentially scanning odd After the scanning signal lines of the series or even columns, the interlaced scanning of the scanning signal lines of the even-numbered columns or the odd-numbered columns is sequentially scanned, and the gray-scale data is sequentially supplied, and the determining mechanism sequentially obtains the gray-scale data, and The display pattern including the majority of the display patterns of the transmitted state and the non-transmissive non-transmissive state in the first-order gray-scale data obtained in the previous one, and the one-row gray obtained this time And a plurality of display patterns including the transmission state of the adjacent output and the display pattern of the non-transmissive state, and selectively outputting the second control signal and the second control signal. Further, the driving method of the liquid crystal display device of the present invention is as follows: the driving method of the display device is the liquid crystal display: the liquid crystal display portion, which has a plurality of pixel electrodes arranged in a matrix for The same plurality of scan signals are supplied to the scan signals of the same column == electrodes respectively, and the plurality of data signal lines respectively supplying the data signals to the pixel electrodes of the same row; and the data reed '°B low light (four) circuit, which makes the gray The created data signal 'the opposite polarity of the adjacent output is output to each of the data signal lines of the liquid crystal display unit, and the driving method includes the i-th step, and is divided into the liquid crystal display unit in the row direction. After each of the plurality of regions, sequentially scanning the odd-numbered or even-numbered columns to scan the information, the material is purely listed or odd-scanned by the interlaced scanning of the scanning signal lines, and sequentially supplies the gray-scale data according to Obtaining the above-mentioned grayscale data, and based on the previously obtained u-column grayscale data, including the display of the adjacent output, the transmitted state and the non-transmission a display pattern of a majority of the display patterns in the non-transmissive state, and a display pattern of the majority of the display patterns including the transmission state of the adjacent output and the display pattern of the non-transmissive state in the grayscale data. Determining whether the polarity of the adjacent output of the data signal line drive circuit is reversed and the short circuit between the adjacent outputs of the poor signal line drive circuit is required. = Step 'When it is determined that the polarity inversion is required, the above The data "the polarity of the adjacent output of the tiger line drive circuit is reversed; and in the third step, when it is determined that the short circuit is required, a short circuit between the adjacent outputs of the data signal line drive circuit is performed. S}· This can effectively The charge sharing is performed, so that the effect is achieved in the case where the liquid crystal display unit is divided into a plurality of regions in the direction of the rod t and the d direction, and the drive is interleaved. When it is called a special image of the killer pattern, it can also reduce the power consumption' and can reduce the heat generated by the power consumption. [Embodiment] _ If the present invention is based on the drawing FIG. 1 is a block diagram showing a configuration of the liquid crystal display device 1G, and shows a case where the polarity inversion switch circuit 33·41 is switched to the a side. FIG. 2 is a block diagram showing FIG. The liquid S 曰 装置 装置 装置 , , , , , 极性 极性 极性 极性 极性 极性 极性 极性 极性 极性 极性 极性 极性 极性 极性 极性 极性

The liquid crystal display device 10 of the present embodiment is mounted on a display device such as a fixed device such as a TV (TeleVlsion' TV) or a mobile terminal such as a mobile phone. As shown in FIG. 2, it includes a liquid crystal panel 2 (liquid crystal display). Not 4) and beryllium k 唬 line driver 3 〇 (data signal line drive circuit). Further, the remaining portion of the liquid sweet display device (not shown) can be realized by the conventional configuration (scan line driver or timing generator, etc.). The liquid crystal panel 20 includes two transparent substrates facing each other (a common electrode 26 to which a common voltage is applied is formed on one of the transparent substrates, and a gate line 21 (scanning signal line) and a source are formed on the other transparent substrate). The polar line 22 (data line k), the TFT 23, and the pixel electrode 24. The gate line 21 and the source line 22 are arranged in a plurality of ways orthogonal to each other, and correspond to respective father parts, respectively The TFT 23 and the pixel electrode 24 are disposed. That is, the TFT 23 and the pixel electrode 24 are arranged in a matrix. The gate line 21 is used to supply the selection signal to the pixel electrode 24 of the same column 148936.doc -18-201106332 (scanning signal The source line 22 is for supplying data signals to the pixel electrodes of the same row. The pixel electrode 24 is connected to the source line 22 via the TFT 23, and the gate of the Ding Ding 23 is connected to the gate line. 21. The scan line driver (not shown) sequentially outputs a selection signal to the gate line 21, and switches the turn-on/off of the tft23 corresponding to the selection signal. When the TFT 23 is turned on, the pixel electrode 24 and the source line 22 Electrical connection, when TFT23 is disconnected, like The electrode 24 and the source line 22 are electrically blocked. A liquid crystal layer is formed between the two transparent substrates, and the common electrode % and the liquid crystal sandwiched between the pixel electrodes 24 opposed to the common electrode 26 (liquid crystal) The unit 25) constitutes one pixel. The liquid crystal cell 25 is applied with a difference between the voltage applied to the pixel electrode 24 and the voltage applied to the common electrode 26. The arrangement of the liquid crystal changes according to the magnitude of the applied voltage, thereby displaying The data signal line driver 30 sequentially outputs the data number (gray scale voltage, driving voltage) corresponding to the image to be displayed to the driving circuit 'of each pixel electrode 24' which is connected to the source line 22. The data signal line driver 30 includes a shift register 31, a data latch 3, a polarity inversion switch circuit 3 3 (polarity inversion mechanism), a lock latch 34, a level shifter 35, and a positive polarity. Side DAC (Digital-to-Analog Converter) 36, negative-polarity side DAC 37, positive polarity operational amplifier 38, negative polarity operational amplifier 39 'short-circuit switching circuit 40 (short-circuit mechanism), polarity reversal switch Circuit 41 Sexual reversal mechanism), output pad (pad) 42, judgment circuit 43 (judgment mechanism), polarity switching control circuit 44 (first control mechanism), output short circuit 148936.doc -19-201106332 control circuit 45 (second control Further, the data signal line driver 3G is designed as a data line driving circuit of 414 output, and 414 pixels are horizontally arranged on the liquid crystal panel 2's. However, as long as it is not special It is to be noted that, for convenience of explanation, a case where six (〇υτι 〇υ 6 6 6) of the output of the data semaphore line driver 30 is set will be described. / 〇 In addition, as follows, the material signal line drive (4) is rotated in polarity, and charge sharing is performed on adjacent outputs. Therefore, for convenience of explanation, in Fig. 2, the constituent elements having the same function are sequentially attached with i numbers from the data output line on the left side. The data signal line driver 3 is sequentially obtained from the outside. (for example, a controller provided in the liquid crystal display device 10, etc.) 8-bit (256 grayscale) grayscale data Data[7j 〇]' supplied as image data (display material) via the data busbar The data Data[7:0] is converted into a data signal, and the data signal is output to the source line 22. The shift register II 31 sequentially generates pulse signals ENB1 to ENB6 in accordance with control from the outside, and outputs each pulse signal to the corresponding data latch 32. The data latch 32 locks the gray scale data Data[7: 〇] supplied via the data bus in synchronization with the pulse signals ENB1 to ENB6. The polarity inversion switch circuit 33 is inserted between the data latch 32 and the lock latch 34. The polarity inversion switching circuit 33 switches the corresponding data latch 32 between the a terminal ... side and the ^ terminal (b side) based on the polarity inversion signal 〇 pt - REV output from the polarity switching control circuit 44. Connect to the destination. 148936.doc -20- 201106332 i, 3, 5 polarity reversal switch circuit 33 a terminal is connected to the 5th, 3, 5 lock latch 34, b terminal is connected to the 2nd, 4th, 6th Lock the lock thief 34. The 3rd terminals of the 2nd, 4th, and 6th polarity inversion switch circuits 33 are connected to the 2nd, 4th, and 6th latch latches 34, and the 1) terminals are connected to the third port, and the 3rd, 5th latch latches 34 are connected. . That is, the odd-numbered polarity inversion switch circuit 33 sets the connection destination of the corresponding odd-numbered data latches 32 to the corresponding odd-numbered lock latches 34 (a side) and the corresponding odd-numbered Switching between the even-numbered lock latches 34 (b side) after twisting. The even-numbered polarity inversion switch circuit 33 associates the connection destination of the corresponding even-numbered data latches 32 with the corresponding even-numbered lock latches H34 (a side) and the corresponding even-numbered ones. The odd number of lock latches 34 (b side) are switched. The lock latch 34 locks the data latch-like output, i.e., the hold data of the data latch 32 connected in accordance with the switching of the polarity inversion switch circuit 33, in accordance with control from the outside. Thereby, image data corresponding to pixels of one horizontal line of the screen is held in each of the lock latches 34. The level shift is $35 to convert the signal level of the grayscale data of the input person. The odd-numbered level shifter 35 outputs the level-converted gray scale data to the positive polarity side DAC 36. The gray scale data of the even-numbered level shifter Qiu's level conversion is output to the negative side DAC3 7 . ΠΓ36 according to the level shifter 35 by the level conversion gray P white shell, the free external chamber for the positive polarity side gray voltage of m select Hg) voltage, and turn it out s τ Kk ^ is out to the positive operational amplifier 38. The DAC37 is based on the gray level of the level conversion by the level of the stomach (four) side, and the level of the gray scale is 148936.doc 201106332. One of the negative polarity side gray scale voltages supplied by p is selected and output to the negative polarity operational amplifier 39. Thereby, the data signal (gray scale voltage) of the positive polarity or the negative polarity which is selected (converted) by the gray scale data is output to the positive operational amplifier 38 and the negative operational amplifier 39. The positive polarity operational amplifier 38 and the negative polarity operational amplifier 39 function as an output buffer, and the output thereof is connected to the output pad 42 via the polarity inversion switch circuit 41. The output pad 42 is connected to the corresponding source line 22 of the liquid crystal panel 2A. Thereby, the data signal corresponding to the gray scale data is output to the source line 22. The knowledge circuit breaker circuit 40 is provided between the adjacent positive polarity operational amplifier 38 and the negative polarity operational amplifier 39. The short-circuiting switch circuit 4〇 short-circuits the outputs of the adjacent positive polarity operational amplifier 38 and negative polarity operational amplifier 39 based on the short-circuit signal 〇pt_cs outputted from the output short-circuit control circuit 45 (short-circuit switching circuit 4〇: through). The polarity inversion switching circuit 4 1 is inserted between the positive polarity operational amplifier 38 and the negative polarity operational amplifier 39 and the output pad 42. The polarity inversion switching circuit 41 connects the corresponding positive polarity operational amplifier 38 and negative polarity operational amplifier 39 to the a terminal (a side) based on the polarity inversion signal Opt_REV output from the polarity switching control circuit 44. Switch between the b terminals (b side). The a terminal of the first '3' five polarity inversion switch circuit 41 is connected to the first, third, and fifth output pads 42, and the b terminal is connected to the second, fourth, and sixth output pads 42. The second terminals of the second, fourth and sixth polarity inversion switch circuits 41 are connected to the second, fourth, and sixth output pads 42, and the b terminals are connected to the first, third, and fifth output pads 42. 148936.doc •22·201106332 That is, the odd-numbered polarity inversion switching circuits 41 are connected to the corresponding odd-numbered operational amplifiers 38, and corresponding to the odd-numbered round-out slabs 42 (a side)' The corresponding odd-numbered plus ones of the even-numbered rounded-out blades 42 (b side) are switched. The even-numbered polarity inversion switching circuit 41 is a connection destination of the corresponding negative-polarity operational amplifier 39, and the corresponding even-numbered output chip 42 (a side) and the corresponding even-numbered one minus one Switch between odd output pads 42 (b side). The judging circuit 43 judges whether or not polarity inversion and charge sharing are required based on the gray scale data Data[7:0]' supplied to the data signal line driver 3. The judging circuit 43 performs the above-described determination at the timing before the scanning of the scanning line, and as a result of the determination, if the polarity inversion is required, the control signal CtH_REv (the first control signal) is output to the polarity switching control circuit 44, if the electric charge is required. The sharing outputs a control signal Ctrl-CS (second control signal) to the output short-circuit control circuit 45. In other words, the determination circuit 43 selectively outputs the control ## (: Bu-1 - REV and control signal ctrl_cs) based on the determination result. Further, when the determination circuit 43 performs the above determination, it is stored in the setting register 46 for judging. The black display benchmark (data Crit-Black[2: 〇]), the benchmark used to judge the white display (data Crit-White[2: 〇]), and the benchmark used to judge the rituals (data Crit-Maj 〇rity[2 : 〇]) The setting register Μ can be arbitrarily overwritten by giving a signal from the outside. The polarity switching control circuit 44 controls the signal ctri_REV output from the judging circuit 43 based on the polarity switching command REV from the outside. And the polarity & inversion of the output ουτι~ [S] from the output line driver 3, that is, the output pad 42. I is switched from the external polarity switching command REV in the block from 148936.doc •23 - 201106332 When the scan of the odd line is turned to the scan of the even line (or vice versa), the polarity is reversed. When the control signal Ctrl_REV from the judgment circuit 43 is output, the polarity is reversed without regard to the polarity switching command REV. Turn The polarity switching control circuit 44 outputs a polarity inversion signal Opt_REV, which is a control signal for performing polarity inversion, to the polarity inversion switching circuit 3 3 · 4 1 , thereby turning the polarity inversion switching circuit 3 3 .丨 Switching between the a side and the b side. The polarity switching control circuit 44 performs the polarity inversion operation by setting the polarity switching command REV from the outside to "1" or the control signal Ctrl_REV to "1". The path control circuit 45 short-circuits the outputs OUT 1 to OUT6 of the output pad 42 from the data signal 5, the line driver 30, based on the external short-circuit command cs and the control signal Ctrl_CS supplied from the determination circuit 43.卩 纽 指令 ( ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The short circuit is controlled, and the output short circuit control circuit 45 outputs a short circuit signal 〇Pt_CS for short circuit, that is, charge sharing, to the short circuit switch circuit 4〇, whereby the circuit breaker circuit 4() is connected. The output short-circuit control circuit performs the charge sharing operation by setting "15" or "control signal Ctrl__CS to 1", for example, in the data signal line driver 30 having the above configuration. In the same way as before, the operation is performed, and on the other hand, the judgment circuit 43 judges according to the black and white pattern of the image alarm 4sL + TM / bucket (transmission state and non-transmission state pattern) | ^ Two polarity inversion and charge sharing, and if necessary, 148936.doc -24- 201106332 Polarity reversal and charge sharing ^ As shown in Figure 1, according to the polarity inversion signal Opt_; REV from the polarity switching control circuit 44 When the polarity inversion switch circuit 33·41 switches to the & side, the gray scale data of the odd-numbered data latches 32 is transferred to the corresponding odd-numbered latch latches 34. Moreover, the gray I1 outputted from the odd-numbered lock latches 34 is level-shifted by the corresponding odd-numbered level shifters, and converted into data signals by the positive polarity _AC36. And outputted to the odd-numbered output pads 42 by the positive polarity operational amplifier 38. In this case, the gray scale data of the even number of data latches 32 is transferred to the corresponding even number of latch latches 34. Moreover, the gray scale data outputted from the even number of lock latches 34 is level shifted by the corresponding even number of level shifters 35, and is converted into a lean signal by the negative polarity side DAC 37. ? The tiger is output to the even number of output pads 42 by the operational amplifier 39 for negative polarity. On the other hand, as shown in FIG. 2, when the polarity inversion switch circuit 33 is switched to the b side, the gray scale data of the odd number of data latches 32 is transmitted to the even number of the odd number plus one. The latch latch is switched, and the gray scale data outputted from the even number of latch latches 34 is level-shifted by the corresponding even-numbered level offset H35, and then converted by the negative polarity side DA(3). The data signal is formed and output to the odd-numbered output pads 42 by operational amplification (4) of the negative polarity. In this case, the gray scale data of the even number of data latches 32 is transferred to the odd-numbered latch latches 34 after the even number of minus ones. Moreover, the gray scale data outputted from the odd-numbered lock latches 34 is level-shifted by the odd-numbered level shifters 35 corresponding to 148936.doc -25 - 201106332, by the positive polarity side. The DAC 36 converts it into a data signal, and outputs it to the even-numbered output pads 42 by the positive-working operational amplifier 38. Thus, by the polarity inversion signal 〇Pt-REV from the polarity switching control circuit 44, the polarity inversion switching circuit 33. 41 is switched between the a side and the b side, thereby causing the data signal from the output pad 42 The polarity of the outputs OUT1 to OUT6 of the line driver 3 is inverted. Further, the short-circuiting switch circuit 40 is switched ON by the short-circuit signal 〇pt_CS from the output short-circuit control circuit 45, thereby short-circuiting the output ουτί~OUT6 from the output pad 〇, i.e., the data k-line driver 30. On the other hand, when the short-circuiting switch circuit 4 is switched to the off state, the outputs OUT1 to UT6 from the output pad 42 are output to the corresponding source line 22. Therefore, when the polarity inversion and the charge sharing are required, the determination circuit 43 can perform the polarity inversion and the charge sharing only by outputting the control signal Ctrl_REV and the control signal Ctrl_CS to the polarity switching control circuit 44 and the output short circuit control circuit 45. . Here, in the data signal line driver 30, the judging circuit 43 judges whether or not polarity inversion and charge sharing, that is, the control signal Ctrl-REV, is required based on the input image data (grayscale data Data[7: 〇]). And whether the output of the control signal Ctrl_CS is valid. Next, the detailed configuration and operation of the judging circuit ^ will be described in order. FIG. 3 shows an example of the configuration of the determination circuit 43. As shown in FIG. 3, the judging circuit 43 includes a pattern detecting circuit 1 〇 1, and a polarity inversion and charge sharing decision circuit 102. 148936.doc -26· 201106332 The pattern detection circuit 101 is as follows: 盥" ° and 土 丰 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 In the judgment result of the black and white combination pattern of the adjacent output pair, the majority (majority) is used as the above-mentioned standard, and the information indicating the gray order of the black display is CHt-Black[2: 〇], indicating that the judgment is made. The number of gray scales displayed for white = poor material Cdt_White[2: 〇], and the poor material Cdt_Ma>rity[2: G] which determines the number of settings of the majority. Also, the pattern detecting circuit (8) is also individually The control signal SRA · SRB · is input. Further, the adjacent output pair corresponds to the output 0UT1 · _2 of the data signal line driver 30, the output 〇υτ3· 〇υτ4, and the output OUT5 · 0UT6. The combination of black and white is "black", "white", "little white, "occupied, m ^ _ ... 臼" white and black". The pattern detecting circuit 101 detects the combination pattern of the majority according to the combination pattern of the black and white of each of the output lines of the horizontal line. As a result, "black" is indicated as "white" as the flag of the majority flag flgMB W, and the pattern detecting circuit 101 is based on the detection of the majority flag flgMBB, the table flgMWW, and the "black and white" White black is the majority flag flgMWB, which is output to the polarity inversion and charge knife-breaking circuit 102. When black is the majority, the mark is "1", when it is the majority, the mark f][gMWW becomes "i", when the black and white is the majority, the mark flgMBW becomes "丄", and when the black is the majority, the mark flgMWB becomes "i" "." When there is no majority, all tags become "0". The polarity inversion and charge sharing decision circuit 1〇2 determines whether or not a circuit for polarity inversion and charge sharing is required according to the majority of the detection results of the pattern detecting circuit 148936.doc -27-201106332 101. The polarity inversion and charge sharing determination circuit 102 uses the flag f]gMBB · ngMww· flgMBw • flgMWB outputted from the pattern detecting circuit 1〇1 to combine the combination pattern of the majority of the previous line with the majority of the current line. By comparison, the pattern of the image of the frame is identified to determine whether polarity inversion and charge sharing are required. Further, a control signal ps is also input to the polarity inversion and charge sharing determining circuit 102. The polarity inversion and charge sharing determination circuit 1〇2 outputs the control signal Ctrl_REV and the control signal ctd_cs to the polarity switching control circuit 44 and the output short-circuit control circuit 45, respectively, based on the determined result. The control signal Ctrl_REV becomes Γι" when the polarity is reversed, and the control signal ctrl_cs becomes "0" when the charge sharing is performed. FIG. 4 shows an example of the configuration of the pattern detecting circuit 101. As shown in FIG. 4, the pattern detecting circuit 101 includes a black collating circuit m (display state judging means), a white collating circuit 112 (display state judging means), D_FF (D 邛, d-type flip-flop) 113, D-FF 114, The pattern comparison circuit 115 (display pattern creation mechanism), the counters 116 to 119, and the majority control circuits 120 to 123 (majority determination means). The black control circuit ill compares with the data Crit_Black[2: 〇] and checks the grayscale data Data[7: whether the funeral is a black display circuit. The black control power: 111 outputs the flag _ indicated as black display to the D-FF113&® case control circuit 115 based on the result of the check. When the black mark is marked as "1", the mark flgB becomes "〇". ... 148936.doc -28- 201106332 White control circuit!! The 2 series is compared with the data Crit_White[2: 〇] and the check 112 is based on the result of the check, and the white display mark is indicated to the D-FFU4 and ffl case comparison circuit. 115. When it is white, the mark is set to "1", and in other cases, the mark flgB becomes "〇". The D-FF 113 and the D-FF 114 lock the outputs of the black collation circuit 111 and the white collation circuit 112 in accordance with the input timing of the control signal SRA. That is, 〇邛^3 locks the value of the flag flgB and holds it as the data regB. Lock the value of the marker figw' and keep it as the data regW. D_ffii3&d_FF丨14 rotates the held data regB and data regW to the pattern control circuit 115. The pattern matching circuit 115 compares the mark flgB · flgW indicating the zero display and white display checked based on the current gray scale data, and the data regB · regW indicating the black display and white display checked based on the previous gray scale data. According to the result, the pattern matching circuit 115 outputs a flag flgBB · flgWW · flgBW . flgWB indicating that the pattern of the gray scale data of the corresponding output pair is black, white, white, black and white, and flgWB, respectively, to the counters 116 to 119. In the case of a black and black pattern, the mark flgBB becomes "i", in the case of a white pattern, the mark flgWW becomes "1", and in the case of a black and white pattern, the mark flgB W becomes "1", and in the case of a white and black pattern, the mark flgWB becomes "1". All tags become "〇" when there is no match. The gray-scale data Data[7:0] is the data obtained from the gray-scale data input from the external application, and k is used for the gray-scale data corresponding to all the output terminals. The D-FF 113 and the D-FF 114 respectively lock the values of the mark flgB and the mark 148936.doc •29-201106332 flgW according to the control signal SRA, and then supply the next gray level data Data[7: 〇] to the data bus. The data regB and the data regW locked by the 'D-FF113 and D-FF114 can be used as the data indicating the black display and the white display according to the previous gray scale data, and the input of the D-FF 113 and the D-FF 114 can be input. That is, the mark flgB and the mark §flgW are used as marks indicating black display and white display according to the current gray scale data. The counters 116 to 119 are incremented by counting the flag flgBB · flgWW · flgBW when the output is displayed in accordance with the input timing of the control signal SRB. As the counters U6 to U9, CNT (CouNTer, counter) 2〇7 is used. The control signal SRB is output after the value of the mark ^fgWW · flgBW · flgWB is determined. The counters 11 6 to 119 output data to the majority control circuit 120 which respectively represent the 8-bit data of the count value cntBB[7 : 〇] · cntWW[7 : 0] · cntBW[7 : 0] · cntWB[7 : 0] ~ 123. The majority comparison circuit 120 to 123 compares with the data Crit-Majority[2: 〇], and checks whether the count value output from the counters 116 to 119 is equal to or greater than the number set in the data Crit-Majority[2:0]. . When the count value is equal to or greater than the set number, the majority control circuits 120 to 123 output the flag flgMBB · flgMWW · flgMBW · flgMWB indicating the majority to the polarity inversion and charge sharing decision circuit 102. Furthermore, the actions of the counters 116 to 119 are in accordance with the level! The output of the line is performed on the quantity. Input the control signal of the rST terminal of the counter 1164! 9 LS ′ is relative to! The display of the line is output when the data signal line driver 3 starts outputting. If the control signal LS is input, the counters 116 to 119 148936.doc -30- 201106332 are reset and the count value is cleared. FIG. 5 shows an example of the configuration of the black comparison circuit 111. As shown in FIG. $, the exclusive circuit 3 includes a logic circuit 13 1 , OR circuits 13 2 to 13 6 , an AND circuit 137 , and an AND circuit 138 . The logic circuit 131 determines the display as a black gray order based on the value of the data Crit-Black[2:0]. The logic circuit 13 outputs the data 〇PE to the AND circuit 138' according to the result of computing the data Crit_Black[2: 〇] according to the predetermined true value, and outputs the data N_EnaMe[4: 〇] to the 〇r circuit respectively. 132~136. The OR circuits 132 to 136 output the result data of the gray-scale data Data[4: 〇] and the data N_Enable[4:0] to the AND circuit 137. The AND circuit 137 outputs the result data obtained by performing AND operations on the data Data [7: 5] and the outputs of the 〇r circuits 132 to 136 to the and circuit 138. The AND circuit 138 outputs the result data obtained by performing AND operation on the data 〇pE from the logic circuit 131 and the output of the AND circuit 137 as the flag flgB. FIG. 6 shows a truth table of the logic circuit 131. The data Crit_Black[2 : 〇] is a 3-bit data. When 0 (000H) and 7 (111H), the output data 〇pE is set to "〇", and the other data is set to "1" at 1~6. "." The value of the data Cnt_Black[2 : 〇] can be set and changed by inputting the data from the input buffer to the setting register. [S] When the data Crit_Black[2 : 〇] is 1 (001H), the data N_Enable[4. : 〇] becomes (〇〇〇〇〇H). Therefore, when the OR circuits 132 to 136 having the data N_Enable[4 . 〇] are input, the output becomes "1" when the grayscale data Data [4] to 148936.doc .31·201106332 is (1). Therefore, the AND circuit 137 outputs "1" only when the gray-scale lean material Data[7: 〇] is 255 (1 1 1 11 11 1H). As a result, the data 〇PE is "丨", so the output of the AND circuit 138, that is, the flag flgB becomes r丨". Therefore, if the data Crit_Black[2 : 〇] is set to i, when the grayscale data Data[7 : 〇] is 255, the flag _ becomes "丨". That is, it is judged to be black only when the gray scale data of the gray scale is used. Thus, the logic circuit 13 1 returns 1 when the gray scale data Data[7: 〇] is black or near black, and returns 〇 when otherwise. The criterion for judging that the grayscale is black or close to black is

When Data>255-X, flgB = l (determined as black or near black) In addition to this, flgB = 0 (determined to be not black). Furthermore, it is determined by the setting of the data Crit-Black[2:0] that the gray order numbers 1 to 32 of the black are corresponding to the gray scale number X regarded as the flowchart of FIG. 14 described below. . In the data signal line driver 3, the set number of history can be set to 1, 2, 4, 8, 16, 32. FIG. 7 shows an example of the configuration of the white comparison circuit 112. As shown in Fig. 7, the white control circuit 112 includes a logic circuit 141, AND circuits 142 to 146, a NOR circuit 147, and an AND circuit 148. The logic circuit 141 calculates the gray scale according to the value of the data Crit_White[2: 〇]. The logic circuit 141 outputs the data 〇pE to the AND circuit 148 based on the result of computing the data Crit_White[2:0] in accordance with the predetermined true value, and outputs the data N_Enable[4: 〇] to the AND circuits 142 to 146, respectively. 148936.doc •32· 201106332 The AND circuits M2 to M6 output the result of the AND operation of the grayscale data Data[4: 〇] and the data N_Enable[4:0] to the n〇r circuit 147. The shame circuit 147 outputs the result of the N〇R operation to the gray-scale data 〇 [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ Information opE, and

The result of the AND operation of the output of the N〇R circuit 147 is output as the flag flgW. FIG. 8 shows a truth table of the logic circuit 141. The data CHt-white[2: 〇] is the data of 3 bits. When 〇(〇〇〇H) and 7(1uh), the output data is set to “〇”, otherwise 1~6 Set the output data 〇ρΕ to Γι”. The value of the data Crit_White[2. 〇] can be set and changed by inputting the data of the hex 6 into the setting register 46. When the Crit_White[2: 〇] is ι(〇〇1Η), the data N-Enable[4 . 〇] becomes (1) UlH). Therefore, the AND circuit 142 to 146 having the data N_Enable[4 . 〇] is input to the gray scale data by ^(4) to

When Data[〇] is 〇", the output becomes "0". Therefore, the NOR circuit 147 outputs 1" only when the gray P white material Data[7:0] is 0 (〇〇〇〇〇〇〇〇H). As a result, the data is "!", so the output of the AND circuit 148, that is, the flag flgW becomes "丨". Therefore, when the data Crit_White[2: 〇] is set to 1 on the right, when the grayscale data Data[7 · 〇] is 〇, the label is marked as "^". That is, it is judged to be white only when it is gray scale data of the gray scale. Further, the poor material Crit_White[2: is set to 2 (the case of N1, the data N-Enable[4: 〇] becomes (1) n〇H). Therefore, the input is [s 148936.doc •33-201106332 material N-Enable[0] AND circuit I46 Since the data N_Enable[〇] is "〇", the output always becomes "ο". Thus, when the grayscale data Data[7: 〇] is O(OOOOOOOOOH) and Ι(ΟΟΟΟΟΟΟΙΗ), the flag f丨gW becomes "1". That is, it is determined to be white only in the gray scale data of 1 gray scale and 2 gray scale. Similarly, when the data Crit-White[2 ··〇] is set to the emotional element of 3 (〇11H), the gray scale data Data[7 · 0] is 〇~3, and the gray scale is determined to be 4 gray scales. The 4th gray scale is white. When the data Crit_White[2:0] is set to 4 (100H), when the grayscale data Data[7:0] is 〇~7, the gray scale of 1 grayscale to 8 grayscale is determined to be white. When the data Crit-White[2:0] is set to a shape of 5 (101H), the gray scale data Data[7:0] is 〇~15, and the gray scale of 1 gray scale to 16 gray scale is determined. For white. When the data Crk-White[2: 〇] is set to 6 (11〇H), when the gray-scale data Data[7:0] is 〇~31, the gray scale is from 32 gray scales to 32 gray scales. The judgment is white. Thus, the logic circuit 141 returns 1 when the grayscale data Data[7: 〇] is white or near white, and returns 〇 when otherwise. The criterion for determining whether the gray scale is white or close to white is, when Data<Y, figw = 1 (determined to be white or close to white), and fgW = 〇 (determined to be not white). Further, the gray scale numbers 1 to 32 which are determined to be white by the setting of the data Crit_White[2:0] correspond to the gray scale number Y which is regarded as white in accordance with the setting of the flowchart 1 of Fig. 14 described below. The set number Y can be set to 1, 2, 4, 8, 16, 32 in the data signal line driver 3'. Fig. 9 shows an example of the configuration of the pattern matching circuit 11$. As shown in Fig. 9, the pattern pair, circuit 115 includes AND circuits 151 to 154. 148936.doc •34- 201106332 The AND circuit M1 is based on the result of the black-and-white mark flgB determined by the current gray-scale white shellfish and the AND operation by the previous gray-scale data regB: the table 7F black The output is displayed with the flag flgBB. The AND circuit 152 performs the result of the Na-based operation on the mark flgW which is displayed by the current grayscale data and the data regW which is displayed by the white color of the previous grayscale data. (4) (4) . The coffee circuit 15 3 is based on the result of the AND operation of the mark flgB indicating the black display by the current gray scale data and the data regW judged by the previous gray scale data. And the input, the output & 3 has flgB W. The AND circuit 1 5 4 is based on the mark ngw which is determined by the current gray scale data and the black display is determined by the previous gray scale data. The result of the AND operation is output, and the flag is output. Fig. 1A shows the state of the input and output of the pattern matching circuit 115 in the display state of the adjacent output pair. For example, the output state of the adjacent output pair is " In the case of black and black, the input system mark _ and the data ring are "!", and the output system mark flgBB is %. Further, when the display state includes a case where it is determined that it is not "black or white" (others), all the outputs of the output system are 0". Further, the state other than the state shown in Fig. 10 does not exist at 0. Here, the data signal line driver 30 is designed as the 414 output circuit, so that the output 斟m, the bamboo green, and the - output pair are 207. Therefore, the maximum count value of the counters 116 to 119 is 207. Therefore, in this state, the flag flg outputted by the multi-190 ^ b r squad control circuit 23 is always "〇". Therefore, the count of crying n6~m is 152 after the juice number (8), and the state of the input 148936.doc •35·201106332 is (11111111H) by the counting of 2Q7. Figure 11 shows the truth table of the counters 116 to 119. The number of counts is 1〇3, which is a normal 8-bit counter. The bit inversion is performed at the time of counting 105, and the state of the output 8-bit of the count number 104 is set to i52 (1〇〇u〇〇〇h). . Thereby, at the time of counting 207, the state of the output 8-bit becomes 255 (11 1 1 11 11η). In this way, the value of the counter is changed. Therefore, if the data Crit_Maj〇rity [2:0] is set to 1, the majority control circuit 12〇123123 sets the flag fi to "1" as the majority when the number of counts is 2〇7. send. Further, when the data CritJVIaj〇rity[2:0] is set to 2, the majority control circuits 12〇 to 123 have the flag fi as "i" as the majority when the count number is 206 or more. When the data Crit_Maj〇rity[2:0] is set to 3, the majority control circuits 120 to 123 set the flag fi to "1" as the majority when the count number is 204 or more. When the data Crit_Majority[2: 〇] is set to 4, the majority control circuits 120 to 123 set the flag flg to "1" as the majority when the number of counts is 200 or more. When the data Crit_Majority[2··0] is set to 5, the majority control circuits 120 to 123 set the flag fi to "1" as the majority when the number of counts is 192 or more. If the data (: one; \^〗 〇 1^ 丫 [2: 〇] is set to 6, the majority control circuits 120 to 12 23 set the flag fi to "1" as the majority when the count number is 176 or more. Furthermore, the 'majority comparison circuit 120 to 123 can be realized by the same configuration as the black comparison circuit m. That is, in the configuration shown in FIG. 5, the input is replaced instead of the gray scale data Data [7 . 0]'. Count value information cntBB[7 : 〇] · cntWW[7 : 0] · cntBW[7 : 〇] · cntWB[7 : 〇], and instead of the data Crit_Black[2 : 〇] ' and enter the data Crit_Majority[2 : 〇 148936.doc • 36 - 201106332 Yes, the output of the AND circuit 138 is indicated as the majority flag flgMBB · flgMWW · flgMBW · flgMWB. Also, the majority of the data Crit_Majority[2:0] is determined as the majority. The set value of the set is the set value Z of the majority determined in accordance with the setting of the flow chart 2 of Fig. 15 below. In the data signal line driver 30, the set number Z can be set to 1, 2, 4, 8, 16, 32. Further, the value of the data Crit_ Majority [2: 0] can be set by inputting the data of 1 to 6 to the setting register 46. Fig. 1 2 shows an example of the configuration of the polarity inversion and charge sharing determining circuit 102. As shown in Fig. 12, the polarity inversion and charge sharing determining circuit 102 includes D-FFs 161 to 163 (holding means) and an AND circuit. 164 to 166 (control signal output means), OR circuit 167 · 168 (control signal output means), and D-FF 169 · 170 (control signal output means). D-FF 161 to 163 are locked according to the input timing of the control signal PS. The output of the pattern detecting circuit 10 1 is the value of the flag flgMBB · flgMBW . flgMWB. That is, the D-FF 161 locks the value of the flag flgMBB and holds it as the data regMBB. The D-FF 162 locks the value of the flag flgMBW and serves as the data. regMBW is maintained. D-FF163 locks the value of the flag flgMWB and holds it as data regMWB. D-FF161~163 outputs the held data regMBB · regMBW · regMWB to AND circuits 164~166 respectively. AND circuit 164 will be The result of the AND operation of the flag flgMWB determined based on the obtained 1 line gray scale data and the data regMBW determined based on the previously obtained 1 line gray scale data is output to the OR circuit 148936.doc -37-201 106332 i67. The AND circuit 165 outputs the result data obtained by performing the AND operation on the flag flgMBW of the Hurricane gray-scale data acquired according to the current acquisition and the data regMWB determined based on the previously obtained stroboscopic gray-scale data to the 〇r circuit 167. . The AND circuit 166 outputs the result data obtained by performing AND operation on the flag HgMWW determined based on the obtained gray scale data of the current time and the data regMBB determined based on the gray scale data acquired the previous time, to the circuit 168. The OR circuit 167 outputs the result data obtained by ORing the output of the AND circuit I64 and the round of the AND circuit 10S to the D-FF 169, and outputs the 2 OR circuit 168. The OR circuit 168 outputs the result data of the OR operation of the output of the OR circuit 167 and the output of the AND circuit 166 to D FFi7 . The D-FF 169 latches the output of the 〇R circuit 167 in accordance with the input timing of the control signal PS. Further, the 'D-FF 169 outputs the held data as the control signal Ctrl_REV to the polarity switching control circuit 44. The D-FF 170 locks the output of the R circuit 168 in accordance with the input timing of the control signal PS. Further, the 'D-FF 170 outputs the held data as the control signal Ctrl_CS' to the output short-circuit control circuit 45. The above information regMBB · regMBW · regMWB indicates the majority of the combination pattern in the grayscale data of the previous scan line. If the data regMBB is "1", the display of the previous line is black and the majority. If the regMBW is "1", the black and white is the majority. If the data regMWB is "1", the white is the majority. On the other hand, the mark flgMBB · flgMWW · flgMBW . flgMWB represents the combination pattern of the majority of the gray scale data of the current scan line. If the standard 148936.doc • 38 · 201106332 ° has flgMBB of “1”, it means black and black is the majority. If the mark flgMWW is “1”, it means that it is white. If the mark flgMBW is “丨”, it will not be black and white. The majority 'if the mark flgMWB is "]" means that the white is the majority. The data regMBW and the flag flgMWB are input to the AND circuit 164, and the field is black and white for the majority, and the current line is the black and white for the majority. The AND circuit 165 inputs the data regMWB and the flag flgMBW. Therefore, the current line is black and white for the majority, and the current line is black and white for the number of times. The ANd circuit 166 inputs the data = mbb and the flag flgww. Therefore, the current line system black is the majority, and when the w line system is white, the output becomes "i. The output of the input circuit 164 in the 0R circuit 167 and The output of the circuit 165 is such that either the output of the tAND circuit 164 and the output of the nano circuit 5 are "when, the turn is 1". That is, the current line system = the majority, the current line system is the majority, or the previous line is white ... for the eve, and the current line is black and white for the majority, the output becomes M". The output state of the OR circuit 167 becomes the control signal Ctrl_REv by the input timing of FF1.〇..w+1, 仡唬pS by D_•negative. 〇R Thunder is input to the circuit 168 - the output of the R circuit 167 and the output of the AND circuit 166 are recognized, so when the output of any of the R circuits 167 A and the circuit 166 are turned out, p The current line system is white for the eve, the current line is black and white, 丫r, and the occupant is a line of white and black. Most of the lines are black and white for the majority, and the leader is ^, Ί A ... The second one is - the black and white is the majority, and the line is white when it is the majority. The OR circuit 148936.doc 201106332 168 is turned on by the input timing of the control signal PS by D_FF17 (^* is held as the control signal Ctrl_CS. The control signal Ctrl_REV is a signal that causes the polarity switching control circuit 44 to operate to perform polarity inversion. Therefore, when the output of the OR circuit 167 is "i", that is, if the black line is a majority, the current line is black, the majority is black, or the current line is black and white, and the current line is black and white. The polarity is reversed. The control 彳§ Ctrl_CS causes the output short-circuit control circuit 45 to operate to perform the signal of charge dispersion. Therefore, when the 0R circuit 丨68 is "丨", the previous line is black and white, and the current line is black and white. Line black is the majority, the former line is black and white is the majority, the current line is black and white is the majority, or the front line is black and the majority, and the current line is white, the charge is shared. If the control signal PS is input, the control signal Ctd_rev and the control signal Ctrl_CS are locked, and the data regMBB · regMBw · regMWB is locked. Thus, by this action, the data regMBB · regMBw · re The gMWB becomes a preparation for comparing the state of the majority of the current line with the information of the majority of the lower line. Next, in the source block inversion driving, the data signal line driver 30 detects the pattern and changes it as needed. Fig. 13 is a flow chart showing the processing flow of the data signal line driver 3 when the one side is displayed. X ' Fig. 14 shows the processing flow shown in Fig. 13 Fig. 1. Fig. 15 shows a flow chart 2 executed by the processing flow shown in Fig. 13. In the case of display, , θ, 月, 旰, as shown in Fig. 13, first, the data signal line drive 148936.doc The 201106332 actuator 30 sequentially acquires the gray scale data Data[7: 〇] of the first line which is displayed in the image data of one side by the shift register 3 and the data latch 32 (step S201). By the operation of the lock latch 34, the level shifter 35, the positive polarity side DAC 36' negative polarity side DAC 37, the positive polarity operational amplifier %, and the negative polarity operational amplifier 39, via the output pad The slice 42 outputs a data signal to the source line 22. Moreover, The data signal is applied to the pixel electrode 24' of the first line, and the liquid crystal panel 20 is displayed (step § 203). Further, the gray scale data Data [7: 0] corresponds to the driving mode of the liquid crystal panel 2 The sequence is output to the data bus. Here, the liquid crystal panel 2 is set as the source block inversion driving. On the other hand, the judging circuit 43 is based on the gray scale data of the i-th line to [7: 0]. The processing shown in the flowchart of FIG. 14 and the flowchart 2 of FIG. 15 is performed, and a combination pattern of black and white of adjacent output pairs in the gray line data Data[7:0] of the first line is inspected. Thereby, the data regMBB · regMBW · regMWB representing the majority of the combination of the second line is obtained (step S202). The processing of step S202 will be specifically described. As shown in FIG. 14, first, the reference value necessary for the processing of the determination circuit 43 (the number of gray scales = n, the gray scale of black as = χ, the gray scale of white as 白 = Υ) is set in advance (step S23 1) ). For example, when the 256 grayscale side of the 256 grayscale is black, the grayscale is regarded as 8 (χ=8, then 248 grayscale to 256 grayscale is black. Similarly If the gray order number of white is set to 8 (Υ=8), it is judged that the 1 gray scale to the 8 gray scale is white. Further, in the judgment circuit 43, the processing is performed with respect to the previous line. · flgWW · flgBw · The number of occurrences of flgWB is maintained in the counters 116 to 119 of the 2011/201106332 case detection circuit 101. Therefore, the control signals 1^ are reset by giving the counters 116 to 119. Mark print 8.^|琛· HgBW. The number of occurrences of flgWB (step S232) e Then, in the output pair, the gray scale data corresponding to the output of the first output is set to K ' It is set to L (step S233), and the judgment circuit 43, that is, the black control circuit 111 of the pattern detection circuit 1 and the white control circuit 112 checks whether the data of κ and L is black or white. Check K and L. After the data, the judgment circuit 43, that is, the pattern comparison circuit 115 determines whether "K>nX" and "L>nX" (K) are satisfied. L· is black) (Step 5234) ° When "K>nX" and "L>nX" are satisfied (YES in step S234) 'The pattern matching circuit 115 determines that the combination pattern is "black black" and marks flgBB Set to "1" and increment the count value of the counter 116 (step 5235). Then the 'decision circuit 43 checks if the output pair is the last (step S242), and when it is the last (YES in step S242), the turn map The processing of the flowchart 2 of 15 is 'when it is not the last (NO in step S242), the output of the next segment is moved to the data (step S243)' and returns to step S233 to perform the combination pattern of the next output pair. On the other hand, when the condition of "K>nX" and "L>nX" is not satisfied (NO in step S234), the pattern matching circuit 115 then determines whether or not "K<Y" and "l<Yj" are satisfied. (K and L are white) (step S236). When the "K<Y" hill "L<Y" is satisfied (YES in step S236), the pattern matching circuit 115 determines that the combination pattern is "white" and marks 148936.doc • 42· 201106332 ngww is set to "1" and counts The count value of 117 is incremented (step S237). Then, the judging circuit 43 similarly checks whether the output pair is the last (step S242), and proceeds to the next process. On the other hand, if "K<Y" is not satisfied and rL< In the case of Y" (NO in step S236), the pattern matching circuit U5 next determines whether "K>nX" and "L<Y" (K is black and l is white) is satisfied (step S238). When "K>nX" and "L<Y" are satisfied (YES in step S238), the pattern matching circuit 115 determines that the combination pattern is "black and white", sets the flag flgBW to "1", and causes the counter 118 to The count value is counted (step S239). Then, the judging circuit 43 similarly checks whether the output pair is the last (step S242), and proceeds to the next processing. On the other hand, when the condition of "K>n_X" and "L<Y" is not satisfied (NO in step S238), the pattern matching circuit U5 then determines whether "K<Y" and "L>nX" (K) are satisfied. It is white and L is black) (step S24〇). When "K<Y" and "L>nX" are satisfied (YES in step S24), the pattern matching circuit 115 determines that the combination pattern is "white black", sets the flag flgWB to "丨", and causes the counter The count value of 119 is incremented (step S241). Then, the judging circuit 43 similarly checks whether the output pair is the last (step S242), and proceeds to the next processing. On the other hand, in the case of "K<Yj and "L>n_x" (NO in step S240), the judging circuit 43 judges that the combined pattern of the output pair is not black, white, black, white, or black. Either way, it is checked whether the output pair is the last (step S242), and proceeds to the next processing. In this way, the judging circuit 43 executes the flowchart of FIG. 14 and determines the combination pattern with respect to the 148936.doc -43-201106332 of the squall line, and displays the combination pattern for the black line when the black line is displayed in the one line, and when the display is white, When black and white is displayed, the number of occurrences when white and black is displayed is counted. Then, the judging circuit 43 executes the flowchart 2 of Fig. 15 to check which combination pattern appears multiple times. As shown in Fig. 15, in order to set how much the pattern is generated in the one line, it is regarded as a majority occurrence, and the set value of the majority is determined in advance = Z (step S261). Thus, if the total number of output pairs is set, the majority number is expressed by m - Z. For example, the data output at 414 is used as the line driver 30, m = 207, and when Z is 16, the majority number is 2 〇 7 · 16 = 191. Then, the majority circuit control circuit 120 of the determination circuit 43, i.e., the pattern detection circuit 1, determines whether or not "flgBB (the number of occurrences of black and black patterns) > m_Z" is satisfied (step S262). When "flgBB>m-Z" is satisfied (yes in step S262), the majority control circuit 120 determines that the black and black pattern is a majority and sets the flag flgMBB to "1". Further, the D-FF 131 of the polarity inversion and charge sharing decision circuit 102 locks it, whereby the data regMBB becomes "i". Further, the data regMWW · regMBW · regMWB becomes "〇" (step S263). Obtaining the result, the judging circuit 43 returns to the processing of the flowchart of Fig. 13. On the other hand, when the "flgBB>m-Z" is not satisfied (NO in step S262), the majority control circuit 120 then determines whether or not "flgWW (the number of appearances of the white pattern) > m-Z" is satisfied (step S264). When "flgWW>m-Z" is satisfied (YES in step S264), I48936.doc -44 - 201106332 The majority control circuit 120 determines that the white pattern is a majority and sets the flag flgMWW to "1". Moreover, the data regMWW becomes "1" by this. Further, the data regMBB . regMBW · regMWB becomes "0" (step S265). Obtaining the result, the judging circuit 43 returns to the processing of the flowchart of Fig. 13. On the other hand, when the "flgWW>m-Z" is not satisfied (NO in step S264), the majority control circuit 120 then determines whether or not "flgBW (the number of occurrences of the black and white pattern) > m-Z" is satisfied (step S266). When "flgBW>m-Z" is satisfied (YES in step S266), the majority control circuit 120 determines that the black and white pattern is a majority and sets the flag flgMBW to "1". Moreover, the D-FF 132 locks it, whereby the data regMBW becomes "1". Further, the data regMBB · regMWW · regMWB becomes "0" (step S267). Obtaining this result, the judgment circuit 43 returns to the processing of the flowchart of Fig. 13. On the other hand, when the "flgBW>mZ" is not satisfied (NO in step S266), the majority control circuit 120 determines whether or not "flgWB (the number of occurrences of the black and white pattern) > mZ" is satisfied (step S268). . When "flgWB>m-Z" is satisfied (YES in step S268), the majority control circuit 120 determines that the black and white pattern is a majority and sets the flag flgMWB to "1". Moreover, D-FF133 locks it and the data regMWB becomes "1". Further, the data regMBB · regMWW · regMBW becomes "0" (step S269). Obtaining this result, the judgment circuit 43 returns to the processing of the flowchart of Fig. 13. On the other hand, when "flg\VB>m-Z" is not satisfied (NO in step 148936.doc -45 - 201106332 S268), the judging circuit 43 judges that there is no combined pattern of the majority. Thereby, all the data regMBB · regMWW · regMBW · regMWB becomes "0" (step S270). Moreover, the result is obtained, and the judging circuit 43 returns to the processing of the flowchart of Fig. 13. Thus, the judging circuit 43 obtains the value of the data regMBB · regMBW · regMWB (step S202 of Fig. 13). Furthermore, the processing of step S202 can be performed every time the gray scale data is obtained, or after all the 1 line gray scale data is acquired. Then, the judging circuit 43 acquires gray scale data Data[7:0] for displaying the line of the next segment (step S204). Further, the judging circuit 43 judges the combined pattern with respect to all the output pairs of the one line using the acquired gray scale data Data[7:0], and displays black and white when the black line is displayed in the one line, and displays black and white, and displays black and white. The number of occurrences when the time is displayed in white and black is counted. Thereby, the value of the number of occurrences of the mark flgBB · flgWW · flgBW . flgWB is obtained (step 5205). The acquisition operation of this number of occurrences is the same as the operation of the flowchart 1 of Fig. 14. Then, the judging circuit 43 checks which combination pattern appears multiple times. The judging action of the majority is the same as that of the flowchart 2 of Fig. 15. Determine the majority setting = Z, the total number of output pairs = m is set before use (step 5206). Next, the judging circuit 43, i.e., the majority of the pattern detecting circuit 101, determines whether or not "flgBB (the number of occurrences of black and black patterns) > m-Z" is satisfied (step S207). When "flgBB>m-Z" is satisfied (YES in step S207), 148936.doc - 46 - 201106332 The majority control circuit 120 determines that the black and black pattern is a majority and sets the flag flgMBB to "1". In this case, when the display of the one line output is black and black, the judging circuit 43 judges that the polarity reversal and charge sharing of the output are not required. Thereby, the liquid crystal panel is displayed without changing the display method (step S216). Further, the D-FF 131 of the polarity inversion and charge sharing decision circuit 102 locks the flag flgMBB, whereby the data regMBB becomes "1". Further, the data regMWW · regMBW · regMWB becomes "0" (step S217). That is, the value of the data regMBB . regMWW . regMBW · regMWB is changed by the value of the mark flgMBB · flgMWW · flgMBW · flgMWB obtained by the line of the next paragraph. After obtaining the result, the judging circuit 43 judges whether or not the acquired data is the final line (step S2 18). In the case of the final line (YES in step S21), the judging circuit 43 ends the processing. When it is not the case of the final line (NO in step S2 18), the process returns to step S204, and the judging circuit 43 sequentially acquires the gray scale data of the line of the next segment and processes it in the same manner. On the other hand, when "flgBB>m-Z" is not satisfied (NO in step S207), the majority control circuit 120 then determines whether or not r flgWW (the number of occurrences of the white pattern) > m-Z is satisfied (step S208). When "flgWW>m-Z" is satisfied (YES in step S208), the majority control circuit 120 determines that the white pattern is a majority and sets the flag flgMWW to "1". Further, the judging circuit 43, that is, the AND circuit 136, judges whether or not the data regMBB obtained from the previous line is "1" (step S209) ° 148936.doc 47 - 201106332 when the data regMBB is "1" (step s2 〇 9) In the middle, YES), that is, when the output of the one line is white and the majority is displayed, and the display of the previous line is black and black, the judgment circuit 43 judges that charge sharing is required. Thus, the control signal ctrl_cs from the D-FF 140 becomes "1", and charge sharing is performed (step S21 0). Thereby, the display method is changed in such a manner as to perform charge sharing, and the liquid crystal panel performs display (step S216). Moreover, by this information regMWW becomes "丨". Further, the data regMBB • regMBW • regMWB becomes “〇” (step S2n). In the case where the data regMBB is "〇" (N〇 in step S2〇9), the liquid crystal panel displays without changing the display method (step S216), and the determination circuit 43 acquires the above-described material (step S217) e and After the result is obtained, the determination circuit 43 similarly determines whether or not the acquired data is the final line (step s2i8), proceeds to the next process, or ends the process. On the other hand, when the condition of "flgWW>m_z" is not satisfied (NO in step S208), the majority control circuit 12 determines whether or not flgBW (the number of occurrences of the black and white pattern) > m Z" is satisfied (step. When the condition of flgBW > mZ is satisfied (YES in step S2U), the majority control circuit 120 determines that the black and white pattern is a majority, and the flag flgMBWa is again "lj. Moreover, the determination circuit 43, that is, the AND circuit 135 determines Whether the data regMWB obtained in the previous line is "丨" (step S212). When the regMWB is "1" (YES in step S212), the display of the i-line output is black and white. The display of the previous line is from the black > number of facts 'Rhythm circuit 43 judges the need for polarity reversal and 148936.doc •48- 201106332 charge sharing. Thus, the control signal ctrl_REV from D-FF139 becomes "1" And the control signal ctd_cs from the D-FF 140 becomes "丨", and polarity inversion and charge sharing are performed (step S213). Thereby, the display method is changed by performing polarity inversion and charge sharing, and the liquid crystal panel performs display (step S216) Further, the D-FF 132 of the polarity inversion and charge sharing determining circuit 1〇2 locks the flag flgMBW, and the data regMBW becomes "1". Further, the data regMBB • regMWW · regMWB becomes "0" (step S217). When the data regMWB is "0" (NO in step S212), the liquid crystal panel displays without changing the display method (step S216), and the determination circuit 43 acquires the above-described data (step S217). After that, the determination circuit 43 similarly determines whether or not the acquired data is the final line (step S218) 'to proceed to the next process, or to end the process. On the other hand, when the situation of "flgBW>mZ" is not satisfied (step S211) Is NO), the majority sends a comparison circuit 12 to determine whether it is satisfied

HgWB (the number of occurrences of the white-and-black pattern) > ιη_ζ" (step S214). When "flgWB>m-Z" is satisfied (YES in step S2i4), the majority control circuit 120 determines that the pattern of white and black is a majority, and sets the flag flgMWB to "1". Further, the determination circuit 43, that is, the AND circuit 134 determines whether or not the data regMBw acquired from the previous line is "1" (step S215) = when the data regMBW is "1" (YES in step S215), that is, the output When the display of the first line is white and black, and the display of the previous line is black and white, the judgment circuit 43 judges that polarity inversion and 148936.doc -49·201106332 charge sharing are required. Thereby, the control signal ctd_rev from the D_FF 139 becomes "1"', and the control signal CtrLCS from the D-FFMO becomes "丨", and polarity inversion and charge sharing are performed (step S213). Thereby, the display method is changed in such a manner that polarity reversal and charge sharing are performed, and the liquid crystal panel performs display (step S216). Further, the polarity inversion and charge sharing decision circuit 1〇2 deletes and locks the mark, whereby the data regMWB becomes Γι”. In addition, when the data re_w is "〇" (in the step - N), the data sheet W is displayed as "〇" (step S217), and the liquid crystal panel is displayed without changing the display method (step). The judging circuit 43 acquires the above information (step S217). Further, after obtaining the result, the judging circuit 4 3 similarly judges whether or not the acquired data is the final line (step S218), and proceeds to the processing, or ends the processing. When the display of the data signal line driver is performed, the data signal is outputted as a display, and on the other hand, the polarity inversion and charge sharing are repeated until the final line is determined. Here, in the above-mentioned processing, there is also a case where the display of the first line of the output is one of the black lines of the majority, the previous one and the line of the strong line is not the white, and the output is The display of the 1st line is the eve of the 'white'. The display of the first line and the display of the front line are black and white for the majority of the sculpt. The time is judged to require polarity reversal and charge molecules. These two cases can be generated when the source block inversion driven killer pattern shown in Fig. 24 is used. That is, extracting the black and white or white and black eve pattern of the adjacent display in the direction of the eternal witch is the killer map macro. This judgment requires polarity reversal and charge sharing. 148936.doc 201106332 • A pattern in which the polarity of the killer pattern shown in Fig. 24(a) is reversed, Fig. 4(4) shows a HI pattern, Fig. 16(b) shows an odd line pattern, and Fig. 16(.) shows an even line. The pattern is darker than the killer pattern, but the black and white patterns do not change. Fig. 17 shows the potential change of the electric charge between the output 1 and the output 2 of the pattern shown in Fig. Figure i 7 (a) shows the potential change of the output ^, Fig. J7 (b) shows the change of the potential of the output 2. In order to make the electric circuit between line 1 and line 3, the output 1 and output 2 are short-circuited. In the case of the case, the output 1 and the output 2 become the voltage of "a," which is the intermediate voltage of + black and - white. The change in voltage at this time is such that the charge held by the output 1 and the charge held by the output 2 cancel each other out, so that the current does not flow. "After releasing the short circuit", the wheel 1 is turned from "a'" - the white potential, and the output 2 is turned from "a" to + black potential. Therefore, the information is sent to the i-line driver _ motion data: at this time, the driving voltage is not performed. In the case of charge sharing, it is the second half of the battery. The current driving the data line is also small. Xiao Guo is the data. The k-line driver 3 has less heat. Further, in the case where the output 丨 and the output 2 are short-circuited by charge sharing between the line 3 and the line 5, the output 1 and the output 2 become the voltage of the intermediate voltage of -white and +black, that is, "b'". As a result, the current does not flow in the same way, and the current is less when the current is turned to the next potential. Therefore, the heat generation of the data signal line driver 30 is also reduced, thereby greatly reducing the heat of the data signal line driver 3 as a whole. . Further, the judging circuit 43 recognizes the pattern of the image by using the combination pattern of the majority as described above, and is therefore not limited to the case of the display of the killer pattern 148936.doc • 51-201106332, even if it is similar The pattern of the killer pattern can also be identified. Thereby, by performing polarity inversion and charge sharing, substantially the same effect can be achieved. Further, in the above-described processing, when the display of the turn-off U line is a majority and the display of the previous line is a majority, it is determined that charge sharing is required. In this case, consider a pattern in which two columns are white or black, and the next two columns are black or white. Fig. 18 shows a pattern of two rows of horizontal stripes, Fig. 18 (4) shows the pattern, the paste shows the pattern of odd lines, and Fig. 18(c) shows the pattern of even lines. When the driving voltage of the white is the common potential, if the white is displayed after the black is displayed as the line t to the line 3, the voltage in the display by the charge sharing can be in the vicinity of the common voltage. For example, the adjacent output ι and output 2 are displayed in line 1 with the display of + black and black. Therefore, when the charge sharing is performed, the voltage of the white driving voltage, that is, "c" is obtained. Thus, in the white display of the output of the next line 3, substantially no driving power is required. Thus, charge sharing becomes a means for effectively reducing the current, so that the judgment circuit 43 judges that charge sharing is required in the case of the pattern of the two rows of stripes. Second, the breaking circuit 43 is not limited to the case of displaying a pattern of two rows of horizontal stripes, and even a pattern similar to the pattern of two rows of horizontal stripes can be recognized. Furthermore, as shown in Fig. 19, in the case of Gu Qianqi _, after the black is not black, the voltage of the positive white is the same as that of the negative electrode. Therefore, the charge sharing is not performed. In the above processing, when the judgment circuit 43 is in the case of a black and black majority, the charge sharing other than the two cases is invalid. Therefore, As shown above, in the data signal line driver 30, the judging circuit 43 is based on the majority of the squall lines corresponding to the gate line 21 of the previous scan in the erroneous scanning. a combination pattern and a combination pattern of the eves of the ridge line corresponding to the gate line 2丨 of the scan, determine whether the polarity of the adjacent output is inverted, and whether charge sharing between adjacent outputs is effective, and It is judged whether or not the polarity inversion is performed without performing the polarity inversion, and whether or not the charge sharing is performed between adjacent outputs is effective. That is, the judging circuit 43 can recognize the pattern of the image to be displayed, and performs the above determination. When the situation, # The output control signal is used to control the polarity of the adjacent output. The polarity switching control circuit 44 controls the polarity of the adjacent output to reverse the polarity of the adjacent output, and the output clear circuit control circuit 45 controls the short circuit switch. The circuit 4 is short-circuited between the adjacent outputs. In addition, when it is judged that the polarity inversion is not performed and the electric branch is divided between the adjacent outputs, the output control signal ctdcs is used to turn the box control circuit. Secret (four) short circuit open „ road post to make phase (four) (four) short circuit. The block reverses the spine to order the electricity and the drought. So when the LCD panel 2 is the source, the method can also be used. When % is the special image of the salty hand pattern, the power consumption is reduced, and the power consumption can be reduced. The heat caused by electricity. ^者' indicates that the above-mentioned liquid crystal display device (10) has an old output = situation 'but when one pixel is composed of 3 pixels of RGB, the data line drives md ο 了 了 1 〇 〇 , , , , , , , , , , , , , , , , , , , Output unit. The polarity to be displayed is changed corresponding to every m out unit, and the drama # is paired in output units. Specifically, if the 3 output is 1钤Ψ> and the right R · G · B corresponds to the output early bit, the polarity is changed for every 3 outputs, and the output is 148936.doc •53-201106332 It is also necessary to perform R to each other, G to each other, and B to each other. Further, the number of outputs of the feed signal line driver 30 is not limited to 414. The output of the data signal line driver 30 can be set to 2 to 2n (n: a positive integer) as needed according to the number of pixels in the horizontal direction in Fig. Further, the liquid crystal display device 1 includes a display device using a liquid crystal panel 20 of a liquid crystal element, and the liquid crystal cell 25 is in a state of being transmitted (white due to light passing through the backlight) when no voltage is applied, and the liquid crystal cell 25 is applied with a voltage. It is set to a state that is non-transmissive (black is not transmitted through the backlight) (normally bright state) ° and 'the state of the most transmitted light is set to 1 gray scale, and the voltage is changed to change the transmittance'. In grayscale, the state of the least transmitted light is set to 256 grayscale. However, depending on the characteristics of the liquid crystal element, there is a case where the voltage is not applied, the case where the voltage is not transmitted (normal black display mode), or the black side is set to the gray level, and the gray scale is sometimes larger than 256. Grayscale, sometimes less than 256 grayscale. The data signal line driver 30 can be widely applied to a liquid crystal panel of any of the normal display mode and the normal black display mode, and the respective conditions can be appropriately changed. Further, in the liquid crystal display device 10 described above, the determination circuit 43 of the data signal line driver 3 determines whether or not the polarity inversion and the charge sharing are required. However, the determination processing may be performed by an external controller or the like. The present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. That is, the embodiment obtained by combining the technical means appropriately changed within the scope of the patent application scope is also within the technical scope of the present invention. 148936.doc 54- 201106332 The data of the present invention (4) The circuit of the fourth (fourth) circuit is configured to: (4) a plurality of pixel electrodes arranged in a matrix, a plurality of pixel electrodes each having a torque applied to the scanning signal, and the pixel electrodes are entangled and used The liquid crystal display I of the plurality of word signal lines for supplying the data to the pixel electrode (four) of the same row causes the data signals prepared based on the gray scale data to be output to the respective liquid crystal display portions in such a manner that the adjacent output polarities are opposite to each other. The data signal line 'the data signal line driving circuit includes: a polarity inversion mechanism to reverse the polarity of the adjacent output; a short circuit mechanism that short-circuits the adjacent outputs; P control mechanism, the root (four) old (four) ^ (4) inverting the polarity of the adjacent output by a polarity inversion mechanism; the g2 (4) means controlling the short-circuiting means to short-circuit the adjacent outputs according to the second control signal; and determining means for performing the t-th control The signal is output to the first control unit, and the second control signal is output to the second control unit; and the liquid crystal display unit is in the row direction Dividing into a plurality of regions, sequentially scanning the scanning signal lines of the odd-numbered columns or the even-numbered columns, and sequentially supplying the gray-scale data to the interlaced scanning of the scanning signal lines of the even-numbered columns or the odd-numbered columns sequentially; The judging unit sequentially obtains the grayscale data, and displays the majority of the display patterns including the transmission state of the transmission and the non-transmission non-transmission state of the display of the adjacent output in the grayscale data obtained in the previous acquisition. And displaying, in the pattern and the display pattern of the plurality of display patterns of the adjacent output and the display pattern of the non-transmissive state, the first control signal and the The second control signal. Further, the invention is characterized in that the above-mentioned 148936.doc • 55-201106332 broken mechanism includes a display state determining mechanism, which sequentially obtains the gray scale data. Determining whether the gray scale data is in the above-described transmission state and the non-transmission state; and displaying a pattern creation mechanism using the determination result, Forming a display pattern including the transparent state and the non-transmissive state of the adjacent output, and the majority determining means respectively counts the created display patterns, and determines a majority of the display patterns of the gray scale data in one column; a holding mechanism that maintains a display pattern of a majority of the ones of the gray scale materials previously determined by the majority decision mechanism; and a control signal output mechanism that maintains the first gray scale data T of the previous determination according to the foregoing The display pattern of the majority and the display pattern of the majority of the gray scales of the above-mentioned determinations are selectively outputted to the second control signal k and the second control signal. Preferably, the display signal determining circuit of the determining means determines whether the grayscale data of the upper/receiving service is the transparent state and the non-transmissive shape according to a predetermined grayscale range. The transmission state and the non-transmission state can be determined within the gray scale range indicated by the gray scale data. Further, in the data signal line driving circuit of the present invention, it is preferable that the predetermined gray scale can be changed by a signal given from the outside. Thereby, the transmitted state and the non-transmissive state of the recognition can be adjusted. Further, in the data signal line driving circuit of the present invention, preferably, the determining the 夕 派 派 疋 将 将 将 将 将 将 将 将 将 将 将 将 将 将 将 将 将 将 将 将 将 将 将 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述The display pattern of a predetermined number or more of the display patterns is determined to be the display pattern of the above-mentioned majority 148936.doc • 56 - 201106332. By this, the pattern. The killer can be judged by appropriately specifying the above number. The above-mentioned predetermined adjustable identification is also preferably changed by the k 5 tiger which is given from the outside. Thereby, the pattern. The driving method of the liquid crystal display device of the present invention is characterized in that it is a driving method of a liquid liquid display device comprising: a liquid crystal display... a plurality of pixel electrodes arranged in a matrix, for the same column The pixel electrode is divided into a plurality of Sakae & signal lines of the scanning signal, and a plurality of poor signal lines '· and a data signal line driving circuit respectively supplying the data signals to the pixel electrodes of the same direction, which are based on the gray scale The data signal prepared by the data is respectively output to the data signal lines of the liquid crystal display unit in such a manner that the polarities of the adjacent outputs are opposite to each other; the driving method includes: the first step of dividing the line in the row direction with respect to the liquid crystal display portion Each of the plurality of regions 'sequentially scanning the scans of the odd-numbered columns or the even-numbered columns is sequentially supplied to the gray-scale data sequentially corresponding to the interleaved scan of the scanning signal lines sequentially scanning the even-numbered columns or the odd-numbered columns, in order Obtaining the above-mentioned gray-scale poor material, according to the display of the adjacent output in the first-order gray-scale data obtained in the previous one, And a display pattern of a majority of the display patterns of the non-transmissive non-transmissive state, and the display pattern including the transmission state and the non-transmission state of the adjacent output in the one-row gray scale gravy obtained this time The display pattern of the majority is determined to determine whether the polarity of the adjacent output of the data signal line driving circuit is reversed, and the short circuit between the adjacent outputs of the k-line driving circuit is the second step; 148936.doc -57 · 201106332, in order to reverse the polarity, the data signal line is driven to drive the polarity inversion of the two adjacent outputs; and in the third step, when it is determined that it is necessary, !, -, the data line driving circuit is performed. A short circuit between adjacent turns. ^ The driving method of the liquid crystal display device of the present invention preferably comprises: displaying a display state determining step, sequentially obtaining the grayscale data to determine whether the grayscale data is the above a transmission pattern and a non-transmission state; a display pattern creation step of using the determination result to create the transmission state including the adjacent rounds and the non-transmission a display mode of the state; a majority decision step of counting the display patterns prepared as described above, and determining a display pattern of the majority of the gray scale data in one column; the maintaining step maintaining one of the previous determinations in the majority determination step a display pattern of a majority of the grayscale data; and a control signal output step, according to the above-mentioned previous determination, the display pattern of the majority of the grayscale data, and the grayscale data of the above-mentioned determination The majority of the display patterns are selectively outputting the second control signal and the second control signal. Further, the driving method of the liquid crystal display device of the present invention is preferably in the display state determining step The predetermined gray scale range determines whether the gray scale data obtained is the non-transmission state and the transmission state, whereby the transmission state and the non-transmission state can be determined within the gray scale range indicated by the gray scale data. Further, the driving method of the liquid crystal display device of the present invention preferably comprises the above-described transmission state of the adjacent output and the I48936.doc • 58-201106332 which is formed in the above-described display pattern forming step. A predetermined number or more of the display patterns in the non-transmissive display pattern is determined as the display pattern of the majority. Thereby, the killer pattern can be judged by appropriately specifying the number. Further, in the driving method of the liquid crystal display device of the present invention, it is preferable that the liquid crystal display unit is of a display type of a normally-on-state mode, and in the first step, 'the majority of the first-order gray-scale data obtained in the previous step. The display pattern of the display is a display pattern of "non-transmissive state/non-transmissive state", and when the display pattern of the majority of the grayscale data acquired in the above-mentioned one is the "transmission state/transmission state" display pattern, it is judged that it is unnecessary. The above polarity is reversed and the above short circuit is required. Thereby, power consumption can be reduced. Further, in the driving method of the liquid crystal display device of the present invention, it is preferable that the liquid crystal display unit is of a display type of a normally-on-state mode, and in the i-th step, a majority of the grayscale data obtained in the previous time When the display pattern of the display is "transmission state or non-transmission state", the display pattern of the majority of the i-column grayscale data obtained in the above-mentioned data (4) "non-transmission state/transmission state" is determined as The above polarity inversion is required and the above short circuit is required. Thereby, power consumption can be reduced. Further, in the driving method of the liquid crystal display device of the present invention, it is preferable that the liquid crystal display is a display type of a normally-on-state mode, and the above-mentioned first-time acquisition is performed in the i-th step! The display of the majority of the columns in the grayscale data is the display map of "non-transmission state. transmission state", which is obtained from the above! When the display pattern of the majority of the gray scale data is displayed, the display pattern of "transmission state and non-transmission sorrow" is determined to require the above polarity inversion, 148936.doc -59 - 201106332 and the above short circuit is required. It can reduce power consumption. Further, in the driving method of the liquid crystal display device of the present invention, it is preferable that the liquid crystal display unit is of a display type of a normal black display method, and in the first step, a majority of the one-step gray scale data obtained in the previous step is used. When the display pattern of the display is "transmission state/transmission state", and the display pattern of the majority of the one-step grayscale data obtained in the above-mentioned one is "non-transmissive state or non-transmissive state", it is judged. The above short circuit is required without the above polarity reversal. Thereby, power consumption can be reduced. Further, in the driving method of the liquid crystal display device of the present invention, it is preferable that the liquid crystal display unit is of a display type of a normal black display mode, and in the third step, a majority of the grayscale data obtained in the previous time The display pattern of the party is "non-transmission state. Transmission state". Fortunately, the display pattern of the majority of the grayscale data obtained is "= state and non-transmission state" (4) when the pattern is displayed. The polarity is reversed and the above short circuit is required. Thereby, power consumption can be reduced. Further, in the driving method of the liquid crystal display device of the present invention, it is preferable that the upper liquid crystal display portion is of a normal black display mode, and in the above step, the majority of the previous gray scale data obtained in the first step is obtained. The display pattern of the display mode is "transmission state. non-transmission state". When the display pattern of the "fourth" "non-transmissive state/transmission state" is displayed in the above-mentioned display (1), the polarity rotation is required and the short circuit is required. Thereby, dry electricity can be reduced. Moreover, it is preferable that the driving method of the liquid crystal display device of the present invention requires the polarity inversion of adjacent rounding of the data signal line driving circuit to be 148936.doc-60-201106332, adjacent to the data signal line driving circuit. The judgment of the short circuit between the turns is performed in the above-mentioned data signal line drive circuit. [Industrial availability j θ can be preferably used not only for the data of the data signal to the liquid crystal panel = 1 driving circuit, but also for the manufacturing method of the data signal line driving electric power, the data signal line driving The related art of the control method of the circuit can be widely used in the field of liquid crystal display devices such as τν or a booked telephone having a data signal line drive circuit, and a method of manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a TF embodiment of a liquid crystal display device of the present invention, and is a block circle in which the polarity inversion switching circuit is switched to _. Fig. 2 is a block diagram showing the case where the above liquid crystal display device switches the polarity inversion switch circuit to the b side. Fig. 4 is a circuit diagram showing the above-described judging circuit. One of the black contrast circuits of one of the pattern detecting circuits is shown in Fig. 5 which is a block diagram showing an example of the pattern detecting circuit. Fig. 6 is a block diagram showing the above-described pattern example. The truth table of the logic circuit in the road. The configuration of the white control circuit in the detection circuit - Fig. 8 is a truth table of the logic circuit of the above white comparison circuit. The θ system does not show the pattern of the pattern control circuit in the above pattern detecting circuit. 148936.doc • 61 - 201106332 The circuit diagram of the example. The graph ίο is a table showing the state of the input and output of the pattern control circuit in the display state of the adjacent output pair of the data signal line driver of the liquid crystal display device. Figure 11 is a truth table of the counter of the pattern detecting circuit. The figure is a circuit diagram showing an example of a configuration of a polarity inversion and charge sharing determining circuit in the above-described judging circuit. Fig. 13 is a flow chart showing the flow of processing when the data signal line driver in the liquid crystal display device is not displayed. The system shows the flow chart executed by the processing flow of Fig. 13. Fig. 15 Fig. 15 is a flow chart showing the flow chart 2 executed by the processing flow of Fig. 13 = the pattern of the pattern when the polarity of the killer pattern is reversed. ,) indicates the odd line 2: the pattern of the number line. The mouth table is not even. Two: The diagram shows the potential change when the electric r knife is output between the output 1 and the output 2 of the pattern of Fig. 16, and Fig. 17 (4) shows the wheel discharge. Fig. 17 (b) shows the potential change of the output 2. Edge-to-edge, Figure 18 is a diagram showing the pattern of two rows of horizontal bars. Figure 1 8(b) shows odd-numbered lines, no. Haitu, the graph of the potential change when sharing, indicates that the charge is being transferred. Figure 19(b) shows the potential change of the output 2. The potential change of 1 is generated, l4S936.doc • 62· 201106332 The source of the drive mode when driving the LCD panel Fig. 20 is a diagram showing the output waveform of the dot inverter. Fig. 21 is a view showing the interleaved scanning. The f 22 of the output waveform of the source driver of i indicates the output waveform of the source driver at the time of completion of the description of both the odd-numbered columns and the even-numbered columns in the interleaved scanning. Fig. 23 is a view showing a scanning sequence when the source block inversion driving is performed. Fig. 24 is a view showing a killer pattern called a source block inversion driving method, Fig. 24(a) shows the pattern, Fig. 24(b) shows a pattern of odd lines, and Fig. 24(c) shows even lines. The pattern. Fig. 25 is a view showing a change in potential when the output ι and the output 乂 of the pattern of Fig. 24 are divided. Fig. 25(4) shows the potential change of the output i, and Fig. 25(b) shows the potential change of the output 2. Figure 26 is a diagram showing a specific pattern. Fig. 27 is a view showing a change in potential when the output 1 and the output 乂 of the pattern of Fig. 26 are shared. Fig. 27 (4) shows the potential change of the wheel i: Fig. 27 (b) shows the potential change of the wheel 2 . [Main component symbol description] 10 Liquid crystal display device 20 Liquid crystal panel (liquid crystal display unit) 21 Gate line (scanning signal line) 22 Source line (data signal line) 24 pixel electrode 30 Data signal line driver (Information letter 148936.doc -63- Extinction drive circuit) 201106332 31 Shift register 32 data latch 33 ' 41 polarity reversal switch circuit (polarity reversal mechanism) 34 lock latch 35 level shifter 36 positive side DAC 37 Negative-side DAC 38 Positive operational amplifier 39 Negative operational amplifier 40 Short-circuit switch circuit (short-circuit mechanism) 41 Polarity reversal switch circuit 43 Judgment circuit (judgment mechanism) 44 Polarity switching control circuit (third control mechanism) 45 Output short-circuit control circuit (second control means) 46 setting register 101 pattern detection circuit 102 charge sharing determination circuit 111 black comparison circuit (display state determination means) 112 white comparison circuit (display state determination means) 113, 114 D-FF 115 pattern comparison circuit (display pattern creation mechanism) 116~119 Counter 120-123 Control circuit (majority decision mechanism) 161-163 D-FF (holding mechanism) 148936.doc -64 - 201106332 164~166 167, 168 169, 170 AND circuit (control signal wheeling mechanism) OR circuit (control signal output Organization) D-FF (control signal output mechanism) 148936.doc 65-

Claims (1)

201106332 VII. Patent application scope: - a data signal line driving circuit, characterized in that it is a plurality of scanning signals for supplying scanning signals to the pixel electrodes of the same column with respect to a plurality of pixel electrodes having a matrix configuration; And a liquid crystal display unit for supplying a plurality of data signal lines for respectively supplying the data signals to the pixel electrodes of the same order, and outputting the data signals according to the gray scale data to the opposite polarity of the adjacent turns Each of the data signal lines of the liquid crystal display unit, the data signal line drive circuit includes: a polarity inversion mechanism that inverts a polarity of the adjacent output; a link mechanism that short-circuits the adjacent outputs; the first control The mechanism controls the polarity inverting mechanism to invert the polarity of the adjacent output according to the second control signal; and the second control unit controls the short-circuiting mechanism to short-circuit the adjacent output according to the second control signal And a judging mechanism that outputs the above-mentioned third control signal to the above-mentioned third control mechanism, and (2) the control signal is output to the second control unit; and the scanning liquid signal is sequentially divided into a plurality of regions in the row direction, and the scanning signal lines of the odd-numbered columns or the even-numbered columns are sequentially scanned, and the even-numbered scanning even numbers are sequentially scanned The gray-scale data is sequentially supplied to the interleaved scan of the scanning signal lines of the column or the odd-numbered column, and the determining unit sequentially obtains the gray-scale data, and includes the adjacent output according to the first-order gray-scale data obtained in the previous time. The display pattern of the transmitted state and the non-transmissive non-transmissive state is 148936.doc 201106332, and the display pattern of the above-mentioned adjacent output in the obtained grayscale data The plurality of display patterns of the transmission state and the non-transmission state pattern are selectively outputted to the second signal and the second control signal. 2. The data signal line driving circuit of claim 1, wherein the determining means display state determining means sequentially obtains the grayscale data to determine whether the grayscale data is in the transparent state and the non-transmissive state; a forming unit that uses the above-described determination result to create a display pattern including the transmission state and the non-transmission state of the adjacent output; 'μ majority determining means for counting each of the created display patterns, and determining the gray scale a display pattern of a majority of the tenth data; a holding mechanism that maintains a display pattern of a majority of the ones of the grayscale materials previously determined by the majority decision body; and a control signal output mechanism that is maintained according to the above Determining the display pattern of the majority of the gray scale data and the display pattern of the majority of the gray scale data of the above-mentioned determination, and selectively outputting the first control signal and the above 2 control signals. 3. The data signal line driving circuit of claim 2, wherein the display state determining means of the determining means determines whether the obtained gray scale data is the transparent state and the non-transmissive shape according to the range of the gray scale. For example, the data signal line driver circuit of claim 3 may be surrounded by the predetermined gray 148936.doc 201106332.卩 Change the signal given. 5. The data of the item 2 is used as a rider ^^r., β" line drive circuit, which causes the majority of the judgment mechanism of the above-mentioned judging mechanism to be a θ 摄 占 , , , , , , , , , , , , , , , , , , , , , In the display pattern of the adjacent rounded state, the display pattern of the transmission pattern is preliminarily transmitted. The display pattern on X is judged to be more than the above. A twist line drive circuit in which the predetermined number can be changed by a signal imparted from the outer 4. - A liquid crystal display device, comprising: a liquid crystal display portion having a plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes of the same column, and: a plurality of tributary signal lines for supplying the data signals to the pixel electrodes respectively; and a data signal line driving circuit for causing the poorness signal 'made according to the gray scale data to be opposite in polarity of the adjacent outputs And outputting to each of the data signal lines of the liquid crystal display unit; ^ the above-mentioned data @号, the line driving circuit is the data signal line driving circuit of any one of items j to 6. a driving method of a liquid crystal display device comprising: a liquid crystal display unit having a plurality of pixel electrodes arranged in a matrix, and a plurality of scanning signal lines respectively supplying scanning signals to the pixel electrodes of the same shape And a plurality of data signal lines for respectively supplying the data signals to the pixel electrodes of the same row; and a bedding signal line driving circuit for making the data signals of the upper 148936.doc 201106332 according to the gray scale data, The opposite polarity of the adjacent output is respectively rotated to the data signal lines of the liquid crystal display unit; and the scanning signals of the odd-numbered columns or the even-numbered columns are sequentially scanned for dividing the plurality of regions in the row direction with respect to the liquid crystal display portion. After the line, the gray-scale data is sequentially supplied corresponding to the interlaced scanning of the scanning signal lines of the even-numbered columns or the odd-numbered columns, and the driving method includes: obtaining the gray/day six m. The display of the above-mentioned adjacent outputs in the 1st row of grayscale data is the transmission state of the T and the non-transmission of the non-transmission. The display pattern of the state 3 is displayed, and the display state of the above-mentioned adjacent output of the U-column grayscale data and the display pattern of the majority of the non-transmissive food:: pattern are determined to determine whether it is necessary to The polarity of the adjacent output of the 唬 line drive circuit is reversed, and the short circuit between the adjacent outputs of the upper ii 枓 枓 signal line drive circuit; 诚/骤, when it is determined that the above polarity reversal is required, the data signal is described The line drive circuit cuts the polarity of the adjacent output of the % path; and the third step, when the material signal line drive circuit is short-circuited, 'performs the above 1 9. The liquid crystal of claim 8: short between outputs . The driving method of the device, wherein the first team of the first team prepares the steps, and the grayscale data is obtained in the order of 3 t to obtain the grayscale data; ^ the above-mentioned transmission state and the above-mentioned non-transmission bear; 4 The non-side rails also use the above-mentioned determination result to create the above-mentioned transmission pattern of the adjacent output in the state of I48936.doc 201106332; the display steps of the state and the non-transmission state, respectively, counting the display patterns prepared above, and determining 1 column a display pattern of a majority of the gray scale data; a maintaining step of maintaining a majority of the display patterns of the gray scale data of the first row of the plurality of determination steps; and a control signal output step, according to the maintaining The first display signal of the majority of the gray scale data and the display pattern of the majority of the gray scale data of the first time of the determination, and the first control signal are selectively outputted. And the above 2nd ίο. 11. 12. The driving method of the liquid crystal display device of claim 9 is shown in the step of determining the state, according to the predetermined gray scale Range, it is determined from the above data taken θ Λ Ρ Cloth NO is the non-transmission state and said transmitting state. The method of driving a liquid crystal display device according to the item 9, wherein the plurality of special determination steps are performed by the display pattern forming step, and the transparent state and the non-transmissive state of the adjacent output are not A predetermined number or more of display patterns in the pattern are determined as the display pattern of the majority. The driving method of the liquid crystal display device of the above-mentioned item 8, wherein the liquid crystal display unit is of a display type of a normal-bright mode, and in the first step, a majority of the first-order gray-scale data obtained in the previous step is The display pattern is a display pattern of "non-transmissive state and non-transmissive state", and when the display pattern of the majority of the one-segment grayscale data obtained in the above-mentioned one is "transmission state/transmission state", 148936.doc 201106332 13. 14. 15. 16. It is judged that the above polarity inversion is not required and the above short circuit is required. The driving method of the liquid crystal display device of item 8, wherein the liquid crystal does not.卩 is the display type of the constant-state mode, and the display pattern of the majority of the (7) gray-scale data obtained in the above-mentioned i_(4) is the "transmission state/non-transmission state"/pattern" When the 2 pattern of the majority of the gray scale data obtained in the first row is the display pattern of "non-transmissive state/transmission state", 1 = the polarity inversion is required and the short circuit is required. The driving method of the liquid crystal display device of claim 8, wherein the liquid crystal person does not have a display type of the normal light state mode, and in the i-th step, when the majority of the front-cut U-row gray scale data is The display pattern is a display pattern of "non-transmissive state/transmission state", and when the display pattern of the majority of the grayscale data acquired in the above-mentioned one of the above-mentioned ones is "transmission state or non-transmission state", it is judged. In order to require the above polarity inversion, the above short circuit is required. The driving method of the liquid crystal display device according to the item 7, wherein the liquid crystal display unit is of a display type of a normal black display mode, and in the first step, the eve of the previous gray scale data obtained in the first step The display pattern is a display pattern of "transmission state and transmission state", and when the display pattern of the majority of the grayscale data obtained in the above-mentioned acquisition is "non-transmission state/non-transmission state", It is not necessary to reverse the above polarity and the above short circuit is required. The driving method of the liquid crystal display device of claim 8, wherein the liquid crystal display unit is of a display type of a normal black display mode, 148936.doc 201106332, in the first step, in the first step of the gray scale data obtained in the previous step. When the display pattern of the majority is the "non-transmissive state/transmission state" display pattern, the display pattern of the majority of the gray scale data obtained in the above-mentioned item is "transmission state and non-transmission state". It is determined that the above polarity inversion is required and the above short circuit is required. 17. The method of driving a liquid crystal display device according to claim 8, wherein the liquid crystal display unit is of a display type of a normal black display mode, and in the first step, the number of eves of the grayscale data obtained in the previous time When the display pattern of the display is "transmission state or non-transmission state", the display pattern of the majority of the one-segment grayscale data obtained in the above-mentioned one is judged to be "non-transmission state/transmission state". In order to require the above polarity inversion, the above short circuit is required. 18. The method of driving a liquid crystal display device according to claim 8, wherein whether the polarity inversion of the adjacent output of the data signal line driving circuit and the short circuit between adjacent outputs of the data signal line driving circuit are required It is carried out in the above data signal line drive circuit. 148936.doc