201044796 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種檢測裝置，特別是指一種用以搜 尋錯誤位置的檢測裝置。 【先前技術】 -編碼信號從傳送端發出後，會藉由—通道的傳遞而 抵達接收端。惟實際通道的傳輸品質不盡理想，所以抵達 帛收端的信號有可能不同於傳送端發出的信號。因此，接 Ο &端通常會根據抵達的那個信號，找出受到通道干擾的位 元位置並加以糾正，使逼近原先傳送端發出的信號。 常見接收端的解碼步驟多是： (一) 從：達的那個信號中’取出-個具有多個位元的 碼字（codeword) (二） 為該碼字，計算出多個癥狀（syndrome)值，且每一 癥狀值會對應有限場GF的一個非零元素。接著， ❹ 以料餘值當作係數，形成-癥狀多項式； (三） 參考該編碼信號的最大可糾錯容量t，為該瘋狀多 項式，求得一個t階錯誤位置多項式（err〇r 1〇cat〇r polynomial);及 (四） 基於錯誤位置多項式的根—t)，獲知受干擾的位 元位置。 〇疋對於一般的錯誤更正碼來說，傳送端只會選用 有限場GF的其中幾個非零元素來編譯該編碼信號，所以步 3 201044796 驟（二）算出的癥狀值不全為有效。因此，接收端必須再經過 多次確認，才能找出有效的癥狀值來形成癥狀多項式，導 致解碼效率不佳，糾錯時間也拉長。 近年來，E_ 0rsini和M, Sala於乂户㈣柳/」如〜， 剔t更提出：以Gr5bnei·基底來決定錯誤位置多項式的 觀念。主要是利用GWbner·基底選出t個函數，進而將該等 癥狀值代人各函數，並則认所得函數值當作該t階錯誤位 置多項式的係數。 這樣的方式不需經過額外的確認程序，有利於糾錯時 間的縮減。不過，純端每讀_碼字巾，發生錯誤的 位元個數可能只有〇丨2 ( ，z…，(t-Ι)或t個。如果每次都求出 達t階的錯誤位置多項戎，i 式其實無助於糾錯能力的提昇，反 而會拖累解碼效率。 【發明内容】 因此，本發明之目的，肖卩4 i 要认w P在如供一種用以搜尋錯誤{ 置的檢測裝置，可隨著铒旌 _201044796 VI. Description of the Invention: [Technical Field] The present invention relates to a detecting device, and more particularly to a detecting device for searching for an erroneous position. [Prior Art] - After the coded signal is sent from the transmitting end, it will arrive at the receiving end by the transmission of the channel. However, the transmission quality of the actual channel is not ideal, so the signal arriving at the receiving end may be different from the signal sent by the transmitting end. Therefore, the Ο & terminal usually finds and corrects the location of the bit interfered by the channel based on the signal arriving, so as to approximate the signal from the original transmitter. The decoding steps of common receiving ends are: (1) From the signal that arrives, 'take out a codeword with multiple bits (2) for the codeword, calculate multiple symptoms (syndrome) value And each symptom value corresponds to a non-zero element of the finite field GF. Then, ❹ taking the residual value as a coefficient to form a symptom-polynomial; (3) referring to the maximum error correctable capacity t of the coded signal, for the mad polynomial, obtaining a t-order error position polynomial (err〇r 1 〇cat〇r polynomial); and (d) based on the root-t) of the error location polynomial, the location of the interfered bit is known. 〇疋 For the general error correction code, the transmitter only compiles the coded signal by using several non-zero elements of the finite field GF, so the symptom values calculated in step 3 201044796 (2) are not all valid. Therefore, the receiving end must go through multiple confirmations to find a valid symptom value to form a symptom polynomial, resulting in poor decoding efficiency and long error correction time. In recent years, E_ 0rsini and M, Sala in Seto (four) Liu / "such as ~, t t further proposed: the concept of the wrong position polynomial with Gr5bnei base. The main function is to select t functions by using the GWbner base, and then the symptom values are substituted for each function, and the obtained function value is regarded as the coefficient of the t-order error position polynomial. This way, there is no need to go through an additional confirmation procedure, which is conducive to the reduction of error correction time. However, for every _code word towel read by pure end, the number of bits in which the error occurred may be only 〇丨2 ( , z..., (t-Ι) or t. If you find the error position multiple times up to t steps each time戎, i-style does not help the improvement of error correction ability, but will drag down the decoding efficiency. [Invention] Therefore, for the purpose of the present invention, Xiao Wei 4 i should recognize that it is used for searching for errors. Detection device, with 铒旌 _
者錯誤位兀個數來改變錯誤位置多S 式㈣數，能增加解物並縮短糾錯時間。 > 於是，本發明用以搜尋 處理θ ^ * 寸錯条位置的檢測裝置，適用方 處理—具有複數位元的碼字 右PP , , 3 癥狀计算器，將一 式，瞀山 代入该碼子所對應的一接收多巧 飞以计算出一癥狀值；— 來求出-錯誤位置多m式產生器，根據該瘋狀仓 ，且是其#兮@ ^的第—階係數與一第二階係类 且疋基於該第一階係數求 出。亥苐二階係數；及一錯誤位 201044796 置決定器’基於該等係數，解析該錯誤位置多項式的根值 ，並據以搜尋該碼字中發生錯誤的位元位置。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚的呈現。 假設一傳送系統是利用一生成多項式g(x)來將一資料訊 息編譯成一（n，k，d)編碼信號。且資料訊息的每k位元會對應 編譯出編碼信號的一碼字（含n位元），而使得編碼信號具有 最大糾錯容量Y位元，其中|^」代表：小於等於χ的最 大正整數。之後，隨著通道的傳遞，這個編碼信號會受到 雜訊干擾，而在一接收系統處形成一待解碼信號。並且， 待解碼信號的一碼字也會對應地具有η位元。 為方便說明，這裡更定義出幾種多項式。並請注意， 每一多項式的係數會隨著對應碼字的内容而不同。 傳送多項式c(x):反映「編碼信號之一碼字」； 通道多項式e(x):在「編碼信號之一碼字」的傳遞過程 中’反映通道的干擾情形；及 接收多項式r(x) : r(x)=c(x)+e(x)，能反映「待解碼信號 之一碼字」。 參閱圖1，本發明用以搜尋錯誤位置的檢測裝置7之較 201044796 Γ::適用：該接收系統7°"，能處理該待解碼信號 的-碼子’以找出該碼字中受到通道干擾的位元位置。 該㈣裝置7包含依序串聯的—瘋狀計算器、一多 項式產生H 72及-錯誤位置決定器73。癥狀計算器將 有限場GF的-個非零元素，代人對應的接收多項式r⑻， 以計算出-癥狀值。多項式產生器72則根據該癥狀值來求 出-錯誤位置多項式如)的多個係數，且是利用—係數類 推出下-階係數。接著，錯誤位置決定器73會解析該錯誤 位置多項式σ(χ，相根(r〇〇t)值，以搜尋該碼字中發生錯誤的 位元位置。 其中，X代表「碼字内容」的變數，z代表「錯誤位元 位置」的變數。而本例是處理單一個碼字，所以錯誤位置 多項式σ(χ,ζ)只會隨z變化。 值得注意的是，癥狀計算器71所代入的那個非零元素 ，是傳送系統選用之生成多項式g(x)的一根值。所以，代入 該非零兀素後，癥狀值=r(x)=0+e(x)=e(x)e也就是說，只要 善用癥狀值’即能檢測出通道的干擾情形。 ❹ 因此’本例進一步使用多項式產生器72，期望藉由癥 狀值的資sfl ’來求出該錯誤位置多項式σ(χ，ζ)的多個係數， 作為搜尋發生錯誤位元位置的準備。該多項式產生器72包 括一初階設疋單元721、一高階設定單元722及一檢驗單元 723。初階設定單元721和高階設定單元722依序串聯於癥 狀计异器71與錯誤位置決定器73間，且檢驗單元723會 電連接這兩個設定單元721、722。 6 201044796 ’包含以下步驟： GF的該非零元紊 參閱圖2 ’該檢測裝置7執行的方法 步驟80:薇狀計算器71接收有限場 ，並自通道接收該碼字。 步驟⑴癥狀計算器71根據該碼字形成該接收多 r(x)，並將該非零元素代人r(x)，以計算出對應的癥狀值。 步驟82:初階設定單元721使錯誤位置多項式外，·The number of errors is set to change the number of errors in the S-type (four) number, which can increase the solution and shorten the error correction time. > Thus, the present invention is used to search for a detection device for processing the position of the θ ^ * inch strip, and the applicable party processes the code word right PP with a complex bit, and the 3 symptom calculator, which substitutes the formula, Lushan into the code. The corresponding one receives more than a fly to calculate a symptom value; - to find the - error position multi-m generator, according to the crazy position, and is the #兮@^'s first-order coefficient and a second The order class is calculated based on the first order coefficient. The second order coefficient; and an error bit 201044796 determine the root value of the error location polynomial based on the coefficients, and search for the bit position of the code word in which the error occurred. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Suppose a transmission system uses a generator polynomial g(x) to compile a data message into an (n, k, d) coded signal. And each k-bit of the data message correspondingly compiles a codeword (including n-bits) of the encoded signal, so that the encoded signal has a maximum error-correcting capacity Y-bit, where |^" represents: the maximum positive of 小于 or less Integer. Thereafter, as the channel is transmitted, the encoded signal is subject to noise interference, and a signal to be decoded is formed at a receiving system. Moreover, a codeword of the signal to be decoded also correspondingly has n bits. For convenience of explanation, several polynomials are defined here. Also note that the coefficients of each polynomial will vary with the content of the corresponding codeword. Transmit polynomial c(x): reflects "one codeword of coded signal"; channel polynomial e(x): reflects the interference situation of the channel during the transmission of "one codeword of coded signal"; and receives polynomial r(x ) : r(x)=c(x)+e(x), which reflects the "one codeword of the signal to be decoded". Referring to FIG. 1, the detecting device 7 for searching for an error position of the present invention is more than 201044796:: applicable: the receiving system 7°" can process the -code ' of the signal to be decoded to find out the received code word The bit position of the channel interference. The (4) device 7 includes a mad calculator in series, a multi-form generation H 72 and an error position determiner 73. The symptom calculator will take a non-zero element of the finite field GF and the corresponding polynomial r(8) for the generation to calculate the - symptom value. The polynomial generator 72 obtains a plurality of coefficients of the -error position polynomial, e.g., based on the symptom value, and derives the lower-order coefficients using the - coefficient class. Next, the error position determiner 73 parses the error position polynomial σ (χ, phase root (r〇〇t) value to search for the bit position in the code word where the error occurs. Where X represents the "code word content" The variable, z represents the variable of the "error bit position." In this case, the single codeword is processed, so the error position polynomial σ(χ,ζ) only changes with z. It is worth noting that the symptom calculator 71 is substituted. The non-zero element is a value of the generator polynomial g(x) chosen by the transport system. Therefore, after substituting the non-zero element, the symptom value = r(x)=0+e(x)=e(x) e, that is, as long as the symptom value is used, the channel interference condition can be detected. ❹ Therefore, this example further uses the polynomial generator 72, and it is expected that the error position polynomial σ is obtained by the symptom value sfl ' ( A plurality of coefficients of χ, ζ) are prepared for searching for the position of the erroneous bit. The polynomial generator 72 includes a preliminary setting unit 721, a high-order setting unit 722, and a checking unit 723. The initial setting unit 721 and The high-order setting unit 722 is sequentially connected in series to the symptom meter 71 and the error. The position determining unit 73 is connected, and the checking unit 723 is electrically connected to the two setting units 721, 722. 6 201044796 'The following steps are included: The non-zero element of the GF is referred to FIG. 2 'The method performed by the detecting device 7 is step 80: Wei The calculator 71 receives the finite field and receives the code word from the channel. Step (1) The symptom calculator 71 forms the reception multi r(x) according to the code word, and substitutes the non-zero element for the r(x) to calculate Corresponding symptom value. Step 82: The initial stage setting unit 721 makes the error position polynomial,
「第-階係數响」設定為該癥狀值，且檢驗單元72 處理階數設定為1。 步驟83:高階設定單元722將「第』·階係數咕）」代 入一第j + 1 P皆函數乃»))而求得一函數值，並以這個函 數值當作「第j + Ι階係數σ川⑴」，即= 〇㈣。而 且檢驗單元723會使處理階數加1。 。月/主思本例的Λ+丨(σ/χ))是利用Lagrange内插法所求 得，且這個函數會滿足常數項為〇，所以又可說：U勾相 當於Ό)之多種幂次方」的總和。而（»))的求法稍 後將再詳細描述。 步驟84 :檢驗單元723檢查^+】(4是否為〇。若否跳 到步驟85 ;若是，則記錄發生錯誤的位元個數v=j，並結束 係數設定，然後跳到步驟86。 t 步驟85 :檢驗單元723檢查處理階數是否小於t。若是 ’跳回步驟83 ;若否’則記錄發生錯誤的位元個數v=t，並 結束係數設定，接著跳到步驟86。這是因為（n，k,d)編碼信 號的最大糾錯容量為t位元，所以σ(χ，ζ)的最高階數只能為 7 201044796 ，即 v St。 步驟86 :錯誤位置決定器73收集各階係數σι(χ)、 %(χ)·‘·σν(χ)，利用習知的錢式搜尋法（Chien ，來找 出錯誤位置多項式σ(ρ)的根，以對應搜尋該碼字中發生錯 誤的位元位置。 其中，σ(χ，·ζ) = 1 +交。 從前述流程可以發現：當本例檢驗出>(χ)為0,即會 停止係數設定的動作，進而形成一個只有ν階的錯誤位置 多項式σ(χ，ζ)。而這也意謂著’本例能同時獲知該碼字中受 到通道干擾的位元數目ν，故又稱如)是—種檢驗⑽叫 錯誤位置多項式。 更具體來說，本實施例能隨發生錯誤的位元個數v來 決定的階數，而^像習知技術總是求出高達【階的 外，:）。®此’形成σ(χ，ζ)的時間可彈性地縮減，也簡化了求 取σ(χ，ζ)之根值的運算。 此外，該檢測裝置7還包含—電連接該多項式產生器 72的函數產生n 75，能產生適用於「所有可能碼字」的第 川階函數乃為㈣，。例如，對於具有3個位元的 碼字來說，「所有可能碼字」為_、〇〇1、〇1〇'〇111〇( 、101 、 110 及 111 〇 假設，...，於是指滿足生成多項式g(x)=〇的非零元素 ，（^<·.·<Ζν<„，且j的初始值為丨。當函數產生器乃要 201044796 產生/}+1(σ7.(χ)) ’會進行圖3的下列步驟： 步驟91 :將··.，々、中的其中一個，代入所有可能的 接收多項式r(x) ’以得到對應的瘋狀值（=σι(χ))。其中每 一種可忐的碼字都會對應一個r(x)，也就會對應一個。 步驟92 :根據錯誤位置多項式σ(χ，ζ)的如下定義，為每 一種可能的碼字整理出第j + 1階係數，其會相關於所 有夕A…，夕〜。 σ(χ,ζ) = (1 + βι> Z) = j + ^ (x)zj 〇 °>办)=ς β、β、…β1ί⑽ <Ϊ_2 <…<ν 步驟93 :利用Lagrange内插法，逼近出第j + 1階函數 ’來從所有可能的S⑷映射到對應的i+办），即 ~+1(x) = /;+1(CTy(JC))。 步驟94 :使j加上1，並重複步驟92和93，直到逼近 出 σν〇)。 而這個映射關係σ;+1(χ) = /;+1(σ7.(χ))，會具有常數項〇且 相當於「⑷之多種幂次方」的總和。舉例來說，對於 (23,12,7)一 次剩餘石馬（binary quadratic residue code)而言，假 設該剩餘碼的一碼字所對應的癥狀值為％，第二階係數為 所2，且這個碼字存在v=3個錯誤位元，那麼σ(χ,ζ)可表示如 下： σ(χ^) = 1 + σι(χ)ζ + σ2(χ)ζ2 +σ3(χ)ζ3 =1 + + (m,25 + + mxlx + mxm + mxm + + m,416 + m,531 + m,784 + mxmi + m,1152 + m/290 + m/313)z2 9 201044796 + (m213 + w236 + m282 + m2128 + w2197 + m2266 + m2519 + m2657 + w21025 + W21048 + Wn1186 + m21232 +m214,6 + m21600 + m2^9)z3 因此，一旦<^·+1(χ)為〇，代入/y+2((J州⑷)就會得到函數 值=勺+2(x)=0。所以，檢驗單元723在步驟84發現u勾吲 ，就會結束係數設定。更明確來說，只要依序設定v+丨個 階數以X)、〜⑷…心丨⑴，並確定σν+ι(χ)=〇 ’就代表該碼字 中有V個位元文到通道干擾，而不需再計算隨後係數。 值得注意的是，前述說明是以檢測裝置7處理一碼字 為例，但實際應用上，可接續地處理多個碼字，且每—碼 字的内容會改變對應接收多項式Γ(χ)的係數。 综上所述，本例用以搜尋錯誤位置的檢測裝置7，主要 是利用内插法逼近出/»))，其會滿足常數項 為〇，所以只要有其中—階係數為G，隨後係數便全部為〇 ，也就可以彈性地提前結束設定係數的動作，解碼效率和 糾錯時間明顯優於f知技術，㈣實能達成本發明之目的 准乂上所述者，僅為本發明之較佳實施例而 能以此限定本發明眘# m 田+ 疋不發月實％之範圍’即大凡依本 範圍及發明說明内衮所你+铉四 甲响專利 合所作之簡單的等效變化與比 屬本發明專利涵蓋之範圍内。 、’白仍 10 201044796 【圖式簡單說明】 圖1是一方塊圖，說明本發明用以搜尋錯誤位置的檢 測裝置之較佳實施例； 圖2是一流程圖，說明本實施例之檢測裝置所執行的 方法；及 圖3是一流程圖，說明本實施例之函數產生器所執行 的步驟。The "first-order coefficient ringing" is set to the symptom value, and the checking unit 72 processing order is set to 1. Step 83: The high-order setting unit 722 obtains a function value by substituting the "th order" coefficient 咕) into a j + 1 P-function (»)), and uses the function value as the "j + Ι step The coefficient σchuan(1)", that is, 〇(4). Moreover, the check unit 723 increments the processing order by one. . The Λ+丨(σ/χ) in this example is obtained by Lagrange interpolation, and this function satisfies the constant term as 〇, so it can be said that U is equivalent to 多种) The sum of the powers. The method of (»)) will be described in detail later. Step 84: The checking unit 723 checks ^+] (4 is 〇. If not, skip to step 85; if yes, record the number of bits in which the error occurred v=j, and end the coefficient setting, and then skip to step 86. Step 85: The checking unit 723 checks if the processing order is less than t. If it is 'jump back to step 83; if no', records the number of bits in which the error occurred v=t, and ends the coefficient setting, and then jumps to step 86. This is Since the maximum error correction capacity of the (n, k, d) coded signal is t bits, the highest order of σ(χ, ζ) can only be 7 201044796, ie v St. Step 86: Error position determiner 73 collects The order coefficients σι(χ), %(χ)·'·σν(χ), use the conventional money search method (Chien) to find the root of the error position polynomial σ(ρ) to search for the code word. The bit position where the error occurred. Where σ(χ,·ζ) = 1 + intersection. From the foregoing flow, it can be found that when this example detects that >(χ) is 0, the action of setting the coefficient is stopped, and the result is formed. An error position polynomial σ(χ,ζ) with only ν-order. This also means that this example can also know that the code word is known at the same time. The number of bits of interference ν, so also called as) is a test (10) called the error position polynomial. More specifically, the embodiment can determine the order with the number of bits of the error v, and Knowing technology always finds up to [outside, :). The time at which this 'forms σ(χ,ζ) is elastically reduced, and the operation of finding the root value of σ(χ,ζ) is simplified. Furthermore, the detecting means 7 further comprises - a function of electrically connecting the polynomial generator 72 to generate n 75, and the second order function which can be applied to "all possible code words" is (4). For example, for a codeword with 3 bits, "all possible codewords" are _, 〇〇 1, 〇 1 〇 '〇 111 〇 (, 101, 110, and 111 〇 hypothesis, ..., then A non-zero element that satisfies the generator polynomial g(x)=〇, (^<·.·<Ζν<„, and the initial value of j is 丨. When the function generator wants 201044796 to generate /}+1 (σ7. (χ)) 'The following steps of Figure 3 will be performed: Step 91: Substitute one of the ··., 々, and all possible receiving polynomials r(x) ' to get the corresponding madness value (=σι( χ)), each of which can correspond to an r(x), which corresponds to one. Step 92: According to the error position polynomial σ(χ,ζ) as defined below, for each possible codeword Sort out the j + 1st order coefficient, which will be related to all eves A..., eve~. σ(χ,ζ) = (1 + βι> Z) = j + ^ (x)zj 〇°> ς β, β,...β1ί(10) <Ϊ_2 <...<ν Step 93: Using Lagrange interpolation, approximate the j + 1st order function 'to map from all possible S(4) to the corresponding i+), ie~ +1(x) = /;+1(CTy(JC)). 94: Add j to 1, and repeat steps 92 and 93 until σν〇 is approximated. And this mapping relationship σ; +1(χ) = /; +1(σ7.(χ)), will have a constant term It is equivalent to the sum of "(4) multiple powers". For example, for a (23, 12, 7) binary quadratic residue code, it is assumed that a codeword corresponding to the code of the remaining code corresponds to a symptom value of %, and a second order coefficient is 2, and If there are v=3 error bits in this codeword, then σ(χ,ζ) can be expressed as follows: σ(χ^) = 1 + σι(χ)ζ + σ2(χ)ζ2 +σ3(χ)ζ3 =1 + + (m,25 + + mxlx + mxm + mxm + + m,416 + m,531 + m,784 + mxmi + m,1152 + m/290 + m/313)z2 9 201044796 + (m213 + w236 + M282 + m2128 + w2197 + m2266 + m2519 + m2657 + w21025 + W21048 + Wn1186 + m21232 +m214,6 + m21600 + m2^9)z3 Therefore, once <^·+1(χ) is 〇, substitute /y+ 2 ((J State (4)) will get the function value = Spoon + 2 (x) = 0. Therefore, the check unit 723 finds the u check in step 84, and the coefficient setting is ended. More specifically, as long as the order is set v + 阶 an order with X), ~ (4) ... heart 丨 (1), and determine σν + ι (χ) = 〇 ' represents that there are V bits in the code word to channel interference, without recalculating the subsequent coefficients . It should be noted that the foregoing description is an example in which the detecting device 7 processes a codeword. However, in practical applications, multiple codewords can be processed successively, and the content of each codeword changes the corresponding receiving polynomial χ(χ). coefficient. In summary, the detecting device 7 for searching for the wrong position in this example mainly uses the interpolation method to approximate /»)), which satisfies the constant term as 〇, so as long as the coefficient of the order is G, then the coefficient All of them are 〇, and the action of setting the coefficient can be terminated elastically in advance, and the decoding efficiency and the error correction time are obviously superior to those of the F-known technology, and (4) the object of achieving the object of the present invention is only the present invention. The preferred embodiment can be used to limit the invention to the invention. #m田+ 疋不发月实%的范围', that is, according to the scope and invention description, the simple equivalent of your +铉四甲响 patent combination Changes and ratios are within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a preferred embodiment of a detecting apparatus for searching for an erroneous position of the present invention; FIG. 2 is a flow chart illustrating a detecting apparatus of the present embodiment. The method performed; and FIG. 3 is a flowchart illustrating the steps performed by the function generator of the present embodiment.
11 201044796 【主要元件符號說明】 700 …接收系統 8 3… *…設定cry+1(x)的步驟 •…檢測裝置 8 ◊ t 1 …檢驗σ^/χ)的步驟 …癥狀計算器 8 5…… 一檢驗處理階數的 多項式產生器 步驟 721 - …·初階設定單元 86 …搜尋錯誤位元位 722… …高階設定單元 置的步驟 723… *…檢驗單元 91 _…·求取所有癥狀值 7 3…… …錯誤位置決定器 的步驟 75''… 函數產生器 …求取所有cry+1〇)的 80" 1收信號的步驟 步驟 81 …計算癥狀值的步 93 …逼近/州(σ/χ))的 驟 步驟 82·*· …§史定qO)的步驟 …·使j遞增的步驟 1211 201044796 [Description of main component symbols] 700 ...Receiving system 8 3... *...Steps for setting cry+1(x)•...Detection device 8 ◊ t 1 ...test σ^/χ) Step...Symptom calculator 8 5... ... a polynomial generator step 721 - ... initial setting unit 86 ... search error bit position 722 ... step 723 of high order setting unit set ... * ... check unit 91 _ ... · find all symptom values 7 3... ...step 75' of the error position determiner... function generator... find all the 80" of the cry+1〇) step 1 of the signal step 81 ... calculate the symptom value step 93 ... approximation / state (σ /χ)) Steps of the steps 82·*· ... § history qO)... Step 12 of incrementing j