201044777 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種單端輸型D類放大器，尤指一種雙 反饋差分迴路之單端輸出型D類放大器。 【先前技術】 一般來說，輸出級的放大電路概包含有A類、b類、 ΛΒ類及D類等放大器，早期較常見的為ab類放大器， Ο但隨著半導體製程的成熟，具有較低消耗功率的D類放大 器漸為常見。 D類放大器與AB類放大器最大差異即是輸出脈寬調 變訊號推動電感性負載，而非以線性訊號推動之；其中該 脈寬調變訊號係包含有聲音訊號以及脈寬調變開關訊號和 諧波訊號。由於D類放大器輸出脈寬調變訊號，使得輸出 級開關電路的各開關自高阻抗切換至極低阻抗，且導通時 間短，使得導通電流流經導通電阻時間相對縮短，而較Ab201044777 VI. Description of the Invention: [Technical Field] The present invention relates to a single-ended transmission type D amplifier, and more particularly to a single-ended output type D amplifier having a double feedback differential loop. [Prior Art] In general, the amplifier circuit of the output stage includes amplifiers of Class A, Class B, Class I, and Class D. The early common ones are ab amplifiers, but with the maturity of the semiconductor process, Class D amplifiers with low power consumption are becoming more common. The biggest difference between Class D amplifier and Class AB amplifier is that the output pulse width modulation signal drives the inductive load instead of the linear signal. The pulse width modulation signal contains the sound signal and the pulse width modulation switch signal harmony. Wave signal. Since the class D amplifier outputs a pulse width modulation signal, the switches of the output stage switching circuit are switched from a high impedance to a very low impedance, and the conduction time is short, so that the conduction current flows through the on-resistance time is relatively shortened, and compared with Ab
D 類放大器更有效率，且消耗功率更小。 請參閱第五圖所示，係為一種既有開迴路的單端輸出 型D類放大器（70) ’該D類放大器（70)包含有一增益放大 器（71)、一 PWM調變器（72)、一振盪器（73)、一邏輯電路（74) 及一半橋電路（75)。其中該增益放大器（7丨）輸入端（Vi)係連 接一外部類比聲音訊號，並將該外部類比聲音訊號予以放 大後，如第七圖所示，放大的聲音訊號（V)經對應的PWM 調變器（72)依據振盪器輸出的振盪訊號（S2)輸出脈寬調變 訊號（P，N) ’藉由邏輯電路（74)依據脈寬調變訊號控制半橋 201044777 電路（75)啟閉，由於該半橋電路供外部電感性負載連 接’該電感性負載（60)即可還原出聲音訊號。 由於該振盪器輸出的振盪訊號頻率高，以2〇ίίζ至 20ΚΗζ的聲音訊號為例’其配合採用的振盪訊號為 350ΚΗζ。請參閱第六圖所示，該pwM調變器（72)將放大 後的聲音訊號加入高頻振盪訊號進行脈寬調變訊號⑴g)之 脈寬調變，故能將包含在放大後的聲音訊號（S1)中的雜訊 (N1)推至高頻段，由於該雜訊（N1)被移頻至較高頻段，而 〇聲音資料（S1)則保留在低頻段中，故D類放大器（7〇)輸出 至電感性負載（60)之前可透過該低通濾波器（80)的特性 (81) ’將高頻的雜訊（N1)濾除。 由於上述單端輸出型D類放大器（70)雖能藉由調變技 術將雜訊移頻至高頻段，但必須再配合一高階低通濾波器 (80)才能將高頻段的雜訊加以濾除，造成使用單端輸出端 型D類放大器電路的整體體積無法小型化。再者，由於增 0益放大器（71)及PWM調變器（72)均分別使用放大器元件， 而放大器本身的雜訊基準（Noise Floor)又屬於動態雜訊的 一種，因此當聲音訊號輸入至該增益放大器（71)時，該動 態雜訊會併入放大後的聲音訊號中，造成最後輸出訊號的 總諧波失真加噪訊比（THD+N)與訊號失真雜訊比（SDNR)* 佳。 是以’目前已有一種閉反饋迴路的單端輸出型D類放 大器（70a)推出’請配合參閱第八圖所示，其包含有： 訊號放大器（71)，係包含有一類比輸入端（ν〖），供類 比聲音訊號輸入之； 4 201044777 一比較器（72)，其一輸入端係連接至該訊號放大器（7 〇 的輸出端’另一輸入端則連接一振盈器（73)，將放大的聲 音訊號與振盪訊號比對後’以輸出脈寬調變訊號； 一邏輯電路（74)，係連接至該比較器（72)的輸出端，依 據脈寬調變訊號輸出驅動訊號； 一半橋電路（75)，係由一上側開關電路（751)及一下侧 開關電路（752)組成，其中該上侧及下側開關電路（751，752) 的控制鳊均連接至該邏輯電路（74)的輸出端，以接受驅動 〇訊號而決定上側及下側開關電路（75 1,752)的啟閉，又該半 橋電路（75)的上側開關電路（751)及下側開關電路（752)的串 聯節點為D類放大器的輸出端（D〇)，故可供一電感性負載 (60)連接；及 一階反饋電路（711)，係連接該半橋電路（75)的串聯節 點與訊號放大器（71)的類比輸入端（Vi)。 上述D類放大器（7〇a)包含有一階反饋電路（71)，可將 〇增益放大器本身放大器雜訊、參考電壓雜訊、增益/頻寬乘 積限制以及含三角波生器的非線性值之反饋輸出訊號等非 線性項（non-linear terms)予以消除，然而，上述一階反饋 迴路僅由單一訊號放大器將聲音訊號予以合成後作放大， 因此整體的開迴路增益相當有限。 【發明内容】 有鏗上述問題’本發明的主要目的係提供一種雙反饋 差分迴路之單端輸出型D類放大器，能提供更佳的雜訊失 真訊就比。 5 201044777 欲達上述目的所使用的主要技術手段係令該單端輪出 型的D類放大器的單端輸出端連接有一反向器，以提供一 組差分輸出訊號端；其中該D類放大器係包含有一增益調 整電路、二階積分器、二比較器、一邏輯電路及一半橋電 路，其中該二階積分器係包含有： 一第一差分放大器，係包含有一正向輸入端、一反向 輸入端、一反向差分輸出端及一正向差分輸出端，其中該 正向輸入端係連接至該增益調整電路，以調整該第一差分 〇放大器的增益； 二第一 RC電路，係分別連接於D類放大器的差分輸 出訊號端與該第一差分放大器的正向及反向輪入端之間， 構成二組第一階積分電路； 一第二差分放大器，係包含有一正向輸入端、一反向 輸入端，其中該正向輸入端係連接至該第一差分放大器的 正向差分輸出端，而該反向輸入端則連接至該第一差分放 大器的反向差分輸出端；及 二第二RC電路，係分別連接於D類放大器的差分輸 出訊號端與該第二差分放大器的正向及反向輸入端之間， 構成二組第二階積分電路。 由於單端輸出型D類放大器僅有單一輸出端供電感性 負載連接，故本發明將該反向器連接至該單一輸出端，令 D類放大器知_供一組差分輸出訊號端，而能設計全差分電 路，並配合二階積分器構成二階回饋電路，以幫助第一及 第一差分放大器本身的雜訊等非線性元件能更快速衰減， 並且能提供更高的高頻衰減值，提高整體的雜訊失真雜訊 6 201044777 :;再者，本發明D類放大器差分輸出訊號經 處理後可以得更精細的修正。 g減 综上所述，本發明除了將全差分電路設計在單 型〇類放大器外，更將第一及第二差分放大器納入二階Ξ 鎮系統中’而能有效消除非線性元件消除，而令整： 放大器全線性化，而相對得到更好的總諧波失真加雜訊比 (THD+N)效能。 成比 ❹ Ο 本發明-人-目的係提供一種可大幅降低電磁干擾的 端輸出型〇類放大器，意即上述半橋開關電路的高側開 組與低側開關組再分成二組第一及第二子半橋電路，其$ 第-子半橋電路的高/低側開關數量多於第二子半橋 的高/低側開關數量，其中第一及第二子半橋電路 節點係連接至D類放大器的單輪出端。令上述邏輯電 出四組脈寬調變訊號至本發明的半橋電路，其中第二子^ 橋電路的驅動方式不變，惟邏輯電路產生驅動第一:半橋 電路组之脈寬調變訊號之邏輯運算式係為Μ = 尤； 2 其中又及Ν2為差分輸出訊號端之差分訊號與 二角波訊號比較後的數值。由此邏輯運算式可知，當〇類 放大器的差分輸出端無輸出時，Ν2會完全相同，使 得無脈寬調變訊號輸出至第一子半橋電路’因此本發明即 能讓開關數量多的第一子半橋電路在無訊號輸出時不作 動；而在D類放大器有訊號輸出時，第一子半橋電路的高 /低側開關組的其中-組有動作；是以，能有效降低半^ 電路的切換損失及輸出切換迴轉率（〇utput Mikh slew rate) ’可降低整體D類放大器的eMI值。 7 201044777 【實施方式】 請參閱第一圖所示，係為本發明雙反饋差分迴路之單 端輸出型D類放大器（10)—較佳實例施例的電路方塊圖， 其包含有一增益調整電路（U)、二階積分器、二比較器 (30,31)、一邏輯電路（4〇)、一半橋電路（5〇)及一反向器（24)， 其中該半橋電路（50)係包含有二相串接的高側開關組（5丨）及 一低側開關組（52)，其串聯節點即為d類放大器單輸出端 〇 (Do);又，該單端輸出型（Do)的D類放大器的單端輸出端（D〇) 連接該反向器（24)，以提供一組差分輸出訊號端（D〇+，D〇_)。 其中該二階積分器係包含有： 一第一差分放大器（20) ’係包含有一正向輸入端（+)、 一反向輸入端（-)、一反向差分輸出端（+)及一正向差分輸出 端（-)’其中該正向輸入端（+)係連接至該增益調整電路 (11) ’以調整該第一差分放大器（2〇)的增益； 二第一 RC電路（21) ’係分別連接至差分輸出訊號端 □ (Do+，D0-)與該第一差分放大器（20)的正向及反向輸入端 (+,-)之間，構成二組第一階積分電路； 一第二差分放大益（22) ’係包含有一正向輸入端（+)、 一反向輸入端（-)’其中該正向輸入端（+)係連接至該第一差 分放大器（20)的正向差分輸出端（+)，而該反向輸入端㈠則 連接至該第一差分放大器（20)的反向差分輸出端（_);及 二第二RC電路（23) ’係分別連接於差分輸出訊號端 (Do+，D0-)與該第二差分放大器（22)的正向及反向輸入端之 間，構成二組第二階積分電路。 8 201044777Class D amplifiers are more efficient and consume less power. Please refer to the fifth figure, which is a single-ended output type D amplifier (70) with open circuit. 'The class D amplifier (70) includes a gain amplifier (71) and a PWM modulator (72). An oscillator (73), a logic circuit (74) and a half bridge circuit (75). The gain amplifier (7丨) input terminal (Vi) is connected to an external analog sound signal, and the external analog sound signal is amplified, as shown in the seventh figure, the amplified sound signal (V) is corresponding to the PWM. The modulator (72) outputs a pulse width modulation signal (P, N) according to the oscillation signal (S2) outputted by the oscillator. The logic circuit (74) controls the half bridge 201044777 circuit (75) according to the pulse width modulation signal. Closed, because the half-bridge circuit is connected to the external inductive load, the inductive load (60) can restore the sound signal. Since the oscillator output frequency of the oscillator is high, an audio signal of 2 〇 ίί ζ to 20 为 is taken as an example. The oscillating signal used in conjunction with the oscillating signal is 350 ΚΗζ. Referring to the sixth figure, the pwM modulator (72) adds the amplified audio signal to the high-frequency oscillation signal to adjust the pulse width of the pulse width modulation signal (1)g), so that the amplified sound can be included. The noise (N1) in the signal (S1) is pushed to the high frequency band. Since the noise (N1) is shifted to the higher frequency band, and the sound data (S1) is kept in the low frequency band, the class D amplifier (7) 〇) Before the output to the inductive load (60), the high-frequency noise (N1) can be filtered out by the characteristics of the low-pass filter (80) (81). Since the single-ended output type D amplifier (70) can shift the noise to the high frequency band by the modulation technology, it must be combined with a high-order low-pass filter (80) to filter the high-frequency noise. The overall size of the circuit using a single-ended output type D amplifier cannot be miniaturized. Furthermore, since the booster amplifier (71) and the PWM modulator (72) each use an amplifier component, the noise floor of the amplifier itself is also a type of dynamic noise, so when the sound signal is input to When the gain amplifier (71) is used, the dynamic noise is incorporated into the amplified audio signal, resulting in total harmonic distortion plus noise ratio (THD+N) and signal distortion ratio (SDNR) of the final output signal. good. It is based on the 'single-ended output class D amplifier (70a) that has a closed feedback loop. Please refer to the eighth figure, which includes: Signal amplifier (71), which contains an analog input (v 〖), for analog audio signal input; 4 201044777 a comparator (72), one input is connected to the signal amplifier (7 〇 output terminal 'the other input is connected to a vibrator (73), After the amplified sound signal is compared with the oscillation signal, the output pulse width modulation signal is connected; a logic circuit (74) is connected to the output end of the comparator (72), and outputs a driving signal according to the pulse width modulation signal; The half bridge circuit (75) is composed of an upper switch circuit (751) and a lower side switch circuit (752), wherein the control ports of the upper and lower switch circuits (751, 752) are connected to the logic circuit ( The output terminal of 74) determines the opening and closing of the upper and lower switching circuits (75 1, 752) by receiving the driving signal, and the upper switching circuit (751) and the lower switching circuit (752) of the half bridge circuit (75). The series node is a class D amplifier The output terminal (D〇) is connected to an inductive load (60); and the first-order feedback circuit (711) is connected to the series node of the half bridge circuit (75) and the analog input terminal of the signal amplifier (71). (Vi) The above Class D amplifier (7〇a) contains a first-order feedback circuit (71) that can amp the gain amplifier itself with amplifier noise, reference voltage noise, gain/bandwidth product limits, and non-triangle-containing devices. The non-linear terms such as the feedback value of the linear value are eliminated. However, the first-order feedback loop combines the sound signals by a single signal amplifier and amplifies them, so the overall open loop gain is rather limited. SUMMARY OF THE INVENTION The above object is to provide a single-ended output type D amplifier with dual feedback differential loops, which can provide better noise distortion ratio. 5 201044777 The main technical means is that the single-ended output of the single-ended wheel-type class D amplifier is connected with an inverter to provide a set of differential output signal terminals; wherein the class D amplifier package The invention comprises a gain adjustment circuit, a second order integrator, a second comparator, a logic circuit and a half bridge circuit, wherein the second order integrator comprises: a first differential amplifier comprising a forward input end and an inverse input end a reverse differential output terminal and a forward differential output terminal, wherein the forward input terminal is coupled to the gain adjustment circuit to adjust a gain of the first differential 〇 amplifier; and the second RC circuit is respectively connected to The differential output signal terminal of the class D amplifier and the forward and reverse wheel-in terminals of the first differential amplifier form two sets of first-order integration circuits; and a second differential amplifier includes a forward input terminal and a An inverting input, wherein the forward input is coupled to a forward differential output of the first differential amplifier, and the inverted input is coupled to an inverted differential output of the first differential amplifier; The two RC circuits are respectively connected between the differential output signal terminal of the class D amplifier and the forward and reverse input terminals of the second differential amplifier to form two sets of second order integration circuits.Since the single-ended output type D amplifier has only a single output power supply inductive load connection, the present invention connects the inverter to the single output terminal, so that the class D amplifier knows that a set of differential output signal terminals can be designed. The fully differential circuit is combined with a second-order integrator to form a second-order feedback circuit to help the nonlinear components such as the first and first differential amplifiers to be attenuated more quickly, and to provide higher high-frequency attenuation values and improve the overall Noise Distortion Noise 6 201044777 : In addition, the differential output signal of the class D amplifier of the present invention can be processed to obtain finer correction. g reduction, in addition to the design of the fully differential circuit in the single-type 〇 class amplifier, the first and second differential amplifiers are incorporated into the second-order Ξ-type system, and the nonlinear component can be effectively eliminated. Integrity: The amplifier is fully linearized, and relatively better total harmonic distortion plus noise ratio (THD+N) performance. The present invention-person-purpose system provides a terminal output type sigma amplifier which can greatly reduce electromagnetic interference, that is, the high side open group and the low side switch group of the above half bridge switch circuit are further divided into two groups. The second sub-half bridge circuit has a higher number of high/low side switches of the first-sub-half bridge circuit than the number of high/low side switches of the second sub-half bridge, wherein the first and second sub-half bridge circuit nodes are connected Single-wheel output to class D amplifier. Let the logic output four sets of pulse width modulation signals to the half bridge circuit of the present invention, wherein the driving mode of the second sub-bridge circuit is unchanged, but the logic circuit generates the driving first: the pulse width modulation of the half bridge circuit group The logical operation of the signal is Μ = 尤; 2 and Ν 2 is the value of the differential signal and the dihedral signal at the differential output signal end. According to the logic expression, when the differential output of the 〇 class amplifier has no output, Ν2 will be identical, so that no pulse width modulation signal is output to the first sub-half bridge circuit. Therefore, the present invention can make the number of switches large. The first sub-half bridge circuit does not operate when there is no signal output; and when the class D amplifier has signal output, the middle group of the high/low side switch group of the first sub-half bridge circuit has an action; The switching loss of the half circuit and the output switching rate (〇utput Mikh slew rate) 'can reduce the eMI value of the overall class D amplifier. 7 201044777 [Embodiment] Please refer to the first figure, which is a circuit block diagram of a single-ended output type D amplifier (10) of a dual feedback differential loop of the present invention, which includes a gain adjustment circuit. (U), a second-order integrator, two comparators (30, 31), a logic circuit (4〇), a half bridge circuit (5〇), and an inverter (24), wherein the half bridge circuit (50) is The high side switch group (5丨) and the low side switch group (52) including two phases are connected in series, and the series node is a single output terminal 〇(Do) of the class d amplifier; further, the single-ended output type (Do) The single-ended output (D〇) of the Class D amplifier is connected to the inverter (24) to provide a set of differential output signal terminals (D〇+, D〇_). The second-order integrator includes: a first differential amplifier (20)' includes a forward input terminal (+), an inverting input terminal (-), a reverse differential output terminal (+), and a positive To the differential output terminal (-)', wherein the forward input terminal (+) is connected to the gain adjustment circuit (11)' to adjust the gain of the first differential amplifier (2〇); the second first RC circuit (21) 'Connected to the differential output signal terminal □ (Do+, D0-) and the forward and reverse input terminals (+, -) of the first differential amplifier (20) to form two sets of first-order integration circuits; A second differential amplification (22) 'includes a forward input terminal (+) and an inverting input terminal (-)', wherein the forward input terminal (+) is coupled to the first differential amplifier (20) a forward differential output (+), and the reverse input (1) is connected to the inverse differential output (_) of the first differential amplifier (20); and the second second RC circuit (23) is respectively Connected between the differential output signal terminal (Do+, D0-) and the forward and reverse input terminals of the second differential amplifier (22) to form two sets of second order products Subcircuit. 8 201044777
一輸出端（D0)，使 的雜訊等非線性元件能更快速衰減，如 月b提供更尚的高頻衰減值，提高整體 (ίο)提供一組差分輸出訊號端 差分電路，並配合二階積分器構 '及第二差分放大器（20,22)本身 如第二圖所示，並且An output (D0) enables nonlinear components such as noise to be attenuated more quickly. For example, monthly b provides a higher frequency attenuation value, and the overall (ίο) provides a set of differential output signal terminal differential circuits, and cooperates with second-order integration. The second differential amplifier (20, 22) itself is as shown in the second figure, and
統中而此有效/肖除非線性元件消除，而令整個D類放大 器全線性t，而相對得到更好的總諧波失真加雜訊比 (THD+N)效能。再者，全差分電路架構的單端輸出型d類 放大器能提高電源紋波抑制比（p〇wer supply ration，PSRR)、共模拒斥比（c〇mm〇n m〇de rejecti〇n)及抗雜 訊串音（crosstalk n〇ise rejection)。 再請參閱第三圖所示，係為本發明單端輸出型D類放 大器（10a)的第二較佳實施例，其大多結構與第一較佳實施 例相同，惟該半橋電路（5〇)的高側開關組與低側開關組再 進一步分成二組第一及第二子半橋電路（5〇a，5〇b)，其中第 一子半橋電路（50a)的高/低側開關數量多於第二子半橋電 路（5〇b)的高/低側開關數量，其中第一及第二子半橋電路 (50a，50b)的串聯節點係連接至d類放大器的單輸出端 (Do)。其中該第一子半橋電路（5〇a)的高/低側開關數量為 第二子半橋電路（50b)的高/低側開關數量的3至5倍》 201044777 再者，本實施例的邏輯電路(40a)増加產生驅動第一子 半橋電路（5〇a)二組之脈寬調變訊號之邏輯運算式’係分別 為及心，其巾χ及N2為差分輸出訊號端之 差分訊號與三角波訊號比較後的數值。 請配合第四A圖所示，由於雙反饋差分迴路設計，當 D類放大器（1〇)輸出大訊號時，本發明的二 會取得差分訊號（V-，V+)，並分別與三角波訊號（咖行^ 較，以輸出第二子半橋電路(5〇b)的二組脈寬調變訊號 〇 (N2，P2)及一組參考脈寬調變訊號(χ)。當邏輯電路(4〇)接收 到此N2，P2兩組脈寬調變訊號後會直接輸出至第二子半橋 電路（50b)，再依據參考脈寬調變訊號（χ)及其中一組脈寬 調變訊號（Ν2)帶入上述邏輯運算式，輸出第一子半橋電路 的二組脈寬調變訊號（Ν1，Ρ1)。誠如本圖所示，當D類放大 器（l〇b)有訊號輸出時，第一子半橋電路（5〇a)的高侧開關組 及低側開關組僅其中一組有動作。 再如第四B圖所示，當D類放大器（1〇b)單輸出端（D〇) 無輸出時，X及N2會完全相同，使得無脈寬調變訊號輸 出至第一子半橋電路（5〇a)，即N1呈低電位而ρι呈高電位， 令第子半橋電路（50a)的高側開關及低側開關均關閉不導 通。因此，本發明即能讓開關數量多的第一子半橋電路（5〇a) 在無訊號輸出時不作動，而在D類放大器（1〇a)有訊號輸出 時’第一子半橋電路（5〇a)的高側開關組及低側開關組僅其 中一組有動作’·是以，能有效降低半橋電路的切換損失及In the system, this is effective/shaw unless the linear components are eliminated, so that the entire class D amplifier is fully linear t, and relatively better total harmonic distortion plus noise ratio (THD+N) performance. Furthermore, the single-ended output type D amplifier of the fully differential circuit architecture can improve the power supply ripple rejection ratio (PSRR) and the common mode rejection ratio (c〇mm〇nm〇de rejecti〇n). Crosstalk n〇ise rejection. Referring to FIG. 3 again, it is a second preferred embodiment of the single-ended output type D amplifier (10a) of the present invention, and most of the structures are the same as those of the first preferred embodiment, but the half bridge circuit (5) The high side switch group and the low side switch group of the 〇) are further divided into two sets of first and second sub-half bridge circuits (5〇a, 5〇b), wherein the first sub-half bridge circuit (50a) is high/low The number of side switches is greater than the number of high/low side switches of the second sub-half bridge circuit (5〇b), wherein the series nodes of the first and second sub-half bridge circuits (50a, 50b) are connected to the single class d amplifier Output (Do). The number of high/low side switches of the first sub-half bridge circuit (5〇a) is 3 to 5 times that of the second sub-bridge circuit (50b). 201044777 Furthermore, this embodiment The logic circuit (40a) adds a logic operation type for generating the pulse width modulation signals of the first sub-half bridge circuit (5〇a), respectively, and the frame is respectively a heart, and the frame and the N2 are differential output signals. The value of the difference signal compared with the triangular wave signal. Please cooperate with the fourth A picture. Because of the dual feedback differential circuit design, when the class D amplifier (1〇) outputs a large signal, the second method of the present invention obtains the differential signal (V-, V+) and respectively the triangular wave signal ( The coffee line ^ is compared to output two sets of pulse width modulation signals N (N2, P2) of the second sub-half bridge circuit (5 〇 b) and a set of reference pulse width modulation signals (χ). When the logic circuit (4) 〇) After receiving the N2 and P2 pulse width modulation signals, they will be directly output to the second sub-half bridge circuit (50b), and then according to the reference pulse width modulation signal (χ) and a set of pulse width modulation signals thereof. (Ν2) Bring the above logic operation formula and output two sets of pulse width modulation signals (Ν1, Ρ1) of the first sub-half bridge circuit. As shown in this figure, when the class D amplifier (l〇b) has signal output When only the high side switch group and the low side switch group of the first sub-half bridge circuit (5〇a) have an action, as shown in FIG. 4B, when the class D amplifier (1〇b) has a single output. End (D〇) When there is no output, X and N2 will be identical, so that no pulse width modulation signal is output to the first sub-half bridge circuit (5〇a), that is, N1 is low and ρι is high. Therefore, the high side switch and the low side switch of the first sub-bridge circuit (50a) are both turned off and not turned on. Therefore, the present invention enables the first sub-half bridge circuit (5〇a) having a large number of switches to be outputted without a signal. No action, and when the class D amplifier (1〇a) has a signal output, 'the high-side switch group and the low-side switch group of the first sub-half bridge circuit (5〇a) have only one of the actions'. Can effectively reduce the switching loss of the half bridge circuit and
輸出切換迴轉率（output switch slew rate)，可降低整體D 類放大盗的EMI值。 201044777 以上所述僅是本發明的較佳實施例而已，並非對本發 2做任何形式上的限制，雖然本發明已以較佳實施例揭露 上’然而並非用以限定本發明，任何熟悉本專業的技術 人員，在不脫離本發明技術方案的範圍内，當可利用上述 揭不的技術内谷作出些許更動或修飾為等同變化的等效實 轭例’但凡是未脫離本發明技術方案的内纟，依據本發明 的技術實質對以上實施例所作的任何簡單修改、等同變化 與修飾，均仍屬於本發明技術方案的範圍内。 【圖式簡單說明】 第一圖：係本發明第一較佳實施例的電路方塊圖。 第二圖：係第一圖輸出放大聲音訊號之頻域圖。 第二圖：係本發明第一較佳實施例的電路方塊圖。 第四A、B圖：第三圖的波形圖。 第五圖：係一種開迴路的單端輸出型D類放大器電路 方塊圖。 第六圖：係第五圖輸出放大聲音訊號之頻域圖。 第七圖：係第五圖的波形圖。 第八圖：係一種閉迴路的單端輸出型D類放大器電路 方塊圖。 【主要元件符號說明】 (10)(10a)D類放大器 （11)增益調整電路 (20)第一差分放大器 （21)第一 RC電路 11 201044777The output switch slew rate can reduce the EMI value of the overall class D amplification. 201044777 The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make a slight modification or modify the equivalent conjugate example of the equivalent change without departing from the technical solution of the present invention, without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications to the above embodiments in accordance with the technical spirit of the present invention are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram of a first preferred embodiment of the present invention. The second picture is the frequency domain diagram of the first picture output amplified sound signal. Second Figure: A block diagram of a circuit in accordance with a first preferred embodiment of the present invention. Figure 4A, B: Waveform of the third figure. Figure 5: Block diagram of a single-ended output type D amplifier circuit with open circuit. Figure 6: The frequency map of the amplified audio signal in the fifth diagram. Figure 7: The waveform diagram of the fifth diagram. Figure 8: Block diagram of a closed-loop single-ended output class D amplifier circuit. [Description of main component symbols] (10) (10a) Class D amplifier (11) Gain adjustment circuit (20) First differential amplifier (21) First RC circuit 11 201044777
(22)第二差分放大器 (30)比較器 (32)三角波產生器 (50)橋式電路 (50b)第一子橋式電路 (52)低側開關組 (70) (7〇a：)D類放大器 (71) 增益放大器 (73)振盪器 (75)半橋開關 (752)低側開關組 (23)第二RC電路 (31)比較器 (40)(40a)邏輯電路 (50a)第二子橋式電路 (51)高側開關組 (60)電感性負載 (701)差分放大器 (72)PWM調變器 (74)邏輯電路 (751)高側開關組 (80)低通濾波器 ❹ 12(22) Second differential amplifier (30) Comparator (32) Triangle wave generator (50) Bridge circuit (50b) First sub-bridge circuit (52) Low-side switch group (70) (7〇a:)D Class Amplifier (71) Gain Amplifier (73) Oscillator (75) Half Bridge Switch (752) Low Side Switch Group (23) Second RC Circuit (31) Comparator (40) (40a) Logic Circuit (50a) Second Sub-bridge circuit (51) High-side switch group (60) Inductive load (701) Differential amplifier (72) PWM modulator (74) Logic circuit (751) High-side switch group (80) Low-pass filter ❹ 12