201044579 P970168 30216twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件及其製造方法，且特 別是有關於一種金氧半導體(metal oxide semiconductor， MOS)電晶體及其製造方法。 【先前技術】 隨著半導體製程技術的快速發展，為了增進元件的速 度與效能，整個電路元件的尺寸必須不斷縮小，且元件的 積集度也必須持續不斷地提升。在對元件積集度要求越來 越咼的趨勢下，必須考量到如漏電流、熱載子效應(h〇t carrier effect)或短通道效應（sh〇rt channei effect，SCE)等元 件特性的改變，以聽對積體電路的可靠度與效能造成嚴 重影響。 以金氧半導體電晶體為例，圖丨是習知之一種金氧半 導體電晶體的剖面示意圖。如圖i所示，閘極結構1〇2配 ^基底100上，而間隙壁104配置在閘極結構1〇2的側 j。源極祕延伸(s峨e dmin extensi⑽，SDE)的偏移間 '、（〇ffSet Spacer)106形成在閘極結構102盥間隙壁104 3 =位於間隙壁刚與基底觸之間。^極區舰 &麵分別配置在間隙壁104夕卜側的基底100中。 ’104^^其1與及極延伸區11%分別配置在間隙壁 sin 巾。也就是說儀延賴服是位 W原極區驗與閑極結構搬之間，而沒極延伸區⑽ 201044579 . —-----30216twf.doc/n 疋位於汲極區l〇8b與閘極結構102之間。閘極結構102、 源極區108a與汲極區1〇肋上還配置有自對準金屬矽化物 (salicide)112。 Ο Ο 考慮到源極延伸區ll〇a與没極延伸區的濃度會 影響元件效能，源極延伸區11〇a與汲極延伸區u〇b的摻 雜劑量必須夠重以確保元件效能及品質。然而，重摻雜的 源極延伸區l10a與汲極延伸區u〇b會導致很高的間極亏丨 發汲極漏電机(gate_incjuce(j drain leakage，GIDL)和嚴重的 ’、、、、載子效應。雖然藉由降低源極汲極延伸的摻雜劑量可以 咸緩閘極引發;及極漏電流與熱載子效應，但卻會使得片電 阻(sheet職伽吻與閘極没極間的重疊電容&秦d咖 erap capacitance)上升而嚴重影響元件效能。再者，間隙 :二=夠厚才能防止源極區施與汲極區_的掺 源極延伸區n〇a與沒極延伸區n〇b，且必須保 m空間使源贿極擴散，^ 效應的發生。此外，當基底刪上L有 ^，二間隙壁104往往會造成應力層遠離通道 Q因而降低應力層輯子遷移率的提升效果。 件政肖b，將疋目前極為重要的課題。 【發明内容】 升。本發明提供—種轉體元件，其元件效能可獲得提 201044579 P970168 302l6twf.doc/n 本發明知供一種半導體元件的製造方法，會形成傾斜 且彎曲的源極汲極延伸(SDE)。 本發明提出一種半導體元件，其包括基底、閘極結 構、摻雜區以及輕摻雜區。基底具有/階狀上表面，其中 階狀上表面包括第一表面、第二表面及第三表面。第二表 面低於第一表面。第三表面連接第一表面與第二表面。閘 極結構配置於第—表面上。摻㈣配置於閘極結構兩側的 基底中，且位於第二表面下。輕摻雜區分別配置於閘極結 構與摻雜區之間的基底中。各輕摻祕包括相互連接的第 一部分與第二部分。第一部分配置於第二表面下，且第二 部分配置於第三表面下。 在本發明之-實施例中，上述之第三表面傾斜於第一 表面’且第-表面之延伸方向與第三表面所 於45。至60。之間。 内’丨 在^發明之-實施财，上述之第—表面實f上平行 於弟—表面。 在本發明之一實施例中，上述之第一表面與第二表面 之=的高度差介於25GA至_A之間，而第_表面 二表面之間的水平間距介於25〇A至35GA之間。” =發明之一實施例中，上述各輕換雜區的第 的長度介於50人至15〇 A之間，而第-邱八 3〇〇A至7〇〇A之間。 而弟一‘的長度介於 明之—實施例中’半導體元件更包括間隙壁， 配置於閘極結_側壁上，錄於輕摻雜上。間隙壁的 302f6twf.doc/n 201044579 厚度例如是介於50 Α至200 Α之間。間隙壁的材料可以是 氧化物、氮氧化物（oxynitride)、氮化氧化物（此仙^ oxide)、氮化物或上述材料的組合。 在本發明之一實施例中’半導體元件更包括自對準金 屬矽化物層，配置於閛極結構上及摻雜區上。 在本發明之一實施例中’半導體元件更包括應力層， Ο Ο 配置於基底上。應力層例如是會提供壓縮應力或拉伸應力 至通道區的氮化物薄膜。 在本發明之一實施例中，半導體元件更包括井區，配 置於基底中，其中摻雜區與輕摻雜區位於此井區中。 在本發明之一實施例中，半導體元件更包括袋狀(環狀 植入區，配置於閘極結構下的基底中，且各袋狀(環狀 入區分別相鄰於各摻雜區。袋狀(環狀)植入區例如是局 (localized)袋狀(環狀)植入區或複合(multiple)袋狀(環狀)植 入區。 本發明另提出-種半導體元件的製造方法。首先 供-基底，胁基底上形朗贿構。㈣ 移除部分基底以形成階狀上表面，其中階狀上表 第表面及第三表面。第二表面低於第-表Ϊ 表面連接弟一表面與第二表面。於閘極結構 美 隹區。各輕摻雜區包括相互連接的第一部二 與弟一部分。第一部分西己晋於笛. 刀 署减弟二表面下，且第二部分配 於基底中形成摻雜區，各摻雜區位於第 一表面下且分別鄰接輕摻雜區。 、弟 7 201044579 P970168 30216twf.doc/n 在本發明之一實施例中，上述之 表面，且第一表面之延伸方向與第三:表面傾斜於第— 於45。至00〇之間。 又面所形成之夾角介 在本發明之一實施例中，上述 於第二表面。 弟''表面實質上平行 在本發明之一實施例中，上述之 之間的高度差介於250 Α至 _人之與第二表面 二表面之間的水平間距介於250人 弟—表面與第 在本發明之-實施例中，上述 =間。 的長度介於50 A至15G A之間，=摻雜區的第-部分 300 A至700 A之間。 乐〜部分的長度介於 在本發明之一實施例中，上述之 構的側壁上雜摻雜區上形成第 去更包括於閑極結 厚度例如是介於5〇 A至2〇〇 A之間。、土第間隙壁的 在本發明之一實施例中，上 包括下列师錢，絲底场的方法 娜結構的側壁上形成第二間隙壁：才第 __上的部分間隙壁材料層 後，ΐί Γ實施Γ ’在移除部分_猜料層之 後以弟一間隙壁為罩幕形成接雜區 層之後且在形成第-㈣、壁之f 麵成間隙土材料 在作M 形成輕摻雜區；或者， 在私除弟一問隙壁之後，形成輕摻雜區。 在本發明之一實施例中，在形成ii隙壁之後，形 30216twfdoc/n 201044579 成輕掺雜區與摻雜區。舞松 製程或兩步驟製程而形2 —與_區例如是利用單一 种’上述之方法更包括在間極結 構上及摻魏切成自對準金射化物層。 形成=明工述之繼包括於基底上 區的氮化物_。健縮應力或拉伸應力至通道201044579 P970168 30216twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a metal oxide semiconductor (MOS) transistor And its manufacturing method. [Prior Art] With the rapid development of semiconductor process technology, in order to improve the speed and performance of components, the size of the entire circuit components must be continuously reduced, and the integration of components must be continuously improved. In the trend of increasing component integration requirements, factors such as leakage current, h〇t carrier effect or short channel effect (SCE) must be considered. The change is severely affected by the reliability and performance of the integrated circuit. Taking a MOS transistor as an example, the figure is a schematic cross-sectional view of a conventional gold-oxide semiconductor transistor. As shown in Figure i, the gate structure 1〇2 is disposed on the substrate 100, and the spacers 104 are disposed on the side j of the gate structure 1〇2. Between the offsets of the source secret extension (s峨e dmin extensi (10), SDE), (〇 ffSet Spacer) 106 is formed in the gate structure 102 盥 spacer 104 3 = between the gap wall and the substrate touch. The polar region ship & faces are respectively disposed in the substrate 100 on the side of the spacer 104. The '104^^1 and the pole extension area 11% are respectively disposed in the spacer sin towel. That is to say, the instrument extension is between the W-primary zone test and the idle pole structure, and the Wuji extension zone (10) 201044579 ..-----30216twf.doc/n 疋 is located in the bungee zone l〇8b and Between the gate structures 102. A self-aligned metal salicide 112 is also disposed on the gate structure 102, the source region 108a, and the drain region 1 rib. Ο Ο Considering that the concentration of the source extension ll〇a and the immersion extension affects the device performance, the doping dose of the source extension 11〇a and the drain extension u〇b must be heavy enough to ensure component efficiency and quality. However, the heavily doped source extension region l10a and the drain extension region u〇b will result in a very high gate loss ratio (GID) and a serious 'G-Drainage (GIDL) and severe ',,,, The carrier effect. Although the doping amount of the source drain extension can be reduced, the gate initiation can be induced; and the leakage current and the hot carrier effect are caused, but the sheet resistance (sheet entanglement and gate immersion) The overlap capacitance & erap capacitance rises and seriously affects the component performance. Furthermore, the gap: two = thick enough to prevent the source region and the drain region _ the source extension region n〇a and no The pole extension n〇b, and must maintain m space to make the source bribe diffusion, ^ effect occurs. In addition, when the substrate is deleted by L, the two spacers 104 tend to cause the stress layer to move away from the channel Q and thus reduce the stress layer The effect of improving the sub-mobility rate is a very important topic at present. [Abstract] The present invention provides a rotating element, and the component performance thereof can be obtained by 201044579 P970168 302l6twf.doc/n. Knowing that a semiconductor component manufacturing method will form Oblique and curved source drain extension (SDE). The present invention provides a semiconductor device including a substrate, a gate structure, a doped region, and a lightly doped region. The substrate has a / stepped upper surface, wherein the stepped upper surface The first surface, the second surface and the third surface are included. The second surface is lower than the first surface. The third surface is connected to the first surface and the second surface. The gate structure is disposed on the first surface. The doped (four) is disposed on the gate The substrate on both sides of the structure is located under the second surface. The lightly doped regions are respectively disposed in the substrate between the gate structure and the doped region. Each of the light doping includes a first portion and a second portion connected to each other. One portion is disposed under the second surface, and the second portion is disposed under the third surface. In the embodiment of the invention, the third surface is inclined to the first surface 'and the extending direction of the first surface and the third surface Between 45 and 60. The inner surface is invented, the above-mentioned surface-surface is parallel to the surface-surface. In one embodiment of the invention, the first surface is The difference in height of the second surface 25GA to _A, and the horizontal spacing between the surface of the first surface is between 25 〇A and 35 GA." = In one embodiment of the invention, the length of each of the above light-changing regions is 50 Between 15 〇A and 第 邱 八 〇〇 〇〇 〇〇 。 。 。 。 。 。 。 而 而 而 而 而 而 而 而 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The junction_side wall is recorded on the lightly doped. The thickness of the spacer is 302f6twf.doc/n 201044579, for example, between 50 Α and 200 。. The material of the spacer may be oxide, oxynitride, Nitrided oxide (this oxide), nitride or a combination of the above materials. In one embodiment of the invention, the semiconductor component further includes a self-aligned metal germanide layer disposed on the drain structure and on the doped region. In one embodiment of the invention, the semiconductor component further includes a stressor layer disposed on the substrate. The stressor layer is, for example, a nitride film that provides compressive or tensile stress to the channel region. In one embodiment of the invention, the semiconductor component further includes a well region disposed in the substrate, wherein the doped region and the lightly doped region are located in the well region. In an embodiment of the invention, the semiconductor component further includes a bag-shaped (annular implanted region disposed in the substrate under the gate structure, and each of the pockets (the annular inlet regions are respectively adjacent to the respective doped regions). The bag-shaped (annular) implanted region is, for example, a localized bag-shaped (annular) implanted region or a composite bag-shaped (annular) implanted region. The present invention further proposes a method of manufacturing a semiconductor device First, the base is provided, and the base is formed on the flank. (4) Part of the base is removed to form a stepped upper surface, wherein the first surface and the third surface are stepped. The second surface is lower than the surface of the surface. a surface and a second surface. The gate structure is in the Meilu area. Each lightly doped area includes a first part of the second part and a part of the brother. The first part is Xijin Jindi. The knife department reduces the second surface, and the first The two portions are formed in the substrate to form doped regions, and the doped regions are located under the first surface and respectively adjacent to the lightly doped regions. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 And the extension direction of the first surface and the third: the surface is inclined to the first - 45. to 00 The angle formed by the face is in the embodiment of the present invention, the second surface is the second surface. The surface of the invention is substantially parallel. In one embodiment of the invention, the height difference between the above is 250. The horizontal spacing between the _ human and the second surface of the second surface is between 250 Å - the surface and in the embodiment of the invention, the length of the above = between 50 A and 15 G A, = between the first portion of the doped region 300 A to 700 A. The length of the portion of the portion is in the embodiment of the present invention, and the formation of the doped region on the sidewall of the above-described structure is further included in the idle The thickness of the pole junction is, for example, between 5 〇A and 2 〇〇A. In one embodiment of the invention, the first spacer wall includes the following division of money, and the method of forming the bottom field of the wire is formed on the sidewall of the structure. The second spacer: after the portion of the spacer material layer on the __, ΐ Γ Γ Γ 在 在 在 在 在 在 在 在 在 在 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 猜 猜 猜 猜 猜 猜 猜 猜- (d), the wall of the f surface into a gap material in the form of M to form a lightly doped area; or, in private After the gap wall, a lightly doped region is formed. In an embodiment of the invention, after forming the ii-gap wall, the shape 30216twfdoc/n 201044579 is a lightly doped region and a doped region. The dance process or a two-step process is formed. 2—the _ region is, for example, a single type of method described above, which is further included on the interpole structure and is doped into a self-aligned gold-emitting layer. Forming a nitride that is included in the upper region of the substrate. Shrinkage stress or tensile stress to the channel
O ❹ r在二 =:===:: 狀，環狀)植，如是局部袋 以在形成階狀上表面之後祕成之^ S i之後而形成之，或在形成間隙壁材料層t = 成輕摻雜區之前而形成之。 後且在形 摻雜元，有傾斜且彎曲的輕 勹厲拉及極延伸（SDE)，可有助於減軔埶 口呈^不需降低輕摻雜區的掺質濃度。再者二二 ⑽(GIDL)與閑極沒極間的重疊電容。 *及極漏 曲的ϊ:雜i發導體元件的製造方法形成傾斜且彎 ^、°°因此摻雜區的擴散不會受到摻雜區擴散 9 201044579 P970168 30216twf.doc/n 的影響’而可以在此半導體元件結構中形成更薄的間隙 壁。如此一來’利用形成更薄的間隙壁，可以讓應力層更 接近通道區，使元件效能能夠獲得進一步的改善。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 圖2是依照本發明之一實施例之一種半導體元件的剖 面示意圖。須注意的是，下述實施例是以P型來表示第一 導電型，而以N型來表示第二導電型，但本發明並不以此 為限。熟習此技藝者應了解，本發明亦可以將第一導電型 置換成N型’並將第二導電型置換成p型以形成半導體元 件。 請參照圖2,本發明之半導體元件至少包括基底2〇〇、 閘極結構204、摻雜區206以及輕摻雜區208。提供具有第 一導電型的基底200，其可以是p型石夕基底、p型蠢晶砍 (epi-silicon)基底或是絕緣層上覆p型半導體 ❹ (semiconductor-on-insulator, SOI)基底。基底 200 例如是具 有階狀上表面201。階狀上表面201包括第一表面201a、 第二表面201b及第三表面201c，其中第三表面201C連接 第一表面2〇la與第二表面201b。低於第一表面20la的第 二表面201b實質上可平行於第一表面201a。當第一表面 201a與第二表面201b實質上為平坦面時，第三表面2〇lc 可傾斜於第一表面201a。也就是說，第三表面201C是介 10 201044579 i v ……30216twf.doc/n 於第一表面2〇la與第二表面201b之間的斜面，其中斜面 的上緣連接第—表面201a,而斜面的下緣連接第二表面 201b。在一實施例中，第一表面2〇la與第二表面2〇ib之 間的高度差介於250人至60〇A之間。在—實施例中’ 第一表面201a與第二表面2〇lb之間的水平間距介於 250 A至350 A之間。在一實施例中，第一表面2〇la的延 伸方向與第二表面201c所形成之夾角0介於45。至60。 ΟO ❹ r in the second =: ===:: shape, ring) planting, such as a partial pocket to form after the formation of the stepped upper surface ^ S i, or in the formation of the spacer material layer t = It is formed before the lightly doped region. After and in the form of doped elements, there are inclined and curved light squeezing and pole extension (SDE), which can help reduce the thickness of the doping of the lightly doped region. Furthermore, the overlapping capacitance between the two (10) (GIDL) and the idle pole is not. * and extremely leaky flaws: the manufacturing method of the hybrid i-conductor element is formed obliquely and bent, °° so that the diffusion of the doped region is not affected by the doping region diffusion [201044579 P970168 30216twf.doc/n] Thinner spacers are formed in this semiconductor device structure. In this way, by forming a thinner spacer, the stress layer can be brought closer to the channel region, so that the component performance can be further improved. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] FIG. 2 is a cross-sectional view showing a semiconductor device in accordance with an embodiment of the present invention. It should be noted that the following embodiment shows the first conductivity type in the P type and the second conductivity type in the N type, but the invention is not limited thereto. It will be appreciated by those skilled in the art that the present invention can also replace the first conductivity type with an N-type and replace the second conductivity type with a p-type to form a semiconductor device. Referring to FIG. 2, the semiconductor device of the present invention includes at least a substrate 2, a gate structure 204, a doped region 206, and a lightly doped region 208. A substrate 200 having a first conductivity type is provided, which may be a p-type slate substrate, a p-type epi-silicon substrate, or an insulating layer overlying a semiconductor-on-insulator (SOI) substrate. . The substrate 200 has, for example, a stepped upper surface 201. The stepped upper surface 201 includes a first surface 201a, a second surface 201b, and a third surface 201c, wherein the third surface 201C connects the first surface 2a and the second surface 201b. The second surface 201b lower than the first surface 20la may be substantially parallel to the first surface 201a. When the first surface 201a and the second surface 201b are substantially flat surfaces, the third surface 2〇lc may be inclined to the first surface 201a. That is, the third surface 201C is a slope between the first surface 2〇1a and the second surface 201b, wherein the upper edge of the slope connects the first surface 201a, and the slope The lower edge connects the second surface 201b. In one embodiment, the height difference between the first surface 2〇1a and the second surface 2〇ib is between 250 and 60 〇A. In the embodiment, the horizontal spacing between the first surface 201a and the second surface 2〇1b is between 250 A and 350 A. In one embodiment, the angle of extension of the first surface 2〇1a with the second surface 201c is between 45. To 60. Ο
之間。 此外，基底中200還配置有具有第一導電型的井區 202，其例如是P型井區(P-well)。在一實施例中，具有第 一導電型(如P型）的局部(1〇calized)袋狀(環狀)植入區或複 合(multiple)袋狀(環狀)植入區更可以配置於井區2〇2中。 局4‘狀(環狀)植入區或複合袋狀(環狀)植入區例如是配 置於閉極結構204的下方，且分別相鄰於各摻雜區2〇6。 井區202例如是只具有極陡崎祕細㈣如印她嗯流， SSR)井。在另一實施例中，輕2〇2也可以是具有極陡崎 退後井與袋狀(環狀)植入區的結合。 閘極結構2〇4酉己置於第一表面上。閘極結構2〇4的長 1例如是對應於第-表面黯的長度。閘極結構2〇4包括 _ 204a與閘介電層鳩，其中閘介電層綱b配置於間 =〇4a與基底200之間。閘極2〇如的長度可小至9〇 他更小的尺寸。閘極204a的材料可以是金屬、換雜 二日日石夕、石夕鍺(sm娜germanium)或是多晶石夕與金屬的組 6。閘介 2帳时效氧化物厚度。他 11 201044579 P970168 30216twf.doc/n ΙνΓ；" ^ 20 Λ ^35 A，204a ”笔層204b的材料可以是氧化 物（mtnded oxide)、氮氧介^匕虱化 (high-K)#,,t ^ 11 ^ ^1 f ^ σ叫、氧化給_,)、氮例如是給㈣、氧化鈦 氧化摩^魏石夕給(腦0N)、氧化祕 某底：〇 if的摻雜區206配置於閘極結構204兩側的 ::。摻雜區206配置於第二表面鳩下。摻： 極/以疋叫錄區’以分卿騎導體元件的源極與汲 雜區2G8配置於閘極結構綱與摻 喊底200中。與摻㈣2❹有__ i心的輕摻雜區208會在閘核社娃 接至對1 n、，構的兩側分別電性連between. In addition, the substrate 200 is also provided with a well region 202 having a first conductivity type, which is, for example, a P-well. In an embodiment, a (1) calized pocket (annular) implanted region or a multiple pocket (annular) implanted region having a first conductivity type (eg, P-type) may be further disposed. The well area is 2〇2. The office 4'-shaped (annular) implanted region or composite bag-like (annular) implanted region is, for example, disposed below the closed-pole structure 204 and adjacent to each of the doped regions 2〇6, respectively. The well area 202 is, for example, a well that has only a very steep and fine (four) such as the Indian River Flow, SSR). In another embodiment, the light 2〇2 may also be a combination of a very steep retreat well and a pocket (annular) implanted region. The gate structure 2〇4酉 has been placed on the first surface. The length 1 of the gate structure 2〇4 is, for example, the length corresponding to the first surface 黯. The gate structure 2〇4 includes a _204a and a gate dielectric layer 鸠, wherein the gate dielectric layer b is disposed between the 〇4a and the substrate 200. The gate 2 can be as small as 9 inches in length and smaller in size. The material of the gate 204a may be metal, mixed with the second day of the day, the smna germanium or the group of polycrystalline stone and metal.闸介 2 accounts for the thickness of the oxide. He 11 201044579 P970168 30216twf.doc/n ΙνΓ;" ^ 20 Λ ^35 A, 204a ” The material of the pen layer 204b can be mtnded oxide, nitroxyl-high (K-high) , t ^ 11 ^ ^1 f ^ σ is called, oxidized to _,), nitrogen is, for example, given (four), oxidized titanium oxide, Wei Shixi (brain 0N), oxidized secret: 掺杂if doped region 206 The doped region 206 is disposed on the two sides of the gate structure 204. The doped region 206 is disposed under the second surface. The doping: the pole/the squeaking zone is disposed in the source and the doping region 2G8 of the branching conductor component. The gate structure and the shattered bottom 200. The lightly doped region 208 with __ i core mixed with (4) 2 会 will be connected to the 1 n, the two sides of the structure
Lit， 因而作為源極汲極延伸陶。各 们μ雜區·包括互相連接的第 Γ表=分鳥配置於第二表面2⑽下=鄰二 20lc。第二部分萬配置於第三表面2(^下。 ^例中’第二部分纖有時還會频地延伸至第— 度會取決^方广區域中。由於各輕摻雜區208的總水平長 小i，= _2()4&的長度’因此當閘極施的長度縮 的再声::雜區观的分布區域可以縮短。以閘極204a 於^^為90 nm為例，各輕摻雜區細的水平分布約介 的导产τ i60()A之間。在—實施例中，第一部分鳥 、1 於50人至150 A之間。在一實施例中，第二 12 201044579 ry/υι〇δ 30216twf.doc/n 部分208b的長度L2介於300 Α至700 Α之間。值得注音 的是’由於第三表面2〇lc為傾斜面’因此各輕摻雜區^ 的傾斜紐控制在45。至6〇。的範_，贿持元件的擊* 特 f生(punch through characteristic)。 ❹ Ο 熟一般而言，橫向電場da—咖她fleld)僅取決於_ 摻雜區208的表面摻雜特性。由於輕摻雜區施具 : 一部分208a與第二部分·b所構成傾斜且彎曲的輪 :部分208a可提供保留的空間給摻雜區2〇6 ‘散。 換二，’在第^面2Glair之小部份_ 2〇8的表面摻雜很淡，因此可以在不降低輕換 2〇8摻雜劑量及不影響輕摻雜區2〇8電阻的情況下、二 效減輕熱載子效應、閘極汲極間 = ，流隊)。詳言之’由於在開; =;ϊ度會顯著地減少’因此熱載子效應'問 =漏電流(GIDL)與閘極没極間的重疊電容也會減少= m雜區208在閑極結構綱τ方的擴散與摻雜區施 的擴放無關，因而摻雜區施的摻雜濃度可以夠重。 對準t ’本發明之半導體元件還可包括間隙壁_、自 ，金屬秒化物層212以及應力層214。間隙壁2 = 辟=結構204的側壁上，且位於輕摻雜區2〇8上。間隙 J例:具有曲的外型’而對應符合閘 隙壁21。可以將閑極結構2。4的側壁與‘： 设现形成有輕掺雜區208的部分基底2〇〇。間隙壁训 13 201044579 P970168 30216twf.doc/n 的材料包括氧化物、氮氧化物(oxynitride)、氮化氧化物 (nitrided oxide)、氮化物或上述材料的組合。在—實施例 中，間隙壁210的厚度210a約介於50 A至2〇〇 A之間。 自對準金屬石夕化物層212配置於閘極結構2〇4上以及 摻雜區206上。自對準金屬矽化物層212的材料例如是矽 化鎳(NiSix)或矽化銘(CoSix)。在一實施例中，還可以在閑 極結構204上與摻雜區206上形成接觸窗（未繪示），由於 配置有自對準金屬矽化物層212,而使得界面上的電阻合 降低。 應力層214'配置於閘極結構204上與基底2〇〇上。應 力層214可以是會提供壓縮應力或拉伸應力至 ^ 化物薄膜。在一實施例中，會在通道區引起拉伸應力的氮 化物薄膜是用於NMOS，而會在通道區引起壓縮應力的氮 化物薄膜是用於PMOS。對90 nm的技術節點而言，應力 層214的厚度例如會落在400人至1000 A的範圍内。一般 而言’間，壁210的厚度21〇a是影響短通道效應的主要^ 鍵之一。藉由使間隙壁210的厚度21〇a變薄至5〇人至2〇〇 A的範圍内，以縮短應力層214與通道區之間的距離，因 而可改善因應力層214所提升之元件效能。 特別說明的是，由於在閘極結構2〇4下方的輕摻雜區 施擴散與摻雜區2G6的擴散無目，因此換雜區2Q6的換 雜濃度會夠重且夠深，而有利於自對準金屬雜物層2Γ2 的形成。此外，因為輕摻雜區208具有第—部分208a而可 使間隙壁210變薄。由於較薄的間隙壁21Q以及具有凹陷 14 30216twf.doc/a 201044579 面的基底200，有助於使應力層2i4能夠更加接近位於閘 極結構204下的通道區，因此可提升載子遷移率並促進元 件效能的改善。 接下來將利用剖面示意圖繼續說明本發明實施例之 半導體元件的製造方法。以下所述之流程僅是為了詳細說 明本發明之方法在形成如圖2所示之半導體元件的製作流 程，以使熟習此項技術者能夠據以實施，但並非甩以限定 本發明之範圍。 〇 圖3A至圖3E是依照本發明之一實施例之一種半導體 元件的製造流程剖面示意圖。 請參照圖3A，提供具有第一導電型的基底3〇〇，其可 以疋P型石夕基底、p型层晶石夕基底或是絕緣層上覆p型半 導體(SOI)基底。第一導電型的井區302形成在基底3〇〇 中，其中井區302例如是p型井區。在一實施例中，井區 302可以是形成極陡峭退後(SSR)井的輪廓。 請參照圖3β ’依序在基底300上形成介電層3〇4、導 〇 體層與圖案化硬罩幕層3〇8。介電層3〇4的材料可以 是氧化物、氮化氧化物(nitrided oxide)、氮氧化物(oxynitride) 或兩介電常數(high-K)材料，其中高介電常數材料例如是 給（Hf)、氧化鈦（Ti〇x)、氧化铪(Hf〇x)、氮氧化矽铪 (HfSiON)、氧化鋁铪(HfAlO)、氧化鋁(ai2〇3)。導體層306 的材料可以是金屬、摻雜多晶矽、矽鍺(silic〇n_germanium) 或是多晶矽與金屬的組合。利用圖案化硬罩幕層3〇8為罩 幕，移除部分介電層304與部分導體層3〇6，以在基底3〇〇 15 201044579 P970168 30216twf.doc/n 上定義出閘極結構310。圖案化的介電層3〇4是作為閘介 電層，而圖案化的導體層306是作為閘極。在一實施例中， 閘極的長度可以是90 nm或是其他更小的尺寸，而閘介電 層的有效氧化物厚度(EOT)可以約介於2〇 A至35 A之 間’以防止漏電流的發生。 之後，移除一部分的基底300，以形成階狀上表面 301。移除部分基底3〇〇的方法例如是以閘極結構3丨〇作為 罩幕而進行傾斜石夕餘刻製程（sl〇ped siHc〇n Process)。在一實施例中，傾斜矽蝕刻製程可以是使用包含 多種酸類的合適配方所進行之濕蝕刻。在另一實施例中， 傾斜矽蝕刻製程也可以是使用包含多種氣體（如CHF3、 邙4、Ar、〇2)的合適組合所進行之電漿蝕刻。所形成之階 狀上表面301包括第一表面3〇la、第二表面3〇lb以及第 —表面301c，其中第三表面3〇lc連接第一表面3〇ia與第 一'表面301b。第一表面301a例如是對應於閘極結構31〇 的位置。低於第一表面301a的第二表面301b實質上可平 行於第一表面301a。當第一表面30 la與第二表面3〇ib實 質上為平坦面時，第三表面3〇lc可傾斜於第—表面3〇ia。 也就是說，第三表面301c是介於第一表面3〇la與第二表 面3〇lb之間的斜面，其中斜面的上緣連接第—表面3〇la， 而斜面的下緣連接第二表面301b。在一實施例中，第一表 面3〇ia與第二表面3〇lb之間的高度差仏介於25〇 a至 60〇A之間。在一實施例中，第一表面301a與第二表面3〇lb 之間的水平間距D2介於250 A至350 A之間。在一實施例 16 201044579 ^ x ^ ivyiwo j〇216twf.doc/n 中，第一表面301a的延伸方向與第三表面301c所形成之 夾角0介於45。至60。之間。 請參照圖3C，移除圖案化硬罩幕層308。接著，於基 底300上形成間隙壁材料層312。間隙壁材料層312例如 疋覆盍閘極結構310、第二表面301b及第三表面3〇lc。在 一實施例中，間隙壁材料層312的厚度約介於5〇人至2〇〇 A之間。間隙壁材料層312的材料包括氧化物、氮氧化物 ◎ (oxymtnde)、氮化氧化物(nitrided oxide)、氮化物或上述材 料的組合。形成間隙壁材料層312的方法可以是利用沈積 製程或快速熱製程(rapid thermal process, RTP)，快速熱製 程例如疋原位蒸汽生成（in-situ steam generation，IS SG)氧 化製程。 隨之，進行植入製程314，以在閘極結構31()兩側的 基底300形成第二導電型(N型）的輕摻雜區316。輕摻雜區 316例如是在基底3〇〇中作為源極汲極延伸(SDE)的接合。 輕摻雜區316可以是利用垂直植入所形成之，或是利用傾 J 斜角植入所形成之，並使用低能量以形成淺的源極汲極延 伸(SDE)接合深度(junction depth)及使用足夠重劑量以降 低片電阻。在一實施例中，當閘極長度約為9〇nm且間隙 壁材料層312的厚度約為100入時，可以使用1〇〜15 KeV 的能量與5e14〜3e15cm-2的劑量來進行植入製程3M，且可 以利用5。〜10。的傾斜角植入掺質。在一實施例中，當元件 尺寸更縮減且間隙壁材料層312的厚度變薄至4〇〜8〇 A 時’植入製程314的能量可減低至2〜7 KeV。 17 201044579 P970168 30216twf.doc/n 值得注意的是’也可以是在形成閘極結構3i〇之後及 形成間隙壁材料層312之前進行植入製程314。以9〇酿 的技術節點為例，可以使用2〜5 KeV的能量* ^的劑量來進行植入製程314，且可以_ q。的傾斜角 垂直植入掺質。當元件尺寸更縮減時，需要較低的能量來 進行植入製程314，可使用約o.iy KeV的能量。 此外，在一實施例中，在形成階狀上表面3〇ι之後或 是在形成輕摻雜區316之後，還可以在井區搬中形成第 ^導電型(如P型）的局部袋狀(環狀)植入區或複合袋狀(環 ί 在另一貫施例中，也可以是在形成間隙壁材料 層312仰之後及形成輕摻雜區316之前，在井區搬中形成 袋狀(壤狀)植人區。也就是說，井區3()2可以是只具有極 陡^退後=SR)井’或是具有極陡，肖退後井與袋狀(環狀)植 Γ局部袋狀(環狀)植入區或複合袋狀(環狀)植入 區例如d別形成於閘極結構31G的下方，且分別鄰接於 之後預域之各雜區。上述錄(環狀)區可關用垂直 植入所^之’或是以7。〜45。的轉肖進行植人所形成之。 3】8㈣極結構训的側壁上形成間隙壁 S〜8覆盒—部分的間隙壁材料層312,以定義 預形成之源極區與没極區。以間隙壁318作為罩幕移 除部分的間隙壁材料層312。剩餘 ™312a，« ，閘極結構3H)的侧壁之間。進行植入製程32()，以在間 隙壁318的外側基底中分別形成第二導電塑的摻雜區 18 o o 201044579 r ^ / υ i 〇〇 30216twf.doc/n 3f。摻雜區322形成於第二表面301b下，且電性連 :參雜區316。摻雜區322例如是N+摻雜區‘ 極區與沒極區。在形成間_318之後，可以使用高乍= 能量以垂直植入的方式進行植入製程320。 冰f的4雜區322可有助於降低片電阻並使後續的金屬 石夕化‘程更容易進行。在—實施射，對9Qnm的技術節 ^占而言’可以使用1G〜2G KeV的能量與lel5〜3el5咖_2的劑 虿來進行植入製程320。 π參肊圖3E，還可以進行回火製程以活化掺質。在 90·的技術節‘點中，回火製程可以是一般的浸入式⑼ 回火製程或是尖峰(spike)回火製程。針對尺寸更小的元 件’退可以使用其他的先進回火技術，如快速伽也)或雷 射(laser)回火製程。 ^之後，移除間隙壁318，並在閘極結構31〇上與摻雜 區322上形成自對準金屬矽化物層324。自對準金屬矽化 物^ 324的材料可以是矽化鎳(NiSix)或矽化鈷(c〇Six)。在 κ施例中，可以在移除間隙壁318之前或之後形成自對 準金屬矽化物層324。接著，在基底300上形成應力層326, 以完成本發明之半導體元件。應力層326可以是會提供壓 縮應力或拉伸應力至通道區的氮化物薄膜。在此實施例 中，應力層326會在NMOS的通道區引起拉伸應力。在另 一實施例中，會在通道區引起壓縮應力的氮化物薄膜可作 為PMOS的應力層。針對9〇 nm的技術節點，應力層326 的厚度例如介於約400人至1〇〇〇 A之間。須注意的是，上 19 201044579 P970168 30216twf.doc/u 述自對準金屬矽化物層324、應力層326等構件的形成方 法及形成順序當為此技術領域的人員所熟知，故於此不贅 述其細節。 請再次參照圖3E’分別配置於閘極結構310與摻雜區 322之間的基底300中的各輕摻雜區316包括相連的第一 部分316a與第二部分316b ’以形成傾斜且彎曲的輪廓。 第一部分316a配置於第二表面3〇lb下，且相鄰於第三表 面301c。第二部分316b配置於第三表面3〇lc下，且第二 部分316b還可以有一小部份的區域延伸至第一表面3〇la 下。當閘極長度約為90 mn時，各輕摻雜區316的水平分 布例如是介於約400 A至600 A之間。在一實施例中，第 一部分316a的長度介於50 A至15〇 A之間。在一實施 例中，弟—部分316b的長度La介於3〇〇 Λ至700 A之間。 值知主思的疋，由於第三表面3〇lc為傾斜面，因此各輕摻 ，區316的傾斜角被控制在45。至6〇。的範圍内，以保持元 f的擊穿特性。傾斜且彎曲的輕摻雜區在表面具有較 二 度，f此可減輕熱载子效應，並在不增加源極 r’Gim、命DE)電阻的情況下減少閘極引發没極漏電流 由料汲極間的重4電容。在回火製程的過程中’ 训在閉極結構曲的輪腐，因此輕換雜區 ^ ^ 322 ^ 屬石夕化製程。而且，ώ辰度可以夠重且夠深以利進行金 ^ ^ 300 刀層326會更罪近通道區，而可有 20 201044579 k y i\j ιυο 30216twf.doc/n 效提升元件效能。 圖4 A至圖4 C是依照本發明之另一實施例之一種半導 體兀件的製造流程剖面示意圖。須注意的是，圖4A至圖 4C所示之製造"IL程是接續圖3B後的步驟。在圖至圖 4C中’和圖3B相同的構件則使用相同的標號並省略其說 明。Lit, thus extending the pottery as a source bungee. Each of the miscellaneous regions includes an interconnected enthalpy table = the split bird is disposed under the second surface 2 (10) = the adjacent two 20lc. The second part is arranged on the third surface 2 (^. ^In the example, the second part of the fiber sometimes extends to the first degree in the square area. Because of the total of the lightly doped areas 208 The length of the horizontal length i, = _2 () 4 & the length ' Therefore, when the length of the gate is reduced, the reverberation: the distribution area of the miscellaneous area can be shortened. Taking the gate 204a as 90 nm as an example, each The fine horizontal distribution of the lightly doped regions is between the mediators τ i60() A. In the embodiment, the first portion of the bird, 1 is between 50 and 150 A. In an embodiment, the second 12 201044579 ry/υι〇δ 30216twf.doc/n The length L2 of part 208b is between 300 Α and 700 。. It is worth noting that 'because the third surface 2 〇lc is an inclined surface', therefore each lightly doped area ^ The tilting button is controlled at 45. to 6〇. The _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The surface doping characteristics of region 208. Due to the lightly doped zone application: a portion 208a and a second portion b form an inclined and curved wheel: the portion 208a can provide a reserved space for the doped region 2〇6. In the second, 'the surface of the 2Glair of the second surface _ 2〇8 is very lightly doped, so it can be used without reducing the dose of the 2〇8 doping and not affecting the resistance of the lightly doped region 2〇8. The lower and second effects reduce the hot carrier effect, the gate bungee =, the flow team). In detail, 'because of the opening; =; the temperature will be significantly reduced 'so the hot carrier effect' asks = the leakage capacitance (GIDL) and the overlap capacitance between the gate poles will also decrease = m miscellaneous zone 208 in the idle pole The diffusion of the structure τ side is independent of the diffusion of the doped region, and thus the doping concentration of the doping region can be sufficiently heavy. Aligning t' The semiconductor component of the present invention may further include a spacer, a self, a metal clad layer 212, and a stress layer 214. The spacer 2 is on the sidewall of the structure 204 and is located on the lightly doped region 2〇8. The gap J case has a curved outer shape and corresponds to the gate wall 21. The sidewalls of the dummy pad structure 2.4 may be formed with a portion of the substrate 2 having the lightly doped region 208. Gap wall training 13 201044579 P970168 30216twf.doc/n materials include oxides, oxynitrides, nitrided oxides, nitrides or combinations of the above. In an embodiment, the thickness 210a of the spacer 210 is between about 50 A and 2 A. The self-aligned metallization layer 212 is disposed on the gate structure 2〇4 and on the doped region 206. The material of the self-aligned metal telluride layer 212 is, for example, nickel hydride (NiSix) or bismuth (CoSix). In an embodiment, a contact window (not shown) may be formed on the dummy structure 204 and the doped region 206. The self-aligned metal telluride layer 212 is disposed to reduce the electrical resistance at the interface. The stress layer 214' is disposed on the gate structure 204 and on the substrate 2. The stressor layer 214 can be a compressive stress or a tensile stress to the film. In one embodiment, a nitride film that causes tensile stress in the channel region is used for the NMOS, and a nitride film that causes compressive stress in the channel region is used for the PMOS. For a 90 nm technology node, the thickness of the stressor layer 214 may fall, for example, in the range of 400 to 1000 Å. In general, the thickness 21 〇a of the wall 210 is one of the main bonds affecting the short channel effect. By thinning the thickness 21 〇a of the spacer 210 to a range of 5 〇 to 2 〇〇 A, the distance between the stress layer 214 and the channel region is shortened, so that the component lifted by the stress layer 214 can be improved. efficacy. In particular, since the diffusion in the lightly doped region under the gate structure 2〇4 and the diffusion of the doped region 2G6 are not visible, the replacement concentration of the replacement region 2Q6 may be heavy enough and deep enough to facilitate Self-aligned metal impurity layer 2Γ2 is formed. Further, since the lightly doped region 208 has the first portion 208a, the spacer 210 can be thinned. Due to the thinner spacer 21Q and the substrate 200 having the recess 14 30216twf.doc/a 201044579, it helps to bring the stress layer 2i4 closer to the channel region under the gate structure 204, thereby improving carrier mobility and Promote the improvement of component performance. Next, a method of manufacturing a semiconductor device of an embodiment of the present invention will be described using a cross-sectional schematic view. The processes described below are merely illustrative of the process of the present invention in forming the fabrication of the semiconductor device as shown in Figure 2, so that those skilled in the art can implement it, but are not intended to limit the scope of the invention. 3A to 3E are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention. Referring to FIG. 3A, a substrate 3A having a first conductivity type is provided, which may be a P-type slate substrate, a p-type smectite substrate, or an insulating layer overlying a p-type semiconductor (SOI) substrate. The first conductivity type well region 302 is formed in the substrate 3, wherein the well region 302 is, for example, a p-type well region. In an embodiment, well zone 302 may be a profile that forms a very steep back-off (SSR) well. Referring to FIG. 3β', a dielectric layer 3〇4, a conductor layer and a patterned hard mask layer 3〇8 are sequentially formed on the substrate 300. The material of the dielectric layer 3〇4 may be an oxide, a nitrided oxide, an oxynitride or a high-k material, wherein the high dielectric constant material is, for example, Hf), titanium oxide (Ti〇x), cerium oxide (Hf〇x), cerium oxynitride (HfSiON), aluminum oxide lanthanum (HfAlO), aluminum oxide (ai2〇3). The material of the conductor layer 306 may be metal, doped polysilicon, silic〇n_germanium or a combination of polysilicon and metal. A portion of the dielectric layer 304 and a portion of the conductor layer 3〇6 are removed by using the patterned hard mask layer 3〇8 as a mask to define the gate structure 310 on the substrate 3〇〇15 201044579 P970168 30216twf.doc/n. . The patterned dielectric layer 3〇4 acts as a gate dielectric layer and the patterned conductor layer 306 acts as a gate. In one embodiment, the gate length may be 90 nm or other smaller dimensions, and the effective dielectric thickness (EOT) of the gate dielectric layer may be between about 2 A and 35 A to prevent The occurrence of leakage current. Thereafter, a portion of the substrate 300 is removed to form a stepped upper surface 301. The method of removing a portion of the substrate 3 is performed, for example, by using a gate structure 3 丨〇 as a mask to perform a sloped siHc〇n process. In one embodiment, the tilt etch process can be wet etch using a suitable formulation comprising a plurality of acids. In another embodiment, the tilt etch process can also be plasma etch using a suitable combination of gases including CHF3, 邙4, Ar, 〇2. The stepped upper surface 301 is formed to include a first surface 〇1a, a second surface 〇1b, and a first surface 301c, wherein the third surface 〇lc is coupled to the first surface 3〇ia and the first 'surface 301b. The first surface 301a is, for example, a position corresponding to the gate structure 31A. The second surface 301b lower than the first surface 301a is substantially parallel to the first surface 301a. When the first surface 30 la and the second surface 3 〇 ib are substantially flat surfaces, the third surface 3 〇 lc may be inclined to the first surface 3 〇 ia. That is, the third surface 301c is a slope between the first surface 3〇1a and the second surface 3〇1b, wherein the upper edge of the slope connects the first surface 3〇1a, and the lower edge of the slope connects the second surface Surface 301b. In one embodiment, the height difference 第一 between the first surface 3〇ia and the second surface 3〇1b is between 25〇 a and 60〇A. In an embodiment, the horizontal spacing D2 between the first surface 301a and the second surface 3〇 lb is between 250 A and 350 A. In an embodiment 16 201044579 ^ x ^ ivyiwo j〇216twf.doc/n, the extending direction of the first surface 301a and the third surface 301c form an angle of 0 between 45. To 60. between. Referring to FIG. 3C, the patterned hard mask layer 308 is removed. Next, a spacer material layer 312 is formed on the substrate 300. The spacer material layer 312 covers, for example, the gate structure 310, the second surface 301b, and the third surface 3?lc. In one embodiment, the thickness of the spacer material layer 312 is between about 5 Å and 2 Å. The material of the spacer material layer 312 includes an oxide, an oxymoxide, a nitrided oxide, a nitride, or a combination thereof. The method of forming the spacer material layer 312 may be by a deposition process or a rapid thermal process (RTP), a rapid thermal process such as an in-situ steam generation (IS SG) oxidation process. Accordingly, an implant process 314 is performed to form a second conductivity type (N-type) lightly doped region 316 on the substrate 300 on either side of the gate structure 31 (). The lightly doped region 316 is, for example, a junction as a source drain extension (SDE) in the substrate 3A. The lightly doped region 316 may be formed using vertical implantation, or formed using a tilted J angle implant, and using low energy to form a shallow source drain extension (SDE) junction depth. And use a sufficient weight to reduce the sheet resistance. In one embodiment, when the gate length is about 9 〇 nm and the thickness of the spacer material layer 312 is about 100, the energy of 1 〇 15 15 VV and the dose of 5e 14 〜 3e 15 cm -2 can be used for implantation. The process is 3M, and 5 can be utilized. ~10. The tilt angle is implanted into the dopant. In one embodiment, the energy of the implant process 314 can be reduced to 2 to 7 KeV as the component size is further reduced and the thickness of the spacer material layer 312 is reduced to 4 Å to 8 Å. 17 201044579 P970168 30216twf.doc/n It is noted that the implantation process 314 may be performed after the formation of the gate structure 3i and before the formation of the spacer material layer 312. Taking the 9-breasted technology node as an example, the implantation process 314 can be performed using a dose of energy of 2 to 5 KeV*^, and can be _q. The tilt angle is implanted vertically. When the component size is further reduced, less energy is required to perform the implant process 314, and an energy of about o.iy KeV can be used. In addition, in an embodiment, after forming the stepped upper surface 3〇 or after forming the lightly doped region 316, a partial pouch of the first conductivity type (such as P type) may be formed in the well region. (annular) implantation region or composite bag shape (in another embodiment, it is also possible to form a pocket shape in the well region after the formation of the spacer material layer 312 and before forming the lightly doped region 316 (Land-shaped) implanted area. That is to say, well area 3 () 2 can only have extremely steep ^ back = SR) well or has extremely steep, Xiaoui back well and bag-shaped (annular) plant A partial pocket (annular) implanted region or a composite pocket (annular) implanted region, for example, is formed below the gate structure 31G and adjacent to each of the subsequent regions. The above-mentioned recorded (annular) region can be closed with a vertical implant or a 7. ~45. The turn of the Xiao is formed by the implant. 3] The wall of the 8 (4) pole structure is formed with spacers S to 8 to cover a portion of the spacer material layer 312 to define a pre-formed source region and a non-polar region. A portion of the spacer material layer 312 is removed with the spacers 318 as a mask. Remaining TM312a, «, gate structure 3H) between the sidewalls. An implantation process 32() is performed to form a second conductive plastic doped region 18 o o 201044579 r ^ / υ i 〇〇 30216twf.doc/n 3f, respectively, in the outer substrate of the spacer 318. The doped region 322 is formed under the second surface 301b and electrically connected to the doping region 316. The doped region 322 is, for example, an N+ doped region 'polar region and a non-polar region. After forming the inter- 318, the implant process 320 can be performed in a vertically implanted manner using sorghum = energy. The 4 miscellaneous region 322 of ice f can help to reduce sheet resistance and make subsequent metallization easier. In the implementation of the shot, for the 9Qnm technical section, the implantation process 320 can be performed using the energy of 1G to 2G KeV and the agent of the ll5 to 3el5 coffee. As shown in Fig. 3E, a tempering process can also be performed to activate the dopant. In the 90's technical section, the tempering process can be a general immersion (9) tempering process or a spike tempering process. For smaller components, you can use other advanced tempering techniques, such as fast gamma or laser tempering. After that, the spacers 318 are removed and a self-aligned metal halide layer 324 is formed over the gate structures 31 and the doped regions 322. The material of the self-aligned metal telluride ^ 324 may be nickel niobide (NiSix) or cobalt antimonide (c〇Six). In the κ embodiment, the self-aligned metal telluride layer 324 may be formed before or after the spacers 318 are removed. Next, a stress layer 326 is formed on the substrate 300 to complete the semiconductor element of the present invention. Stress layer 326 can be a nitride film that provides compressive or tensile stress to the channel region. In this embodiment, the stressor layer 326 induces tensile stress in the channel region of the NMOS. In another embodiment, a nitride film that causes compressive stress in the channel region can act as a stress layer for the PMOS. For a 9 〇 nm technology node, the thickness of the stressor layer 326 is, for example, between about 400 and 1 〇〇〇A. It should be noted that the forming method and the forming sequence of the self-aligned metal telluride layer 324, the stress layer 326 and the like are well known to those skilled in the art, and therefore will not be described herein. Its details. Referring again to FIG. 3E', each lightly doped region 316 disposed in the substrate 300 between the gate structure 310 and the doped region 322 includes an associated first portion 316a and second portion 316b' to form a sloped and curved profile. . The first portion 316a is disposed under the second surface 3〇1b and adjacent to the third surface 301c. The second portion 316b is disposed under the third surface 3〇lc, and the second portion 316b may have a small portion extending to the first surface 3〇1a. When the gate length is about 90 mn, the horizontal distribution of each lightly doped region 316 is, for example, between about 400 A and 600 Å. In one embodiment, the first portion 316a has a length between 50 A and 15 A. In one embodiment, the length La of the portion 316b is between 3 〇〇 and 700 Å. As the value is known, since the third surface 3 lc is an inclined surface, the inclination angle of each lightly doped region 316 is controlled at 45. To 6 〇. Within the range to maintain the breakdown characteristics of the element f. The tilted and curved lightly doped region has a second degree on the surface, which can reduce the hot carrier effect and reduce the gate induced immersed leakage current without increasing the source r'Gim, life DE) resistance. The weight of the material is 4 capacitors. In the process of tempering process, the rotation of the closed-circuit structure is rotted, so the light-changing area ^ ^ 322 ^ belongs to the Shi Xihua process. Moreover, the ώ 度 degree can be heavy enough and deep enough for the gold ^ ^ 300 knives 326 will be more sinful near the channel area, but there are 20 201044579 k y i\j ιυο 30216twf.doc / n effect to improve component performance. 4A to 4C are schematic cross-sectional views showing a manufacturing process of a semiconductor element in accordance with another embodiment of the present invention. It should be noted that the manufacturing "IL process shown in Figs. 4A to 4C is the step subsequent to Fig. 3B. The same components as those in Fig. 3B are denoted by the same reference numerals and their description will be omitted.
GG
請參照圖4A，移除圖案化硬罩幕層3〇8。接著，於閘 極結構mo的側壁與部分基底上形成間隙壁4〇2 隙壁404。彎曲的間隙壁搬可以利用可棄式(disp〇sabie) 間隙壁4〇4來形成之。間隙壁4〇2分別配置在間隙壁侧 ，閘極結構310的側壁之間。間隙壁4〇2與間隙壁4〇4覆 蓋第三表面301c且覆蓋部分第二表面3〇lb，因此可利用 間隙壁術與間隙壁抱來定義後續預形成之源極區與汲 接著，進行植入製程406，以在間隙壁4〇4的外側基 & 300中分別形成第二導電型的摻雜區·。形成在第二 J=01b下的摻雜區408例如是讲摻雜區，以分別作為 極區。可以使用高於形成源極汲極延伸(sde) 垂直植入的方式進行植入製程鄕。在—實施例 旦盥15二的技2術節點而言’可以使用10〜紙…的能 里與le〜3e cm-2的劑量來進行植入製程仞“ 請參照圖4B，移除間隙壁撕。進行植入製程41〇， 極結構310兩側的基底·切成第二導電师型） 的輕摻雜區412。輕摻雜區412可以是利用垂直植入所形 21 201044579 P970168 30216twf.doc/n 成之’或是使用低能量並利用傾斜角植入所形成之。在一 實施例中，當閘極長度約為90nm且間隙壁402的厚度約 為100Λ時，可以使用1〇〜i5KeV的能量與5e14〜3e15cm-2 的劑量來進行植入製程410，且可以利用5。〜10。的傾斜角 植入捧質。在一實施例中，當元件尺寸更縮減且間隙壁4〇2 的厚度變薄至40〜80人時’植入製程410的能量可減低至 2〜7 KeV。 請參照圖4C，還可以進行回火製程以活化掺質。之 後，在閘極結構310上與摻雜區408上形成自對準金屬矽 化物層416。接著，在基底300上形成應力層418，以完成 本發明之半導體元件。如圖4C所示，分別配置於閘極結 構310與摻雜區408之間的基底3〇〇中的各輕摻雜區412 包括=一部分412a與第二部分412b，其中第一部分412a 連接第二部分412b。第一部分412a配置於第二表面301b 下，且相鄰於第三表面301c。第二部分412b配置於第三 ^面3〇^lc下，且第二部分412b還可以有一小部份的區域 =伸至第-表面鳥下。當閘極的長度約為肩_時，各 二杉雜區412的水平分布可以介於約4〇〇 a至6〇〇人之 實施财，第—部分412a的長度Μ介於％人至 之間。在一實施例中，第二部分412b的長度1^2介 急至7〇0 A之間。特別說明的是，由於第三表面301c 面，目此各輕摻雜區412的傾斜角可被控制在45。 的範圍内，以保持元件的擊穿特性。 圖5A至圖5C是依照本發明之又一實施例之一種半導 22 201044579 ry/υι〇δ 30216twf.d〇c/n 體元件的製造流程到面示意圖。須注意的是，圖5Α至圖 5C所示之製造流程是接續圖3Β後的步驟。在圖5Α至圖 5C中，和圖3Β相同的構件則使用相同的標號並省略其說 明。 ’、 Ο ❹ 請參照圖5Α，移除圖案化硬罩幕層3〇8。接著，於閘 極結構310的侧壁與部分基底3〇〇上形成間隙壁5〇2以及 間隙壁504。具有f曲外型的間隙壁5〇2例如是藉由可棄 式(disposable)間隙壁504來形成之。間隙壁5〇2分別配置 於間隙壁504與閘極結構31〇的側壁之間。間隙壁5〇2與 間隙壁504覆蓋第三表面她且覆蓋部分的第二表面 301b，而可用於定義後續預形成之源極汲極延伸(sde)、 源極區與没極區。 請參照圖5B_1，移除間隙壁5〇4。進行植入製程5〇6， 以於閘極結構310兩側的基底中形成第二導電型 的輕摻雜區508與摻雜區谢a。輕摻雜區遞例如是形成 於間隙壁502的下方’而摻雜區職例如是形成於間隙壁 502的外側。 請參照圖5B-2,在另—實施例中，更可 =性地進行植入製程507，以在閘極結構則的兩: 底300甲形成第二導電型(N型）的摻雜區鳩，而使源極 散^深。接雜區篇例如是形成在摻雜區 a的:圍。在此况明的是，本發明對進行植入製程鄕 與植入衣程507的先制序財作任何_，亦即上述進 订植入製程與植人製程5G7 _序可以對調。 23 201044579 P970168 30216twf.d〇c/n 承上述，淺的源極汲極延伸（SDE)區以及源極汲極(SD) 擴散區可以是使㈣當能量進行單—植人製㈣同時形 成，或是進行雙次植入製程以將掺質植入基底獨兩次。 在一貝把例中’如圖5B-1所示，在單一植入製程以同時形 成，摻雜區508與摻雜區顺的過程中，由於間隙壁5〇2 覆蓋在基底3〇〇上，輕摻雜區5〇8會形成淺接合(shaii〇w Jimchon);由於沒有間隙壁5〇2的遮蔽，摻雜區遍會形 成較深的接合。以90 nm的技術節點且間隙壁5〇2的厚度 約，1。。A為例，可以使用約15 KeV的能量與iel5〜3el5 :的劑里來進行單—植入製程，並使用5。〜1〇。的傾斜角 來植入掺質’如此—來就可關時形成所需的接合輪廊。 谓實施例中’在兩步驟植入製程以形成輕摻雜區 :士與摻雜區5〇9a、5〇%的過程中，藉由植入製程5〇6可 ^形成轉雜區508與摻雜區施(如圖5B]所示）；而 =隙壁502的遮蔽效果’另外使用較低的能量進行植 私507只會增加摻雜區5〇%的摻雜濃度(如圖你2所 以90 nm的技術喊點且間隙壁5〇2的厚度約為刚a 以Γ約15KeV的能量與1e15〜3elw的劑量 n Μ時形雜_區508與推雜區 、fM其中。〜1G。的傾斜絲植人㈣。袖同於上 件下:可以使用約5〜10 KeV的能量與iel5〜3ei w 度=里來進订植人製程5()7，以增加摻雜區遍的換雜濃 晴蒼照圖5c ’在進行植入製程5〇6之後或在進行植 24 201044579 ry/υι〇ώ 30216twf.doc/n 入製程5〇7之後，還可以進行回火製程以活化掺質，因而 形成摻雜區509。之後，在閘極結構31〇上與摻雜區5〇9 上开>成自對準金屬石夕化物層510。接著，在基底3〇〇上形 成應力層512，以完成本發明之半導體元件。如圖5(：所 示’为別配置於閘極結構310與摻雜區之間的基底 中的各輕摻雜區508包括第一部分5〇8a與第二部分 508b，其中第一部分508a連接第二部分5〇肋。第一部分 〇 508a配置於第二表面301b下，且才目鄰於第三表面 301c。 第一部为508b配置於第三表面3〇lc下，並選擇性地包括 -小部份的區域延伸i第—表面㈣下。當閑極的長度約 為90mn時，各輕摻雜區508的水平分布例如是介於約4〇〇 Λ至600 A之間。在一實施例中，第一部分5〇8a的長度 L ”於15GA之間。在—實施例中，第二部分5〇8b j長度L2介於300人至· A之間。特別說明的是，由於 第二表面3〇lc為傾斜面’因此各輕摻雜區爾的傾斜角可 被控制在45。至6〇。的範圍内，以保持元件的擊穿特性。 為證5本發明之半導體元件可有效改善元件效能，接 :來將以錄例朗其躲。以下實驗狀綱僅是用來 -兄明本發明之半導體元件崎構配置躲橫向電場㈣w eleCtriCfldd)的影響，但並非用以限定本發明之範圍。 實驗例 k NMQS及本發贿驗例之 、’仃於第-表面的通道區中不同位置所對應的橫 25 201044579 P970 ί 68 30216twf.doc/n 向電場分布曲線圖。 如圖6所示，分別模擬習知之NM〇s及本發明所提出 之NMOS在接近閘極結構與石夕基底之間界面的通道區的 橫向電場分布。習知之NM〇S與本㈣#驗例之觀〇8 的閘極長度約為9G nm。在分別提供_偏壓至兩個元件 的情況下，習知之ΝΜ Ο S的橫向電場分布遠高於本發明實 驗例之NMGS職向電場分布。由於橫的場顯著影絲 載子效應’因此具有較高橫向電場的習知NM〇s會遭遇嚴 重的熱載子效應’而導致元件效崎低。由此可知，本發 明所提出之NMOS結構具有更低的橫向電場值，因而能^ 達到提升元件效能的功效。 …综上所述’本發明之半導體元件包括具有第一部分斑 部分的輕摻顏，而傾斜且彎曲的輕摻騎可以在不 減她摻雜轉度的情況下降低熱載子效應。而且， 輕摻雜區具有傾斜且f曲的輪#，還可以減輕如問 電流(GIDL)等漏電流及閘贿極間的重桑 此$卜，树明之半導體元件的製造枝湘可棄成 易隙壁來形成傾斜且f曲_摻雜區，而可輕 成太=現有製程中。因此，製程簡單而不會增加製造 =導;具有更佳效能。心 用。 干尺孩細至90 _以下的MOS元件也適 雖然本發明已以實施例揭露如上，然其並非用以限定 26 201044579 l^y/Ul(>is 30216twf.doc/n 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤倚，故本 發明之保護範®當視後附之巾請專職_界定者為準。 【圖式簡單說明】 圖1是習知之一種金氧半導體電晶體的剖面示意圖。 圖2疋依知本發明之一實施例之一種半導體元件的剖 ❹ 面示意圖。 圖3A至圖3E是依照本發明之一實施例之一種丰導許 元件的製造流程剖面示意圖。 圖4A至圖4C是依照本發明之另一實施例之一種半導 體元件的製造流程剖面示意圖。 圖5A至圖5C是依照本發明之又一實施例之一種半導 體元件的製造流程剖面示意圖。 圖6所繪示是根據習知之NMOS及本發明實驗例之 NMOS在平行於第一表面的通道區中不同位置所對應的橫 q 向電場分布曲線圖。 【主要元件符號說明】 100、200、300 :基底 102、204、310 :閘極結構 104、210、312a、318、402、404、502、504 :間隙 壁 106 :偏移間隙壁 10 8 a ·源極區 108b :汲極區 27 201044579 P970168 30216twf.doc/n 110a :源極延伸區 110b :汲極延伸區 112 :自對準金屬矽化物 201、 301 :階狀上表面 201a、301a :第一表面 201b、301b :第二表面 201c、301c :第三表面 202、 302 :井區 204a :閘極 204b :閘介電層 206、322、408、509、509a、509b :摻雜區 208、316、412、508 :輕摻雜區 208a、316a、412a、508a :第一部分 208b、316b、412b、508b :第二部分 210a :厚度 212、324、416、510 :自對準金屬矽化物層 214、326、418、512 :應力層 304 :介電層 306 :導體層 308 :圖案化硬罩幕層 312 :間隙壁材料層 314、320、406、410、506、507 :植入製程 :高度差 D2 :水平間距 Li、L2 :長度 0 :夾角 28Referring to FIG. 4A, the patterned hard mask layer 3〇8 is removed. Next, a spacer 4 〇 2 gap 404 is formed on the sidewall of the gate structure mo and a portion of the substrate. The curved spacer can be formed by using a disp〇sabie spacer 4〇4. The spacers 4〇2 are disposed on the gap side and between the side walls of the gate structure 310, respectively. The spacer 4〇2 and the spacer 4〇4 cover the third surface 301c and cover a portion of the second surface 3〇1b, so that the gap pre-formed source region and the spacer can be defined by the spacer and the spacer. The implantation process 406 is performed to form doped regions of the second conductivity type in the outer bases & 300 of the spacers 4〇4, respectively. The doped region 408 formed at the second J = 01b is, for example, a doped region to serve as a polar region, respectively. The implant process can be performed using a higher vertical implant than the source drain sde. In the embodiment of the technique, the technique can be performed using a dose of 10 to 30 lbs and a dose of le 〜3e cm-2 for the implantation process 仞 "Please refer to FIG. 4B to remove the spacers. The light-doped region 412 is implanted in the implantation process 41〇, the substrate on both sides of the pole structure 310 is cut into a second conductive type. The lightly doped region 412 may be formed by vertical implantation 21 201044579 P970168 30216twf. The doc/n is formed either by using low energy and implanting with a tilt angle. In one embodiment, when the gate length is about 90 nm and the thickness of the spacer 402 is about 100 ,, 1 〇 can be used. The energy of i5KeV and the dose of 5e14~3e15cm-2 are used for the implantation process 410, and the implant can be implanted with a tilt angle of 5.10. In one embodiment, when the component size is further reduced and the spacer 4〇 When the thickness of 2 is thinned to 40 to 80 people, the energy of the implantation process 410 can be reduced to 2 to 7 KeV. Referring to Fig. 4C, a tempering process can also be performed to activate the dopant. Thereafter, on the gate structure 310. A self-aligned metal telluride layer 416 is formed on the doped region 408. Next, stress is formed on the substrate 300. Layer 418 to complete the semiconductor device of the present invention. As shown in FIG. 4C, each lightly doped region 412 disposed in the substrate 3〇〇 between the gate structure 310 and the doped region 408 includes a portion 412a and a portion a second portion 412b, wherein the first portion 412a is connected to the second portion 412b. The first portion 412a is disposed under the second surface 301b and adjacent to the third surface 301c. The second portion 412b is disposed under the third surface And the second portion 412b can also have a small portion of the area = extending to the surface of the first surface. When the length of the gate is about the shoulder _, the horizontal distribution of each of the cedar 412 can be about 4 〇〇a. The length of the first portion 412a is between % and 10,000. In one embodiment, the length of the second portion 412b is between 1 and 2 A. It is noted that, due to the surface of the third surface 301c, the inclination angle of each lightly doped region 412 can be controlled within a range of 45 to maintain the breakdown characteristics of the element. Figures 5A to 5C are in accordance with the present invention. A semi-conductor 22 of another embodiment 201044579 ry/υι〇δ 30216twf.d〇c/n body component manufacturing process to the surface It is to be noted that the manufacturing flow shown in Fig. 5A to Fig. 5C is the step subsequent to Fig. 3. In Figs. 5A to 5C, the same members as those in Fig. 3A are denoted by the same reference numerals and the description thereof will be omitted. Referring to FIG. 5A, the patterned hard mask layer 3〇8 is removed. Then, a spacer 5〇2 and a spacer 504 are formed on the sidewall of the gate structure 310 and the partial substrate 3〇〇. The curved outer spacer 5〇2 is formed, for example, by a disposable spacer 504. The spacers 5〇2 are disposed between the spacers 504 and the sidewalls of the gate structures 31A, respectively. The spacers 5 and 2 and the spacers 504 cover the third surface and cover the second surface 301b of the portion, and can be used to define subsequent pre-formed source drain sde, source and gate regions. Referring to FIG. 5B_1, the spacer 5〇4 is removed. The implant process 5〇6 is performed to form a light-doped region 508 of the second conductivity type and a doped region in the substrate on both sides of the gate structure 310. The lightly doped region is formed, for example, under the spacer 502, and the doped region is formed, for example, on the outside of the spacer 502. Referring to FIG. 5B-2, in another embodiment, the implant process 507 is performed more selectively to form a second conductivity type (N type) doped region in the gate structure: Oh, and the source is deep and deep. The junction region is formed, for example, in the doping region a: In this case, the present invention can perform any of the prior art processes for the implantation process and the implant process 507, that is, the above-mentioned implant process and the implant process 5G7 can be reversed. 23 201044579 P970168 30216twf.d〇c/n In view of the above, the shallow source-drain extension (SDE) region and the source-drain (SD) diffusion region may be such that (iv) the energy is single-implanted (four) simultaneously. Or a double implant process to implant the dopant into the substrate twice. In a case of a case, as shown in FIG. 5B-1, in a single implantation process to be simultaneously formed, in the process of doping the region 508 and the doped region, the spacer 5 〇 2 covers the substrate 3 The lightly doped region 5〇8 will form a shallow joint (shaii〇w Jimchon); since there is no shielding of the gap wall 5〇2, the doped region will form a deeper joint. At a 90 nm technology node and the thickness of the spacer 5 〇 2 is about 1, . For example, A can be used for a single-implantation process using an energy of about 15 KeV and an iel5~3el5: and use 5. ~1〇. The angle of inclination to implant the dopant 'as such" can form the desired jointed gallery when closed. In the embodiment, in the process of implanting the process in two steps to form the lightly doped region: the germanium and the doped region 5〇9a, 5〇%, the implant region 508 can be formed by the implantation process 5〇6 Doping zone application (as shown in Figure 5B); and = shielding effect of the gap wall 502 'In addition to using lower energy for planting 507 will only increase the doping concentration of the doping region 5〇% (as shown in Figure 2 Therefore, the 90 nm technique is called and the thickness of the spacer 5 〇 2 is about a Γ 15 K K K 15 15 15 15 15 15 15 15 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 The slanting silk implants (4). The sleeves are the same as the upper ones: you can use about 5~10 KeV energy and iel5~3ei w degrees=into the implanting process 5()7 to increase the doping area After the implantation process 5〇6 or after the implant 24 201044579 ry/υι〇ώ 30216twf.doc/n into the process 5〇7, the tempering process can also be performed to activate the dopant. Thus, a doped region 509 is formed. Thereafter, a self-aligned metallization layer 510 is formed on the gate structure 31 and the doped region 5〇9. Next, a stress layer is formed on the substrate 3〇〇. 512, Completing the semiconductor device of the present invention. As shown in FIG. 5 (each of the lightly doped regions 508 disposed in the substrate between the gate structure 310 and the doped region, the first portion 5a 8a and the second portion 508b are included The first portion 508a is connected to the second portion 5 rib. The first portion 〇 508a is disposed under the second surface 301b and is adjacent to the third surface 301c. The first portion 508b is disposed under the third surface 3〇lc. And optionally comprising - a small portion of the region extending i - surface (d). When the length of the idler is about 90 mn, the horizontal distribution of each lightly doped region 508 is, for example, between about 4 〇〇Λ and 600 Å. In an embodiment, the length L" of the first portion 5"8a is between 15GA. In the embodiment, the length L2 of the second portion 5〇8b j is between 300 and A. Since the second surface 3 〇 lc is an inclined surface ′, the inclination angle of each lightly doped region can be controlled within a range of 45 to 6 〇 to maintain the breakdown characteristics of the element. The semiconductor component of the invention can effectively improve the performance of the component, and then it will be hidden by recording. The following experimental form only The effect of the semiconductor component of the present invention is to hide the lateral electric field (four) w eleCtriCfldd), but is not intended to limit the scope of the invention. Experimental Example k NMQS and the present bribery test case, '仃 on the surface- In the channel area corresponding to the horizontal 25 201044579 P970 ί 68 30216twf.doc / n electric field distribution curve. As shown in Figure 6, respectively, the simulation of the conventional NM 〇 s and the proposed NMOS in the proximity of the gate The transverse electric field distribution of the channel region of the interface between the structure and the base of the stone. The gate length of the conventional NM〇S and the (4)# example of Guanlan 8 is about 9G nm. In the case where the _ bias is supplied to the two elements, respectively, the transverse electric field distribution of the conventional Ο Ο S is much higher than the NMGS duty electric field distribution of the experimental example of the present invention. Since the transverse field significantly exhibits the effect of the carrier, so the conventional NM〇s with a higher transverse electric field will encounter a severe hot carrier effect, resulting in a low component efficiency. It can be seen that the NMOS structure proposed by the present invention has a lower lateral electric field value, thereby achieving the effect of improving the performance of the component. In summary, the semiconductor component of the present invention includes a lightly doped face having a first partial spot portion, and the oblique and curved light doping can reduce the hot carrier effect without reducing the doping degree of the doping. Moreover, the lightly doped region has a tilted and f-curved wheel #, and can also reduce the leakage current such as the current (GIDL) and the heavy sorrow between the gate and the brigade. The manufacture of the semiconductor component of Shuming can be abandoned. The gaps are formed to form a sloped and f-doped region, which can be lightly too = in the existing process. Therefore, the process is simple without increasing manufacturing = conductivity; with better performance. Use. The present invention has been disclosed in the above embodiments, but it is not intended to limit 26 201044579 l^y/Ul (>is 30216twf.doc/n, the present invention, any Those skilled in the art will be able to make some changes and reliances without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention is subject to the full-time definition. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional MOS transistor. Fig. 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. Fig. 3A to Fig. 3E are in accordance with the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4A to FIG. 4C are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with another embodiment of the present invention. FIGS. 5A to 5C are diagrams according to the present invention. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to another embodiment. FIG. 6 is a view showing that the NMOS according to the conventional NMOS and the experimental example of the present invention are in different positions in the channel region parallel to the first surface. The transverse q-direction electric field distribution curve. [Main component symbol description] 100, 200, 300: substrate 102, 204, 310: gate structure 104, 210, 312a, 318, 402, 404, 502, 504: spacer 106 : offset spacer 10 8 a · source region 108b: drain region 27 201044579 P970168 30216twf.doc/n 110a: source extension region 110b: drain extension region 112: self-aligned metal germanide 201, 301: order Upper surface 201a, 301a: first surface 201b, 301b: second surface 201c, 301c: third surface 202, 302: well 204a: gate 204b: gate dielectric layer 206, 322, 408, 509, 509a, 509b: doped regions 208, 316, 412, 508: lightly doped regions 208a, 316a, 412a, 508a: first portions 208b, 316b, 412b, 508b: second portions 210a: thicknesses 212, 324, 416, 510: from Aligning metal halide layers 214, 326, 418, 512: stress layer 304: dielectric layer 306: conductor layer 308: patterned hard mask layer 312: spacer material layer 314, 320, 406, 410, 506, 507 : Implantation process: height difference D2: horizontal spacing Li, L2: length 0: angle 28