TW201044541A - Transient voltage suppressor having symmetrical breakdown voltages - Google Patents

Abstract

A Vertical transient voltage suppressing(TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.

Description

201044541 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a structure and a manufacturing method of a transient voltage suppressor (TVS), in particular, a vertical suspension having a symmetric breakdown voltage and a low process sensitivity Structure and fabrication method of a state voltage suppressor (TVS). [Prior Art] [0002] Voltage and current transients are the main cause of damage to integrated circuits in electronic systems. Transients are generated from a variety of internal and external sources to the system. For example, transient common sources include power supplies, AC circuit fluctuations, lightning overvoltages, and normal discharge of electrostatic discharge (ESD). Transient voltage suppressors (TVS) are typically used to protect integrated circuits from transients or Damage caused by overvoltage. The Transient Voltage Suppressor (TVS) is a unidirectional or bidirectional device. Since electronic components are sensitive to positive or negative transient voltages, more and more electronic devices require bidirectional transient voltage suppressor (TVS) protection. For example, two-way transient voltage suppressors (TVS) can be used to protect high-speed data lines for portable handheld devices, keyboards, notebook computers, digital cameras, portable global positioning systems (GPS), and MP3 players. Figure 1 shows a schematic diagram of a bidirectional transient voltage suppressor (TVS) for protecting a signal line. There are several ways to implement a two-way transient voltage suppressor (TVS). In most cases, a vertical structure is used to limit the mold size of a transient voltage suppressor (TVS) device. In addition, transient voltage suppressors (TVS) based breakdown diodes are typically used in low voltage situations. More specifically, the low voltage bidirectional transient voltage suppressor () based on the breakdown diode is implemented using an NpN or PNP structure with an emitter-base and collector-base breakdown voltage of 099113694, It is also necessary to optimize the doping concentration of the NPN or PNP layer in order to punch through the breakdown form number A0101. Page 4 / Total 40 pages 0993265071-0 201044541 For example, the 'punch-through diode transient voltage suppressor (TVS) is often lightly doped shallow The base bipolar junction transistor (BJT) is characterized by the ability to pass through the lightly doped base region even when the voltage is below the avalanche breakdown voltage. Transient voltage suppressors (TVS) based on punch-through diodes are typically formed by a stacked structure of multi-doped layers, such as a four-layer structure containing np p + _p__n+, and a p-layer as a lightly doped layer. The traditional transimpedance diode-based transient voltage suppressor (TVS) exists

Not enough. First, due to the limitations of the fabrication process, the breakdown voltage of a transient voltage suppressor (TVS) device is generally asymmetrical. That is to say, the breakdown voltage of the emitter-base and collector_base of the transient voltage suppressor (!VS) | is not. Secondly, the breakdown voltage often occurs very largely. The most representative change is that the transient state voltage suppressor (tvs) buildup layer is formed by epitaxial growth of each layer, or by subsequent layer ions.

〉Into the initial epitaxial layer formed. The breakdown voltage is a function of the thickness of the epitaxial layer and the doping of the epitaxial layer doped with the 4 base region. The epitaxial layer has an inherent change in doping concentration. Moreover, the thickness of the epitaxial layer, especially the relatively thin outer layer, also varies across the wafer and from the wafer to the wafer. Therefore, the variation of the breakdown voltage can be observed only when the thickness of the epitaxial layer is changed. . In addition, if the epitaxial layer is too thin, overdoping from the re-transformed pure bottom will adversely affect the doping concentration of the polar regions. The layer or even the base device uses two conventional doping structures for making a transient voltage suppressor (TVS). Traditional vertical temporary bear voltage suppressor (TVS, station 4 $罝 transient power (8) diagram ~ with fineness (2nd (4) and 2 099113694 5 / one step in the impurity concentration (2nd (form number A0101, c / map) The basis of page 5 / total 4 pages 09932 (201044541 polar region formed. The base region is not the same as the __ structure is usually due to the low energy of forming the base region in the thin epitaxial layer. The doping structure of the uniform sentence will produce a symmetric shot pressure, and the sensitivity of the breakdown voltage to the manufacturing process change. [Invention] [0003] According to the present invention, a kind of vertical transient voltage suppression The device (TVS) device includes a heavily doped semiconductor substrate of a first conductivity type, an epitaxial layer of a first conductivity type formed with a first thickness on the substrate, and - a hetero person is located outside the epitaxial layer t (4) The base region of the second conductivity type of the intermediate region. The cation region and the epitaxial layer provide substantially symmetrical vertical doping structures on both sides of the base region such that the breakdown voltages in the two directions are symmetrical. According to another aspect of the invention, a transient voltage suppression is prepared The method of the present invention (TVS) comprises preparing a heavily doped semiconductor substrate of a first conductivity type, forming an epitaxial layer of a first conductivity type having a first thickness on the substrate, and forming one in the epitaxial layer a base region of a second conductive region located in a middle gate region of the epitaxial layer. The base region and the epitaxial layer are provided on both sides of the base region to provide a substantially symmetrical vertical doping structure. The regions are formed by high energy implantation in the epitaxial layer. In another embodiment, the 'base region formed as a buried layer' is located in the middle of the epitaxial layer. In another embodiment, the epitaxial layer The impurity concentration is extremely low' and a buffer layer of the first conductivity type is implanted respectively above and at the bottom of the base region in the epitaxial layer. _ Read the following detailed shirt test _, the invention will be better understood 〇099113694 Form No. A0101 Page 6/Total 4 Page 0993265071 201044541 [Embodiment] [0004] Ο

In accordance with the principles of the present invention, a high energy base implant is utilized based on a through-diode or avalanche mode transient voltage suppressor (TVS) device to form a base region in the thick layer to achieve a symmetric NPN or PNP structure. This high energy implantation ensures that the transient voltage suppression H (TVS) device has a symmetrical base doping structure that aligns the breakdown voltage of the transient 'voltage suppressor (TVS) device. The thick epitaxial layer is used so that when the base region is completely depleted under reverse bias, the depletion layer does not reach the edge of the epitaxial layer, but is still in the epitaxial layer. In this case, variations in the thickness of the epitaxial layer will not affect the breakdown voltage of the transient voltage suppressor (TVS) device. In an optional implementation, in the epitaxial layer cap, the doped layer technique forms the base region to obtain the same symmetric doped structure. According to another aspect of the invention, an epitaxial layer having a low doping concentration plate is used, and the doping level of the epitaxial layer is corrected by implanting a buffer layer in the epitaxial layer and carrying a base region. The buffer layer is capable of isolating the sensitivity of the Transient Voltage Suppressor (TVS) device to the 挣g in the epitaxial layer. The breakdown voltage of the formed vertical transient voltage suppression II (TVS) will no longer be susceptible to the thickness and doping concentration of the epitaxial layer. In another embodiment, a buffer layer is implanted into the top and bottom of the base region in the epitaxial layer such that the buffer layer and the base region control the breakdown voltage. Since the buffer layer and the base region are formed by implantation, this will further solve various problems caused by the variation of the doping in the epitaxial layer. In the present description, the avalanche mode transient voltage suppressing device and the transient voltage suppressing device based on one punch-through body are referred to as a transient voltage suppressor (TVS). Optimize the doping level of avalanche mode transient voltage suppressor (TVS) to facilitate avalanche breakdown in the base region, avalanche power in the base region 099113694 Form No. A0101 Page 7 / Total 40 Page 0993265071-0 201044541 The bipolar gain - from the rise, can improve the clamping of the «pole-to-emitter voltage. On the other hand, a temporary voltage suppressor (TVS) based on a punch-through diode is characterized as a bipolar junction transistor having a 9-doped base and optimizing the doping level of the base. , easy to punch through. Especially when the voltage is lower than the punch-through voltage, the punch-through of the lightly doped base region occurs. The avalanche mode and the punch-through diode-based transient voltage suppressor (TVS) device are particularly effective in suppressing peak voltages in the low voltage range of 5 volts or less in low voltage applications. Whether it is an avalanche-based vertical transient voltage suppressor (TVS) or a punch-through transient voltage suppressor (that), their breakdown voltage is the base region doping level and thickness relative to the surrounding collector and emission. The function of the doping level and thickness in the region. In the transient diode suppressor (TVS) based on the punch-through diode, the thickness and doping level of the suitable lightly doped base region are selected so that the base region is under the punch-through voltage. Completely exhausted. More specifically, as long as the lightly doped base region is shallow, most of the depletion enthalpy extends into the lightly doped base region, and when the depletion layer reaches the other side of the base region, the punchthrough is achieved. . Therefore, the punch-through diode acts as a short circuit. If the device's punch-through voltage is lower than its avalanche voltage, the device will pass through the punch-through. If the avalanche voltage of the device is below its punch-through voltage, the device will break through the avalanche. Figure 3 is a cross-sectional view showing the fabrication of a vertical transient voltage suppressor (TVS) device using an NPN structure in accordance with one embodiment of the present invention. Referring to FIG. 3, a vertical transient voltage suppressor (TVS) device 1 is formed on the re-substituted N + profile 102 to form a nappy N- epitaxial layer 104 on the N + substrate 102. . High energy ion implantation into the N- epitaxial layer 1〇4, 099113694 Form No. A0101 Page 8 of 40 0993265071-0 201044541 Area 112 bit Forms a lightly doped (four) p-base region 112. Thereby, germanium and a base are formed in the intermediate portion of the N- epitaxial layer 1〇4. The wound epitaxial layer 1 () 4 made in accordance with the present invention is thicker than the epitaxial layer used in conventional vertical dielectric devices. In particular, the thickness of the 'N- epitaxial layer m is much thicker than the base region 112. In this case, the epitaxial layer thickness variation will not affect the breakdown voltage of the transient voltage suppressor (m) device 100 due to the inherent limitations of the epitaxial fabrication process.

After the formation of the G P-base region ι12, a heavily doped N+ contact region 114 is formed on the surface of the N- epitaxial layer 1G4 to form an ohmic contact. The dielectric layer ΐ6 is used to cover the semiconductor structure, _protection. An opening ' is formed in the dielectric layer 116 to form an anode electrode 118, which contacts the layer ι4 to form an electrical contact. And on the bottom surface of the substrate, a cathode electrode 12A is formed to make electrical contact with the N+ substrate 102. A typical anode electrode ι 8 and cathode electrode 12G are composed of a conductive material such as a metal layer.

In this example, the 'transient voltage suppression n (, TVS) device lh forms an array of the same transient electrical (T) (Tvs) split on the substrate by channel isolation, or forms a temporary with other devices. The state voltage suppressor (tvs) device 'to achieve the purpose of the protection circuit required for the integrated circuit. In this embodiment, an extension-bottom channel is prepared, and a transient voltage suppressor (tvs) device 100 is disposed. The channel is in line with the oxide layer 1〇8 and is filled with a polysilicon layer 110. This channel. By using a thick lightly doped N-type epitaxial layer 1Q4 and a high energy base implant 'forming base region 112, the transient voltage suppressor (TVS) device 1 is in the N-/P-/N- region. A symmetrical push structure is realized. 4(4) and 4 099113694(b) show two forms of form number A0101, page 9 of total 40, in accordance with two different embodiments of the present invention, two of which are available in the transient voltage 0993265071-0 201044541 suppressor (m) device ιοο Vertical doping structure. Referring to Figures 4(a) and 4(b), it can be seen from the figure that the doping structure of the transient voltage suppressor (TVS) device 1〇〇 is from N + contact layer 114 down to N + substrate 102. A symmetric P-type doping is formed in the middle of the lightly doped (n-) epitaxial layer. Due to this symmetrical structure, the breakdown voltage of the transient voltage suppressor (TVS) device 100 at the second junction 2 of the first junction is the same. Therefore, the transient voltage suppressor (TVS) device 1 is characterized by a breakdown voltage breakdown. In addition, the base charge of the 'transient voltage suppression H (TVS) device (10) can only be surnamed by the base region implant with the doping level of the semiconductor epitaxial. Therefore, good base charge control is achieved. In the fourth (a) diagram, a p-base region is formed such that the doping concentration is less than or substantially equal to the drain n_outer layer. The doped structure in Fig. 4(a) has a very light basis, and the pole doping v is therefore easily depleted and optimized for the through-breakdown's transient voltage suppressor (TVS) device. In the 4th (b)th picture, the P-base region is formed to have a doping concentration greater than that of the η-epitaxial layer. The doped structure in Figure 4(b) has a higher base doping, so for avalanche breakdown, the state voltage suppressor (TVS) device can be easily optimized ^ by optimizing the base region doping Rating and thickness, select the required breakdown voltage (avalanche or punch-through) for the Transient Voltage Suppressor (TVS) device. The Transient Voltage Suppressor (TVS) device 1 can operate in two ways. In a low-voltage environment, an accurate breakdown voltage can be obtained by well controlling the charge of the base region by implantation through a high-energy base region in a thick epitaxial layer. At this time, the breakdown voltage is determined by the breakdown voltage of the collector_emitter (BVce〇). In high-voltage applications, the avalanche breakdown voltage at junction n*j2 tends to dominate, since the breakdown voltages of the two junctions are the same, so 099113694 Form No. A0101 Page 10/Total 40 Page 0993265071-0 201044541 In positive and negative voltage polarities, the transient voltage suppressor (TVS) device 100 operates symmetrically. One of the main features of the transient voltage suppressor (TVS) device 100 is that its breakdown voltage depends only on the doping level of the epitaxial layer and the control of the base doping. Since the thickness of the epitaxial layer formed does not reach the substrate by the thickness of the epitaxial layer regardless of the thickness of the epitaxial layer, the breakdown voltage of the transient voltage suppressor (TVS) device 100 changes with respect to the thickness of the epitaxial layer.

Deuteration is not sensitive. Figure 5 shows a conventional transient voltage suppressor (TVS) with an asymmetric doping structure, and a transient voltage suppressor (TVS) device with a symmetric doping structure and a thick epitaxial layer as shown in the present invention. The relationship between the breakdown voltage and the thickness of the epitaxial layer. Referring to Figure 5, for a conventional transient voltage suppressor (TVS) with an asymmetric doping structure (line 180), the breakdown voltage is a function of the thickness of the epitaxial layer. Therefore, any change in the thickness of the epitaxial layer caused by the limitations of the entanglement will result in a breakdown voltage variation. However, for the inventive symmetrical structure and the 'thickness of the epitaxial transient suppression n (Tvs) device (line 182), the breakdown voltage will become insensitive to changes in the thickness of the epitaxial layer. . Therefore, the transient voltage suppressor (TVS) device of the invention is more powerful and less susceptible to variations in the manufacturing process. In the above embodiment, the base region 112 is formed by a high energy ion implantation technique. In one embodiment, the implant energy used is on the order of 1000 keV. The high energy implantation into the thick epitaxial layer is good to obtain a symmetric doped structure. In addition, in one embodiment, a high energy ion implantation process is used. In another embodiment, the P-base region is formed by two or more ion implantation processes. The symmetry of the doped structure can be improved by using multiple implantation processes. Therefore, in a 099113694 page 11 / a total of 40 page form number A0101 my one through 099326 201044541 in the example, as shown in Figure 6, using at least two high-energy implantation process to obtain the desired symmetric doping structure . The dotted line in Fig. 6 shows a longitudinal sectional view of a doped structure in which a base region is formed by a first ion implantation process. This base region may be slightly deformed by the first ion implantation process. The doped structure represented by the solid line in Fig. 6 can enhance the symmetry of the base doped structure by an additional implantation process. Whether these additional implants are either n-type or p-type depends on the need to enhance doping and breakdown symmetry. Figures 7(a) through 7(d) illustrate the fabrication of a transient voltage suppressor (TVS) device as shown in Figure 3, in accordance with one embodiment of the present invention. Referring to Figure 7(a), the first step in the preparation process is to use N + substrate 102 as the starting material. The N-type epitaxial layer 104 is grown by an epitaxial process. The N-type epitaxial layer 104 is lightly doped to a thickness of about 5-6/m. In accordance with the present invention, the thickness of the N-type epitaxial layer 104 is greater than the thickness of the epitaxial layer in a conventional vertical transient voltage suppressor (TVS) device. On an integrated circuit, when the transient voltage suppressor (TVS) device 100 is fabricated with other devices, the transient voltage suppressor (TVS) device must be isolated. Fig. 7(b) shows a trench isolation structure for isolating the transient voltage suppressor (TVS) device 100 formed on the N + substrate 102 and the N - epitaxial layer 104. The trench isolation structure as shown in Figure 7(b) is for illustrative purposes only, and in other embodiments, other isolation structures may be used. The specific type of isolation structure is not a critical factor in determining the practice of the invention. The transient voltage suppressor (TVS) device of the present invention can be fabricated using various types of isolation structures currently known or unknown. Referring to Fig. 7(b), a trench 106 is formed in the N- epitaxial layer 104, and a portion of the trench 106 extends into the N + substrate 102. A transient voltage suppressor (TVS) device is fabricated in the area defined by the channel 106. Channel 106 and oxide layer 108 099113694 Form No. A0101 Page 12 of 40 0993265071-0 201044541 In a straight line, this channel is then filled with a polysilicon layer 110. The polysilicon layer 110 is back etched such that a portion thereof is recessed toward the upper surface of the Ν-epitaxial layer 104. Referring to Fig. 7(c), the Ρ-base region 112 is formed by an ion implantation process. This Ρ-base implant is a high energy implant in which the Ρ-type implant is placed in the middle of the Ν-elongation layer 104. In one embodiment, to form a pass-through diode-based transient voltage suppressor (TVS) device, boron is used as a Ρ-type dopant, implanted with a P-base, and the implant energy is 1000 keV, the dose It is 3 x 1013 atoms/cm2. In another embodiment, an avalanche breakdown transient voltage suppressor (TVS) device is prepared using an implantation dose of 9 x 1013 atoms/cm2. According to an alternative embodiment of the invention, the symmetry of the doped structure is enhanced by the second P-base implant. The second P-base implant can be performed before or after the first P-base implantation process. The second P-base implant can also be performed using the same or different processing parameters of energy, dose, and the like. Referring to Fig. 7(d), after the formation of the P-base, an N+ contact layer 114 is formed over the N- epitaxial layer 104 by an ion implantation process. The N + contact layer 114 is heavily doped and is only over the N- epitaxial layer 104 to form an ohmic contact with the N- epitaxial layer. In one embodiment, the N+ contact implant has an implant energy of 80 keV and a dose of 4 x 1015 atoms/cm2, which is broken down as an N-type dopant. Then, as shown in Fig. 3, a dielectric layer 116 is formed over the entire semiconductor structure, and an opening is formed in the dielectric layer to form an anode electrode 118 in electrical contact with the N + contact layer 114. A cathode electrode 120 is formed at the bottom of the N + substrate 102. Transient voltage suppressor (TVS) device 100, prepared in this manner, has many advantages over conventional transient voltage suppressor (TVS) devices. 099113694 Form No. A0101 Page 13 of 40 0993265071-0 201044541 First, by using a thick epitaxial layer and a high energy base implant, the resulting base region is located in the middle of the epitaxial layer. In particular, a thick epitaxial layer ensures that the base region is not formed outside the edge of the epitaxial layer or outside the epitaxial layer. Common variations in the thickness of the epitaxial layer do not adversely affect properties such as doping structure or breakdown voltage. Ensure that the symmetrical doping structure does not change due to process variations. Secondly, a p-base region is formed by high energy implantation, and a precise and more symmetrical doping structure is realized. Moreover, the symmetry of the doped structure can also be enhanced by the second implantation. Finally, the breakdown voltage of the Transient Voltage Suppressor (TVS) device depends only on the doping level of the base region and the doping level of the epitaxial layer, so that the breakdown voltage can be well controlled. Alternative Embodiment 丨 In another embodiment, an epitaxial layer having a very low doping concentration is used, and the doping level of the epitaxial layer is corrected by a buffer layer carrying a base region formed in the epitaxial layer. Figure 8 is a cross-sectional view showing a first alternative embodiment of a vertical transient voltage suppressor (TVs) device formed using an NPN structure in accordance with the present invention. Referring to FIG. 8, the transient voltage suppressor (TVS) device 200 has a basic structure similar to that of the state of view voltage suppressor (tvs) device shown in FIG. 3, and gives similar reference materials. However, the transient voltage suppressor (TVS) device 2 is fabricated using an N-type epitaxial layer (N-- epitaxial layer) 204 having a very low doping concentration. A lightly doped N-type buffer layer 205 is formed in the N- epitaxial layer 204 by ion implantation. The P-base region 212 of the transient voltage suppressor (TVS) device 200 is located in the middle of the N-buffer layer 205. Therefore, the doping level of the formed n-buffer layer 205 is dominant, and the background doping of the N- epitaxial layer 204 becomes negligible. Transient Voltage Suppressor (tvs) as shown in Figure 3 099113694 Form No. A0101 Page 14 of 40 〇993 201044541 装置 Device 100' The remaining structure of the Transient Voltage Suppressor (TVS) device 200 is prepared. A plurality of contact layers 214 are formed on the upper surface of the germanium-epitaxial layer 204 through the openings in the mass layer 216 to form a positive electrode 218 in electrical contact with the germanium + contact layer 214, and a germanium + substrate 202 The electrically contacted cathode electrode can be isolated from the other devices formed on the integrated circuit using a polycrystalline litter filled trench isolation structure 8'210'. Since the N- epitaxial layer 2G4 is located between the N-buffer layer 205 and the N + substrate, the vertical doping structure of the transient voltage suppressor (m) device 200 is from the N + contact layer 214 to the N + base 2 〇 2, Not 70 fully symmetrical yet '.P — near the base 212, that is, from the top of the N-buffer layer 205, through the p_base 212, the bottom of the job-buffer layer 2〇5' this vertical doping structure remains It is said to be painful. More importantly, the appropriate N' buffer layer 2〇5 and the base concentration of the base 212 are chosen such that the breakdown voltage of the transient voltage suppressor (TVS) device 2〇〇 is still symmetrical. Another advantage of the Transient Voltage Suppressor (TVS) device 2 (10) is that n —

The buffer layer solves the sensitivity of the device to the inherent doping variations in the epitaxial layer. There are many variations in the doping concentration and thickness of the epitaxially grown layer. Conversely, precise control of implantation can have minimal changes in dopant concentration and thickness. The vertical transient suppressor (TVS) device 2_breakdown voltage is not sensitive to changes in epitaxial layer thickness and change/agronomy. Therefore, the transient voltage suppressor (tvs) device 200 is more powerful than the conventional transient voltage suppressor (TVS) device. 099113694 The 9th chart of the data according to the present day (four) - a second alternative embodiment, a vertical transient voltage suppressor (TVS) device prepared using the Qing structure of the cross-sectional form number A0101 page 15 / a total of 40 pages 0993265071 -0 201044541 Face view. The transient voltage suppressor (TVS) device 300 in Fig. 9 represents another method of preparing an N-buffer layer. To simplify the discussion process, Figure 9 uses references similar to those in Figure 8. Referring to Figure 9, a transient voltage suppressor (TVS) device 300 has a very low doping concentration epitaxial layer 204 and an N-buffer layer as two separate doped regions 3〇5A and

305B to define the range of the P-base region 212. The N-buffer layers 305A and 305B have a higher doping concentration than the N- epitaxial layer 204. The N-doped regions 3〇5a and 305B are isolated from the channel by a certain distance and do not extend to the full width of the p-base region 212. Therefore, this semiconductor function is mainly embodied in the junction between the top N-buffer layer 305A and the P-base region 212, and the junction between the p-base region 212 and the bottom N-buffer layer 305B. The transient voltage suppression: the <TVS) device _, the transient voltage suppressor (TVS) device 3_n, and the push level of the epitaxial layer are not sensitive to the thickness. Moreover, the breakdown voltage of the transient voltage suppressor (TVS) device 300 is only a function of the thickness and doping level of the N-buffer layers 305A, 305B and the base region 212. These quantities are well controlled. It is known that the breakdown voltage of an electro-optical vessel is usually distorted in the vicinity of the trench isolation structure (210, 2〇8). Transient voltage suppressor (ie, device 3_ another advantage is that n-buffer layer Cong and 3_ isolated from the channel, forcing breakdown occurs in the middle of the side of the base region away from the channel isolation structure'. Therefore, breakdown voltage The average sentence is controllable. Figures 10(a) to (d) show the preparation process of the transient voltage suppressor (TVS) device shown in Fig. 9 in accordance with an embodiment of the present invention. ) Figure, HM m; The first step of ^仏 is + the base layer 204. . material. The epitaxial layer 104 has a thickness of about 5 by the epitaxial light growth lightly doped type 099113694 苐16 pages/total 40 pages. The form number _ order 厌, ·] is 5-6/zm. According to the invention of 0993261 201044541, the thickness of the germanium-type epitaxial layer 104 is greater than the thickness of the epitaxial layer in a conventional vertical transient voltage suppressor (TVS) device. Section 1 (b) shows the fabrication of a trench isolation structure in a transient voltage suppressor (TVS) device 300. A channel 206 is formed in the N- epitaxial layer 204, and a portion of the channel 206 extends into the N+ substrate 202. The channel 2〇6 is in a straight line with the deuterated layer 2〇8, and then the channel is filled with a polysilicon layer 210. The polysilicon layer 210 is back etched such that a portion thereof is recessed toward the upper surface of the N- epitaxial layer 2〇4.

Ο At this time, the N-buffer layer 2〇5 can be formed by the ion implantation process, and then the transient voltage suppressor shown in the entire FIG. 8 is completed by the processes shown in FIGS. 7(c) and 7(4) ( TVS) Preparation of device 2〇〇. The p-base region 212 is bound to form at the f-position of the implanted buffer layer 2〇5. Referring to Fig. 10(c), a transient voltage suppressor (TVS) device 3A as shown in Fig. 9 is prepared by forming an p_base region 212' by an ion implantation process. This P-base implant is a high energy implant that is placed in the middle of the epitaxial layer 204. In one embodiment, boron is used as a dopant, implanted with a P-base, with an implantation energy of 1 〇〇〇 keV and a dose of ί: blue 5x1013 atoms/cm2. In a ▲ embodiment, the symmetry of the doped structure is enhanced by performing a second P-base implant. in? After the base is implanted, two N-type ion implantations are performed to form N_buffer layers 3〇 and 305Β. These two implants require different implant energies to place the Ν-type region at the top and bottom junctions of the Ρ-base region 2丨2. In one embodiment, the implantation energy of the N-base implant is 2500 keV for the bottom buffer layer 305B, and for the top buffer layer 3〇5^6 〇 okeV, the dose is 7×10 13 atoms/cm 2 , and phosphorus is used as the N — Type dopant. After implantation, heat treatment is performed at 1100 ° C to anneal the implanted region to form a diffusion region as shown in Fig. 099113694 0993265071-0 Form No. A0101 Page 17 of 40 201044541 10 (C). Referring to Fig. 10(d), after the base electrode and the buffer layer are formed, a material contact layer 214 is formed over the epitaxial layer 2G4 by an ion implantation process. The N + contact layer 214 is heavily doped and is only over the epitaxial layer 2 〇 4 to form an ohmic contact with the N- epitaxial layer. In one embodiment, the implanted energy of the N+ contact implant is 8 〇 keV, the dose is 4 x 1015 atoms/Cln2, and arsenic is used as the N-type dopant. Then, as shown in Fig. 9, a dielectric layer 216 is formed over the entire semiconductor structure, and an opening ' is formed in the dielectric layer to form an anode electrode 213 which is in electrical contact with the N + contact layer 214. A cathode electrode 220 is formed at the bottom of the N+ substrate 202. PNP transistor r; things, in the above embodiment, a symmetric NPN transient voltage suppressor (TVS) device is formed. The transient voltage suppressor (TVS) device of the present invention can also be formed by a symmetric PNp > profile as shown in Figures 11, 12 and 13. In one embodiment, when preparing a symmetric PNP Transient Voltage Suppressor (TVS) device, except for the use of materials and dopants of opposite polarity, the other processes are as described above, that is, for For the NPN structure, the ruthenium bases 412 and 512 are prepared using high energy implantation as described above. Channel isolation structures 408, 410, 508, 510 isolate transient voltage suppressor (TVS) devices 400, 500, 600. The dielectric layers 416, 516 cause the anode metal 418, 518 to contact the re-doping regions 414, 514. Cathode metal layers 420, 520 contact heavily doped P+ substrates 402, 502. In accordance with another aspect of the invention, the N-base regions 412, 512 of the PNP Transient Voltage Suppressor (TVS) device are formed as N-type buried layers without the use of ion implantation. 099113694 For example, when using a buried layer in a transient voltage suppressor (TVS) device as shown in Fig. 11 Form No. A0101 Page 18 of 40 0993265071-0 201044541 400, the intermediate process will form _? The epitaxial layer is then implanted into the germanium-epitaxial layer formed by the intermediate process by type implantation. Finally, the remaining portion of the epitaxial layer 4〇4 is formed. In the subsequent heat treatment process, a Ν-type buried layer is formed in the middle of the Ρ-epitaxial layer as the Ν-base region 412 (Ui). For the transient voltage suppressor (TVS) shown in Figures 12 and 13 for 500 and 6 〇 (), 进行 perform the same buried layer process 4 in this case, the intermediate process forms a lightly doped P_ The epitaxial layer 504 is implanted with an N-type implant H512 by N-type implantation. The remainder of the p-phase layer 5G4 is then formed. The Transient Voltage Suppressor (TVS) device contains a p_buffer layer 5〇5 β transient voltage suppressor (tvs) implanted in the p-epitaxial layer 504 of the nudger. The device 600 contains two distance channel spacers. The P-buffer layers 605A and 605B, which are difficult to structure far, define the range of the N-base region 512. In the NpN type transient voltage suppressor (TVS) device as described above, the buried layer preparation process can also be used to form the P-base regions 112, 212. Fundamentally speaking, through one or more high-energy ion implantations, or by masking

The buried layer preparation process forms a base region in the NpN and pNp smart state voltage suppressor (TVS) devices of the present invention. In accordance with an alternative embodiment of the present invention, in order to reduce electric field distortion near the edge of the isolation structure, the P_base region is enlarged at the trench isolation edge to prevent the interface between the dream epitaxial layer and the channel isolation. Low breakdown voltage at the place. Figure 14 is a cross-sectional view showing a vertical transient voltage suppressor (TVS) device fabricated using an NPN structure in accordance with a third alternative embodiment of the present invention. Referring to Fig. 14, the basic structure of the transient voltage suppressor (TVS) device 700 is similar to that of the transient voltage suppressor (TVS) device 100 shown in Fig. 3 and a similar reference is given. In Transient Power 099113694 Form No. A0101 Page 19 / Total 40 Stomach 0993265071-0 201044541 Pressure Suppressor (TVS) Device 7〇〇, at the edge of the channel isolation junction 8, 11〇, P-base region 712 Together with the additional p-type implant 75() forms 'to form an enlarged P-base portion. The enlarged P-base portion 750 in this embodiment is only a bit element on the bottom surface of the P-base region 712. In an alternative embodiment illustrated in Figure 15, on the top and bottom surfaces of the base region 812, the P-base region 812 is formed with the enlarged p-base portion 85A. As shown in Fig. 9, in the transient voltage suppressor (τνς) device 3, the N-doped regions 305A and 305B defining the range of the P-base region 212 have the same thickness "d". In other embodiments, as shown in FIG. 16, the two doped regions are formed for the bottom doped region to reach the substrate 1. FIG. 16 shows a fifth embodiment according to the present invention, an NpN structure is used. A cross-sectional view of a vertical transient voltage suppressor (TVS) device. Referring to Fig. 16, the basic structure of the transient voltage suppressor (TVS) device 900 is similar to the transient voltage suppressor (TVS) device 300 shown in Fig. 9, and a similar reference port is shown for transient voltage suppression. In the (TVS) device 900, 'the bottom N-buffer 905B is formed so that it is up to the N+ substrate 202. The top N - buffer layer 905 A is largely identical to the top N - buffer layer 305A shown in FIG. An advantage of this embodiment is that the epitaxial layer 204 and its inherent doping variations can be completely bypassed. As shown in Fig. 17, the PNP type transient voltage suppressor (TVS) device can use the same structure. Figure 17 is a cross-sectional view showing a vertical transient voltage suppressor (TVS) device using a PNP structure in accordance with a third embodiment of the present invention. Referring to Fig. 17, the basic structure of the transient voltage suppressor (TVS) device 1000 is similar to the transient voltage suppressor (TVS) device 600 shown in Fig. 13, and a similar reference is given. At 099113694 Form No. A0101 Page 20 of 40 0993265071-0 201044541 In the Transient Voltage Suppressor (TVS) device 1000, a bottom N-buffer layer 1 005B is formed to bring it to the P+ substrate 502. The top N-buffer layer 1 005A is largely identical to the top N-buffer layer 605A shown in FIG. The above detailed description is only for the purposes of illustration and description There are many modifications and variations within the scope of the invention. The scope of the invention is defined by the appended claims. [Simple description of the map]

Figure 1 shows a bidirectional transient voltage suppressor (TVS) for protecting signal lines. Figures 2(a) through 2(c) show various conventional doping structures used in fabricating transient voltage suppressor (TVS) devices.

Figure 3 is a cross-sectional view showing a vertical transient voltage suppressor (TVS) device formed using an NPN structure in accordance with one embodiment of the present invention. Figures 4(a) and 4(b) show two vertical doped structures available in a transient voltage suppressor (TVS) device 100 in accordance with two different embodiments of the present invention. Figure 5 shows a conventional transient voltage suppressor (TVS) having an asymmetric doping structure, and a transient voltage suppressor (TVS) device having a symmetric doping structure and a thick epitaxial layer according to the present invention, The relationship between the breakdown voltage and the thickness of the epitaxial layer. Figure 6 is a longitudinal cross-sectional view showing the doping structure of a transient voltage suppressor (TVS) device when two base regions are formed using two high energy ion implantation processes in accordance with one embodiment of the present invention. - Figures 7(a) through 7(d) show the preparation of a transient voltage suppressor (TVS) device as shown in Figure 3, in accordance with one embodiment of the present invention. 099113694 Form No. A0101 Page 21 of 40 0993265071-0 201044541 Figure 8 shows a cross-dressing of a vertical transient voltage suppressor (TVS) device formed using an NPN structure in accordance with a first alternative embodiment of the present invention. Face view. Figure 9 is a cross-sectional view showing a vertical transient voltage suppressor (TVS) device formed using an NPN structure in accordance with a second alternative embodiment of the present invention. Figures 10(a) through 10(d) illustrate the fabrication of a transient voltage suppressor (TVS) device as shown in Figure 9 in accordance with one embodiment of the present invention. Figure 11 is a cross-sectional view showing the preparation of a vertical transient voltage suppressor (TVS>: device using an NPN structure in accordance with an embodiment of the present invention. Figure 12 is a view showing a first alternative embodiment of the present invention, used in accordance with the present invention. Cross-sectional view of a structure-prepared vertical transient voltage suppressor (TVS) device. Figure 13 shows a cross-sectional view of a vertical transient voltage suppressor (TVS) mounted using a pNp structure in accordance with a second alternative embodiment of the present invention. Wear a face view〇

Figure 14 is a cross-sectional view showing the preparation of a vertical transient voltage suppressor (TVS) device using an NpN structure in accordance with a third alternative embodiment of the present invention.

Figure 15 is a cross-sectional view showing a vertical transient voltage suppressor (TVS) device using an NpN structure in accordance with a fourth alternative embodiment of the present invention. Figure 16 is a view showing a fifth alternative embodiment in accordance with the present invention. Cross-sectional view of a vertical transient voltage suppressor (TVS) device using an NpN structure 099113694 Form No. A0101 Page 22 of 40 0993265071-0 201044541 Figure 17 shows a third alternative implementation in accordance with the present invention Example, cross-sectional view of a vertical transient voltage suppressor (TVS) device using a pnp structure [Main component symbol description] [0006] 100, 200, 300, 400, 500, 600, 700, 900, 1000: Transient voltage Suppressor (TVS) device 102: N+ substrate 104, 204: N-epitaxial layer 106, 206: channel

108: oxide layer 110: polycrystalline layer 112, 212: P-base region 114: heavily doped N+ contact regions 116, 216, 416, 516: dielectric layers 118, 218, 418, 518: anode electrodes 120, 220 : Cathode electrode. :,

180, 182: line 202: N + basic 205: buffer layer

208, 210, 408, 410, 508, 510: trench isolation structure 214: N + contact layer 305A, 305B: N-doped region 402, 502: P + substrate 404: P - epitaxial layer 412, 512 : N - Base 414, 514: heavily doped region 099113694 Form ed. St A0101 Page 23 / Total 40 pages 0993265071-0 201044541 420, 520 · Cathode metal layer 605A, 605B: P_buffer layer 712, 812 ·· P - Base region 750: P-type implant 850: P - base portion 905A, 905B, 1 005A, 1 005B: N - buffer layer TVS: transient voltage suppressor 099113694 Form number A0101 Page 24 of 40

0993265071-0

Claims (1)

201044541 VII. Patent application scope: 1. A vertical transient voltage suppressor (TVS) device comprises: a heavily doped semiconductor substrate of a first conductivity type; an epitaxial type of a first conductivity type formed on the substrate a layer having a first thickness; and a base region of a second conductivity type implanted in the epitaxial layer. The base region is located in an intermediate region of the epitaxial layer, wherein the base region and the epitaxial layer are at the base The two sides of the zone provide a vertical doping structure of - substantially symmetrical Q. The vertical transient voltage suppressor (TM) device of the first aspect of the patent range draws a suitable doping concentration of the base region epitaxial layer such that the base region is puncated through. 3. The vertical transient voltage suppressor (7)$) device of claim i, wherein a suitable base region and a doping concentration of the epitaxial layer are selected such that the base region is broken by avalanche. The vertical transient voltage suppressor (claw Q) device of claim 1, further comprising: one or more trench isolation structures formed in the epitaxial layer and a portion of the semiconductor substrate, the channel The isolation structure surrounds a portion of the base region and a portion of the epitaxial layer to isolate the transient electrical suppressor (TVS) device. 5. The vertical transient electrical repeat suppressor (Tys) device of claim 4, wherein the base region comprises an enlarged portion at a periphery of the base region adjacent the trench isolation structure. 6. The vertical transient electrical suppressor (TVS) device of claim 1, wherein the first conductivity type comprises a 1 - type conductivity, the 099113694 form number A0101 page 25 / A total of 40 pages 0993265071-0 201044541 The second conductivity type includes P-type conductivity. A vertical transient voltage suppressor (tvs) device as described in claim 1, wherein the first conductivity type comprises p-type conductivity and the second conductivity type comprises N-type conductivity. The vertical transient voltage suppressor (TVS) device of claim 1, wherein the second thickness of the base region is much smaller than the first thickness. The vertical transient voltage suppressor (tvs) device of claim 1, wherein the first thickness of the epitaxial layer is at least 5 from m. 10. The vertical temporary state suppressor (tvs) device of claim 1, wherein the epitaxial layer comprises an epitaxial layer doped with an n-degree pole, the transient voltage suppressor (TVS) The device further includes: a second doped region of the first conductivity type formed in the epitaxial layer, the second doped region is lightly doped, but the doping concentration is higher than the epitaxial layer, and the base region is formed in the second doping The middle area of the miscellaneous area. 11. The vertical transient voltage suppressor (TVS) device of claim 1, wherein the epitaxial layer comprises an epitaxial layer having a very low doping concentration, and the transient voltage suppressor (TVS) device is further The method includes: a bottom doped region of a first conductivity type at a bottom junction between the base region and the epitaxial layer; and a first conductive region at a top junction between the base region of the bottom junction and the epitaxial layer Type of top doped region, the bottom and top doped regions are lightly doped, but the doping concentration is higher than the epitaxial layer, a portion of each of the bottom and top doped regions is in the base region, and the other portion is in the epitaxial layer in. 12. The vertical transient voltage suppressor (tvs) device of claim 11, further comprising: 099113694 one or more channel isolation form numbers A0101 formed in the epitaxial layer and a portion of the semiconductor substrate 26 pages/total 40 pages 0993265071-0 201044541 structure, the trench junction is wound around the -partial (four) and - part of the epitaxial layer to isolate the transient voltage suppressor (TVS) device, /, top P and bottom. The p-doped region is at a distance from one or more of the trench isolation structures. ό 14 〇 15 G 16 17 18 099113694 A vertical transient voltage suppressor (TVS) device as described in claim 11 of the patent application, wherein the bottom doped region reaches the bottom. A method for preparing a vertical transient voltage suppressor (tvs) device, comprising: t providing a semiconductor substrate of a first conductivity type, the substrate is heavily substituted; forming a first conductive on the substrate a type of epitaxial layer having a first thickness; and a base region of a second conductivity type formed in the epitaxial layer, the base region being located in an intermediate region of the epitaxial layer, wherein the base region and the epitaxial region The layers provide a substantially symmetrical vertical doped structure on both sides of the base region. As described in claim 14 of the scope of patent application, the shape of the base region is composed of a high-energy separation material formed by a base. As described in claim 15, the method of forming a base region by high energy ion implantation comprises implanting a base region with a high energy ion implantation energy of about iOGGkeV. The method of claim 14, wherein the forming a base region of the second conductivity type comprises: performing a first high energy ion implantation of the second conductivity type; and performing additional high energy ion implantation to enhance the doping The symmetry of the hetero structure. The method of claim 14, wherein forming the base region comprises forming a base region through a buried layer structure. Form No. A0101 Page 27 of 4 932 0993265071-0 201044541 19 · The method of claim 14, forming an epitaxial layer and forming a base region comprises selecting an appropriate doping concentration to form an epitaxial layer and The base region causes the base region to break through through. 20. The method of claim 14, forming an epitaxial layer and forming a base region, and selecting a suitable doping concentration to form an epitaxial layer and a base region' such that the base region is broken by avalanche. The method of claim 14, further comprising: one or more isolation structures formed in the epitaxial layer and a portion of the semiconductor substrate, the trench isolation junction extending to the substrate to isolate the transient Voltage suppressor (TVS) device. 22. The method of claim 21, wherein forming the base region further comprises forming a portion of the base region adjacent the trench isolation structure: an enlarged portion is formed at the edge. 23. The method of claim 14, wherein the first conductivity type comprises N-type conductivity and the second conductivity type comprises p-type conductivity. The method of claim 14, wherein the first conductivity type comprises P-type conductivity and the second conductivity type comprises N-type conductivity. The method of claim 14, wherein the epitaxial layer has a first thickness of at least 5 v m. 26. The method of claim 14, forming the epitaxial layer of the first conductivity type comprises forming an epitaxial layer of a first conductivity type having a very low doping concentration. The method further comprises: in the epitaxial layer A second doped region of a first conductivity type is formed, the second doped region being lightly doped, but having a higher doping concentration than the epitaxial layer, the base region being formed in an intermediate region of the second doped region. 099113694 The method of claim 14, wherein forming the first conductivity type epitaxial layer comprises forming a first conductivity type 0993265071-0 with a low doping concentration Form No. A0101 Page 28 / Total 40 Page 27 201044541 Epitaxial layer, the method further includes: forming a bottom at the bottom between the base region and the epitaxial layer, forming a bottom of the first conductivity type doped with the first ion implantation at the bottom At the junction of the junction __ and the outer county, a second doping region of the first conductivity type is formed by the second ion implantation, wherein the bottom and top doped regions are lightly doped, but the impurity concentration ratio epitaxial layer is changed. Further south 'each bottom and top doping (four) - part is located in the base region and the other portion is located in the epitaxial layer. Ο 〇 28 · The method according to claim 27, wherein the first doping region is formed by the first ion implantation, including implanting ions having an energy of about 2500 keV by the first ion implantation, and doping The impurity region is implanted with ions having an energy of about 600 keV by a second ion implantation to form a top doped region. The method of claim 27, further comprising: forming one or more trench isolation structures in the epitaxial layer and a portion of the semiconductor substrate, the trench isolation structure surrounding a portion of the base region and a portion Around the epitaxial layer to isolate a transient voltage suppressor (TVS) device, wherein the top and bottom doped regions are at a distance from one or more trench isolation structures. 30. As described in claim 27, the bottom doped region reaches the bottom 〇 099113694 Form No. A0101 Page 29 of 40 0993265071-0