TW201033896A - Systems, methods, and devices for configuring a device - Google Patents

Abstract

Disclosed are methods and devices, among which is a method (130) for configuring an electronic device (93). In one embodiment, an electronic device (93) may include one or more memory locations (97) having stored values representative of the capabilities of the device (97). According to an example configuration method, a configuring system (94) may access the device capabilities from the one or more memory locations (97) and configure the device (93) based on the accessed device capabilities.

Description

201033896 VI. Description of the Invention: [Technical Field of the Invention] Embodiments of the present invention generally relate to electronic devices, and more particularly, in some embodiments, to the configuration of such electronic devices. [Prior Art] In the calculation domain, the pattern recognition task is more and more challenging. The amount of data transmitted between computers continues to increase, and the number of types that users expect to identify increases. For example, spam or malware is usually measured by searching for patterns in a beech stream (for example, a specific phrase or fragment code). The number of patterns increases with spam and malware, as new types of samples can be implemented to search for new variants. For each of these types: search - data contention can form - the computational bottleneck. Usually, when the i-string/4 is received, it is searched for each pattern, one time. In f, the delay before the search for the _ part under the data stream is first: the number of patterns increases. Therefore, pattern recognition can slow down the reception of data. & hardware (eg, hardware that performs the above-described type identification tasks) can interface with multiple devices, systems, or systems. For example, the pattern recognition device can include a processor in a processor-based system to detect a desired type in the data stream. The manufacturer can select an electronic device to be "family". Same as the ability of each other in the same device. Bandit. Packed:: Less similar functionality' but different in terms of ability or other characteristics. In some instances 'this-family can contain (in order of increasing capacity) a basic device, a standard device'-advanced device, and an ultra-high 145319.doc 201033896 class device. However, the different capabilities of such devices often require each device to be configured in a uniform and rigorous manner. The flexibility of designing and configuring components in a family of devices will be limited, and it is believed that this will increase the cost of design and implementation associated with such devices. [Embodiment] Figure 1 illustrates the operation of a data stream 12 The search 10 shows an example of a system. The system 10 can include a pattern recognition processor 14 that searches the data stream 12 based on the search criteria 16. Each search criterion can specify one or more Standard expression (ie, pattern). The phrase "target expression" 14 Search data sequence of pattern-recognition processor means. Examples of target expressions include a sequence of spelling a character, a detailed description—genetic-genetic checkpoint sequence, formation-image division-image or video (4) __bit sequence, forming a program One of the parts may execute one bit sequence in the file or form one bit sequence in one of the audio files of one of the song or the mouth phrase. A search criterion can specify more than one target expression. For example, a material criterion can be used to specify all five-letter children beginning with the letter sequence "(1): any word beginning with the parent-child sequence "Cl" containing the word "cloud" and more. The number of possible groups of target expressions is arbitrarily large, for example, there may be as many target expressions as the data arrays that the data stream can present. The search criteria can be expressed in a variety of formats, including formal representations, concisely specifying a number of objects, and the main expressions of the target expressions without having to enumerate the expressions of each target. Therefore, each search criterion can be composed of one or more search terms. 145319.doc -4 - 201033896 Each of the search criteria can be included with one or more search terms and some target expressions can use a common search term. As used herein, the phrase "search term" refers to a sequence of data that is searched during a single seek cycle. The data sequence j may include a plurality of data bits in a binary format or other format (e.g., decimal, ASCII, etc.). The sequence can encode data by a single digit or multiple digits (❹'s number of binary digits). For example, the pattern recognition processor 14 can pair a text data one character at a time.

Stream 12 performs a search, and the search term can be a set of single characters, for example, a letter "mother" or "6", or a wildcard search term for a set of all single characters. A search term may be less than or greater than the rule m (or other glyphs - that is, the basic unit of information expressed by the data stream, for example, a note, a genetic base pair, a -1G carry bit, or a - sub-pixel) The number of yuan. For example, the search term can be 8 bits and a single character can be 16 bits. In this case, two consecutive search terms can specify a single character. The search criteria 16 can be formatted by the code 18 for use in the pattern recognition processor 14. Formatting can include deconstructing the search term from such search criteria. For example, if the g-stream represented by the f-stream 12 is larger than the search terms, the compiler can decompose the search criteria into a plurality of search terms to search for a single glyph. Similarly, if the glyphs represented by the data stream 12 are smaller than the search terms, the compiler 18 can provide unused bits for a single search term for each individual glyph. The compiler 18 may also format the search criteria 16 to support various rule representation operators that are not locally supported by the processor. The pattern recognition processor 14 can search the data stream 12 by evaluating each new item 145319.doc -5 - 201033896 from the data stream 12. Here, the wording "items" refers to the amount of data that can be matched - searched. During the -search cycle, pattern recognition processor 14 may determine whether the currently presented item matches the current search term in the search criteria. If the item matches the search item, the evaluation is "advanced" and, in other words, the next item is compared with the search item in the search order. If the ^ does not match 'the next item is compared with the first item of the search target f, thereby resetting the search. s Each search criterion can be compiled into one of the different finite state machines in the pattern recognition processor 14. The finite state machines can be run in parallel to search the data stream 12 in accordance with the search criteria 16. When the data is streamed. The finite state machine may step through each of the consecutive search terms in a search criterion when matching the previous search term, or the finite state machine may start searching for the search criteria if the search term is not matched A search item. Pattern recognition processor 丨4 may, for example, evaluate each new item based on a plurality of search criteria and their respective search terms at approximately the same time during a single device cycle, each of which may receive at approximately the same time From the item of data stream 12, and each of the parallel finite state machines can determine whether the item advances the parallel finite state machine to the next search term in its search criteria. The parallel finite state machines may evaluate terms based on a relatively large number of search criteria (e.g., more than 100, more than 1000, or more than 1 。). Because of their parallel operation, they can apply the search criteria to a data stream 12 having a relatively high frequency width (eg, greater than or substantially equal to 64 MB per second or 128 MB per second). Do not slow down the data stream. In some embodiments, the search loop duration is not scaled by the number of search criteria 145319.doc 201033896' so the number of search criteria may have little effect on the performance of the pattern recognition processor 14. While satisfying a search criterion (i.e., after advancing to and matching with the last search term), pattern recognition processor 14 may report the satisfaction of the criteria to a processing unit, such as a central processing unit (CPU) ) 20. The central processing unit 2 can control the system identification processor 丨4 and other parts. The system 10 can be any of the four systems or devices that search for the data stream. For example, system 10 can monitor one of the data streams 12, a laptop, a handheld or other type of computer. System 10 can also be a network node, such as a router, a server, or a user (e.g., in a computer of the type previously described). The system ^ can be a certain type of electronic device, for example, a copying machine, a scanning j, a printing machine, an axis (four), a television, an on-board video distribution or a 5 recording system, - Leh Human power slowdown, a mass media player, a factory automation system, FAW Fish® '脳 ... % dry system or a medical device. (The various methods used to describe the system, such as the many ', terms used in this article, can share some of the reference objects, ^ · ', and therefore should not Narrowly understood based on other items listed). The data stream 12 can be one of the users and other types of data turbulence that other entities can expect to search for. For example, the slanting electric cooling can be received via the network. 12 M / string ^ 丨 L, for example, a packet received via the Internet or "-hive road stream 12 can be self-healing Li Tong 1 〇, "Wei Zhi" or data. Information ... System 1 handle-sensor (for example, - imaging 145319.doc 201033896 detector, a temperature sensor, an accelerometer or the like or a combination thereof). The data stream 12 can be received by the system as a series of data streams, where the data is received in a meaningful order (e.g., in an apparent time, lexical or semantic order). Alternatively, data stream 12 can be received in parallel or out of order and then converted to a series of data streams, for example, by reordering packets received over the Internet. In some embodiments, data stream 12 can present items in a serial fashion, but the bits expressing each of the items can be received in parallel. The data stream 12 can be received from a source external to the system 10 or can be formed by interrogating a memory device and forming a data stream 12 from the stored data. Looking at the type of data in the data stream 12, a designer can select different types of search criteria. For example, the search criteria 16 can be a virus definition standard. The virus or other malware can be characterized and the pattern of malware can be used to form a search criterion indicating whether the data stream 12 is likely to be delivering malware. The resulting search criteria can be stored on the server, and a user's system's operator can subscribe to download the search criteria to one of the systems 10. When different types of malware appear, the search criteria 16 can be updated periodically by the server. These search criteria can also be used to specify undesired content that can be received by the network, such as unwanted emails (known as spam) or other content that the user dislikes. The data stream 12 can be made up of a material, ^, and a pair of data that the system 10 is receiving, and the U-s can be used for a text, an audio sequence, a phase, a phase, and a video sequence that appear in a copyrighted work. The data stream 12 is monitored. It can be monitored for comments related to a criminal investigation or a direct investigation of Tn 事#3 public or an employer. 145319.doc 201033896 Depends on data stream 12. The search criteria 16 may also include a pattern in the data stream 12, for example, in a memory addressable by the CPU 20 or the pattern recognition processor 14. For example, the search criteria 16 may each define an English sub-for which a corresponding Spanish word is stored in the memory. In another example, the search criteria 16 encodes an encoded version of the data stream 12 (e.g., MP3, MPEG 4, FLAC, Ogg Vorbis, etc.) for which a decoded version of the data stream 12 is available. Or vice versa. The pattern recognition processor 14 may be integrated with the CPU 2's hardware into a single component (e.g., a single device) or may be formed as a single component. For example, σ, the pattern recognition processor 丨4 can be a separate integrated circuit. The pattern recognition processor 14 may be referred to as an "r-coprocessor" or a "type identification cooperative processing". FIG. 2 illustrates an example of a pattern recognition processor 14. The pattern recognition processor #14 can include an identification module 22 and an aggregation module 24. The identification module 22 can be configured to compare the received item with the search term & line, and the recognition module and the aggregation module 24 can cooperate to determine whether matching one item with a search term satisfies a search criterion. . The identification module 22 can include a column of decoders 28 and a plurality of characteristic cells. Each feature cell 30 can define a search term, and the feature cell group can form a parallel finite state machine that forms a search criterion. The components of the feature cell can form a search term array 32, a detection array 34, and a boot routing matrix %. The search term array 32 can include a plurality of input conductors 37, each of which can cause each of the features 145319.doc • 9· 201033896 cells 30 to communicate with the column decoder. The column decoder 28 can be based on data electrical methods. + coffee - + The content of the Becca stream 12 selects a particular guide among the plurality of input bodies 37. For example, column decoder 28 may initiate one of the 256 columns to one of the 256 column decoders based on a value that can represent a byte received by one of the items. The byte item 0_ 〇_ may correspond to the plurality of input conductors 37, and the bits 1111 1111 may correspond to the bottom of the plurality of input conductors 37. Therefore, depending on which items are received from the data stream 12, different input guides can be selected (4). When a different item is received, the column solution (10) 28 can start the column corresponding to the rule item and start the column corresponding to the new item. The detection array 34 is slidably coupled to a detection bus 38 that outputs a signal indicating that the search criteria are fully or partially satisfied to the aggregate mode 24. The actuating routing material 36 can be selectively enabled and activated based on the number of search terms for which the search for the quasi-finance has been matched. The aggregation module 24 can include a &# &, 匕3 latched state matrix 40, an aggregate routing matrix 42, a threshold logic matrix 44, a "romatic logic product matrix 46, a logical sum matrix 48, and an initialization. Routing matrix 5〇. The latch matrix 4G can implement some search acquisition sections. Some search criteria (for example, some rule expressions) count only—the first occurrence of a match or a match group. Latch matrix 40 can include a latch that records whether a match has occurred. The latch can be cleared during initialization and periodically re-initialized during operation, either because it is determined or no longer meets the search criteria - that is, an earlier tomb is- 1 Items may need to be matched again before the search criteria can be met. 145319.doc -10- 201033896 Aggregate routing matrix 42 can operate similar to starting routing matrix 36. Aggregated routing matrix 42 may receive signals indicative of matching on detection bus 38 and may route the signals to different group logic lines 53 connected to threshold logic matrix 44. The aggregate routing matrix 42 may also route the output of the initialization routing matrix 50 to the detection array 34 to reset portions of the detection array 34 when it is determined that a search criterion is satisfied or may not be further satisfied.

The threshold logic matrix 44 may include a plurality of counters, for example, a 32-bit counter configured to count up or down. The threshold logic matrix 44 can be loaded with an initial count and can count up or down from the count based on the match sent by the recognition module. For example, the threshold logic matrix 44 can count the number of occurrences of a word in a certain length of text. The output of the threshold logic matrix 44 can be the input of the logical product matrix. The logical product matrix 46 can selectively produce a "product" result (e.g., an "AND" function in Boolean i〇glc). The logical product matrix a can be implemented as a - square matrix, the number of output products in Λ being equal to the number of input lines from the threshold logic matrix 44 or the logical product matrix 46 can have an input different from the number of outputs. The resulting product value can be output to the logical sum matrix 48. The logical summing material 48 can selectively generate sums (e.g., "OR" functions in the Boolean logic). The logical sum matrix 48 may also be a matrix of ones, or the logic = sum matrix 48 may have a different number of inputs than the number of rounds. Because of this: the logical product of the logical sum, the logic of the logical sum matrix 48 is rounded up: such as the logical sum (sop) form of the Boolean product. The logical sum matrix output can be received by the initialization routing matrix 50. The initialization routing moment (4) can be used to reset the detection array 145319.doc 201033896 34 and the portion of the aggregation module 24 via the aggregation routing matrix C. The initialization routing matrix 5 can also be implemented as a square matrix, or the initialization routing matrix 5 can have an input different from the number of outputs. The initialization routing matrix 50 may recognize the other portions of the processor 14 in response to the # from the logical sum matrix 48 and reinitialize the pattern 14 when, for example, a search criterion is satisfied or it is determined that the search criteria are not met. The aggregation module 24 can include an output buffer 51 that receives the output of the threshold logic " matrix, 44, aggregated matrix 42 and logical sum matrix 48. The output of the cluster module 24 can be passed from the output buffer 51 to the CPU 2_υ on the output bus 26. In some embodiments, the output multiplexer can ride the signals from the components 42, 44, and 48 and output a signal to the cpu 2 〇 (Fig. In an embodiment, the result from the pattern recognition processor 14 can be reported without transmitting the signals through the output multiplexer, which is not meant to imply or omit any other feature of I ==. For example, The signals may be transmitted to the CPU in parallel on the output bus 6 = the threshold logic matrix 44, the logical product matrix Μ, the logical sum matrix, or the initialization routing matrix 50. A = map: the search term array 32 (Fig. 2) One of the individual characteristic cells 3. It can be referred to as a component of the search term cell 54. Search for the cell 54 after: ! 56 and a plurality of memory cells 58. Among the memory cell conductors: each of the cells (4) of the turn-off conductor 56 and the plurality of input conductors 37 should be selected by the input conductor 37 to be selected by the memory output conductor 56. Body 37 may be referred to as a "word line". In some embodiments, the plurality of input conductors J and output conductor 56 may be referred to as a "data 145319.doc 201033896 line." Memory cell 58 can comprise any of a variety of types of memory cells. For example, memory cell 58 can be a volatile memory such as a dynamic random access memory (dram) cell having a transistor and a capacitor. The source and drain of the transistor can be respectively connected to one of the capacitor plates and the output conductor 56, and the gate of the transistor can be connected to one of the input conductors. In another example of volatile memory, each of the memory cells 58 may comprise a static random access memory (SRAM) cell. The sram cell can have an output that is selectively occluded to the output conductor 56 by an access transistor controlled by one of the input conductors 37. Memory cell 58 may also comprise non-volatile memory, such as phase change memory (eg, a two-way device), flash memory, germanium oxide-nitride-oxide (SONOS) memory, Magnetoresistive memory or other types of non-volatile memory. The memory cell 58 can also include a flip-flop (e.g., a memory cell made up of logic gates). • Figures 4 and 5 illustrate an example of a search term cell 54 in operation. Figure 4 illustrates an example in which the search term cell 54 receives a search term that does not match the cell, and Figure 5 illustrates a match. As illustrated in Figure 4, the search term cell 54 can be configured to search for one or more items by storing the data in the memory cell 58. The memory cell can represent one of the data streams 12 that can be presented. For example, in FIG. 3, each memory cell 58 represents a single letter or number, starting with the letter "&" and ending with the number "9". . The memory cell 58 representing the item satisfying the search term can be programmed to store a first value, and does not represent the item that satisfies the search term. 1453l.doc • 13- 201033896 The memory cell 58 can be programmed to be stored - different value. In the illustrated example, the search term cell 54 is configured to read the letter "b". Indicates that "b memory cell 58 can store -1 or logic high, and does not indicate "b: the age; cell 58 can be programmed to store a 〇 or logic low. ° '. For data stream 12 The item-and-search item is toned, and the column decoder 28 can optionally consume the input conductor 37 of the memory cell 58 representing the selected item. In Figure 4, the data stream 12 presents a lowercase. Stream 12 is presented in the form of an eight-bit coffee code, and column decoder 28 can interpret the byte as a column address, thereby outputting a ~ signal thereon by energizing conductor 60. In response to the 'memory cell 58 controlled by the conductor 6 可 can output a signal indicating the data stored in the memory cell 58 - the line signal can be sent by the output conductor % : in this case 'because the letter "e" is not searched One of the items of the cell (10), so it does not match the search term, and the search term cell outputs a value of ', indicating that no match was found. . In Figure 5, the data stream 12 presents a character "b". Similarly, column decoder 28 interprets this as a single address and column decoder selects conductor 62. In response, the memory cell 58 representing the letter "b" outputs its stored value 'in this case the value is a 1 ' indicating a match. The search term cell 54 can be configured to search for more than one item at a time. A plurality of memory cells 58 can be programmed to store a 1 to specify a search term that matches more than one item. For example, the memory cell 58 representing the lowercase "a" and the uppercase "A" can be programmed to store a 1, and the search term 54 can search for any one. In another example, the search term cell 54 can be configured to output - match in the event that any-child is received, 145319.doc • 14- 201033896. All memory cells can be programmed to store -1 such that the search term 54 can act as a wildcard entry in one of the search criteria. 6 through 8 illustrate the identification module 22 performing a search (e.g., searching for a word) based on a plurality of search criteria. In particular, Figure 6 illustrates that the recognition module 22 detects the first letter of a word, Figure 7 illustrates the detection of the second letter, and Figure 8 illustrates the home of the last letter. As illustrated in Figure 6, the recognition module 22 can be configured to search for the word big". Two batches of neighboring characteristic cells 63, 64 and 66 are graphically illustrated. The feature cell 63 is configured to detect the letter rb". The feature cell M is configured to detect the letter "i". The feature cell 66 is configured to detect both the letter "g" and the search criteria being satisfied. FIG. 6 also depicts additional details of the detection array 34. Detection array 34 can include one of characteristic cells 63, 64, and 66 to detect cells 68. Each of the detection cells 68 can include a memory cell 7 (such as one of the above memory cell φ types (eg, 'a flip-flop)) indicating the characteristic cell 63, 64 or 66 Is it active or inactive? The detection cell 68 can be configured to output a signal indicative of the detection cell 疋 系 activity to the activation routing matrix % and has received a signal indicating a match from its associated search term cell 54. Inactive features Cells 63, 64, and 66 can ignore matches. Each of the detection cells 68 can include an AND gate having inputs from the memory cell 70 and the output conductor 56. The output of the AND gate can be routed to either or both of the detection bus 38 and the routing matrix 36. The routing matrix 3 6 can be selectively activated by writing to the memory 145319.doc -15- 201033896 cell 70 in the detection array 34. The initiation routing matrix 36 can initiate the signature cells 63, 64 or 66 based on the search criteria and which search term is searched for in the data stream 12. In Figure 6, data stream 12 presents the letter "b". In response, each of the characteristic cells 63, 64, and 66 may output a signal indicative of a value stored in the memory cell 58 coupled to the conductor 62 (which represents the letter "b") on its output (4) 56. Then, the detecting cells 56 can each determine whether they have received the number of matching matches and whether they are active. Since the feature cell is configured to detect the letter "b" and is active (as indicated by its memory cell 7), φ therefore the detection cell 68 in the feature cell 63 can match the first search term indicating the search criteria. One of the signals is output to the startup routing matrix 36. As illustrated in Figure 7, after matching the first search term, the initiation routing matrix 36 can initiate the feature cell by writing an i to the memory cell 70 in the detection cell 68 of the next feature cell 64. In the case where the next item satisfies the first search term (e.g., if the item sequence "bbig" is received), the routing matrix 36 is activated to maintain the active state of the feature cell 63. During a portion of the time or substantially all of the time during which the data stream η is searched, the first search term of the search criteria may remain in an active state. In FIG. 7, data stream 12 presents the letter "丨" to the recognition module 22〇. In response, each of the feature cells 63, 64, and 66 can output an indication on its output conductor 56 to be stored in the connection. A signal from one of the values of the conductor 72 (which represents the letter "丨"). Then, the detecting brothers can each determine whether they have received a signal indicating that a match and whether they are active. Since the feature cell 64 is configured to detect the letter "丨" and is active (as indicated by its corpus 145319.doc -16- 201033896 cell 70), the detection cell 68 in the feature cell 64 can indicate that it has been matched. One of the search items under the search criteria is output to the start routing matrix 36. Next, the routing matrix 36 is enabled to activate the feature cell 66, as illustrated in Figure 8. Before evaluating the next item, the characteristic cell 64 can be deactivated, and the characteristic cell 64 can be activated by the detection cell 68 of the characteristic cell 64 to reset its memory cell 7 between detection cycles, or the routing matrix 36 can be activated. The feature cell 64 can be deactivated (for example).

In Figure 8, data stream 12 presents item "g" to column decoder 28, which selects conductor 74 representing item "g". In response, each of the characteristic cells 63, 64, and 66 can output a signal indicative of the value stored in the memory cell 58 coupled to the conductor 74 (which represents the letter "g") on its output conductor 56. The detection cells 68 can then each determine whether they have received a signal indicating a match and whether they are active. Since the characteristic cell 66 is configured to detect the letter "g" and is active (as indicated by its memory cell 7), the detection cell 68 in the feature cell 66 can indicate the last searcher that has matched its search criteria. One of the items is output to the start routing matrix %. The end of a search criterion or a portion of a search criterion can be identified by the initiation routing matrix 36 or the detection cell 68. Such components 36 or 68 may include memory indicating whether their characteristic cells 63, 64 or 66 specify a last search term for a search criterion or a component of a search criterion. For example, a search criterion may specify all sentences in which the word "cattle" appears twice, and the recognition module may output a signal indicating each occurrence of "cattle" in a sentence to the aggregation module, the aggregation. The module can count the occurrences to determine if 145319.doc •17· 201033896 meets the search criteria. The characteristic cells 63, 64 or 66 can be activated under a number of conditions. A characteristic cell 63, 64 or 66 may be "material activity", which means that it remains active throughout or substantially throughout the search. - Always active feature cell 63, material or heart instance is the first characteristic cell of the search criteria (e.g., characteristic cell 63). - The feature cell 63, 64 or 66 may be "active at request", which means that the feature cell 63, 64 or 66 matches a previous condition (eg, when matching a previous search term in a search criterion) ) is active. An example is a feature cell that is active when requested by the feature cell 63 of Figures 6-8 and a feature cell 66 that is active when requested by the feature cell 64. A feature cell 63, 64 or 66 may be "self-starting", which means that once it is activated, it initiates itself as long as its search term is matched. For example, a self-starting feature cell having one of the search terms matched by any numeric digit can remain active in the sequence "123456xy" until the letter "X" is reached. Each time a search term of the self-starting feature cell is matched, it can initiate the next feature cell in the search criteria. Therefore, an always active feature cell can be formed by a self-starting feature cell and a feature cell active at the time of request. The self-starting feature cell can be programmed together with all memory cells 58 storing one, and it can be in the parent cell. After the item is repeated, the feature cell that is active at the time of the request is started. In some embodiments, 'each characteristic cell 63, 64, and 66 may include in its detection cell 68 or in the initiation routing matrix 36 a memory cell that specifies whether the characteristic cell is always active, thereby A single characteristic cell forms an always active characteristic cell. FIG. 9 illustrates an example of an identification module 22 configured to search in parallel based on a first search criterion 75 and a second search criterion 76. In this example 145319.doc • 18- 201033896, the first search criterion 75 specifies the word "bigj and the second search criterion % rules the sub-cab". A signal indicating that one of the current entries from data stream 12 can be passed to the feature cells in each of search criteria 75 and 76 at substantially the same time. Each of the input conductors 37 spans both search criteria 75 and 76. As a result, in some embodiments, both search criteria 75 and 76 can generally evaluate the current term at the same time. It is believed that this accelerates the evaluation of search criteria. Other embodiments may include more feature cells configured to evaluate more search criteria in parallel. For example, some embodiments may include more than one, five, 1000, 5,000, or one 并行, characteristic cells operating in parallel. These traits can generally evaluate hundreds or thousands of search criteria simultaneously. Search criteria with a different number of search terms can be formed by assigning more or fewer signature cells to the search criteria. Simple search criteria can consume fewer resources in the form of eigencells than complex search criteria. It is believed that this reduction identifies the cost of processor 14 (Fig. 2) relative to processors having a large number of substantially identical cores (all configured to evaluate complex search criteria). Figures 10 through 12 illustrate both an example of a more complex search criterion and the features of the boot routing matrix 36. The initiation routing matrix 36 can include a plurality of initiating routing cells 78' whose groups can be associated with each of the characteristic cells 63, 64, 66, 80, 82, 84, and 86. For example, each of the eigencells can include 5, 10, 20, 50 or more priming routing cells 78. The boot routing cell 78 can be configured to transmit an enable signal to the next search term when one of the search criteria is matched to the previous search term. The boot routing cell 78 can be configured to route the enable signal to neighboring trait cells or other boot 145319.doc -19- 201033896 routing cells 78. The initiate route cell 78 can include memory indicating which feature cells correspond to the next search term in a search criterion. As illustrated in Figures 10-12, the recognition module 22 can be configured to search based on complex search criteria rather than criteria for specifying a single word. For example, the recognition module 22 can be configured to search for words beginning with a first code 88 and ending with one of the two end codes 90 or 92. The illustrated search criteria are those beginning with the letter sequence "c" and "1" and ending with the letter sequence "ap" or the alphabet sequence "oud". This is an example of one of a plurality of target expressions (eg, the word "clap" or the word r cl〇U(j"). 10 In Figure 10, the data stream 12 presents the letter "c" to The identification module 22' and the feature cell 63 are both active and detect a match. In response, the initiation routing matrix 36 can initiate the next feature cell 64. The initiation of the routing matrix 36 also maintains the active state of the feature cell 63. The feature cell 63 is the first search term in the search criteria.

In Figure 11, data stream 12 presents a letter "丨" and feature cell 64 identifies a match and is active. In response, the initiation routing matrix 36 can transmit a start nickname to both the first signature cell 66 of the first trailer code 9 and the first feature bank 82 of the second trailer code %. In other instances, more tail codes may be initiated, or multiple first codes may initiate one or more tail codes. Next, as illustrated in Figure 12, data stream 12 presents the letter "〇" to recognition module 22, and feature cell 82 of second tail code 92 detects a match and is active. In response, the initiation routing matrix 36 can initiate the characteristic cell 84 below the second tail code 92. When the feature cell 66 is allowed to become inactive, the search for the first tail code 9〇 can be stopped. The steps illustrated in Figures 1 to 12 can be continued by the letters "and "d"" or the search can continue until the next match of the first code 88 following 1453l9.do« -20- 201033896. In an embodiment c, such as the embodiment illustrated in Figure 13, the .1 identification processor 14 may be accessed by a controller or some other device or system computer system 94). Part of the pattern recognition device 93. For example, the Thunderbolt system 94 may include a processor such as a central processing unit (CPU) 2G that is accessed via a memory management unit (s) 96 - § Remembrance 95 . The memory % may include any suitable memory /, 匕 a but not limited to static random access memory (sraM), random access Z) 3⁄4 body (DRAM) or double data rate (10) r) memory generation (eg, DDR1) ,nr»r»i

DR2, DDR3 or DDR4). In addition, the MMU 96 can be provided in a separate hardware component of the system 94 (e.g., a north bridge of a motherboard chipset) or can be integrated into the CPU 20. System 94 can also include one or more storage media 103 that can store various data and application A commands that can be downloaded into memory 95 and that can be executed by cpU2. Such application instructions may include, but are not limited to, operating system routines, firmware, software drivers, and instructions adapted to configure the device (as discussed in more detail below). Moreover, the storage medium m can comprise any suitable device or article capable of storing such instructions, including a magnetic or solid state hard drive, a CD_ROM, a flash memory or some other optical, magnetic or solid state medium. Furthermore, the storage medium may comprise a single device that has all of the application instructions for providing the functionality described herein or may comprise a plurality of devices that collectively include the application instructions. Although device 93 is currently illustrated as being separate from computer system 94, some or all of the components of 145319.doc • 21 - 201033896 system 94 are explained and discussed herein, but it should be understood that device 93 and computer system (including but Not limited to the components of the map as illustrated in Figure 13) integrated into a single device. In some embodiments, the 'type identification processor 14 or the device 94 having the pattern identification processor may include a plurality of temporary storages (4) Accurately store information related to the type identification system described above. To facilitate self-storage (4) reading of data and writing data to the scratchpad 97, the temporary logic logic (10) manages access to the scratchpad 97. The scratchpad access logic 98 can be implemented in hardware or in any other suitable manner. In various embodiments, the scratchpad or register access logic 98 can be separated from, but can be accessed by, the _ portion or the (9) pattern recognition processor 14 of the pattern recognition processor 14. The plurality of temporary storages H 97 may include a temporary storage device that stores matching results, counts, configuration information, control information and status, debug information, and the like. Any desired information relating to the pattern recognition process described above can be found in the scratchpad 97. A large amount of data that can be stored in the temporary storage (4) can result in a number of registers. The MMU 96 can facilitate the direct storage of the CPU 20 for various memory locations (e.g., 'in memory 95 and scratchpad 97') using an address map 99 containing physical memory addresses that are directly accessible by CPU 20. take. However, the address mapping " can have a limited number of addresses that can be mapped to the physical memory location of system 94 and other devices (e.g., device 93). For example, in some embodiments, the system 94 can include a 32-bit address bus, 932>te J-w, and a different address mapped to the physical memory location in the address map 99. . In this embodiment, and assuming a fixed size address space, it can be mapped 145319.doc •22- 201033896

The number of addresses to the physical location in the memory 95 is inversely proportional to the number of addresses that can be mapped to the physical location outside the memory 95 (e.g., in the scratchpad 9?). For example, if each address is mapped to a one-bit tuple entity S, the 232 available addresses can be mapped to 4 GB of memory, and the CPU 20 is allowed to directly store 4 GB of memory. take. If a significant number of addresses in the address map 99 are allocated to the scratchpad 97, fewer addresses will be available for mapping to the 3 memory 95, which may reduce the memory 95 accessible by the CPU 20. The amount and resulting in reduced performance of system 94. In some embodiments, the address space of the system and address map 99 can be saved by the indirect addressing technique discussed below. In accordance with some embodiments of the present invention, most of the registers 97 may be indirectly accessed by the system 9 (and not included in the address space or address mapping of the system 94) and a particular subset of registers. 97 can be accessed directly by system % and from within the memory space of system 94. The two types of scratchpads can be respectively: "indirect scratchpad" and "direct register". That is, in order to save the memory system (example % 'system 94), the memory address is empty, and a large number of registers are logically and/or physically positioned so that they cannot be directly processed by the processing unit: The memory can have any desired size, for example, an 8-bit temporary ", a 16-bit scratchpad, a 32-bit scratchpad, a 36-bit scratchpad, a 64-bit scratchpad, etc. In the two embodiments, the device 93 includes a separate address map 101 for facilitating access to the physical address of the register 97, and to the interposer in the address map 99 of the system 94. As discussed below, direct staging allows access to the indirect scratchpad J45319.doc -23· 201033896 and can be used to aggregate access to the direct scratchpad through easy access. All requests to the scratchpad. The direct register allows for quick access by system 94 (e.g., CPU 20), but limits the direct register to a subset of temporary scams 97 for use in the system 94 for the scratchpad 97 The amount of memory address space. The indirect addressing technique disclosed herein can be distinguished from a type in some embodiments. The processor is used in combination, and in other embodiments that do not include the type identification processor, the indirect addressing may also be used. Figure 14 illustrates a pattern recognition processor 14 or device 93 according to an embodiment of the invention. One of the direct and indirect registers. System 〇〇 contains a direct register group (or group) 1〇2 (also known as a “basic register group”) and an indirect temporary storage. Group (or group) 104 〇 basic register group 1 〇 2 may contain any number of "critical" registers, that is, system 94 (or some other controller, system or device) may directly Accessibility is the most desirable of their registers. In the embodiment illustrated in Figure 14, the basic register set 102 includes six registers, but in other embodiments any number of registers can be used in the basic register set 1-2. In addition, it should be understood that the selection of the "critical" register used in the basic register set 1 can be configured based on the pattern identification processor and the system. Therefore, in other embodiments, some of the scratchpad banks 1〇2 of FIG. 14 may be omitted, and other registers may be included in the basic scratchpad group 1〇2. In the illustrated embodiment, the basic register set 1〇2 includes the following registers: a critical state register 106; a critical control register. - a stimulus byte input register 110'. An indirect library select register ιΐ2: - an indirect address select register m; and an indirect data input/output buffer 145319.doc -24· 201033896. In one embodiment, each of the scratchpad sets 102 can be a 32-bit scratchpad and can be accessed via a 32-bit address bus. In addition, the scratchpad in the scratchpad bank 102 can be a read/write scratchpad, allowing both read and write. As further explained below, the indirect bank select register 112, the indirect address select register ι4, and the indirect data input/output register 116 help access the indirect registers 1〇4. These three registers 112, 114 and 116 can be collectively referred to as "indirect addressed access registers".

Critical state register 106, critical control register 1 〇 8 and stimulation byte

Input register 110 provides access to power month b and information that can be quickly accessed by system 94 or some other controller, thereby preventing access delays associated with providing such functions and information via indirect register 104. . The critical control register 108 provides a critical control bit during the pattern matching operation when the processing speed is critical. For example, such bits can include stop/run, reset, DMA start/stop, mode selection, and the like. Any other critical control bits can be used in the critical control register 108. The critical state register 1G6 provides critical state information during pattern matching for f. The status information bits stored in the temporary memory 1()6 can be "sticky" bits (updated only when explicitly requested), can be "automatically updated", or can be never updated. Examples of status bits stored in the scratchpad (10) may include byte order mode status, match status, match guess, and the like.

The byte sort selection, DMA mode, DMA stimulus byte input register 11 provides the data stream search: data storage. The storage of this data in the stimulus byte input temporary storage nn I45319.doc -25- 201033896 allows the parallel function to occur, thereby accelerating the work of the pattern recognition processor 14. For example, the data from data stream 12 can be processed at the same time as the indirect "match result" library register. The indirect register bank 104 can include any number of scratchpad banks 118 including one or more registers i 2 . Various types of indirect scratchpad groups are set forth below. However, it should be understood that the groups set forth are merely illustrative and may include any other register, register group, and/or register bank. The indirect scratchpad set 104 can include a flow save and restore group 122, a match result and debug group 124, a power up configuration group 126, and a type configuration group @128. The flow save and restore group 122 can include status indicators and counter values, such as a threshold counter, a processed byte counter, and the like. The match result and debug group 124 can include the group logic output, the identification array output, and any other results and outputs. The power-on configuration group 126 includes a register that identifies and configures the pattern recognition processor 14 (e.g., device capability library 15 (Fig. 16), manufacturer identification code, system parameters, etc.). Finally, the pattern configuration group 128 contains functions and information for use with the pattern recognition process, such as identifying array status, aggregation functions, and the like.间接 Indirect library selection register! 12 Select the bank 118 to be accessed in the indirect scratchpad group 1〇4. Each of the various banks 118 can be selected by a particular address value, as indicated by a bank selection bus line 丨19. In one embodiment, the indirect bank select register 112 can be a 32-bit scratchpad. The indirect address select-select register m in turn sets the particular register 12() to be accessed within the bank of the register selected by the indirect bank register select 112, such as the scratchpad address bus 121. The indicated values are in the per-repository, and the registers start with the -zero address 145319.doc • 26 · 201033896 p幵'. The indirect data input/output register 116 provides write or read functionality to the indirect scratchpad group as indicated by the scratchpad data input/output bus 123. Write to the indirect data input/output register ι6 to write the data to the register specified by the indirect bank select register 112 and the indirect address select register 114 from the indirect (four) input/ The output register 116 reads and reads the register at the address specified by the combination of the indirect bank select register 112 and the indirect address select register 114. By using the indirect bank select register 112, the indirect address select register 14 and the indirect data input/output register 116, the data can be written to the indirect register 104 or from the indirect temporary The memory ι〇4 reads the data. Although certain examples of the various features of the processor 14 and the device 93 are provided above, it is contemplated that the particular capabilities and characteristics of such processors and devices or other non-patterned devices may vary from embodiment to embodiment. In some embodiments 'a family of devices may share a set of substantially similar functionality (eg, 'type identification functionality'' but each device in the family may include a different number of components to provide such functionality . For example, in addition to the other examples provided below, one of the devices in a family may contain approximately 100,000 characteristic cells 30 (Fig. 2), while the other two devices in the family may contain approximately 500,000 characteristic cells, respectively. And 1, 〇〇〇, 特征 a characteristic cell. As can be appreciated, the desired operation of a particular device will generally depend on the proper configuration of the device. Moreover, in a type identification embodiment, the accuracy of the pattern recognition device 93 will be properly configured and controlled depending on one of the characteristic cells 3 other than the other components. Thus, according to one embodiment, one of the methods 130 of the configuration 145319.doc • 27-201033896 93 is generally illustrated in FIG. Although the various steps of method i3 are discussed in more detail below, method 130 generally includes the step 132 of accessing data from a memory location (eg, from one or more registers in scratchpad 97), And in a step 134, the capabilities of the device 93 are determined based on the accessed data. The method 13A also generally includes a step 136 of configuring the device based on the device capabilities determined in step 134. As indicated by decision block 138, steps 132, 134, and 136 may be repeated for any additional devices to be configured prior to termination at end block 14〇. By way of example, in one embodiment, the method 130 can be used to index (e.g., map) the bit locations of at least some of the registers in the scratchpad 97 to a particular circuit of the pattern recognition processor 14. The register of one embodiment can generally be divided into two types of scratchpad banks: a disparity register library 146 and a formula register library 148. The disparity register library 146 typically contains one or more A scratchpad library (eg, a device capability library 150), wherein the scratchpads in each of the libraries are significantly different from other scratchpads in the library. Note that device capabilities One or more registers in library 150 are typically encoded with a value indicative of the capabilities of device 93 and may include a read-only register. For such disparity register library 146, device functionality to temporary storage The mapping of the device can be done through a table, such as the following table: Table 1: Mapping an instance of a disparate library

Register Name Register Description of the function and/or content of the indirect address Reg 1 Reg 1 OxOOOOOOOOh Description of the function and / or content of Reg_2 Reg 2 0x0000000lh .-- -- Λν ππ ArvnnrvNTU Reg_N | Reg_Ni function and / Or inner color - UXvUvvFVlwvflNO 145319.doc -28- 201033896 Each of the disparity register libraries 146 may contain a unique description, and the indirect register address may be - not eight associated. 'The mode is directly related to this unique description ^ 'Different from the disparity register library 146' formula temporary storage n library 148 can have a temporary storage device with the same definition as other scratchpads in the library. Save 1" library. For example, it is used to configure the pattern recognition processor 14 to search for the register of the Gothic type (for example, the pattern configuration group 128), or to temporarily save and restore the operation data with φ. The registers (eg, the register group 122) may be only in the scratchpad (and its bits) to one or more logical cells (eg, the signature cell 30, the search term cell 54, the fingerprint test, the boot route cell) 78. Logical cells of other arrays or other components are mapped differently from each other. In some embodiments, some or all of the formula register banks 148 may be associated with the various logical cell arrays described above with respect to Figures 2-12. Such logical cells may include, but are not limited to, a search term array 32M, a start routing matrix 36, an aggregate routing matrix 42, a threshold logical matrix, a logical product matrix 46, a logical sum matrix 48, and an initialization route. The logical cell of matrix 50. The various logic cells of device 93 (e.g., the pattern recognition processor from their logic cells) can receive unique control or configuration signals, respectively, to facilitate device functionality, and such signals can be stored in scratchpad 97. For example, some of the scratchpad bits in the scratchpad library can be used to set the characteristic cell 63 (Fig. 6) to bias the letter "b". The other scratchpad bits of the bank can set the characteristic cell 64. To detect the letter %, and other scratchpad bits in the library can set the feature cell 66 to detect the letter "§". Similarly, other scratchpad bits in the scratchpad library can control the forward-routed and backward routing signals through the logical-cell array 145319.doc -29- 201033896, for example, starting the routing matrix % (Figure 10). In at least one embodiment, the method 130 can be used to index some or all of the formula register library 148 to the logic cell or other component of the pattern recognition processor 14 such that it will be stored in the formula register library 148. The control signals in the registers are routed to the appropriate logical cells or components to configure the device %. - The number of scratchpads in a given bank can be dictated by the width of each register and the number of rows and columns of logical cells to be configured in the array. For example, in the implementation, the boot routing matrix 36 may include 512 rows and 8 columns of boot routing cells 78, for a total of 4, 〇 96 boot routing cells μ. Each of the start-up routing cells 78 can be controlled by one or more control signals unique to the start-up routing cell, for example, a set of three control signals CTL-1, CTL-2, and CTL-3. In this example, the control signals can be stored in an individual register bank: If each of the three control signal register banks t contains a location register and requires a register bit to store a specific control channel, each control signal, each control signal register bank The number of bits will be equal to the number of boot routing cells 78, and the number of registers in each bank will be equal to the total number of cells 78 divided by the width of the scratchpad. Therefore, in this real money, some of the registers in the scratchpad 97 can be organized into a 128 temporary register. a hole] scratchpad library containing all of the five (5) control signal bits for starting the routing matrix 78; - 128 registers of the scratchpads of the scratchpad, which contain all of the routing matrix 78 CTL-2 control signal bit; request CTL-3 temporary transfer of the scratchpad, which similarly contains all the gua 3 control signal bits used to start the routing matrix 78, although this is for clarity 145319.doc -30- 201033896 OBJECTS Some examples have been provided, but it should be noted that a device may have numerous other logical cells or components that are controlled according to control signals stored in the registers of the device. As noted above, different devices 93 may have different characteristics, capabilities, or different numbers of components for providing such capabilities. The pattern recognition processor 14 associated with the pattern recognition embodiment can include a number of differences in addition to the total number of characteristic cells 30. For example, as generally depicted in FIG. 17, the circuitry of the pattern recognition processor 14 can be divided into one or more logic blocks 154, each having the same as described above with respect to Figures 2 through 12. One of the identification modules 22 and an aggregation module 24 is discussed. Moreover, such pattern recognition processors may differ in the number of logical blocks they contain and the characteristics of each of the logical blocks. A non-limiting example of such differences may be the number of feature cells 30 per block (e.g., graphics, forward and reverse start per block, and/or routing lines)

❿ or the number of threshold counters per block.

145319.doc device driver or other software to come • 31 - 201033896 access. In one example of a type identification device 93, a device capability library 150 can include the following registers: Table 2: Device Capability Register Summary Register Name Register Description Indirect Address Block Device Number of logical blocks OxOOOOOOOOh FC# Number of characteristic cells per block 0x00000001h FP# Number of forward start/route lines per block 0x00000002h RP# Number of reverse start/route lines per block 0x00000003h GLL# Group logic Number of lines 0x00000004h CTR# Number of thresholds per block 0x00000005h Bits# Number of bits per threshold counter 0x00000006h P# Number of logical products per block 0x00000007h SP# Number of logical sums per block product 0x00000008h RSV # Number of reinitialization lines per block 0x00000009h Number of bits in P# bit processed byte group OxOOOOOOOAh Number of bits in M# bit matching counter OxOOOOOOOBh FIFO# Matching library FIFO register depth OxOOOOOOOCh Of course, it will be appreciated that the device capability library 150 may contain less than all of the registers indicated in the above table, or in addition to the above Outside of their registers or register their place of the above indicated, may contain other register. Based on this information, a configuration system (e.g., system 94 of FIG. 13) can determine the characteristics and capabilities of device 93 in step 134 and then configure device 93 in step 136. As will be appreciated, this determination and configuration can be performed by system 94 in accordance with various software or firmware stored within device 94 and executed by CPU 20. In one embodiment, the step 136 of the configuration device 93 can be performed automatically via the method 160 generally illustrated in FIG. In particular, in the embodiment of 145319.doc-32-201033896, various configuration equations may be provided in a step 162. For example, such configuration equations can be stored in storage medium 1〇3 of system 94. These configuration equations may include various parameters typically associated with the characteristics of one of the devices 93 to be configured. For example, in one embodiment, these parameters may include the following parameters: Table 3: Device Capability Parameter Definition Scratchpad Name Description Parameter_Name - NI Di index name, and value equation η ~ιαχ=(Ν-1 ) _0<=»<=(Ν-1) ι 4αχ=(Ι-1) 〇<=ί<=(ι_ι) Number of logical blocks in the block device FC# Number of characteristic cells per block FP # Number of forward start/route lines per block Jr _____ .Jr Jfnax=(Jrl) ο<=/«Λη RP# Number of reverse start/route lines per block Jr ---- \ J /___ J 'r j.rmax=(Jr-l) 0<=!/r<=(Jr-l) GLL# Number of logical lines per block group Μ m »W=(M-1) 0<=w< =(Ml) CTR# The number of threshold counters per block C c Cmax—(Cl) 0<=c<=(Cl) Bits# The number of threshold bits per threshold B b ^max=(Bl) 0<=Z)<=(B-1)P# Number of logical products per block P Pmax=(Pl) 〇<=/?<=(Pl) SP# Number of logical sums per block product SP Spma^iSY-l) 0<=i/K=(SP-l) RSV# Number of reinitialization lines per block RSV rsv ^vmax=(RSV-l) 0<=riv<=(RSV-1) 145319 .doc • 33- 20 1033896 Table 4: Fixed parameters Parameter name Parameter Description Index range and value equation sb 8-bit imaginary byte 8-to-256 solution; 0<=^<=255(00h to FFh) INT register bit width all The scratchpad is 32 (20h) T1 threshold logic line (always equal to the number of GLL, Μ) τι 77 leg = (Μ-1) 0<=27<=(Μ-1) These are provided in step 162 The configuration equations can be adapted to configure the device 93 based on the particular capabilities of the device 93. In one embodiment having the parameters set forth above in Tables 3 and 4, the configuration equations provided in step 162 may include the calculations provided in the following table for calculation to be included in the formula register library 148. These configuration equations for the number of registers in the various scratchpad banks. Table 5: Equations for the total number of scratchpads per formula library

Library name complete "descriptive" library name is used to calculate the number of scratchpads in the library. Equation type identification group RES_MEM Potential response memory type library N*RC*256 INI-ST Identification array initial state library N*RC ~~ AF starts N*RC*Jf SF on the previous route line. Sends the output N*RC*Jf on the previous route line. PF continues to forward the previous route line N*RC*Jf ~~~ AR starts on the reverse route line. N*RC*Jr ~~ ~~— SR sends the output N*RC*Jr on this reverse routing line~—· PR continues to pass this reverse routing line N*RC*Jr — LnL recognizes that the array output is latched or Non-latching version N*RC*M ~~~ 145319.doc -34- 201033896 Library name Complete "Descriptive" library name Equation type identification group for calculating the number of scratchpads in the library 启用 Enable identification array Output Aggregation N*RC*M CRB Reinitialize N*RC*M TLMC on this RSV signal Initial count value N*C for each threshold CTR [per counter bit <=INT] SelLPM Select this T1 line to include In the logical product term N*P [77 lines <=INT] DnDLPM selects the T1 or NOT-T1 line to be included in the logical product N*P in the item [77 line <=INT] SelLSM Select the P line to be included in the logical sum of the product N*SP [P line <=INT] DnDLSM Select P or NOTJP to be included in the logical sum of the product N *SP [P line <+INT] RiRM is reinitialized on this SP item (output RSv signal) N*RSV [SP line <=INT] Flow save and recovery group ACT_ST Current active state library N*RC LATCH Latch matrix state N*RC TH_VAL Threshold counter value N*C [per counter bit <=INT] _ a match result and debug group MATCH match result bank N*13 GLL_OUT group logic line output N* 1 [M<=INT] REC—OUT Identification Array Output N*RC CUR_MM Current Matching Matrix N*4 For the above equation, the factor Rc can refer to the number of scratchpad rows and is included in a specific scratchpad library. The number of registers can be dependent on a logical region 145319.doc • 35· 201033896 The number of considerations does not depend on the number of signature cells in the temporary block and in a single scratchpad median. The generalized equation of RC (which allows the number of bits (INT) in the number of registers of the characteristic cell (j) can be provided by:

(I+INT-1)/INT=RC This generalized equation allows all data bits for a particular scratchpad library to be "packed" into a minimum number of registers. However, in some implementations: I can be limited to an integer multiple of INT, and RC can be defined as follows:

(I/INT)=RC In addition, it should be noted that each of the scratchpad banks of Table 5 may include all of the registers associated with the function of each of the above-described devices, one of which has a contiguous address space. Cross the block boundary. For example, all of the input buffers of the plurality of logical blocks used in the pattern recognition processor may be included in the AF scratchpad library. As with #', it will be apparent from the above equation that the various register banks can have the same or a different number of registers compared to each other. In step 164, the configuration system or device (e.g., system 94) can define values for various device parameters based on the scratchpad data accessed from device capability library 150, including but not limited to those parameters discussed above. The device 然后 can then be configured in a step 166 using the configuration equations. By way of example, in one embodiment, the equations may facilitate mapping of bits of the formula register bank 148 to particular portions of the pattern recognition circuit discussed herein. In this embodiment, the configuration equations provided in step 162 may further include equations for indexing (e.g., mapping) each bit in the formula register library ι48. 145319.doc -36- 201033896

Table 6: Example library index for indexing to the scratchpad library. The index parameter is used to index the equation to a specific point RES_MEM n, I, sh (constant INT) bit = 〇 · INT模) Library register = 1: (^^(^256)+((//11^1^256)+(^)] INT_ST n, i (constant INT) bit = 〇 · modulo INT ) Library register = [〇?*RC)+(//lNT)] AF, SF, and PR N, I, jf (constant I, Jf, and INT) Bit = (modeling of tree INT) Library Register = [(« * RC * Jf) + 汾 / INT) * AR, SR, and PR h jr (constant I, jr, and INT) Bit = 〇 · modulo INT) Library register =[(«*RC* JJK/J ENA, CRB, and LnL n, i, m (constant I and INT) bit = (ί modulo INT) Library register = [(«*RC*M&gt ;K〇yiNTf M)+(w)] TLMC n, b, c (constant C and INT) Bit = 求 modulo INT) Library register =[(«*C)+c] SelLPM and DnDLPM n, Tl, p (constant M, P, and INT) Bit = (77 for INT modulo) Library register = [(«*((M+INT-iyiNT)*P)+ ((77/ INT)*P)+(p)] SelLSM and DnDLSM n, p, sp (constant P, SP, INT) Bit = 求 modulo INT) Library register = [〇2*((P+INT -iyiNT)*SP;)+ ((p/INT)*SP)+(4)] RiRM n, sp, rsv (constant SPA INT) Bit=0/7 modulo INT) Library register =[(«*(SP+INT-1) )/INT)*RSV)+ ((5p/INT)*RSV)+(m;)] REC_OUT n, i (constant INT) Bit = 求 modulo INT) Library register = [(„* rC)+〇tint)] GLL-OUT n, m (constant INT) Bit = 〇« modulo INT) Library register =[(a〇+((w/INT)J 145319.doc -37 - 201033896 The library name index parameter is used to index the equation to a specific point ACT_ST n, i (constant ΙΝΤ) bit = 求 求 )) library register = [(#RC) + (i / INT)] LATCH η, i (constant ΙΝΤ) bit = (tree modulo) library register =[(«*RC)+(i/INT)] TH_VAL η, b, c (constant C and ΙΝΤ) bits = (6 pairs of modulo modulo) Library register = [(n * C) + c] As will be appreciated from the discussion of certain embodiment examples above, system 94 can read device 93 from device 93 itself. The ability, and then configures the device 93 based on its own unique capabilities. In an additional embodiment, system 94 can be configured with any or all of the devices family 168 having different characteristics or capabilities. For example, system 94 can be configured with devices 170 and 172 having, for example, 500,000 and 1,000,000 feature cells, in addition to being configurable to have 100, one feature cell device 93. System 94 can access the capabilities of each of the family 168 and configure the device based on its own unique capabilities. Since the configuration of each device is adaptable based on the capabilities of the device, system 94 enables flexible and adaptive configuration of each of device families 168 without the need to modify system 94 for communicating with such devices. Software or drive. Moreover, the present technology facilitates experimentation and subsequent development of other devices in the family 168 as compared to a rigid configuration system in which the scratchpad for various functions is forced to be at a predetermined address, without modifying the configuration. software. Finally, it should be noted that in at least one embodiment, any one or more of the techniques disclosed herein may be used in conjunction with one or more of the techniques described in the following copending patents: 2008 10 Application dated 18th and named "System and Method of Indirect 145319.doc -38- 201033896

Registered Access No. 12/253,966, co-pending U.S. Patent Application and October 18, 2008, filed with the name "Indirect

Access Method and System, No. 12/253,967, unpublished US patent application. The present invention has been shown by way of example in the drawings, and </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; , equivalent content and alternatives. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a system for searching for a data stream; FIG. 2 illustrates an example of a pattern recognition processor in the system of FIG. 2; FIG. 3 illustrates the pattern of FIG. Identifying one of the instances of the search cell in the processor; • Figures 4 and 5 depict the search term cell of Figure 3 for a single character search data stream; Figures 6-8 illustrate several search terms One of the cell identification modules searches for a data stream for a word; FIG. 9 illustrates an identification module configured to search for data streams in parallel for two words; FIGS. An identification module for searching for one of a plurality of words of the same first code; FIG. 13 illustrates a type identification device according to an embodiment of the present invention, which includes 145319.doc-39-201033896 including the type of FIG. A sample identification processor and a set of registers associated with a processor-based system; Figure 14 illustrates one system of direct and indirect registers having the pattern recognition device of Figure 13 in accordance with one embodiment; A device is configured in accordance with an embodiment of the invention (eg, Figure 13 Flowchart of one of the methods of the type identification device; FIG. 16 illustrates the inclusion of the disparity register library and the formula register library in the register of the device of FIG. 13 according to an embodiment; FIG. One embodiment illustrates additional details of the type identification processor of FIG. 2; FIG. 18 illustrates an example of a method of configuring the apparatus of FIG. 13 in an adaptive manner using parametric equations; and FIG. 19 is in accordance with an embodiment. The ability of system 94 to configure one or more different devices in a family of devices is generally illustrated. [Main component symbol description] 10 System 12 Data stream 14 Pattern recognition processor 16 Search criteria 18 Compiler 20 Central processing unit 22 Identification module 24 Aggregation module 26 Output bus 145319.doc 201033896 ❹ 28 column decoder 30 Feature cell 32 search term array 34 detection array 36 start routing matrix 37 input conductor 38 primary bus 40 latch matrix 42 aggregate routing matrix 44 threshold logic matrix 46 logical product matrix 48 logical sum matrix 50 initialization routing matrix 51 output Buffer 53 Group logic line 54 Search term cell 56 Output conductor 58 Memory cell 60 Conductor 62 Conductor 63 Characteristic cell 64 Characteristic cell 66 Characteristic cell 68 Detection cell 145319.doc -41 201033896 70 Memory cell 72 Conductor 74 Conductor 75 First Search Criteria 76 Second Search Criteria 78 Start Routing Cell 80 Feature Cell 82 Feature Cell 84 Feature Cell 86 Feature Cell 88 First Code 90 Tail Code 92 Tail Code 93 Pattern Recognition Device 94 System 95 Memory 96 Memory Management Unit 97 Scratchpad 98 Scratchpad Access Logic 99 Address Map 10 0 System 101 Single Address Map 102 Direct Register Group (or Group) 103 Storage Media 145319.doc -42- 201033896 104 Indirect Scratchpad Group (or Group) 106 Critical State Register 108 Critical Control Staging 110 stimulus byte input register 112 indirect bank selection register 114 indirect address selection register 116 indirect data input/output register node 118 register bank 120 register 121 register address Bus 122 Flow Save and Restore Group 123 Register Data Input/Output Bus 124 Match Result and Debug Group 126 Power-on Configuration Group 128 Model Configuration Group Reference 146 Disparity Register Library 148 Formula Staging Library 150 Device Capability Library * 154 Logic Block - 168 Device Family 170 Device 172 Device 145319.doc -43-

Claims (1)

201033896 VII. Patent Application Scope 1 · A system includes: a device comprising a plurality of memory locations - the plurality of memory locations comprising a set of memory locations encoded by the capability data; wherein the system The device is configured to access the device from the set of memory locations and configure the device based on the device capability data. 2. The system of claim 1, wherein the device is a device in a family of devices - the device family includes an additional device having a different capability than the one device and wherein the system is configured to be self- The additional device capability data for one or more memory location accesses of the additional device automatically configures the additional device. 3. The system of claim 1, comprising a processor, wherein the system is configured to enable the processor to access the device capability data from the set of memory locations. 4. The system of claim 3, comprising storing the call media in one of executable instruction codes, the executable instructions configured to perform the following operations when executed by the processor: accessing the set of memory locations Device capability data; and - automatically configuring the device based on the device capability data and an equation encoded in the storage medium. 5. The system of claim 4, wherein the executable instructions include a fingerprint configured to define a parameter value of the equation based on the accessed device capability data. For example, a system of &quot;monthly item 3, wherein The device contains at least one of the processor or a storage 145319.doc 201033896 media. 7. 8. 9. 10. 11. 12. 13. 14. 15. The system of claim 1, wherein the plurality of memory locations comprises a set of additional memory locations. For example, the system of claim 7 wherein the set of additional memory locations includes a set of registers, and the system is configured to logically organize the set of registers into a plurality of scratchpad banks based on the device capability data . Such as. The system of claim 8, wherein at least two of the plurality of scratchpad banks of the plurality of scratchpad banks have different numbers of scratchpads. The system of claim 1, wherein the device comprises a plurality of logical blocks, and the set of memory devices encoded in the device capability data includes device capabilities to represent one of the plurality of logical blocks. At least one memory location of the data. The system of claim 1 wherein the set of memory locations comprises a read only memory location encoded by the device capability. For example, the system of claim 1, wherein the device is a type identification device. The system of month length item 1 wherein the system is configured to automatically configure the device based on the device capability data. The system of claim 1 wherein the system is configured to configure the device with only capability data. In the method of the garment, the method comprises: taking the storage of one or more registers stored in a plurality of registers: the department and the accessed data containing the capability of the representation-device; &gt; The device is automatically configured based on the accessed capability data. 145319.doc 201033896 16. The method of claim 15 wherein accessing data stored in one or more registers in the plurality of registers comprises accessing one or more registers stored in the device Information in the middle. The method of claim 15, wherein the accessing is stored in a plurality of registers, and the data in the plurality of registers includes access to the capability data indicating the force of the type identification device. 18. The method of claim 17, wherein the access capability data comprises accessing data indicative of the number of logical blocks of the pattern recognition device. 19. The method of claim 17, wherein the access capability data comprises accessing data indicative of the number of characteristic cells per logical block of the pattern recognition device. 20. The method of claim 17, wherein the access capability data comprises accessing at least one of a number of start lines or a number of reverse start lines per logical block before each logical block representing the pattern recognition device data. 21. The method of claim 15, wherein automatically configuring the device comprises automatically indexing the plurality of registers to the device indirect register address. 22. The method of claim 21, wherein automatically mapping the plurality of registers to the indirect register address comprises: defining a parameter of the at least one equation based on the accessed capability data; and based on the at least one equation One of the plurality of registers is indexed to an indirect register address. 23. The method of claim 15, wherein automatically configuring the apparatus comprises automatically calculating a number of device registers to be included in an indirect scratchpad bank. 24. A device comprising: 145319.doc 201033896 A computer readable storage medium having executable instructions encoded thereon, the executable instructions comprising: instructions for accessing data from a register of a device An instruction to determine the capabilities of the device based on the accessed data; and θ to configure an instruction for the device based on the determined capabilities. 25. The method of claim 24, wherein the instruction to configure the device with τ % includes a means for mapping a plurality of device registers to the logical register library. The device of claim 24, wherein the instructions for arranging the device, such as 蟑笙田, 兵〒肩, etc., are included for determining a parameter based on the energy 旯 雉疋 雉疋 雉疋 配置 配置 配置 配置 配置 配置 配置 配置 配置 配置 配置 配置 配置 配置 配置And an instruction to configure the device based on the configuration equation. 27. At least one of the optional memory devices of claim 24. The computer readable storage medium comprises a magnetic-optical memory device or a solid-state memory device. 28. The device of claim 24 at least co-stores the media. The computer readable storage medium includes a plurality of computer readable storages of the above executable instructions, a method comprising: a material; and a device-storage output capable of indicating the capability of the device, the receiving basis The one or more configuration formulas of the rounded capacity body, the body stores the mapping of the bit to the logical cell of the device. &lt;plurality of registers 145319.doc 201033896 30. If the party of claim 29, the land ^ ^ , goes, it includes updating the address of the device with the mapping of the bits received by the class Mapping. 31. The method of claim 30, wherein updating the address map of the shouting device comprises updating an address map stored in the device. 145319.doc