TW201030947A - Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device - Google Patents

Abstract

A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large when compared to a physical size of the storage MOS transistor to establish a large coupling ratio between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.

Description

201030947 Sixth, invention description: [Technical field of invention] _] Shuming involves a kind of non-volatile _ circuit memory device, especially related to - single-layer polycrystalline floating gate electronic erasable programmable read-only memory ( EEPR0M) and fast fA] electronically erasable programmable read-only memory (FLASH MEMORY) 〇 [prior art] [0002] [0003] In the semiconductor industry, in general, there are two important categories of "(10) memory: "Volatile" and "non-volatile"."Volatile" memory means that the stored chapters are not preserved when the low-voltage power source is removed or turned off. The memory bank includes static information stored in ¥ (^^. Dynamic Random Access (DRAM) Memory Remembrance · '>, \ '% I:- "Non-Playing" Memory (NVM) will not be stored Destruction, usually after the power supply voltage is cut off, can also save twenty Feng. Now there are many different kinds of NVM gram scales suitable for the corresponding. For example, the most common sf ifelleCTurii ❹ draw flash notes, it has about inch 0.5T, that is, 4 and 2 "2 is the minimum area of the specific complement I#, NAND Flash memory is used to store a large amount of audio and video data. In 2008, with 45nm process technology, NAND memory has an effective density of up to 16 Gb. [0004] The second largest class of NVM is a NOR flash memory whose memory cell is a single transistor 'NOR flash memory' having an area of about 10 λ 2 for storing program code. The maximum effective memory density of NOR flash memory on the market today is 2 Gb, which was made in 2007 using 70 nm process technology. The third type of NVM is a double crystal floating gate tunnel oxidation (FLOTOX) EEPR0M, which is 099103898 Form No. A0101 Page 4 of 106 0992007313-0 201030947 [0005]

[0006]

The memory cell size is 8 〇 λ2. At present, the density of EE_M is only the same as the application of the byte modification level. The fine fiber or the surface flash memory only allows the change of the large data to be different, and the EEp_ can achieve the maximum programming/erasing. (P/E) cycle. Currently, EEPR0M can achieve a million Million) P/E cycles for changes to a small amount of data in the early position of the byte. There are several disadvantages to this: in order to perform basic erase and program operations, it is necessary to build high voltage devices, charge pump circuits, and complex double-layer polycrystalline silicon unit structures on the same wafer. At present, the above-mentioned unit cells are all utilizing complex two-layer polysilicon. The double-layer polycrystalline single sheet|^ emblem' mentioned above. _ 4 required to perform programming and erasing operations (4) pressure "the components manufactured are too high. The smuggling of the current NAND5T transistor of each NAND cell structure requires 2 〇V to do Fowler-Nord Han (Fowler-N〇rdheim, FN)^|t^|^0^^ 0 Single crystal NOR* flash unit to the external sense of the street ▼ programming operations need about lov. Then 'Fowle divination (θ_ Na Dao wipe In addition to operation, it requires +10V and -10V. Currently, a dual-transistor EEPR〇M memory cell structure requires +15V to perform fowler-Nordheim programming and erase operations. Gentleman, if the above three NVM units are built together Programming and erasing operations on the same die requires a charge pump circuit to provide a high voltage of approximately 1 〇v to 20 V. Therefore, the NVM array peripheral device requires a Breakdown voltage for such operations. The high breakdown voltage is not compatible with the current single-layer polycrystalline low-voltage logic device process technology. To achieve this high breakdown voltage, the process must be modified, which will increase the number 099103898 Form No. A0101. Page 5 / Total 106 pages 0992007313-0 201030947 Production costs. [0007] A new Single-Poly Flash Memory Cell with Low-Voltage and Low-Power Operations for Embedded Applications ("A New Single-Poly Flash Memory Cell with Low-Voltage and Low-Power Operations for Embedded Applications" CHI, ETAL., THE 5TH ANNUAL IEEE DEVICE RESEARCH CONFERENCE DIGEST, JUNE 1997, PP:126 -127, POSTED IEEEXLORE. IEEE.ORG : 2002 -08 -06 [0008] 21:21:45.0) The article is discussed in the triple Triple wells Single-layer polycrystalline flash memory cell structure under CMOS technology and new programming and erasing spiders with operating voltage not exceeding ±Vcc. _❸Single polycrystal... EPROM is fully compatible with standard C»0Sft; Cheng S. County has the disadvantages of high voltage operation, slow programming and inability to erase the power. The flash unit with this new programming/erasing scheme allows the system single-chip CMOS mixed-signal circuit to allow low voltage, low power. And the application of non-volatile Chinese body.. Guangrif.'!;ecr' US Patent 5, 929, 478 (?81^!3 to 6^:€^) describes a single layer of non-volatile memory. It consists of a ΐLu·, __ΡΕΤ and a substrate on the p

电容器 Substrate A capacitor fabricated in two p-wells of the N-epitaxial layer. The Pf type sinker and N-type buried layers provide isolation in the two P wells. The programming and erasing operations of the NVM device are performed by the fet bias and the charge of the capacitor in and out of a conductive layer. The conductive layer is equivalent to the floating gate of the FET. Reading data from the NVM is based on the capacitor applying a read. The FET current is sensed when the voltage is taken. [0009] 099103898 U.S. Patent Nos. 6,992, 927 and 7, 164, 606 (Poplevine, et al.) provide an NVM array comprising a four-electron crystal pm 〇s non-form number A0101 Page 6 of 106 Page t 201030947 f memory_unit, which has a floating gate that is connected in common. Any one of the four transistors is used to perform different control, erase, write, and read operations. Therefore, each device is allowed to be individually selected to optimize its different operations.阙 US Patent 7,263,001 (Wang, etal.)_T___ Units and arrays of money. The column arranges the _ cells in horizontal and straight rows. Each NVM unit includes a floating gate, a programming component, and a logic storage component. In programming and erase modes, the floating gate of each cell is charged to a predetermined voltage value. At the beginning of reading, all the storage elements are pre-charged to a high electric value β. After pre-charging, the selected _ is read to determine the bit value corresponding to its meta-floating data, and the original pre-charged potential is pulled down. SUMMARY OF THE INVENTION The present invention provides a face-to-face memory component that is more than one or two layers of process and g/supply voltage compared to conventional single-layer multi-pass. 0伏。 [0012] Another object of the present invention is to provide a single-layer polycrystalline floating gate NVM memory element, the programming and erase voltage are less than 6. 0V. [0013] Further, another object of the present invention is to provide a single-layer polycrystalline floating gate NVM memory vessel element whose programming and erasing operation operations can be completed by Fowler-Nordheim edge tunneling of extremely low current. . Another object of the present invention is to provide a single layer polycrystalline floating gate NVM memory element that is relatively small compared to conventional NVM memory elements. 099103898 Form Number A0101 Page 7 of 106 0992007313-0 201030947 Another object of the present invention is to provide a single layer polycrystalline floating gate NVM memory element with multiple programming and erasing capabilities. [0016] In order to achieve at least one of the above objects, a single-layer polysilicon floating gate non-volatile memory device must include a MOS capacitor and a MOS transistor. The fabrication dimensions of the MOS transistor are fabricated using current low voltage logic integrated circuit processes. The first electrode plate of the MOS capacitor is connected to the gate of the MOS transistor such that the gate of the MOS transistor can float to form a floating gate. The second electrode plate of the MOS capacitor is typically the drain of the drain, the source diffusion, and the bulk of the MOS transistor. The drain of the MOS transistor is connected to a bit line, the source, and the source is connected to a source.

Or bigger. The size ratio line. The MOS capacitor is relatively large. The large ratio between the physical dimensions of the MOS capacitor and the MOS transistor provides a large coupling ratio of 80% or more. When a voltage is applied to the second electrode plate of the M〇s capacitor, an external voltage applied to the second electrode plate of the brain capacitor reaches the body gate. The voltage is applied to the source of the MOS cell or to generate an electric field oxidation zone in the gate oxide region of the M〇s transistor, thereby initiating F边缘wler — Nordheim's edge tunneling. When the voltage at the second electrode plate is a negative value and the voltage of the MOSFET of the MOS plate is positive, the charge on the floating gate is drawn to complete the programming operation of the floating gate non-volatile memory device. In addition, the voltage of the right second electrode plate is positive, and the MOS transistor is 汲 or source or base; when the voltage is negative, the electron will be injected into the floating gate and positively combined to complete the non-volatile operation of the floating gate. Erase operation of the memory component. 099103898 Form Compilation A0101 Page 8/Total 1 Page 6 201030947 [0018] An embodiment of a non-volatile memory element is to first form a first conductivity type (N-type) first on the surface of the substrate. Deep diffusion well. The first deep diffusion well is connected to a first deep diffusion well bias source, and then a second conductivity type (P type) first shallow diffusion well and a second shallow diffusion well are formed in the first deep diffusion well . The first shallow diffusion well is connected to the first well bias source. The second shallow diffusion well is connected to the second well eccentricity source. [0020] The non-volatile memory component includes a programmed electrically-occluded metal oxide semiconductor (MOS) transistor that is connected as a capacitor. The programming charge of the Heli crystal includes the m-poly crystals. The size of the programming coupling floating gate provides a large ratio between the wheel vertical and the floating _¥^ sound_go diffusion well: the old y|M〇s transistor includes a source of the first type of conductivity type impurity and no source Both the pole and the finite pole are diffused in the first shallow diffusion well. The non-volatile f±remembered TL pieces are included. The storage load is floating closed. The charge storage is floatingly closed to: the dirty sugar 4 gate so that the handle is closed to the coupled float _ charge will be recorded _ charge _ floating idle. The == body includes—the source and the wave pole of the first type of conductivity type impurity are diffused in the second shallow diffusion well, and the pole is connected to the source line, and the threshold voltage of the connection _tree bias H transistor is set To wipe (four) bound ==:: row erase operation, save ==: Γ voltage, _ hair-recall 099103898 form number Α 0101 page 9 / total 106 page 0992007313-0 201030947 [0021] The non-volatile memory component The programming operation is accomplished by Fowler-Nordheira charge tunneling in the gate oxidation between the charge storage floating gate and the storage M0S transistor drain. The programming operation of the non-volatile memory device is set by the potential of the first well bias source from about -7. 0V to about -5.00V, and the potential of the bit line bias source is from about + 5. 0V to about The volts are about 0. 0V to about 1. 0V. The voltage is set to a threshold voltage of about 0. 0V to about 1. 0V. [0022] The erase operation of the non-volatile memory element is accomplished by setting a threshold potential for storing the MOS transistor to erase the critical potential. The eraser critical potential is from about 3.0 V to about 4. 0 V » ' 画 Λ [0023] When reading the non-volatile memory component, the threshold voltage is detected. The threshold voltage of the S transistor is the programmed critical potential or whether To erase the critical potential. When the non-volatile memory element is read, the potential of the second shallow diffusion well is set to be greater than the programming threshold potential and less than the critical potential, and the potential of the bit line bias source is set at approximately + 1. 0V. . [0024] In another embodiment, the non-volatile memory component further includes a select gate transistor. The select gate transistor includes a select gate coupled to a select gate control terminal. A source of a first type of conductivity type impurity diffuses in the second shallow diffusion well while also being connected to the source line bias source. A ruthenium of a first type of conductivity type impurity stores the source of the MOS transistor. [0025] The programming operation of the non-volatile memory device is performed by setting a potential of the first well bias source from about -7. 0V to about -5.00V, and the potential of the bit line bias source is from about + 5 . 0V to nine about + 7. 0V. In addition, the selection gate control 099103898 form number Α0101 page 10 / total 106 page 201030947 system terminal is set at an inactive potential to turn off the selection gate transistor, so that the threshold voltage of the storage MOS transistor is set at the programming threshold Potential [0026] [0028] 099103898 When reading the non-volatile memory element, it is detected whether the threshold voltage of the memory M?s transistor is the programming threshold potential or the erase critical potential. The potential of the second relegation well is read to be greater than the programming threshold potential and less than the erase critical potential. The bias potential of the bit line bias source is set at approximately + UV. The source line bias source is shaped at a ground reference potential, and the select terminal is set at an activation potential to turn on the selected hip, from calling the programming state of the non-volatile memory element < In the method, the cap member further includes a second deep diffusion well of the first type conductivity type impurity formed on the surface layer of the substrate. The second deep diffusion well is connected to a second shallow well of a second deep well bias source, a second type of conductive impurity, and is formed in the third shallow diffusion well. The wire is privately-used by a single layer of polycrystalline material, and the wiper is connected to the coded floating gate and the charge storage floating gate, and the eraser is closed and closed. The size is smaller than the _ _ floating gate. The erase charge-consuming bile transistor includes a source (four) of a -type conductivity type impurity, and the source and the drain are both diffused in the third shallow diffusion well. The erased electric matching MGS electro-crystal (four) material is connected to the erase line bias source. The programming operation of the non-volatile memory component is performed by one: between the two lions and the storage of the occupational crystals between the poles of the nath page 11 / 1.06

The form number A0101 0992007313-0 201030947 is completed by the Fowler-Nordheim charge tunneling effect. The programming operation of the non-volatile memory device is set by the potential of the first well bias source from about -7. 0V to about -5.00V, the bit line bias source sets the potential from about + 5. 0V to about + 7. 0V, set the threshold voltage for storing the M0S transistor as the programmed critical potential. The programming threshold potential is from about 〇 〇v to about + 1.0V. [0030] 099103898 The erase operation of the non-volatile memory element is through a gate oxidized region between the channel (channe 1) region of the erased coupled gate and the erased charge-faced MOS transistor. Fowler-Nordheiffl charge tunneling occurs, and at the same time, the critical electric enthalpy for storing the M0S worm is set to the critical potential of the socks.

About +4. 0V. The line bias is removed. The erase potential is set to a potential of about -7. 0V to about - 5. 0. The potential of the first well bias source is set to be from about + 5. 0V to + 7. 0V, set the potential of the third well bias source to be from about -7., 0V to the office -5·0Y, the first deep well 4n! 丨乂太刼+7. OV, thus Let the potential of the ΙΓϊΙρ*! bias source be set from about 5. 0' Γ-,, ij·-® to store the switching voltage of the M0S transistor, |>|The erased critical potential is read When the non-volatile memory component is taken, the threshold voltage of the memory MOS transistor is detected to determine that the non-volatile memory component is at a programming threshold potential or an erase critical potential. When reading the non-volatile memory component, the first The potential of the two shallow diffusion wells is set to be greater than the programming threshold potential and less than the erase critical potential. In addition, the potential of the bit line bias source is set at approximately + 1. 0V. In another embodiment, the non-volatile memory device further includes a second deep diffusion well of a first type of conductivity type (N type) impurity, the second deep diffusion form number A0101 page 12 / 106 [0031] 201030947 [0032] The well is formed on the surface layer of the substrate. The second deep diffusion well is also connected to a second deep diffusion well bias source. The erased charge-closed crystal is formed on the surface of the second deep diffusion well. The erased charge _ MOS transistor includes - a single layer of polycrystalline smear wipes out the floating closed ‘the single layer polycrystalline dream erase _ _ float ask to connect to the _ _ float (four) and the charge storage floating gate. Compared with the floating wheel of the programming wheel, the hybrid material is floating and the size is small. The erased charge is combined with the source and secret of the MGS transistor and formed by the first conductivity type impurity and diffused in the second deep diffusion well. The erased charge combines the source and the drain of the M〇s transistor. Connect to the erase line bias source. The non-volatile memory removal component is operated by the Fowler-Norc^l^lii^^mineD effect occurring in the gate oxidation region between the erased coupling floating gate and the erased charge coupling (4). And setting the threshold voltage of the M0S transistor to the erase critical potential is completed. The erase critical potential is from about +3 〇v to about +4 〇v. The non-volatile memory needs to be erased; the potential of the erase bias source is set at about -7. GV, and the potential of the well bias source is set at about +5 to the third well. The potential of the bias source is set from about -7. 0V to about -5 · 〇v, and the potential of the first deep well bias source is set from about + 5. 〇v to about + 7. 〇v to set The threshold voltage for storing the MOS transistor is the erase critical potential. [0033] In still another embodiment, the non-volatile memory element includes a common deep diffusion well of a first type of conductivity type (N type) impurity, and the common deep diffusion well forms 'on a substrate and is connected to the deep well A first shallow diffusion well of a second type of conductivity type (P type) impurity and a second shallow diffusion well are formed in a common deep diffusion well. A charge coupled MOS capacitor is formed in the first shallow diffusion well 099103898 Form No. A0101 Page 13 / 106 pages 0992007313-0 201030947, which consists of a single-layer polycrystalline adult ~ floating gate size such that the coincidence ratio is very large . The second closed 'source of the impurity and the secret diffusion in the first - shallow expansion of the second type of conductivity are connected to the first well (4). Continued. 4-pole and immersed two-well bias source. The 尧 diffusion well is connected to the [0035] [0035] 099103898 The non-volatile memory element includes a memory _ transistor including a charge storage floating gate formed by a single layer polysilicon, the charge storage floating The gate is connected to the coupled floating gate so that the charge is collected on the charge storage floating gate when it is engaged to the light-closed floating gate. -

The enthalpy and cascade of the first type of conductive impurities diffuse in the second shallow diffusion well.

Bit line offset Erasing critical power The source is connected to the source line bias source kil^·. The memory of the memory MOS transistor is erased by the non-volatile memory element; the threshold voltage of the memory M?s transistor is set to a programming threshold potential to the non-volatile memory element Perform programming operations. 『This non-volatile memory component occurs over the gate storage oxidation gate of the charge storage floating gate and the memory M0S transistor.

Fowler-Nordheim charge tunneling is done. To complete the programming operation of the non-volatile memory component, the potential of the first well bias source must be set from about -7. 0V to about -5.00V, and the potential of the bit line bias source must also be set from Approximately +5.0 V to about +7. 0 V ' is set to store the critical potential of the M0S transistor as the programmed critical potential. The programming threshold potential is from about 0. 0V to about + 1. 0V. The erase operation of the non-volatile memory element is to set the threshold voltage of the memory MOS transistor to the erase critical potential. The erased critical potential is from the form number A0101 page 14/106 page 0992007313-0 [0036] 201030947 approximately + 3. 0V to approximately + 4. 0V. [0037] Upon reading the non-volatile memory component, the critical voltage of the memory MOS transistor is sensed to determine whether the non-volatile memory component is at a programmed critical potential or at an erase critical potential. When the non-volatile memory element is read, the potential of the second shallow diffusion well is set to be greater than the programming threshold potential and less than the erase critical potential. Also, the potential of the bit line bias source is set at approximately + 1. 0V. [0038] In another embodiment, the surface of the substrate includes a deep diffusion well of a first type of conductivity type (N type) impurity, and the deep diffusion well is connected to a 笮f笮 pressure 缪? A shallow diffusion well of a second type of conductivity (P type) impurity is formed in <. The non-volatile memory component includes an electrical (poly) semiconductor (MOS) transistor connected as a capacitor. The charge-coupled M〇s electro-crystalline ship: consists of a single layer consisting of a single layer: ::two: a floating damper: the brewing inch must make the diffusion well & - The first type of conductive impurity source and the pole are commonly connected to the ★ diffusion well and the first well bias source. The non-volatile enteroelectric crystal crystals are intended to include a Γ storage 嘱 crystal boat, and the storage of the charge is called =1 layer polycrystalline material into (four) financial entanglement, and is coupled to the turn-in hp _ floating gate to make the charge Engage ° ° 3 will be collected on the charge storage floating gate. A first type of conductive (four) quality... She and - secret in the substrate are connected to the source line bias 湃 ^ ^ Xinyuan pole connected to the storage hall, the pole is connected to the bit line bias source. The memory form number is set to - erase the critical potential, and the non-volatile memory element is erased by page 15 / page 106 0992007313-0 201030947; the criticality of the memory M〇s transistor The voltage is set to a programmed threshold potential to program the non-volatile memory element. [0040] programming operation of the non-volatile memory element occurs through a gate deuteration region between the charge storage floating gate and the storage MOSFET dipole

Fowler-Nordheim charge tunneling is done. The programming operation of the non-volatile memory element requires setting the potential of the first well bias source from about -5.0 V to about -7. 0 V 'setting the potential of the bit line bias source from about

+ 5. 0V to approximately + 7. 0 V ' to set the threshold voltage for storing the JI0S transistor to the programmed critical potential. ...the programming glare potential is from about 〇. 〇 V to about [0041] 1.0V. ^ ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S 临界When reading the non-volatile memory element, the threshold voltage for detecting the memory of the M〇s is first detected by programming the 临界_雠 erase threshold. The potential of the non-volatile recording shallow diffusion well is set in the large bell programming pro θ Ι β ® # is less than the erase critical potential. The potential of the bit line bias source is set at approximately + 1 〇V. [0042]

In another embodiment, a non-volatile memory component is formed on a substrate, the surface of the substrate includes a deep diffusion well of a first type of conductivity type, and the deep diffusion well is connected to a deep well bias source. . A shallow diffusion well of a second type of conductivity type (P type) impurity is formed within a common deep diffusion well. The non-volatile memory 7G device includes a charge coupled metal oxide semiconductor (M〇s) transistor that is connected as a capacitor. The charge coupled MOS transistor comprises a single layer polycrystalline germanium formed 099103898 Form No. A0101 Page 16 / 106 pages 0992007313-0 201030947 =:::: One of its: inch makes the floating - in, electricity type (4)汲 扩散 diffusion [0043] [0044] scattered wells. The source and drain are commonly connected to a shallow diffusion well. The memory device component also includes an electrical material capacitor. The =he tMGS capacitor includes - from a single layer of polycrystalline material into a _heavy float ^ its size must be verified from the floating __ 散 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Shallow: scattered wells. The bribe source and the shallow diffusion well are connected together to the first well source. The storage surface 5 "body_bound is set to " erase the critical potential to erase unless the volatile memory|component, if set to the programming political power ^ ^ # # ^ ^ ^ ^ ^ to the non, the memory component ^Fowler-Nordheim charge tunneling occurs in the gate oxidation region between the charge storage floating gate and the drain of the MOS transistor. F〇wUr_

The Nordherm electric_channel effect is programmed by a fine-grained memory element. The potential of the voltage source is from about -7. 0V to about -5. The potential of the voltage source is about + 5.0V. To approximately +7.0V, to set the threshold voltage of the M〇s transistor to the programmed critical potential. The programming threshold potential is from about 〇.0V to about 1.0V. [0045] The erasing operation of the non-volatile memory element is to erase the critical potential by setting a threshold voltage for storing the M〇s transistor. 0伏。 The erased threshold potential is from about +3.00V to about +4. 0V. [0046] When reading the non-volatile memory element, the memory of the m〇S transistor is 099103898, the form number A0101, page 17 / 106 pages 0992007313-0 201030947 I voltage is detected to determine the non-volatile memory The component is located at the programmed critical potential or at the bit (four) (four) boundary potential. When reading the non-volatile cryptographic element, the potential of the first-diffusion well is set to S greater than the programmed critical potential and less than the erase critical potential. In addition, the potential u of the bit line bias source is about +1.0 GV, and the source line bias I source is set to the ground reference potential. [0048] 099103898 13 In the formula (4), a non-volatile memory element is formed on the substrate, and the surface of the substrate includes a first-type conductivity type (10) impurity-first deep diffusion well and a second deep Diffusion wells... The second type of conductivity type (4)) The first shallow shallow diffusion well and the first shallow shallow diffusion well are formed in the first deep diffusion well and the second reverse diffusion well, respectively - the electrical Weihe metal oxide semiconductor is transferred to I ,, the short charge-consuming metal oxide ___ is connected as "electric'.": The transistor consists of a single-layer multi- (four) sense-closed gate, and the material (four) is very large. - the first h and the remaining Both are diffused in the first shallow diffusion well. The immersed, source ^1^^ well is commonly connected to the gas well money source. The first 'two shallow second well bias source. The first deep diffusion well is connected to the first Deep well source.” The second deep diffusion well is connected to the second deep well bias source. The non-volatile memory device includes a memory_transistor including a single layer of polycrystalline material (4), a charge storage gate, and the money is connected to the (four) floating gate to make the charge_合_= The gate will be collected on the charge storage gate. The source of the first-type conductivity is recorded in the second_well and connected to the polar line bias source. - The drain of the first-type conductivity type impurity diffuses in the second shallow diffusion well and the form number A0101 is connected to a one-line bias source. The non-volatile memory component further includes - a select gate MOS transistor 'which includes a select gate connected to the select gate control terminal. A source of a first type of conductivity type impurity diffuses in the second shallow diffusion well and is connected to the source line bias source. The select gate M〇s transistor includes a drain of a first type of conductivity type impurity, which is also the source of the memory MOS transistor. The threshold voltage of the memory M?s transistor is set to erase the critical potential to erase the volatile memory element; or is set to a programmed threshold potential to program the non-volatile memory element. The non-volatile memory component is activated by the owler-N ordheim charge tunneling effect in the charge storage floating gate and the storage Μ 0 S electro-crystal 艎汲 "* Fowler-Nordheim^:^ ι area The non-volatile memory element is programmed to operate, and the potential of the first well bias source needs to be set from about -7. GV to about the source potential from about +5 to about +7. 槪'槪g (four)! The criticality of the electric crystal Zhao is the programming threshold _^ the ^_|; 彳| from about Q wide to about 1. 0V. And a pair of non-volatile memory elements are erased by Fowler-Nordheim charge tunneling in the gate oxide region between the erased floating gate and the erased charge coupled MOS transistor channel region. At the same time, it is also necessary to set the threshold voltage for storing the M0S transistor to erase the critical potential. The erasing threshold potential is from about +3.00V to about +4, ^ the erasing of the non-volatile memory element requires setting the potential of the first well bias source from about +1.0V to about +7. 〇V, The potential of the second well bias source is from approximately - Form No. A0101, page 19. / page 106, 201030947, 7. 0V to approximately -5. 〇V, the potential of the first deep well bias source is approximately +5 〇v Approximately +7.00V, and the potential of the source line bias source is from about _7 to about -5.00V, to set the threshold voltage for storing the MOS transistor to the programmed critical potential. [0052] [0052]

Upon reading the non-volatile memory component, the critical voltage of the memory MOS transistor is sensed to determine whether the non-volatile memory component is at a programmed critical potential or at an erase critical potential. When reading the non-volatile memory element, the potential of the first shallow diffusion well is set to be greater than the programming threshold potential and less than the erase critical potential. In addition, the potential of the bit line bias source is set to approximately +m:': The 1 濂 line bias source is set to the ground reference potential, select the gate control, ^^ is activated to activate the select gate MOS transistor, and let the programming state of the non-volatile memory component. [Embodiment] ❹ Please refer to 囷1 ’Wang et al. for a single-layer symplectic floating gate single crystal flash memory. The gp y includes a first programming transistor M106 and a second programming capacitor M102. At the beginning of the read operation, the precharge circuit 108 precharges the storage transistor M102 with a power source VDD. The first programming transistor M106 and the second programming transistor M104 are combined to form a programming unit of the NVM cell C100. The gates of the first programming transistor M106 and the second programming transistor Mi〇4 are coupled together and share a floating junction 11〇 with the storage transistor M102. The source, drain and N well terminals of the first programming transistor M106 are consumed together with the first compiled voltage source VEE. The source, drain and N well of the second programming transistor M1 〇4 are coupled together to a second programming voltage source vpp » 099103898 Form No. A0101 Page 20 of 106 Page 0992007313-0 201030947 [0053] 0054] Ο ❹[0055] Floating Π 〇 Storage of injected electrons

What is the purpose of adjusting the criticality of NVM n (10). ^ The amount will increase the threshold voltage of the storage electricity 1Q2 and reduce the amount of electrons stored in the oceanic junction 110. The expansion will reduce the voltage of the storage transistor_2. The size of the first-programmed electro-crystalboard 06 must be the crystal size of the crystal shirt 2 (10). When the operation is performed, the Fowler_Nc)rdheim channel will have a second programming electro-optical ship between the 4 channel and the closed pole. Oxidation zone. When the first step is fine (four) 峨 spider 1 inquiry: the programming wire is rushed through the second programming electric crystal _4, so injected into the floating knot (1), in order to add storage electricity m critical power slightly, a reverse Fowler -Nordheim tunneling electrons from the second programming body Μι_ evaluation and floating junction u°; moving junction 110 leaves the gate oxidation region of thickness 2 less than 1G and drinking the second process electron crystal After reaching the second bamboo electric Lu (four) after the erasing '_s storage transistor' ts programming operation, the injection of electrons into the floating junction 110 is set by the first programming power source VEE - high voltage + 1G. GV to - The larger first-programmed crystallizer G6 has the pole, source and at-end termination points, and sets the ground reference voltage (00v) to a second programming voltage by placing the second programming voltage source VPP The end point of the crystal M104 whose drain, source and N well are stuck together is achieved. The ground reference voltage (〇. 〇v) is applied to the output bit line Vo(BL) and the word line voltage source WL connected to the source of the NMOS storage transistor jn〇2. Since the size of the first programming transistor Mi〇6 is larger than the second programming 099103898 Form No. A0101 Page 21/Total 1 Page 6 0992007313-0 201030947 The crystal M104 and the NM0S storage transistor Ml〇2 are combined in size four The potential of the five-fold 'floating junction 110' is approximately 9 QV. Electrons are attracted from the second programming transistor M104 through the Fowler-Nordheinrit tunnel to the floating junction no. The threshold voltage of the NM0S memory transistor M1〇2 increases after the programming operation. [0056] 〇 During the erase operation, the high potential of +10. ον is from the second programming voltage source vpp to the source, drain and N well terminals of the smaller second programming transistor Mi〇4. The ground reference voltage (0. 0V) is applied to the source of the larger first programming transistor M106, the terminal of the terminal well, the voltage source of the word line, the source of the NM〇s storage transistor M102, and the source The bit line shame (she) and the NM〇s store the drain of the transistor Ml 〇2'. Based on the gas seven: the partial pressure of the pressure plate 110 is near +1V, and the voltage drop between the second programming power source VPP and the floating junction lio of the 祥4 crystal is about +9V. . Due to the tunneling effect of the f〇w 1 er_ Nordheim channel between the gate of the second programming transistor U1.04 and the n-well, the electrons of the azimuth junction are passed from the floating junction 110 through the second programmed electro-crystallizer Mlj4. ; suction #今丨涂二programming voltage source vpp. After the socking operation, the critical 'I! ί* voltage of the transistor M102 drops. [0057] The erase operation and the programming operation described by Wang et al. are based on F〇wler_

Nordheim channel tunneling is done. This single-layer poly-crystal flash Ννΐί unit C100 has the benefits of low current programming and erase operations. However, it has the following disadvantages: a +10Vi^j pressure is required to effectively perform Fowler-Nordheim channel erasing and Fowler-Nordheim channel programming. + 10V high voltage requirements are too high, it can not be obtained from most single-layer polycrystalline logic 099103898 of the device that can only provide +6.0V breakdown voltage. Form No. A0101 Page 22 / 106 Page 0992007313-0 201030947 》 [0058] 玟, it is necessary to provide a single-Ma process compatible with a single voltage and a low power supply operating voltage and a crystal floating gate Nv when the storage unit floats NVM in Eclipse s....

[0059] -----", "丨甘两早兀^ The single-occupation of the oceanic and horizontal storage unit programming and wiping _ the money layer in the + 6. paste shoulder. This single-layer polycrystalline floating reservoir uses very low current to pass through the channel for programming and erase operations. What is required for the further step is that the thickness of the hardened region of the single-layer polysilicon floating gate_storage unit is smaller than just α = the size is smaller than the physical size of the conventional storage unit. It is worth noting that the feature of the floating layer of the polycrystalline silicon is that it is considered to be a metal oxide semiconductor ceramic transistor. Single Qing is not a metal, however, it can still be used to conduct electricity; this feature of field effect electric TMOS transistors. f _ 2^ Stomach _ «Sexual memory 2 〇〇 is formed on the Ρ-type substrate 205. The upper surface is formed - a deep diffusion well of N-type impurity __ a deep diffusion well 21 〇 through an N-type connection point connected to a first deep well bias source 265 ◊? The type substrate is connected to a ground reference voltage source (〇. 〇v) via a connection diffusion point 270. The first deep diffusion well 210 is obtained by adding a small change in the process of the current single-layer polysilicon logic integrated circuit process. Crystal [0060] 099103898 A first shallow diffusion well 215 and a second shallow diffusion well 220 forming a p-type impurity within the first deep diffusion well 210. The first and second shallow diffusion wells 215 and 220 are The current single-layer polymorphic logic accumulation circuit is based on an additional layer of process. Form No. A0I01 Page 23 of 106 0992007313-0 201030947 [0061] A programmed charge coupled metal oxide semiconductor (MOS) transistor 225 is connected as a capacitor. The programmed charge coupled MOS transistor 225 is formed on the surface of the first shallow diffusion well 215 and includes a source 226 and a drain 227 of N-type impurities both diffused within the first shallow diffusion well 215. The source 226, the drain 227 and the first shallow diffusion well 215 are commonly connected to a first shallow well bias source VTPW1 230. The P-type connection diffusion point 216 connects the first shallow diffusion well 215 to the first shallow well bias source VTPW1 230. The first shallow diffusion well 215 is coupled to the first shallow well bias source VTPW1 230 through a connection diffusion point 216. The gate oxide region 229 has a programmed coupling floating gate 228 formed of a single layer of polysilicon. The material and thickness of the gate oxide region 229 is one of the techniques commonly used in the current CMOS field.

[0062] IT,: In the second shallow diffusion well 220, the shape is poor and the hips are more insulting. The memory MOS transistor 235" has an N-type drain 236 and an N-type source 237, and the N-type drain 236 and the N-type source 237 are both diffused in the second shallow diffusion well 220. The drain 236 is connected to a bit 4 voltage source called 240, and the source | ^ I f J | f1 - f 237 is connected to the source line bias source 2: the top of the region 1 239 has a single Layered polycrystalline germanium formed, 4|^^>& gate 238. The material and thickness of the gate oxy-III region 239 is consistent with the current techniques commonly used in the process of the art. The second shallow diffusion well 220 is coupled to the second shallow well bias source vTPW2 255 through the connection diffusion site 250.

[0063] The programming and erasing operations of the memory MOS transistor 235 are implemented in accordance with the rib ... redundancy - Nordheim tunnel edge programming (FN edge programming) effect. Edge programming means that the Fowler-Nordheim effect occurs at the edge of the cell near the drain 236 or between the source 237 and the floating junction, rather than in the channel region 280 where the MOS transistor 235 is stored. Over the edge programming operation 099103898 Form number A0101 Page 24 / Total 1 page 6 0992007313-0 201030947 [0064]

[0066] During the process, electrons are drawn from the charge storage floating gate 238 to the gate 236 that stores the MOS transistor 235. When programming at the edge of the Fowler-Nordheim tunnel, each single-layer polysilicon floating gate non-volatile memory 2 consumes less than 1.0 π 〇〇 of current during programming operations. The programming charge coupled MOS transistor 225 is formed between a programming coupled floating gate 228, a gate, a source and a channel region 275, and a memory MOS transistor 235 at the charge storage floating gate 238, drain 236, source 237 There is a coupling ratio between the storage capacitor formed between the channel region 280 and the coupling ratio, which must be very large, greater than 803⁄4^ to achieve the coupling ratio 'the actual physical size of the programmed charge coupled MGS-the transistor 225 relative to the memory MOS The transistor is often large. The size ratio between the programmed charge coupled MOS transistors _ body 2 3 5 is more than 10 times. The coupling ratio requires that the programming potential of the memory MOS transistor 235 be as shown in Table 1:

InfeSiectual transistor 235 pain: move all over... 285 " bungee Pr( ”236 7_fy VTPW2 220 NVRAM cell 200 Vt FN edge programming -5V floating /0V —-—^— + 5V ον Vtl Note: Vt2>Vtl [0067] When the floating gate non-volatile memory 200 is programmed, electrons are drawn from the floating gate junction 285 to the 汲 pole 2 36. The floating gate junction 285 is connected to the programmed floating gate 2 2 8 and the charge storage floating gate 2 3 8. For the selected 099103898 form number Α 0101 page 25 / 106 page 0992007313-0 201030947 selected floating gate non-volatile memory 200, to send electrons from the floating gate 285 The drain 236 is drawn, the potential of the floating gate 285 must be about -5.0 V, and the potential of the drain 236 must be set at about + 5. 0 V. For the floating gate non-volatile memory that is not selected. 200, the potential of the drain 236 is set to a ground reference voltage source (0. 0V). The second shallow diffusion well 220 and the first deep diffusion well 210 are set as a ground reference voltage source (0. 0V). The source 237 is set to a floating state or a ground reference voltage source (0. 0V).

Referring to Figure 2b, in order to achieve the conditions described in Table 1, f〇wi-er, the edge of the Nordheim tunnel is required to be applied to the floating gate.

Gate non-volatile 30 potential large volatile memory 200 potential ^ For memory 2 〇〇, the first shallow filial i source! . ... is set at about -6. 0V to -7. Between 0V, the potential of the voltage source bl 240 is set approximately between + |.:=(|V to + 7. 0V. For those not selected

For the floating gate non-volatile memory body 200, 丨 the bit turn voltage source bl 24〇 is set to the ground reference voltage case. A deep well bias a source 265 is set to the ground reference g, and the second shallow-\ J The 1 I f ^ well bias source VTPW2 255 and the source line bias source 245 can be selectively set to a floating state or a ground reference voltage source (0.0V). As described above, the physical size of the programmed charge coupled MOS transistor 225 is greater than the sigma storage MOS transistor 235 such that the coupling ratio between the programming capacitor and the storage capacitor exceeds 8〇%. In order for the floating gate 285 to have a programming voltage of approximately -5.0 V, the coupling voltage of the first shallow well bias source VTPW1 230 must be between approximately _6 (^ to _7 〇v. Thus at the drain 236 The edge produces a low current F〇wler- 099103898 Form No. A0101 Page 26 / Total 1 Page 6 0992007313-0 201030947 Φ [0070]

Nordheim senses with the road effect. The stored electrons are drawn from the floating gate 285 into the drain 236' to reach the bit line voltage source bl 240. After the Fowler-Nordheim edge programming operation, the programming threshold voltage Vt2 of the floating gate non-volatile memory 2A begins to decrease from its erase threshold voltage vtl after a predetermined programming time. After the erase operation, the erase threshold voltage Vtl rises from approximately + 3. 〇V to approximately + 4. 0V, and the programming threshold voltage Vt2 is approximately + l. 〇v ^ erase the threshold voltage vti should not be negative, Avoid excessive erasure and enter the memory M〇s transistor 235 depleted state. According to the thickness of the gate oxide region 239 and the potential of the bit line voltage source BL 240 and the floating junction, the Fowler-Nordheim programming time can be completed in a few mouths. In one operation, the first fragment is set to verify the read potential (VriiD), and the verification read clamp (V) is

READ Ref. [0071] Coupling to the floating gate junction 2 85 ^Verification The verify read potential (vread) is set between the erase critical potential Vtl and the programming critical first octave 2 potential of the bit line voltage secret 240 is approximately 41^ |^ The second shallow well bias source 2 255 and the source line are biased as the source (〇. ον). The first deep well bias source 26 is set to the potential of the power supply voltage source (VDD). If the floating gate non-volatile memory 2 is programmed to operate, then the potential of the floating gate 285 is approximately the second critical potential, and a conductive current flows from the bit line voltage source BL 240 through the floating gate. The volatile memory 200 reaches the source line bias source 245. When the critical potential of the floating gate non-volatile memory 200 is the second critical potential yt2, the read data is a binary "0". If the floating gate non-volatile memory 2 has no 099103898 form number A0101 page 27 / page 106 0992007313-0 201030947 is selected as the programming operation, then its threshold voltage is still at its erase critical potential Vtl, so the potential of the floating gate 285 is less than the erase critical potential Vtl ^ When the floating gate non-volatile memory 2 〇〇 has no conduction current 'and the threshold voltage of the floating gate non-volatile memory 2 是 is the erase critical potential', the binary data read is "1". [0072] The benefit of the floating gate non-volatile memory 200 is that the maximum potential requirement for all erase, program, and read operations is approximately +5.00V, which is compatible with current single-layer polysilicon logic integrated circuit processes.

Please refer to FIG. 3' for the structure of another embodiment of the single-layer polysilicon floating gate non-volatile memory Q of the present invention. The structure and structure of this embodiment

The structure of Fig. 2a differs in that; 2, the Qin charge-coupled Μ 0 S transistor 225 is charge-coupled on the first '.Cl, shallow diffusion well 215. < has two Ρ-type diffusion regions The charge coupled MOS capacitor 325 is connected to the first well bias source VTPW1 23〇. The depth and concentration of the first shallow diffusion ^μ丨5 摹2 shallow diffusion well mo are opposite to those in FIG. 2a; this simplifies the complexity of the process processing, thereby observing the cost of the ritual process and the current logic CMOS process compatible. The program coupled floating gate 328 is coupled to a charge storage floating gate 238 to form a floating gate 385. The charge coupled MOS capacitor 325 and the memory MOS transistor 235 have the same operational bias conditions as the programmed charge coupled metal oxide semiconductor (MOS) transistor 225 and the memory MOS transistor 235 of FIG. 2a. As with the floating gate non-volatile memory 200 of FIG. 2a, the size ratio of the charge coupled MOS capacitor 325 of the floating gate non-volatile memory 300 to the memory MOS transistor 235 must be sufficiently large that the coupling ratio exceeds 8 〇%. 099103898 Form No. A0101 Page 28 / Total 106 Pages 0992007313-0 201030947 [0075] When the first shallow well bias source VTPW1 230 is set to the programming potential (approximately from -7.00 to _5. 0V), The voltage on the floating gate 385 is higher than -5.0 V when programmed. The result of the electron absorption is the same as that shown in Fig. 2a and the offset potential shown in Fig. 2b. Referring to FIG. 4a, a structure of still another embodiment of a single-layer polysilicon floating gate non-volatile memory of the present invention is shown. The single-layer polysilicon floating gate non-volatile memory 400 is formed on a P-type substrate 405. The surface of the p-type substrate 405 forms a first deep diffusion well 41 of an N-type impurity. The first deep diffusion well 410 is obtained by adding a further process to the current single-layer polysilicon suppression integrated circuit process. The deep diffusion well is connected to a deep well biased bead 465 via an N-type connection point. The P-series diffusion-diffusion point 470 is connected to a tapping voltage source (〇. /: [0077] The dog in the deep diffusion well 410 forms a p-type impurity shallow diffusion well 415. The shallow diffusion well 415 is When the Weng layer polycrystalline dream logic integrated circuit circuit process adds another layer and pays ° Welleckjol

Just in the surface of the shallow diffusion well 4 i 5 | ^ ug% of the surface of the metal oxide semiconductor (M0S) electro-crystal Zhao 425, 竣, _ gastric-coupled metal oxide semiconductor transistor 425 is connected as a capacitor. The programmed charge coupled M?s transistor 425 includes a source 426 and a drain 427 of an N-type impurity that is diffused in the shallow diffusion well 415. The source 426, the drain 427 and the shallow diffusion well 415 are commonly connected to a shallow well bias source ^^^. The shallow diffusion well 415 is connected to the shallow well VTPW1 430 through a connection diffusion point 416. - A single layer polycrystalline wafer forms a programmed floating gate 428 on the gate oxide region. The material and thickness of the gate oxide region 429 is consistent with the process technology used in the current CMOS field. 099103898 Form No. A0101 Page 29/Total 1 Page 6 0992 (201030947 [0079] [0081] A memory M s transistor 435 is formed on the P-type substrate 405. The memory MOS transistor 435 has a N The type drain source 437 is diffused in the p-type substrate 405. The drain 436 is connected to a one-bit line voltage source 乩44〇, which is connected to the source line bias source 445. The gate is oxidized The region 439 has a single-layer polycrystalline stone formation-charge storage floating gate. The material and thickness of the gate oxide region 439 are consistent with the process technology used in the current CM〇s field. The floating gate non-volatile memory 4 〇〇 is different from the floating gate non-volatile memory 200 of FIG. 2a in that the memory M 〇 电 嬷 435 is formed directly on the surface of the base @ 405. In the 加 加, let the 閛 閛 285 It is a programming M M H material semiconductor and a memory M 〇 s transistor 2_ connection point. Since the transistor 435 is formed directly on the surface of the substrate 405, the memory transistor 435 and the programmed charge coupled metal oxide semiconductor (10) s) The spacing between the deep diffusion wells 410 where the transistors 425 are located must conform to the current Cjj〇s, the fabric of the domain process. Design rules. As shown in Fig. 2a, the gas-charged programmed charge-coupled metal oxide semi-conducting vessel (Μ(^华IX25 is used as a voltage-surface-capacitor during programming operation) ^The surface of the i'4Q5 is formed. ❼ Storage M0S The transistor 435 is a single layer polycrystalline memory floating gate device. The programming operation of the memory MOS transistor 435 is a Fowler_N〇rdheim edge programming operation that extracts electrons from the floating gate non-volatile memory 400. Fowler-Nordheim The voltage required for edge programming for reading and programming operations is similar to that of Table 1. The erase operation is performed by injecting electrons into the floating gate 485, and the threshold voltage of the floating gate non-volatile memory is erased. The threshold voltage Vtl (approximately +3 〇v to +4. 〇v). 099103898 Form No. A0101 Page 30 / Total 1 〇 6 Page 0992007313-0 201030947 [0082] Please refer to FIG. 4b, read and For a table of bias potentials for programming operation, the coupling voltage at the shallow well bias source VTpw 43〇 must be from about -6. 0V to -7. 0V, and a low current Fowler-Nordheim can be generated at the edge of the drain 436. Tunneling effect The floating gate 485 is drawn into the drain 436 to reach the bit line voltage source BL 440. After a predetermined programming time after performing the Fowler_N〇rdheim edge programming operation, the floating gate non-volatile memory The threshold voltage Vt2 is decreased from the erase threshold voltage Vtl.

Thereafter, the erase threshold voltage Vtl is approximately between +3·0V and +4·0V, and the program threshold voltage Vt2 is approximately 〇v. The erase threshold voltage vtl should not be negative to prevent the stored MOS power supply 435 from entering the depleted state after the hop. According to the gate oxygen servant ^9 # wave seven bit # line voltage source 虬 2 4 ° and: 'moving junction 485 5 electric fiber e e m programming time can be completed from a few microseconds to a few milliseconds. [0083]

During the read operation, the shallow well bias source VT^W 430 is pulled (vREAD), which verifies the junction 485. This verification reads between the potential critical potential ηι and the programming threshold potential Vt2. The potential of the voltage source bl 440 is set to approximately + 1. 0V. The P-type substrate 405 and the source line bias source 445 are set to a ground reference voltage source (0 V). The deep well bias source 465 is set to verify that the read QJ yi is coupled to the floating potential and is set to the supply voltage. The potential of the source (VDD). [0084] If the floating gate non-volatile memory 4 is programmed to operate, the potential of the floating gate 485 is approximately the second critical potential, and a conductive current passes from the bit line voltage source BL 440 through the floating Gate non-volatile memory 400 to source line bias source 445. When the floating gate non-volatile memory 099103898 Form No. A0101 Page 31 / Total 106 Page 0992007313-0 201030947 [0085] [0086] 099103898 When the critical potential of 40〇 is the second critical potential vt2, the data read is - "进制" in hexadecimal. If the floating gate non-volatile memory 4 is not programmed, its threshold voltage remains at the erase critical potential Vtl. Therefore, the potential of the floating gate 485 is smaller than the erase critical potential Vtl. When the floating open non-volatile memory 400 has no conduction current, and the critical potential of the floating gate non-volatile memory 400 is the erase critical potential, the read data is a binary "1". Please refer to FIG. 5' for the structure of another embodiment of the single-layer polysilicon floating gate non-volatile memory of the present invention. The structure of this embodiment is essentially the same as that of FIG. 4a except that the 褊衮 charge coupled M 〇 电 transistor 425 is coupled with the charge coupled M 〇 s capacitor of the 〇 电 电 电 舆 舆 舆 舆 舆The corresponding 喝 搞 〇 〇 谷 325 325 325 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有Bias #VTpw 43〇. The shallow-diffusing well 41S is the same as that recorded in Figure 3, which simplifies the complexity and reduction of the process: the cost of the pre-crystallized ▲ process is compatible with the standby month, the logic coffee s process. The order is converted into a floating gate 528 and connected to the charge storage floating gate 438 to form a floating gate\#5. The charge-to-surface MOS capacitor 525 and the memory cell 435 have the same operational bias conditions as the programmed charge-planar metal oxide semiconductor (10) s) cell 425 and the memory MOS die 435 of Figures 4 & Like the floating gate non-volatile memory Zhao 400 of _, the floating gate non-volatile memory 艎 5 〇〇 charge surface sealing capacitor 525 is larger than the physical size ratio of the storage surface s transistor post, so that _ The ratio is over 8%. When the shallow well Wei VTPW 43〇 is set to the programming potential (approximately from _ form number A0101 page 32 / total 106 pages

0伏。 0992007313-0 [0087] 201030947 7. 0V to -5. 0V) when the voltage of the floating gate 585 is greater than -5.00 in the programming operation. The resulting electron pickup phenomenon is the same as that described in the previous figure and the bias potential shown in Fig. 4b. [0088] Please refer to FIG. 6a'. The details of FIG. 5 are the same as those of FIG. 6a for those skilled in the art. The floating gate non-volatile memory 2A includes a programmed charge coupled MOS transistor 225 and a memory MOS transistor 235 connected as a MOS capacitor, the memory MOS transistor 235 being connected as A charge reservoir. The programming coupled floating gate 2 2 8 is coupled to the charge storage floating gate 238 to form a floating gate 285. The source, drain and base (first shallow diffusion well) of the programmed charge coupled |f〇s 艟 艟 225 are connected to the odor-Wl 230. The memory of the MOS transistor 23 5 is stored. The source of the memory MOS transistor 235 is connected to the source line bias source 245 ·.; mi rr . The second shallow diffusion well '% stores the base of the MOS transistor 235 to be connected to the second shallow well bias source VTPW2 » #Note 芩, the memory in the figure stores the M0S electric crystal 4 4 5 is on the substrate 40Iplf ί Therefore, the present embodiment [0089] .rf ΟΟΘΓι V may not provide the second shallow well partial insult fl_W2 'Urnce Please refer to FIG. 6b. For those skilled in the art, the details of FIG. 5 are the same as FIG. 6b. The structure of the floating gate non-volatile memory 3A in this embodiment is different from the structure of the 囷2a in that the programmed charge-surface MOS transistor 225 in Fig. 2a is replaced by a charge-junction JJ0S capacitor 325. The program coupled floating gate 328 of the charge coupled MOS capacitor 325 and the charge storage floating gate 238 of the memory MOS transistor 23 are connected to form a floating gate 385. Two P-type diffusion regions are coupled to the first shallow well bias source VTPW1 230. In Fig. 2a, the gate of the memory MOS transistor 235 is connected to the bit line. 099103898 Form No. A0I01 Page 33 of 106 0992007313-0 201030947 Source BL 240. The source of the storage MOS transistor 235 is connected to the source line bias source 245 » the second shallow diffusion well 'ie, the base of the storage M 〇 transistor 235 is connected to the second shallow well bias #VTPW2 ^ It is to be noted that the memory jjos transistor 435 is formed on the surface of the substrate 405 in FIG. Therefore, the second shallow well bias source VTpff2 may not be provided in this embodiment. [0090] Please refer to FIG. 6c, which is a non-volatile memory device 6A, which includes an array formed by the non-volatile memory 2 洋 of FIG. 6 a. Those skilled in the art will only need some appropriate modifications,

The array 6 〇5 formed by the floating gate non-volatile memory 2 便可 can be replaced by the floating gate non-volatile memory 3 图 of Figure 6b, as described in the figure, each floating gate non-volatile memory #一-Coupled M〇s transistor 22b and memory MOS transistor 2, in the programmed charge-coupled MOS transistor 225 in each column of Q5, the drain, the source and the base are both Connected to the first year old well bias source VTpwl[〇] 645a,...,

VTPW1[1] 645b. Each bit line is called [〇] 640a, BL[1] 64〇b '...' BL[n] 64〇n even 1 yellow to the '歹, j array BTM〇5 is associated with each float The gate of the non-volatile memory is stored in each of the drains of the transistor 235. The base of the storage transistor 235 in each row is connected to a second shallow well bias source VTPW2 [0] 650a'...'VTPW2 [1] 650b associated with each row. The source of each row of storage MOS transistors 235 is connected to an associated source line bias source 655 °. The bit lines BL[0] 640a, BL[l] 640b, ..., BL[n] 640η are connected. In place of the bit line sense amplifier 615, the bit line sense amplifier 615 includes a bit line voltage source to provide the floating gate non-volatile memory 2 to 099103898. Form number Α 0101 page 34 / total 1 page 6 page 0992007313-0 [0091] 201030947 A bias voltage necessary for programming and reading operations. In addition, the bit line sense amplifier 615 further includes a sense amplifier circuit for sensing the data state of the floating gate non-volatile memory 2〇〇 selected during the read operation and providing the sense at the data output port 635. Data to. [Reward-仃 decoding controller 610 includes the first, shallow well bias source VTpwl (4)

..., VTPWltl] 645b, second shallow well bias source VTPW2[G] 65Ga,...,VTPW2[1] 65Qb and source line offset source 655. An address signal 62, a data signal 625, and a control signal 63 are coupled to the row decoding controller 61 and the bit line sense amplifier 615 after being decoded to implement programming and reading of the array & The selected floating gate non-volatile memory 200 must be a green bee [Career _7a, which is the structure of the implementation of the 单 && 4: ^ 发 记忆 记忆 memory 700. The structure differs from germanium in that it adds-selects a hybrid transistor 790. In this embodiment, the =1 floating gate 228 and the electric gate are formed together to form a (four) closure 785. Property ...

The form of the storage MOS transistor 735 is formed in the second shallow diffusion well 220 to form the memory cell 235. The memory cell 735 has a -N Wei 736 - N source m diffused in the second shallow diffusion well 220. The drain 736 is coupled to a bit line voltage source 240. A charge storage floating closure 738 is formed over the gate oxide region 739 by a single layer (4). The material and thickness of the gate oxide region 739 is consistent with the techniques commonly used in current field processes. Deleted in the second shallow diffusion well 220 also formed a selection at the same time 0992007313-0 099103898 Form No. A0101 Page 35 / Total 1 page 6 201030947 A P-type source 793 diffuses in the second shallow diffusion well 22〇. The drain of the select gate transistor 790 is simultaneously the source of the memory MOS transistor 735, i.e., the P-type impurity diffused in the second shallow diffusion well 220. The source of the select gate transistor 790 is coupled to the source line voltage source SL 245. A select gate 792 is formed over the gate oxide region 794 by a single layer of polysilicon, and the select gate 792 is coupled to a select gate control signal 795. The select gate transistor 790 is used to control the connection of the memory M s transistor 735 to the source line 245 during programming and read operations. [0096] As described in Figures 2a and 2b, The programming and erasing operations of the memory MOS transistor 735 are in accordance with the Fowler-Nordheim tunnel edge programming theory. The programming charge coupled MO S transistor 2 2 is one year old storage M 〇 s transistor 735 of the storage capacitor of 8 〇 %. To achieve the coupling ratio 'the physical size of the programmed charge coupled M?s transistor 22 5 is also very large relative to the physical size of the memory MOS transistor 735. The programmed charge-coupled MOS transistor 2 2 is for storing M0S transistors; the size ratio of ··:: "5 ' 735 is greater than ten times ^ ^f .11: ":· * ί •j^;; ϋ 》

Please refer to Figure 7b' for reaching Table 1* to turn the bee to generate f〇w 1 er-

The potential of the Nordheim tunnel edge programming effect is applied to the floating gate. Non-volatile memory. For the selected floating gate non-volatile memory 700, the potential of the first shallow well bias source ντρ\Π 230 is set between about -6. 0V and -7. 0V, and the bit line voltage source BL 240 The potential is set between approximately + 5. 0V and + 7. 0V. For the floating gate non-volatile memory 700 that is not selected, the potential of the bit line voltage source BL 240 is set to the ground reference voltage source (0. 0V). The potential of the first deep well bias source 265 is set to a ground reference voltage source (ο.ον), 099103898 Form No. Α0101, page 36/1, page 6, 0992007313-0 201030947 and the second shallow well bias source VTPW2 255 And the source line bias source 245 is configured to permit floating or selectively set to a ground reference voltage source (0.0V) 'The potential of the selected gate control signal 795 is set to a ground reference voltage source (0. 0V) The gate 790 is selected to be turned off, thus allowing the source 737 to float during the programming operation, and charge can be drawn from the programming coupled floating gate 228 to the drain 236 of the memory MOS transistor 235 [0098] The physical device size of the programmed charge coupled MOS transistor 225 is larger than the memory 73 0 S transistor 73 5 such that the coupling ratio between the programming capacitor and the storage capacitor exceeds 803⁄4. There is a programming power of about -5.0V, the coupling voltage of the ___voltage source VTPW1 23〇 must be hang between the current 0V so that Fowler- low current occurs at the edge of the bungee 2 3 6

Nordheim tunneling effect. The stored electrons are sucked from the floating gate 785 into the drain 236 to reach the gas source write source BL^4. After ~ "one er-Nordheim edge programming operation programming time, the floating gate non-volatile memory < boundary / voltage v 12 is reduced from the erase threshold voltage vtl. After erasing ϋ%, the erase threshold voltage vtl is approximately Between + 3. 0V and about +4. 〇V, and the programming threshold voltage Vt2 is about +1. ον. The erase threshold voltage Vtl should not be negative to avoid over-wiping to make the memory_electric crystal I want the 235 to be depleted. According to the thickness of the gate oxide 739 and the potential of the bit line voltage source team 240 and the floating gate 785, the Fowler-N〇rdheim programming time can be completed in a few microseconds to a few milliseconds. [0099] In the read operation, the potential of the first shallow well bias source VTPW1 23G is set to the verify read potential (Vread) by 099103898 Form No. 1010101 Page 37/106 page 0992007313-0 201030947 The read potential (VREAD) is matched to the floating gate 785. The verify read potential (V) is set to READy between the erase critical potential Vtl and the programmed critical potential Vt2. The bit line is electrically generated by the BL 240 The potential is approximately set at h.ov. The second shallow well bias source VTPW2 255 Source line bias source 245 is disposed on a ground reference voltage source (0. 0V). The first deep well potential bias potential source 265 is provided at the power supply voltage source (VDD) of. [0100] [0101]

If the floating gate non-volatile memory 7 is programmed to operate, then the potential of the floating gate 785 is approximately the second critical potential, and a conductive current is electrically discharged from the bit line. Draw a few moving non-volatile memory 7〇〇 and reach the source line bias source 2 The critical potential of the selective memory 700 is the second data. The data is binary "0" if the floating If the gate non-volatile memory 7 is not selected for programming operation, then its threshold voltage depends on the erase potential vtl, so the n of the floating gate 785 is smaller than the erase boundary potential vtl. When the floating gate is non-volatile, the current is recorded, and

The floating gate non-volatile memory is 7/^44 electric 1 is the erase critical potential \ ^ s I ί~-Λ'6, the binary data read is "i Guangyi 1a single crystal floating gate The operational point of the non-volatile memory vessel is to store the threshold voltage of the M〇s transistor 235 during the Fowler-Noniheim edge programming operation. If any of the memory MOS transistors 235 in the (4) has a negative threshold Voltage, which may cause erroneous sensing data during normal read operation. Increase the selection of gated transistor (4) 〇 to form - "double transistor" floating gate non-volatile memory 7 (10) to eliminate excessive programming operation Wipe I select gate galvanic 099103898 during read operation Form Tungsten A0101 Page 38 / Total 1 〇 6 Page 0992007313-0 201030947 Body 790 Prevents leakage of unselected floating gate non-volatile memory 7〇〇 Current. [0102] FIG. 7c is a schematic diagram of the floating gate non-volatile memory 7〇〇 depicted in FIG. 7a. The coupling capacitor is the aforementioned programmed charge coupled M〇s transistor 225. The storage MOS transistor 735 and the base of the select gate transistor 79 are commonly connected to the second shallow well bias source VTpW2 255 相似 similar to FIG. 4a, the memory MOS transistor 735 and the select gate transistor 79. The germanium may be formed directly on the substrate 205, and the charge coupled dummy 5 transistor 225 may not be required, such that the bulk of the memory MOS transistor 735 and the select gate transistor 790 are directly connected to the ground reference through the substrate 205. Voltage source (0.0V). Say %_:·.. The floating gate non-volatile memory thinks 7.Q|Qincao 2 a floating gate The non-volatile pole memory 200 phase 诜 is the size of the unit. However, due to the floating thyristor non-volatile memory of the present invention, the main determinant is that the programming charge is engaged in the large spacing between the crystals of the crystal 1 crystal 5" in the floating gate non-hybrid ^ ^ _ 700 storage M0S The area added to the selection gate added to the transistor 735 is negligible. [0104] FIG. 8a shows a non-volatile memory boat 800 comprising an array 805 of floating gate non-volatile memory 700 of FIG. 7c. As described in FIG. 7c, each floating gate non-volatile memory The body 70 includes a programmed charge coupled MOS transistor 225, a memory MOS transistor 735, and a select gate transistor 790. The drain, source and base of the programmed charge coupled M〇s transistor 225 of each row in the array 805 are connected to word lines WL[0] 845a,...' WL[1] 845b ' The word line WL[0] 845a,... 099103898 Form No. A0101 Page 39/106 page 0992007313-0 201030947, WL[1] 845b are all connected to the first shallow well bias source VTPW1. Each bit line BL[0] 840a 'BL[1] 840b,...,BL[n] 840η is connected to the storage MOS transistor 735 of the floating floating gate non-volatile memory 700 associated with the array 850 Nothing. The storage MOS transistor 735 of each horizontal column of the floating gate non-volatile memory 700 and the base of the selection gate transistor 790 are connected to the associated second shallow well bias source VTPW2[0] 850a, ..., VTPW2[1] 850b. The source line of each row of select gate transistors 790 is coupled to an associated source line bias source 855. The select gates 829a of the select gate transistors 790 of each row of memory MOS transistors 735 are coupled to associated select gate control signals SG[0] 860a,..., SG[1] 8-60b » ., ::. Bu: ':.::>'. Xinjiang 1 [0105] The main line is connected to the bit line sensing device 815, and the 815 device includes a bit line voltage source. The bit line voltage source provides the necessary bias voltage when programming and reading the floating gate non-volatile memory 700. In addition, the bit line sense amplifier 815 also includes: τ: inductive discharge hex circuit, the sense 1 0| [ri; 1 ;! should be the amplifier circuit can be selected in the floating operation of the floating gate non-h «.if ^ ^ |,- |ji ζ. I jj -·

Volatile memory 700: Data sin data output port 835 provides: J T | I / f read data. [0106] The row decoding controller 810 includes a first shallow well bias source connected to the word lines WL[0] 845a, . . . , WL[1] 845b, and a second shallow well bias source VTPW2[〇] 850a, ..., VTPW2[1] 850b, select gate control signals SG[0] 860a,..., SG[1] 860b and source line bias source 855. In addition, an address signal 820, a data signal 825, and a control signal 830 are coupled to the row decoding controller 810 and the bit line sense amplifier 815 after being decoded to implement the programming operation and reading the array 805 for the 099103898. Form No. A0101 Page 40 / Total 106 Pages 0992007313-0 201030947 Selected floating gate non-volatile memory 700 necessary control and partial waste β [〇1〇7] Please refer to FIG. 8b, the non-volatile memory 800 includes An array 805 of floating gate non-volatile memory 7A of Figure 7c. In this embodiment, the structure of the floating gate non-volatile memory 70〇 is essentially reversed, and the gate transistor of each floating gate non-volatile memory 7〇〇 on the straight line of the array 805 is selected. The drain of 790 is correspondingly connected to one bit line BL[〇] 840a 'BL[1] 840b,...,BL[n] 840η and the source of the storage MOS transistor 225^

[0109] [0109]

The benefits of connecting the drain, source and base of all of the programmed charge coupled MOS transistors 225 within the array 805 to the common line CWL 845 and to the array in the floating gate non-volatile are The size of the physical area of the array 8 〇 5 can be saved. Each of the bit lines BL[〇] 840a, BL[1] 840b, ..., BL[n] 840n corresponds to the stored MOS power connected to the array floating gate non-volatile memory 700. The floating gate of each row of non-volatile memory 700〇f^§s the base of the transistor 735 is connected to the corresponding second shallow well bias source VTPW2[〇] 85〇a,...,

, the common word. This embodiment 5 is compared to Fig. 8a VTPW2[1] 850b. The source of each row of memory MOS transistors 735 is coupled to a corresponding source line bias source 855. The select gate 792 of each select gate transistor 790 of each column of memory MOS transistors 735 is coupled to a corresponding select gate control signal SG[0] 860a, ..., SG[1] 860b. [0110] 099103898 The bit line is connected to a bit line sense amplifier 815, which is placed on the form number A0101. Page 41/106 page 0992007313-0 201030947 The amplifier 815 includes a bit line voltage source, the bit line The voltage source provides the necessary bias voltage when programming and reading the floating gate non-volatile memory 700. In addition, the bit line sense amplifier 815 includes a sense amplifier circuit that senses the data state of the selected floating gate non-volatile memory 700 during the read operation and is provided at the data output port 835. The data read. [0112] The row decoding controller 810 includes a first shallow well bias source connected to word lines WL[〇] 845a,...' WL[1] 845b, and a second shallow well bias source VTPW2[0] 850a , signal SG [〇] 860a. In addition, VTPW2[1] 850b, select gate control 'SG[1] 860b and source: polar line bias source 855, an address signal 82, and a digital signal 830 are connected to the line decoding Shou 358 after being decoded: #表·Secondary line sense amplifier 815 'to achieve the necessary control and bias for the selected floating gate non-volatile memory 7 when operating the array and reading the array gg 5 . ❹ In all of the above embodiments, the edge of the Nordhe i m is determined by the effect of reducing the criticality of the transistor. In the general one: £_可: _ single-layer polycrystalline rock floating gate non-volatile memory, the erasing operation is erased by ultraviolet light. Erasing by ultraviolet light irradiation has a disadvantage for the single-layer polycrystalline dream floating gate non-volatile memory of the present invention, and if the module containing the floating gate non-volatile memory is packaged for blocking ultraviolet light, then It is impossible to achieve repetitive programming and erasing. In the absence of specialized erase and programming equipment, it is not possible to modify the data within the package again. Therefore, what is needed is a device that combines programming and erasing capabilities in the same-floating gate non-volatile memory. Different from one-time programmable single layer multi 099103898 Form No. A0101 Page 42 / Total 1〇6 Page 0992007313-0 201030947 Crystal floating gate non-volatile memory, the programming or erasing endurance period of the invention exceeds one thousand Times. Referring to FIG. 9a, yet another embodiment of the single layer polysilicon floating gate non-volatile memory 900 of the present invention achieves the requirement of avoiding ultraviolet light erasing by electronic programming and erasing capabilities. The programmed charge storage unit 7A includes a program charge MOS transistor 225, a memory MOS transistor 735, and a select transistor 790. Their construction and function are the same as those set forth in Figures 7a*7b. A wiper element 905 of a P-type material is formed in the third shallow diffusion well 915. The third shallow diffusion well 915 is formed in a second deep diffusion well 910 formed of an N-type material and the second deep diffusion well 91 is formed on the surface of the substrate 2〇5. The first deep diffusion ^ihg 袴钵 择 多 多 梦 梦 梦 梦 梦 梦 。 。 。 增加 增加 增加 增加 增加 增加 增加 增加When the - _ source 921 and the 汲-type 9 9 2 2 are diffused in the ^ 3 ^ well 9 丨 5, a wipe-off charge MOS transistor 920 β - 源 source diffusion 921 and Ν will be formed. Type bungee diffusion such as 2 呷 呷 荠 I I I I I 弘 弘 弘 弘 弘 弘 弘 弘 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [0114] -. . Above 924, and formed by a single layer of polysilicon. The material and thickness of the gate oxide region 924 are consistent with techniques commonly used in current CMOS field processes. The erase coupling floating gate 923, the program coupled floating gate 228, and the charge storage floating gate 738 are commonly connected to form a floating gate 985. [0115] The second deep diffusion well 910 is connected to the second deep well bias source 930 via a connection diffusion point 925. The p-type expansion junction 935 connects the third shallow diffusion well 915 to the third shallow well bias source VTPW3 940 » the P-type substrate is connected to the ground reference voltage source (〇.〇v) through the connection diffusion point 270. 099103898 Form No. A0101 Page 43 of 106 0992007313-0 201030947 [〇116] The floating operation of the non-volatile memory 900 is based on Fowlei·.

The channel effect of the Nordheim channel tunneling effect is required to perform a programming operation and a wiper operation than the Fowl-(10) ray effect described in (4) of the above embodiment. Table 2 is a comparison of the voltage requirements for the floating gate non-volatile = memory-gamma Urn called the correction effect and the side effect. Saki

Fowler-Nordh er- ei [0117] Table 2 [0118]

Figure 9b provides the potential e SFowler-Nordheim channel tunnel erase operation required for the present embodiment of the present invention. The erased charge coupled MOS transistor 920 is from its third shallow diffusion well 915. The channel injects electrons into the erase coupling floating gate 923 and causes the electrons to pass through the gate gate oxide region 924 to the floating gate 985. The erase coupled floating gate 923 acts to couple a negative floating gate voltage to the floating gate 985, thereby inducing the execution of Fowler_

Nordheim edge tunnel programming operations. During the channel erase operation or edge programming operation of the floating gate non-volatile memory unit 900, the 099103898 form number A0101 page 44/106 page 0992007313-0 201030947 erase the charge to engage the MOS transistor 92G The programming charge chamber hall 225 and the storage_transistor 735 must be sized such that the programming operation and the erase operation can be performed under 7. 〇v. [0119] During the Fowler-Nordheim channel tunnel erasing operation, when the potential of the first well bias source VTPW1 230 is set to approximately +7 〇v and is applied to the first shallow diffusion well 215, the floating gate The junction 985 and the storage floating gate 228 must have a potential of approximately + 6 3V. This will cause a potential of approximately + 6. 3V to be coupled to the floating gate 985. The area of the programmed charge coupled MOS transistor 225 is equal to the erase charge coupled M 〇s transistor 92 〇 and the stored MOS transistor 735. The potential of the bias source VTPW3 940 is set to be offset by the third shallow diffusion well 9丨. Further, the potential of the erase control line 950 is set to about -7.0 V to additionally ensure that the potential of the channel region 975 of the third shallow diffusion well 915 is set to about -7. 〇V# is floatable or Set to

The potential of the I-two shallow expansion well 220 is two shallow (D. 0V). The bit ., , · C- ' ί^: ' Line voltage source BL 240, source line and "Mold ||, 2+45 and select gate control. V ?F^iC© No. 795 are set To the ground reference '^ bit (〇〇v) ^ The potential of the first deep well bias source 265 and the first shallow well bias source VTPWi 230 is set to approximately +7.00V. The potential of the second shallow well bias source VTPW2 255 and the second deep well bias source 930 can be floating or set to a ground reference potential (0.0V). When the potential of the third shallow well bias source VTPW3 940 is set to about -7. 0V to bias the third shallow diffusion well 915, the gate oxidized region 924 of the erased charge coupled MOS transistor 920 will have approximately 13. The voltage of 3V is 099103898 Form No. 1010101 Page 45 / Total 1 〇 6 Page 0992007313-0 [0120] 201030947 Between the kinetic gate 985 and the third shallow diffusion well 915. The erased charge-transferred MOS transistor 92G has an oxidized region thickness that is sufficiently thick to cause Fowler-Nordheim channel tunneling. Electrons in the third shallow diffusion well 915 are injected into the floating gate junction 985 via the channel gate deuteration region 924 of the erase charge coupled MOS transistor 920. Since the electric field of +13. 3V is across the entire channel 975 of the erased charge coupled M〇s transistor 92, the erase operation is defined as the Fowler_N〇rdheim channel erase operation. [0121] Due to the large size of the programmed charge coupled MOS transistor 225, the gate oxygen

The electric field of the 229 is only +〇. 7V during the erase operation. This prevents all tunneling effects of programming charge coupled M0S electro-crystals 2,5. Similarly, when the potential of the floating gate junction 985 is large + 6) 3 V, the shallow diffusion well 220 is biased to the ground reference potential (the voltage level of the 氧化 阑 氧化 oxidation zone 739 is only + 6. 3V). 'It is not big enough to produce F〇wler_

Nordheim's accompanying effect. Thus, in the erasing operation, only the erased charge is combined with the M0S electric crystal boat 9 20 having r heights of the electric lift to cause the Fowler-Nordhei, i^;it effect during the erasing operation. In: erase operation is completed ^ r 『Τ\/

Later, since the electrons are floating, the threshold voltage of the memory MOS transistor 735 is increased. In the present embodiment, for the power supply waste of _ + 3.0 V, the target value of the erase threshold voltage of the floating gate non-volatile memory 9 被 is designed to exceed the potential of + 4. 〇V. [0122] In the Fowler-Nordheim edge tunnel programming operation, the first well bias source VTPff1 230 is set at approximately -7. 0V and applied to the first shallow diffusion well 215. The bit line voltage source BL 240 is set at a potential of approximately + 5. 〇v to be applied to the selected floating gate non-volatile memory 900, or is set at a ground reference potential (0.0V) to be applied to Float 099103898 Form No. A0101 Page 46 / Total 106 Pages 0992007313-0 201030947 Non-volatile memory 900. The erase control line 95 is set at the ground reference potential (0.0V). The second shallow diffusion well 220 can be floated or set at a ground reference potential (ο. ον). The source line bias source 245 is allowed to float or set to a ground reference potential (〇. 0V). The third shallow well bias source VTPW3 940, the erase control line 950, the select gate control signal 795, the first deep well bias source 265, and the second deep well bias source 93 are all set to the ground reference potential (0.0V). » [0123] ❹ When the above bias voltage is applied to the floating gate non-volatile memory 鳢9〇〇, since the 90% coupling ratio is from the _ 7 〇v potential of the first shallow diffusion well 215 through the storage MOS transistor 735 'The voltage of the floating closed junction 985 is about _

6.3V. Since the bit line voltage source ΒΙ/2·4 〇 is selected by the gate control signal 795 to control the residual margin 〇 ν), the source 737 of the memory MOS transistor 735 is floating and is stored at m 〇 S μ 0V, And the Fowler-Nordheim edge tunnel programming effect is induced at the drain 736 of the transistor 735. The electrons continue to pass from the floating 1 junction 9 through the twist 736 into the second shallow diffusion well 22q. The voltage of the sacred boundary is reduced by the reference [0124] «a period of programming without a decision 文 磬 约 / about +3 〇 v to about 4. 0V erase the critical potential is reduced to about _ 丨〇 v to about 丨The programming threshold voltage expectation. In the present embodiment, the negative threshold voltage of the memory MOS transistor 735 is allowed due to the presence of the dual transistor unit structure of the MOS transistor 735 and the selection of the closed-electrode crystal 790. Since the select gate transistor 790 is a modified NMOS device, by setting the select gate control signal 795α to the ground reference potential (0.0V), all the negative voltages of the memory of the MOS transistor 735 can be leaked. The current is selected by the gate transistor 099103898 Form No. 1010101 Page 47 / Total 1 〇 6 Page 0992007313-0 201030947 [0125] 79 〇 blocked. Read operation Referring to Figure 7b, the potential of the third shallow well bias source VTPW3 940 and the erase control line 950 is set to the ground reference potential (〇〇Ό. The second deep well bias source 910 can be floated or set to Ground reference potential (0.0V). Even if the erase programming potential is large, the detection of the data state is the same as above. [0126] Referring to Figure 8a, a set of floating gate non-volatile memory 9 is arranged in rows and The columns are similar to the array shown in Figure 8a. The necessary bias and control signals are applied to the row decode controller 81A and the bit line sense amplifier 815 to complete the floating gate non-swinging, sample recording, Wiping and editing

Operation [0127] 1 and ground 4, #: Please refer to the schematic diagram of a cross-sectional view of an embodiment of the single-layer multi-turn V floating wheel non-volatile memory 1000 of the present invention. In the present embodiment, the single-layer polysilicon floating gate non-volatile memory 1 is formed on the P-type substrate 1005. The first second deep diffusion well 1014 of an n-type impurity is increased in the process of the surface of the substrate 1005 in the process of the 1st 12th ...

Add a treatment layer to get. The first deep diffusion well 1012 is coupled to the first deep well bias source 1030 through an N-type connection point 1062. The second deep diffusion well 1014 is coupled to the second deep well bias source 1 065 through an N-type connection point 1060. The P-type substrate 1005 is connected to the ground reference voltage source (0. 0V) through the connection diffusion point 1070. The first shallow diffusion well 1015 of the P-type impurity is formed in the first deep diffusion well 1012, and the second shallow diffusion well of the P-type impurity 1020 is formed in the second deep diffusion 099103898 Form Compilation A0101 Page 48 / Total 106 Page 0992007313-0 [0128] 201030947 Well 1014. The charge coupled MOS transistor 1025 is connected as a capacitor. The charge coupled MOS transistor 1025 is formed on the surface of the first shallow diffusion well 1015, and the charge coupled MOS transistor 1025 has a source 1 026 and a drain that diffuse into the N-type impurity in the first shallow diffusion well 1015. 1027. The source 1026, the drain 1〇27 and the first shallow diffusion well 1〇15 are commonly connected to the first shallow well bias source VTPW1 1050. The first shallow diffusion well 1015 is connected to the first shallow well bias 1〇5〇 through the connection diffusion point 1016. The transfer floating gate 1028 is formed by a single layer of polysilicon in the gate oxide region 1〇29. Wherein the material and thickness of the gate oxide region 1029 are consistent with the techniques commonly used in current CMOS field processes.

.il|·^· ' IPjS

[0129] After 0, the second shallow diffusion well 1〇2〇^| The dance megaphone 1035 Nuo to the younger shallow diffusion well. ‘·., 士! ::ΐ Xiao 1038 in the gate oxidized zone of the j. The material of the coffee 11 〇 39 1020 Ν 汲 10 1036 and Ρ source 1037. The drain 1036 is coupled to a one-bit line voltage source BL 1040, which is coupled to a source line bias source 1〇45. Charge storage _ Ze 鶊 | 10 3 9 by a single layer polycrystalline ί ▲ Wide PropeiT ·; and thickness is consistent with the current commonly used technology in the field of CMOS. The second shallow diffusion well 1020 is connected to the second shallow well bias source VTPW2 1 055 through a connection point 1021. [0130] Meanwhile, a select gate transistor 1090 is formed in the second shallow diffusion well 1020. The N-type source 1093 of the select gate transistor 1090 diffuses within the second shallow diffusion well 1020. The drain 1 〇 37 of the selected gate transistor 1090, that is, the source 1037 of the MOS transistor 1035, is formed by diffusion of an N-type impurity in the second shallow diffusion well 1020. The source 1 093 of the selected gate transistor 1 090 is connected to the source line voltage source SL 1045. The selection 099103898 Form No. A0101 Page 49 / Total 1 Page 6 0992007313-0 201030947 The selection gate 1〇92 of the gate transistor 1090 is formed by a single layer of polysilicon in the gate oxide region 1〇94. The select gate 1〇92 is connected to the _select gate control signal 1095. The select gate transistor 1090 is used to control the connection of the memory M〇s transistor 1〇35 to the source line 1045 during programming and read operations. [0131] A similar operation to the single-layer polysilicon floating gate non-volatile memory 〇〇9〇〇 in Figure 9a is the use of Fowler-Nordheim edge tunneling, while the erase operation uses the Fowler-Nordheim channel tunneling effect. In this embodiment, the charge coupled M〇s transistor 〇1〇25 is required to perform Fowler-Nordhei* pass-through erase, operation and Fowler- built in the same wafer.

Nordheim Edge Programming Operation In Figure 9a, the memory MOS transistor

[0132]

The Nordheim channel erase operation will be increased by β. The memory of the M〇s Cryptography 1035 will be reduced after the Fowler-Nordheim edge programming operation. Electron 礴 § § zero shoulder body 丨〇 3 5 gate oxidized zone 1039 is injected into the float to increase the storage M〇s • .:.':: #

The threshold voltage of the transistor 10 3 5 . f":5 [0133] Please refer to FIG. 10b' During the erase operation, the potential of the first shallow well bias source VTPW1 1 050 is set to approximately +7.0 V to be applied to the charge coupled MOS transistor 1025. The first shallow diffusion well 1015. The potential of the second shallow well bias source VTPW2 1055 is set to approximately -7.0 V to be applied to the second shallow diffusion well 1020. The potential of the source line voltage source 1 045 is set to about -7. 0V. The bit line voltage source 1040 is separated from the drain 1036 storing the MOS transistor 1035 such that the pole 1036 floats. The potential of the first deep well bias source 1 030 and the first deep diffusion well 1〇12 is set to approximately 099103898 Form No. Α0101 Page 50/Total 1〇6 Page 0992007313-0 201030947

[0134] 7. [0135] + 7. OV 'to prevent unwanted forward currents in the Fowler-Nordheim channel erase operation while the first deep diffusion well 1〇12, the second deep diffusion well 1014' first The shallow diffusion well 1〇15 and the second shallow diffusion well flow in 1〇2〇. The potential of the gate control signal 1 095 and the second deep well 1 〇 65 is set to the ground reference voltage (0.0V). The same as the previous cell structure, the size of the MOS transistor 1025 is larger than that of the memory cell 1035. The ideal size ratio between the charge coupled MOS transistor 1025 and the memory MOS transistor 1035 is 10 times or more to achieve a coupling ratio of more than 〇%, thereby reducing the high voltage necessary in a low voltage logic process.七七J Climb: ί' 'II Following f As mentioned above, due to the ratio of the first shallow gluten ( ^ (9090 plus the potential through the charge coupled container is about +7.0 V, the bias will force the floating gate The potential of the junction 1〇{^5 is approximately +6' 3V. When the potential of the second shallow diffusion well 1〇2〇 is approximately _7. “When a large electric field will be established in floating bamboo, 5 and 2 P diffusion The closed-end oxidation of the channel between the wells 1020 is 10 mothers, and the T release is g|〇wler_

The second shallow diffusion well 1020 of the Nordheim channel tunnel is injected into the charge storage floating gate 1038 to the floating gate junction 1〇85 through the i-channel gate oxidation region 1〇39 of the storage MOS transistor 1035, so that the channel is erased. After operation, the number of electrons of the floating gate junction 1 085 will be increased, so that the threshold voltage of the memory MOS transistor 1035 is increased to an expected value of about 4.0 V, which is suitable for the floating gate non-volatile memory. A supply voltage source (vdd) of approximately 3.0 V used by the array. During the Fowler-Nordheim edge tunnel programming operation, the potential of the first well bias source VDNW1 1030 is set to approximately _7 〇 v to be applied to 099103898 Form No. A0101 Page 51 / Total 106 Pages 0992007313-0 201030947 First Shallow diffusion well 1015 ^ The potential of the bit line voltage source BL 1〇4〇 is set to approximately + 5. 0V to be applied to the selected floating gate non-volatile memory 1000, or set to the ground reference potential (〇〇v) to be applied to the non-volatile memory of the floating gate that is not selected. The second shallow well bias source VTPW2 1055 is isolated or connected to a ground reference potential (0.0V) such that the second shallow diffusion well 1020 can be allowed to float or be set to a ground reference potential (〇. ον). The source line bias source 1〇45 can be allowed to float or set to the ground reference potential (〇.0V). The select gate control signal 1095, the first deep well bias source 1030, and the second deep well bias source 1〇65 are all set to ground reference silver (1). ·. - · · ^ [0136]

When the above-mentioned bias voltage is applied to the floating gate, the money mouth; when 〇〇〇, since 90% of the coupling is transmitted from the first shallow diffusion well through the charge-transferred MOS transistor 1025, it is floating The electricity house of the gate junction ^85 is approximately -6. 3V. Since the potential of the bit line voltage source BL 1040 is set at + 5. 0V., and the gate is controlled, the signal is selected. No.||〇95 is being controlled] in the ground reference potential CO. 0V:) ‘so store nos push|1|return ^8‘1〇37 is floating propo 卞莉

The '’健H〇S electric crystal 1035's card 纟Ϊρβ6$ will occur F〇wier one _ face 嚷琴+5 contend.::w \ β ψ j I ή: -SiuieS' - -»· ~

Nordheim edge tunnel programming effect. Electrons enter the second shallow diffusion well 1020 from the floating gate 1 〇 85 through the drain 1 036. The threshold voltage for storing the MOS transistor 1035 is reduced from a threshold voltage of about + 3. 0V to +4·0V to a programmed threshold voltage of about + 1 after a predetermined programming time has elapsed. The advantage of the non-volatile memory 900 in the single-layer polycrystalline floating gate non-volatile memory 1 〇0 0 圏9a of the present embodiment is that only one nm 〇S capacitor (charge-coupled MOS transistor 1025) is required. Implementation built in the same crystal 099103898 Form compilation A0101 Page 52 / Total 1 page 6 page 0992007313-0 [0137] 201030947 [0138] [0139] ❹ [0140] .❹ [0141] On-chip F〇wler-Nordheiin wipe In addition to operation and F〇wlerN〇rdheim programming operations. Moreover, the physical size of the floating gate non-volatile memory 1 较 is small, so that the cost of the substrate 1025 can be reduced. A set of floating gate non-volatile memory 10's can be arranged in rows and columns similar to the array shown in Figure 8a. The necessary bias and control signals are applied to the row decode controller 810 and the bit line sense amplifier to effect the erase and program operation of the floating gate non-volatile memory. Referring to Figure 11a, the structure of another embodiment of the single-layer polycrystalline material _ volatile memory 11 本 of the present invention is substantially the same in line except for the second deep diffusion 汫W0 There are many second deep diffusion wells 1110 replaced. The second deep expansion. The deep well source of the deep well is 113G. Erase the unit replacement. In FIG. 11a, the programming and charge storage device 7A includes a programmed charge coupled MOS transistor 225, a memory MOS transistor 735, and a select gate transistor 790. The select gate is electrically crystallized 79 丨 _ ^ (^# The structure and effect are the same. The charge coupling % is erased, including two p-types and H22 formed in the second deep diffusion well 1110, and the erased charge-coupled MOS capacitor 1020 is connected to the erase line control signal 114 The erase coupling floating gate 1123 is coupled to the charge storage floating gate 738 and programmed to engage the floating gate 228 to form a floating gate 丨 185. In this embodiment, the erase operation is non-volatile from the single layer polysilicon floating gate of Figure 9 & The F〇wler_N〇rdheim tunnel tunnel erase operation of the memory 900 is changed to the Fowler-Nordheh edge tunnel erase operation, thereby further reducing the 099103898 form when performing write (program) operations built on the same-wafer No. A0101 Page 53 / Total 1 〇 6 Page 0992007313-0 201030947 [0142] Operating voltage. Please refer to Figure lib, which will describe the Fowler_NGrdheim edge tunnel erasing operation. The first - shallow well VLpwi 23〇 and Dijon Shallow expansion The potential of the well 215 is set to approximately + 7 〇 v. The second shallow well bias source VTPW2 255 is isolated or set to the ground reference potential (〇〇v) such that the second shallow diffusion well 22G can float or The shallow diffusion well 215 is set to the ground reference potential (uv)»the second deep well eccentric source 113() is isolated or set to the ground reference potential (〇〇V) such that the second deep diffusion well 1110 can float or be set to Ground reference potential (〇. 〇v) connected to the diffusion regions 1121 and 1122 of the PMOS erase charge coupled capacitor 112A

The potential of the line control signal U40 is erased in the ash 5·〇ν. The first deep well bias source 265 and the first deep-expanded to approximately +7.0V+bit line voltage source BL240, source select bias source 245, and select gate control signal 795 are all set to ground reference potential (〇 〇ν). [0143] The situation described above is a significant difference between the bead sound and the dance pole diffusion regions 1121 and 1122 of the charge light coupling capacitor 1120. PMOS erased electric Wei He wounded mixed floating gate

1123 is then brought to the potential of about -6·3V ^ because the coupling ratio of the PM〇s erased charge capacitor 1120 to the programmed charge coupled M〇s transistor 225 and the stored MOS transistor 735 is very large. (approximately 9〇%), such that the coupling of the + 7.〇¥ voltage from the first shallow diffusion well 215 forces the floating gate junction 1185 and the erased floating gate 1123 to have a potential of + 6 3V. When the potential of the erase line control signal is -5' (^, the pM〇s erased charge coupled capacitor 1120 will remain in a non-conducting state. This will cause the Fowler-Nordheira edge tunnel erase to act at the source and the 汲Pole diffusion 099103898 Form No. A0101 Page 54 / Total 106 pages 0992007313-0 201030947 The edges of the regions 1121 and 1122 are as previously described, such potentials are prevented in the first deep diffusion well 210, the second deep diffusion well 1110, The first shallow diffusion well 215 and the second shallow diffusion well 220 have undesired forward currents. [0144] The potential of the floating gate non-volatile memory 1100 in the present embodiment during the Fowler-Nordheim edge tunnel programming operation The potential of the potential of the first shallow well bias source VTPW1 230 and the first shallow diffusion well 215 is thus set to about -7. 0V. The potential of the bit line voltage φ source BL 240 is set to approximately +/- 5.0V to be applied to the selected

Select the floating gate non-volatile memory 艟ιιαο, or set to ground reference potential (O.OV) memory 1100. The well 215 is set to the ground reference potential (〇. 〇ν), and the second shallow well bias source VTPf2 255 is isolated or set to the ground reference potential (〇.ον), so that the second shallow diffusion well 2 2 0 floats ; or the thief set the ear to the ground reference potential (0. 0V:). The erase line control signal W erases the charge light-r i〇fj^rh. The diffusion region 1 〇 21 of the capacitor 1020 is set to the ground reference potential (0·0 V). The first deep well bias source 265, the first deep diffusion well 210, and the second deep diffusion well 111A are set to a ground reference potential (〇 〇 y). The select gate control signal 795 and the bias source 245 are set to the ground reference potential (0. 0V). [0145] During the programming operation, the potentials of the select gate control signal 795 and the erase line control signal 1140 are controlled. Ground reference potential (〇〇v) to turn off select gate transistor 790 so that the source of residual crypto transistor 735 can float to aid Fowler-Nordheim edge tunnel programming operation 0992007313-0 099103898 Form No. A0101 55 Page / Total 106 pages 201030947 ° When the voltage in the diagram lib is applied to the floating gate non-volatile memory 11 00 'a low current Fowler-Nordheim edge tunneling phenomenon will occur in the drain of the storage MOS transistor 735. As such, electrons will be absorbed from the floating gate 1185 to the drain 736 of the selected floating gate non-volatile memory 1100. After the Fowler-Nordheim edge programming operation, the threshold voltage will be reduced to a range from -1. 〇V to 1. 〇v. [0146] At the time of the read operation, the first shallow well bias source VTPW1 230 is set to a potential for verifying the read bias voltage (V), after which the verification reads the waste

The potential of (V) is coupled to floating gate 1185. The verification read

Potential (V

) is set between the programming threshold potential Vt2. The potential of the bit line reject source BL 240 is set to approximately 1. 0V «• The second shallow well bias source VTPW2 255, the erase control signal 114 0 and the source line bias source 2 4 5 Insults Bend Qin test voltage source (0. 0V). The first deep well bias source ^the second well bias source 255 is set to the supply voltage source (VDD). The selected gate control signal 795 of the floating gate non-volatile memory 1100 is set to the power supply voltage source ( VDD). The selection of the floating gate non-volatile memory 11〇〇 that is not selected The gate control signal 795 is set to the ground reference potential (〇 〇ν). [0147]

If the floating gate non-volatile memory 1100 is programmed to operate, the potential at the floating gate junction 1185 is approximately at a second threshold voltage, and there is a conduction current from the bit line voltage source BL 240 to the source line bias source 245. Flow through the floating gate non-volatile memory. When the critical potential of the floating gate non-volatile memory 1100 is the second critical potential vt2, the read data is 099103898 Form No. A0101 Page 56 / Total 1 Page 6 0992007313-0 201030947 [0148]

[0149]

It is designated as a binary "〇". If the floating gate non-volatile memory 1100 is not selected for programming operation, its threshold voltage is still at its erase critical potential Vtl. Therefore, the potential of the floating gate 1185 is smaller than the erase critical potential V11. When the floating gate non-volatile memory 1丨〇〇 has no conduction current, and the floating gate is non-volatile, the threshold voltage of the It body 1100 is erased. At the threshold voltage, the read data is designated as a binary "1". Similar to other embodiments, the physical size of the programmed charge coupled MOS transistor 225 is greater than the physical size of the combination of the memory M?s transistor 735 and the programmed charge coupled m?s transistor 225. The program, the physical size of the process charge MOS transistor 225, stores the total area of the M0s cell 735 and the programmed charge coupler to achieve a coupling ratio of more than 90%, thereby reducing the necessary potential so that the logical product of the general low voltage The bulk circuit process can also be used to fabricate a volatile device that includes a floating gate non-volatile memory bank. A set of floating gate non-volatile memories _ arranged in rows and columns is similar to the array shown in Figure 8a. And control signals are applied to row decode controller 810 and bit line sense amplifier 815 to erase and program the floating gate non-volatile memory 1 described in this embodiment. [0150] A single layer polysilicon floating gate non-volatile memory includes a MOS capacitor and a MOS transistor, the fabrication dimensions of which allow the use of current low voltage logic integrated circuit processes. The first electrode plate of the MOS capacitor is connected to the gate of the MOS transistor such that the gate of the MOS transistor can float and form a floating gate of the floating gate non-volatile memory. The second electrode of the MOS capacitor 099103898 Form No. A0101 Page 57 of 106 0992007313-0 201030947 The plate is usually the 汲_pole diffusion, source diffusion and bulk of the MOS transistor. The drain of the MOS transistor is connected to a one-bit line voltage source, and the source of the MOS transistor is connected to the source line. The physical size of the m〇S capacitor is relatively large compared to the physical size of the MOS transistor. In the present embodiment, the physical size of the MOS capacitor is more than 10 times or more larger than the physical size of the MOS transistor. [0152]

The physical size ratio between the MOS capacitor and the MOS transistor provides > a large coupling ratio of greater than 80%. When a voltage is applied to the second electrode plate of the MOS capacitor, the large coupling ratio enables most of the voltage at the second electrode plate of the MOS capacitor to be coupled to the floating 閛 junction * 麇 is applied to the M 〇 s transistor

The drain or source, to establish an electric field in the M0S transistor, so that F〇wler-N〇rdh^^|i^^ can be activated. When the voltage at the second electrode plate is the negative electrode and the voltage of the MOS transistor applied to the drain (or source) is the positive electrode, the charge at the floating gate is absorbed to program the floating gate non-volatile memory dream. In addition, the electrical history of the second electrode plate is the positive electrode's and is applied to the bulk of the MOS transistor. The charge of the voltage ^ floating gate is injected to erase the floating gate non-volatile memory. In summary, the present invention meets the requirements of the invention patent, and the patent application is filed according to law. However, the above is only a preferred embodiment of the present invention, and those who are familiar with the art of the present invention are in accordance with the spirit of the present invention. Modifications or changes should be covered in the following patent application. [Simplified Schematic] Figure 1 is a schematic representation of a conventional single-layer polycrystalline dream floating gate non-volatile memory 099103898 Form No. A0101 Page 58 / Total 106 pages 0992007313-0 [0153] 201030947 [_2a is a cross-sectional view of the first preferred embodiment of the single-layer polycrystalline material gate non-volatile memory of the present invention. Figure 2b is a single Figure 2a Schematic diagram of the potential of the layered polycrystalline material _ volatile kelong's electric source. _] is the cross-sectional view of the second preferred embodiment of the single-crystal kinetic volatility (four) of the present invention. [_® 4a is the first reference of the non-volatile neon memory of the single-layer polycrystalline material A cross-sectional view of an embodiment. [0159] FIG. 4b is a schematic diagram of the potential of a voltage source of a single-layer polycrystalline material in a non-uniform memory in FIG. 4a. 2::, 响卜':_ , Λ.P t =^v', s, Figure 5 is a cross-section of a single-layer polycrystalline raft of the present invention

Hair transplant: the fourth comparison of the corpus body [0160] ❹ [0161] Fig. 6a is a schematic diagram of the single 'polycrystalline hair in Fig. 2a, moving non-volatile memory. '0 °·,.Ι»Γ.Ι: :Ϊ *ri%!iecluai _ is a schematic diagram of 中3. Medium memory _], which is an array of single-layer polycrystalline gate non-volatile memory in Figure 2a. Figure 7a is a cross-sectional view of a fifth preferred embodiment of the single layer smashing transfer memory of the present invention. _ Figure 71) is a schematic representation of the potential of the voltage source of the single-layer polysilicon floating closed non-volatile memory of Figure 7a. 099103898 Form No. A0101 Page 59 / Total 1 Page 6 0992007313-0 201030947 [0166] [0168] [0170] [0170] [0175] [0175] [0176] 099103898 FIG. 7c is a schematic diagram of the single-layer polysilicon floating gate non-volatile memory of FIG. 7a. Figure 8a is a schematic illustration of the single layer polysilicon floating gate non-volatile memory array of Figure 7a. Figure 8b is a schematic illustration of a sixth preferred embodiment of the single layer polysilicon floating gate non-volatile memory of Figure 7a. Figure 9a is a cross-sectional view showing a seventh preferred embodiment of the single-layer polysilicon floating gate non-volatile memory of the present invention. Figure 9b is a schematic illustration of the potential of the voltage source of the single-layer polysilicon floating gate non-volatile memory of Figure 9a. Figure 10a is a cross-sectional view of an eighth preferred embodiment of the single layer polysilicon floating gate non-volatile memory of the present invention. Figure 10b is a schematic illustration of the potential of a voltage source for a single layer polysilicon floating gate non-volatile memory of Figure 10a. Figure 11a is a cross-sectional view of a ninth preferred embodiment of a single layer polysilicon floating gate non-volatile memory of the present invention. Figure lib is a schematic illustration of the potential of a voltage source for a single layer polysilicon floating gate non-volatile memory in Figure 11a. [Main component symbol description] NVM unit: C100 First programming transistor: M106 Second programming transistor. Μ10 4 Form number Α0101 Page 60/Total 106 page 0992007313-0 201030947 [οΐπ] Storage transistor: Μ102 [0178] Precharge circuit: 108 [0179] Power supply voltage source: VDD [0180] Floating junction: 110 [0181] First programming voltage source: VEE [0182] Second programming voltage source: VPP [0183] Reference [0184] Word line Voltage source: WL output bit line: Vo(BL) [0185] Floating gate non-volatile memory: 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100 [0186] Substrate: 205, 405, 1005 [0187] First deep diffusion well: 210, 410, 101 · f [0188] First deep well bias source: 265, 465, 10 plus.. # 1 [0189] Connection diffusion point: 270, 470 411^416, 250, 1070, 1021 [0190] First shallow diffusion well: 215, 1015 [0191] Second shallow diffusion well: 220, 1020 [0192] Programming charge coupled MOS transistor: 225, 425 [0193] Charge-Coupled MOS Capacitor: 325 [0194] Source: 226, 237, 426, 437, 737, 1026, 1037, 1093 099103898 Form No. 0101 Page 61 / 106 pages 0992007313-0 201030947 [0195] Bungee: 227, 236, 427, 436, 736, 1027, 1036 [0196] First shallow well bias source: VTPW1 230, VTPW1[0] 645a ,..., VTPW1[1] 645b , VTPW1 1050 [0197] Gate oxime zone: 229, 239, 429, 439, 739, 794, 924, 1029 [0198] Storage MOS transistor: 235, 435, 735, 1035 [0199] Source Line Bias Source: 245, 445, 655, 855 [0200] Charge Storage Floating Gate: 238, 438, 738, 1038 © [0201] Second shallow well bias source: VTPff2 255, VTPW2 [fl] 650a,..., VTPW2 [1] 650b ' VTPW^t J: 850a » - * VTPW2[ 1 ] 850b, VTPW2 1055 ' [0202] Channel area: 280, 275, 975 [0203] Programmable coupling floating gate: 228, 3得得, 08*, 争28 : 11 11J : 1 ^ * i [0204] Floating gate: 285, 385, 48^ "Turtle, 5, Aunt, 985, 1085, 1185 Office ® [0205] Bit line voltage Source: BL 240, BL 440 [0206] Shallow diffusion well: 415 [0207] Shallow well bias source: VTPW1 430 [0208] Charge coupled M0S capacitor: 525 [0209] Array: 605, 805 [0210] Bit line: BL [0] 640a, BL [1] 640b,...,BL[n] 640η 099103898 Form No. A0101 Page 62/Total 106 Page 0992007313-0 201030947 'BL[η] 840η [0211] [0212] [0214] [0215] [0216 ] [0217] [0218] [0220] [0222] [0223] [0228] [0228] [BL], BL[0] 840a, BL[1] 840b,... Bit line sense amplifier: 615, 815 data output port: 635, 835 line decoding controller: 610, 810 address signal: 620, 820 control signal: 630, 830 select gate transistor: 790 select gate :792,1092 Select gate control signal: 795, SG[0] 8tt0a,... 860b, 1095 character line: WL[0] 845a, 845b data signal: 825 y. I will refer to I s _ ' i § ps _ s ss Is gs Common word line CWL : 845 ;· Wipe component: 905 . Third shallow diffusion well: 915 Second deep diffusion well: 910, 1014, 1110 Erasing charge coupled MOS transistor: 920 N-type source Diffusion: 921 N-type bungee diffusion: 922 erase control line: EL 950 ? SG[1] 099103898 Form No. A0101 Page 63 / Total 106 Page 0992007313-0 201030947 [0229] Erasing the coupled floating gate: 923, 1123 [ 0230] section Shallow well bias source: VTPW3 940 [0231] N-type connection point: 1060, 1062 [0232] Charge-coupled M0S transistor: 1025 [0233] Coupling floating gate: 1028 [0234] Bit line voltage source: BL 1040 [0235] Gate Transistor: 1090 [0236] Source Line Voltage Source: SL 1045 [0237] Erase Unit: 1105 [0238] P Type Diffusion Area: 1121, 1122 [0239] Erase Line Control Signal: 1140 [0240] PM0S Wipe the charge-coupling capacitor: 1120: 099103898 Form number A0101 Page 64 of 106 ❿ 0992007313-0

Claims (1)

201030947 VII. Patent application scope: A non-volatile memory component formed on a substrate, the non-volatile memory component comprising: a first deep diffusion well formed on a surface of the substrate by a first type of conductivity type impurity a first shallow diffusion well formed by a second type of conductivity type impurity in the first deep diffusion well; a second shallow diffusion well consisting of a second type conductivity impurity in the first deep diffusion well Formed inside A programmable charge coupled metal oxide semiconductor (MOS) transistor is coupled as a capacitor, the programmed charge coupled MOS transistor comprising: a programmed coupling floating gate formed by a single layer of polysilicon: one formed in the first shallow diffusion well a source of the first type of conductivity type impurity; and a drain τ of the first type of conductivity type impurity formed in the first shallow diffusion well, «, ϋ ρ π I , and the source, the first The shallow diffusion #first source is connected together, -nr - a memory M0S transistor, comprising: a charge storage floating gate formed by a single layer polysilicon, the charge storage floating gate is connected to the programming coupling floating gate to form a floating gate; a source of a first type of conductivity type impurity formed in the second shallow diffusion well, the source being connected to the source line bias source; and a first type formed in the second shallow diffusion well a drain of the conductive impurity, wherein the threshold voltage of the memory MOS transistor is set to a erase threshold voltage to erase the non-volatile memory component, or is set to 099103898 Form No. A0101 65 / Total 106 201 030 947 Cloth 0992007313-0 programming to a threshold voltage to the non-volatile memory devices for programming operations. 2. The winter non-volatile memory component according to the scope of claim 2, wherein the second shallow diffusion well is connected to a second well bias source. 3. The non-volatile memory component of claim 3, wherein the first deep diffusion well is coupled to a first deep well bias source. 4. The non-volatile memory component of claim 3, wherein the non-polar memory of the memory MOS transistor is connected to a one-line bias source. 5. The non-volatile memory component according to claim 1, wherein the programmed charge-coupled MOS electric vessel has a physical size larger than a physical size of the stored MOS transistor, and is edited by a night 皞〇 〇 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电6. The characterizing element as recited in claim 5, wherein the large coupling ratio is greater than 80%. 7. The non-volatile memory element according to claim 1, wherein the non-volatile memory element is immersed in ice: the layer is present in the electricity. ^ i. The charge storage floating gate and the storage The gate oxide between the MOS and the MOS is used to realize the Fowler-Nordhei®^^1^1^ convergence. 8. The non-volatile memory component of claim 7, wherein the potential of the first well bias source is set from about -7. ov to about - 5. 〇V, the bit line bias source The potential is set from about +5· to about +7. 0V to set the critical voltage of the MOS transistor to the programmed critical potential. 9. The non-volatile memory component of claim 8, wherein the programming threshold voltage is from about 〇.0V to about +1.0V. 10. The non-volatile memory component of claim 1, wherein the erasing operation of the non-volatile memory component is performed by using the memory M〇S 099103898 Form No. A0101. 1〇6页0992 201030947 The threshold voltage of the transistor is set to the erase critical potential. 11. The non-volatile note, as described in claim 1, wherein the erased critical potential is from about + 3. 0V to about + 4. 〇v. 12. The non-volatile memory component of claim 4, wherein reading the data of the non-volatile memory component detects whether the threshold voltage of the storage transistor is the programming threshold potential or the erase The non-volatile memory element of claim 12, wherein when the non-volatile 3 memory element is read, the potential of the second shallow diffusion well is set to It is larger than the programming threshold potential but smaller than the erase critical potential, and the bias potential of the bit line bias source is set to t +. For example, in the claim 4, the device further includes a select gate transistor, the side: a select gate MOS transistor, comprising: a select gate connected to a select gate control terminal; A source of a first type of conductive impurity enters the second shallow diffusion well and is connected to the source line bias source ί β r fy. A source of the first type of conductivity type impurity does not substantially store the source of the MOS transistor. The second shallow diffusion well is connected to the second well bias source β as described in claim 14 of the patent scope, such as the non-volatile memory component described in claim 14 A deep diffusion well is connected to the first deep well bias source. The non-volatile memory component of claim 14, wherein the memory MOS transistor is coupled to a one-bit line bias source. Non-volatile memory components as described in claim 14, wherein 099103818 form number Α0101 page 67/106 page 0992007313-0 201030947 * The physical size of the charge-programmed MOS transistor is greater than the memory MOS The physical dimensions of the transistor establish a large coupling ratio between the drain, source, and base of the programmed charge coupled MOS transistor and the floating gate junction. 19.20. The non-volatile memory component of claim 18, wherein the large coupling ratio is greater than SO%», such as the non-volatile memory component of claim 16, wherein The programming operation of the non-volatile memory element is accomplished by a Fowl stomach r-Nordheim charge tunneling effect through a layer of gate oxide present between the charge storage floating gate and the drain of the memory MOS transistor. For example, in the patent application scope 2Q item, the 挥发性 挥发性 挥发性 德 , , , , , 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性 挥发性Miscellaneous and iij + 5|0V to about + 7. 〇V, simultaneous solution: the choice: the gate is very good to activate the potential to turn off the selection gate Μ 电S transistor to set the storage Μ 0 S transistor threshold voltage Go to the programming threshold potential. 22 . 23 . If you apply for patents in the 20th item of the patent garden iid # 挥, body components, where the programming critical value is from about 〇. The method of claim 14, wherein the erasing operation of the non-volatile memory element is performed by setting a threshold voltage of the memory M〇s transistor to the erase critical potential. . 1。 The non-volatile memory component of claim 23, wherein the erase critical potential is from about + 3. 0V to about +4.00V. 25. The non-volatile memory component of claim 1, wherein reading the data of the non-volatile memory component detects whether the threshold voltage of the memory M?s transistor is the programmed critical potential or The erasing threshold potential 099103898, the form number A0101, page 68, the total number of non-volatile memory elements described in claim 17 or 21, wherein the non-volatile memory is read. In the component, the potential of the second shallow diffusion well is set to be larger than the programming threshold potential but smaller than the erase critical potential, and the bias potential of the bit line bias source is set to about +1.0V, The source line bias source is set to the ground reference potential, and the select gate control terminal is set to the active potential to activate the select gate Μ 0 s transistor to read the forward '14', (d) programming state. 27. The non-volatile memory component of claim 1, further comprising: a second deep diffusion of the first type of conductivity type impurity formed on the surface of the substrate a third well of impurities; a shallow diffusion well within the first deep diffusion well; and an erasing charge coupled MOSf crystal, comprising: - an erased surface floating gate formed by a single layer of multi-bright hair, The erased floating gate is connected to the chime storage floating closed, and the erased coupled floating suction is smaller than the gj Qin brake; the wiiice diffuses into the third shallow diffusion well a source of a first type of conductivity type impurity; and a drain region of the first type of conductivity type impurity diffused into the third shallow diffusion well and connected to the source region. 28. The non-volatile memory component of claim 27, wherein the second shallow diffusion well is coupled to the second well bias source. The non-volatile memory cartridge component of claim 28, wherein the second deep diffusion well is coupled to the second deep well bias source. 0992007313-0 099103898 Form No. A0101 Page 69 / Total 106 pages 201030947 3〇. Non-volatile memory element as described in the scope of claim π, wherein the drain of the memory MOS transistor is connected to a one-dimensional line bias Pressure source. 31. The non-volatile memory component of claim 27, wherein the drain of the charge-coupled MOS transistor is connected to the eraser bias source 32. 33 . 36. The non-volatile memory component of claim 27, wherein the physical size of the programmed charge coupled MOS transistor is greater than the physical size of the memory M〇s A large coupling ratio is established between the drain, source, and base of the charge coupled M〇s transistor and the floating gate. For example, in the non-volatile memory element described in claim P, wherein the large coupling ratio is greater than 80%, as described in claim 27 of the patent application, the _ component, wherein the non- The volatility memory component is programmed to achieve Fowler-Nordheim charge tunneling by a layer of gate oxide present between the charge storage floating gate and the drain of the storage MOS transistor. For example, in the object of claim 30, wherein the non-volatile memory (four) component __ 44 sets the potential of the first well source from about -7·0V to the potential of the bit line bias source. Approximately + 5. 0V to about +7.00V, and the selected gate control terminal is set to a non-activation potential to turn off the selection gate 臓 transistor to set the threshold voltage of the memory MOS transistor to the programming threshold potential . For example, the non-volatile memory component described in Item 35 of the full-time application, wherein the programming critical potential is from about 〇 〇v to about + 1 〇v. The non-volatile memory component of claim 27, wherein the non-volatile memory component is present in the erased floating gate and the erased charge The gate region of the surface of the MOS transistor is set to 0. At this point, the critical potential is erased. The singularity of the singularity is from about + 3. 0V to about +4.00V. The non-volatile memory device of claim 31, wherein the erasing operation of the non-volatile memory device is performed by setting the potential of the eraser bias source from about -7. 0V to about -5. 〇v, setting the potential of the first well bias source from about +5. 0V to about + 7. 〇v, setting the potential of the bias source of the third well from about -5·0V to about - 7. 0V, and set the first deep well bias source potential from approximately + 5. 〇 such that the critical electrical history of the storage MOS transistor is up to ★ f. The S non-issued body element as described in claim 27, wherein when the non-volatile memory element is read, it is detected whether the critical voltage of the memory cell is the programming threshold potential or the threshold potential is erased. As described in the scope of claim 30, the corpus caller element 'where the non-volatile memory is read to be smaller than the erased threshold potential of the shoe, and the bias of the bit line bias source The zeta potential is set to approximately + 1.〇V, the source line dust source is set to the ground reference potential, and the select gate control terminal is set to activate the electric W to activate the select gate to read the transistor Take the programming state of the non-volatile memory. For example, applying for a full-time PM# non-volatile body-reducing element' further includes: forming a well on the surface of the substrate; a second deep-form form number of the first type of conductivity type impurity Α0101 71 71 / 106 pages 0992007313 -0 201030947 A erased charge coupled M0S transistor, comprising: a erased coupled floating gate formed by a single layer of polysilicon, the erased floating gate being connected to the programming coupled floating gate and charge storage floating, and The erase coupling floating gate has a size smaller than a size of the programmed coupling floating closure - a source of the first conductivity type impurity diffused into the second deep diffusion well: and a diffusion into the second deep diffusion well And connected to the source of the drain of the first type of conductivity type impurity. 43. The non-volatile recording element of claim 42, wherein the second deep diffusion well is connected to the second deep well "hemiple 44<44> .101 component, wherein the storage Μθέ transistor has no geek to source. 45. The non-volatile memory component of claim 44, wherein the drain of the erased charge coupled MOS transistor is coupled to the eraser bias source. :' inleiiecfuaJ 4 6. The body element of claim 42 of the patent application, wherein the programmed charge coupled MOS transistor is larger than the physical size of the memory MOS transistor to be at the charge surface A large coupling ratio is established between the immersed, source, and base of the M0S cell, and the floating gate. 47. The non-volatile memory component of claim 46, wherein the large coupling ratio is greater than 80%. 48. The non-volatile memory component of claim 42, wherein the erasing operation of the non-volatile memory component is performed by a layer present in the erase coupling floating gate and the erase charge coupling The threshold voltage of the memory MOS transistor is set by the gate oxide between the channel regions of the MOS transistor to the actual Fowler-Nordheim charge with the channel 099103898 Form A0101 page 72 / 丨 06 page 0992007313-0 201030947 effect The non-volatile memory element of the invention is the non-volatile memory element as described in claim 42 wherein the erased critical potential is from about +3.00 V to about +4.0 V. 50. A non-volatile memory component as described in claim 45, wherein The potential of the first well bias source is set from about 0. 0V to about -5.00V, by setting the potential of the eraser bias source from about 7.5V to about -5.00V. +5. 0V to about + 7. 0V, the potential of the bias source of the third well is set from about -5.00V to about -7. 0V, and the potential of the first deep well bias source is set from about + 5 0V to about + 7. 0V, so that the threshold voltage of the memory MOS transistor reaches the erase critical potential. 51. A non-volatile memory component formed on a substrate ±_, the non-volatile memory component comprising: a common deep diffusion well of a first type of conductivity type impurity formed on a surface of the substrate; a first shallow diffusion well of a common deep-diffusion well of a type I-corrugated conductivity type impurity; a first shallow diffusion well of a second type conductivity type within the common deep diffusion well a charge coupled MOS capacitor comprising: a coupled floating gate formed by a single layer of polysilicon; a first diffusion region of the second conductivity type impurity diffused into the first shallow diffusion well, and a diffusion into the first a second diffusion region of the second conductivity type impurity of a shallow diffusion well, the second diffusion region being commonly connected to the first diffusion region and the first well bias source to the first shallow diffusion well; Α0101 Page 73/106 page 0992007313-0 201030947 A memory MOS transistor, comprising: a charge storage floating gate formed by a single layer polysilicon, the charge storage floating gate is connected to the floating gate to form a floating brake ; Source of the first conductivity type impurity diffused into a shallow diffusion and the second pole of the source connected to a source line bias voltage source; and a drain that diffuses into the first conductivity-type impurity of the second shallow diffusion well, the drain is connected to a one-line bias source, wherein 'the threshold voltage of the storage transistor is set to a erase critical potential The non-volatile memory element is erased or set to a programming threshold potential to program the non-volatile memory element. 52 . 53 . 54 . 55 . 56 . 57 . The body element of claim 51, wherein the second shallow diffusion well is connected to a first well; as stated in claim 51 & a 'body' element in which the deep diffusion well is connected to a deep well bias source The non-volatile memory component according to claim 51, wherein the physical structure of the charge coupled MOS capacitor is in the physical size of the read _M 〇 S transistor, A #笑, reference ratio is established between the source and the base and the floating gate. The non-volatile memory component of claim 54, wherein the large coupling ratio is greater than 80%. The non-volatile memory component of claim 51, wherein the programming operation of the non-volatile memory component is performed by a gate between a charge storage floating gate and a drain of the memory MOS transistor. The polar oxide is used to achieve Fowler-Nordheim charge tunneling. The non-volatile memory component of claim 51, wherein the programming operation of the non-volatile memory component is performed by setting the first well 099103898 Form No. A0101 74th Yellow/Total 106 Page 0992007313-0 201030947 The potential of the bias source is from about _7. 〇v to about -5.00 V and the potential of the bit line bias source is set from about +5. 〇V to about + 7. 0V, and the memory MOS transistor is set. The threshold voltage is to the programmed critical potential. 58. The non-volatile memory component of claim 51, wherein the programming threshold potential is from about 0. 0V to about + i. 〇V. 59. The non-volatile memory component of claim 51, wherein the erasing operation of the non-volatile memory component is to set a threshold voltage of the memory MOS transistor to the erase critical potential. 60V. The non-volatile memory component of claim 59, wherein the erase critical potential is from about +3.0 V. to the big fishing +4.0 V. 61. As claimed in claim 51, the non-volatile body element is read, wherein the threshold voltage of the non-volatile memory element is read as the programming critical power & 'or check potential 62. The non-volatile body element according to claim 51, wherein the second shallow diffusion potential is read when the non-volatile memory element is read. : *1 II I . Larger than the programmed critical potential, the potential is small, and the voltage of the W% bit line bias source is about Vi. ον, the source line® bias source is set to The ground reference is shy and the selected open polarity control terminal is set to an active potential to activate the select gate MOS transistor to read the programmed state of the non-volatile memory element. 63. A non-volatile memory element 'formed on a substrate'. The non-volatile memory element comprises: a deep diffusion well of a first type of conductivity type impurity formed on a surface of the substrate; a second type of conductivity type A shallow diffusion well of impurities is formed within the deep diffusion well f. A charge coupled metal oxide semiconductor (MOS) transistor is connected as an electric 099103898 Form No. 1 Page 75 / Total Page 〇992〇〇7313-〇 201030947 Container 'The charge coupled MOS transistor comprises: a coupled floating gate formed by a single layer of polysilicon; a source of a first type of conductivity type impurity, the source diffusing into the shallow diffusion well; and a first type of conduction a drain of a type of impurity that diffuses into the shallow diffusion well and is commonly coupled to the shallow diffusion well to the source, the shallow diffusion well and the first well bias source; a storage MOS transistor, including : a charge storage floating gate formed by a single-layer polysilicon, the charge storage floating gate is connected to the coupled floating 瞎Panwei-floating closed junction; a source of the first type of conductive impurity is taken into the base And connected to a source line bias source, ·# $, a first type of conductivity type impurity 转" is transferred into the substrate and connected to a one-element bias 墀, wherein the MOS transistor is stored The critical characterization is set to a erase critical potential to erase the non-volatile memory component, or is set to record a non-volatile =: memory component. j ίν 64 . 65 · 66 . 67 . 099103898 The sexual memory element of claim 63, wherein the deep diffusion well is connected to a deep well bias source. The non-volatile memory component of claim 63, wherein the physical size of the programmed charge coupled MOS transistor is greater than the physical size of the memory MOS transistor to be the drain and source of the charge coupled transistor A large coupling ratio is established between the pole and the base and the floating gate. The non-volatile memory component of claim 65, wherein the large coupling ratio is greater than 80%. Non-volatile memory components as described in claim 63, wherein Form No. A0101 No. 76 Buy / Total 106 Pages 099 201030947 The programming operation of the non-volatile memory component is performed by a layer of charge storage floating gate This is accomplished by the Fowler-Nordheim charge tunneling effect with the gate oxide between the drain of the MOS transistor. 68. The non-volatile memory component of claim 63, wherein the programming operation of the non-volatile memory component is performed by setting a potential of the first well bias source from about -7. 0.V to Approximately -5. 〇V and setting the potential of the bit line bias source from about +5.0 V to about +7.0 V, and setting the threshold voltage of the memory MOS transistor to the programming threshold. 69. The non-volatile memory component of claim 63, wherein the programming threshold potential is from about Q. GV to about 1. 70. The component of claim 63, wherein the non-volatile memory component is not floating: the threshold voltage of the memory MOS transistor is set to be. The non-volatile recording element of claim 63, wherein the erasing threshold potential is from about +3.0 V to about +4.0 V. 72. The component of claim 63, wherein reading the non-volatile memory click is the critical power of the S 0 S transistor is the critical time of the programming. 73. The non-volatile memory component of claim 63, wherein when reading the non-volatile memory component, the potential of the second shallow diffusion well is set to be greater than the programming threshold potential but The erased threshold potential is small, and the bias potential of the bit line bias source is set to approximately +1.0V. 74. A non-volatile memory component formed on a substrate, the non-volatile memory component comprising: a deep diffusion well of a first type of conductivity type impurity formed on a surface of the substrate 099103898 Form No. A0101 106 0992007313-0 201030947 A shallow diffusion well forming a second type of conductivity type impurity within the deep diffusion well; a charge coupled metal oxide semiconductor (MOS) transistor is connected as a capacitor 'The charge coupled MOS transistor includes : a coupled floating gate formed by a single-layer polysilicon, the physical dimension of which is such that the coupling ratio from the coupled floating gate to the shallow diffusion well is very large; the source of a second type of conductive impurity, The source diffuses into the shallow diffusion well; 渌 a second type of conductive impurity of the drain 'the liquid zen scatter into the shallow diffusion well, and is connected to the shallow diffusion well, the ^ and the bias source; a storage _ transistor, including:: A battery formed by a single layer of polycrystalline silicon is floating in the spring, and;;. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a diffusion well; and a second type of conductive type of sorghum bran d R into the shallow diffusion well f% | , and connected to the source, the old source of the sacred Xuan Qin Qin well bias source, wherein the storage The aging of the MOS transistor is set to a erase critical potential to erase the non-volatile memory component' or set to a programming threshold potential to program the non-volatile memory component. 75. The non-volatile memory component of claim 74, wherein the deep diffusion well is connected to a deep well bias source 76. The non-volatile memory component of claim 74 is disclosed in claim 74. Wherein the physical size of the programmed charge coupled MOS transistor is greater than the physical size of the memory MOS transistor to establish a large coupling ratio between the drain, source, and base of the charge coupled MOS transistor and the floating gate junction . 099103898 Form No. A0101 Page 78 of 106 0992007313-0 201030947 77 • Non-volatile memory components as described in claim 74, wherein the 6-high conversion ratio is greater than 80%. 78. The non-volatile memory component of claim 74, wherein the programming operation of the non-volatile memory component is performed by a layer of a floating gate stored in the electric street and the storage M〇S transistor bungee The gate oxide between the Fowler-Nordheim charge is achieved by the effect of the gate. 80 . 81 . 82 . The non-volatile memory component of claim 74, wherein the programming operation of the non-volatile memory component is performed by setting a potential of the first well source from about -7. 0V to about 0V and setting The potential of the bit line bias source is from about + 5·0V to about G▼, and the memory is set. Wherein the threshold voltage of the MOS transistor is to the #, as described in claim 74, the programming threshold potential is from about 0? The non-volatile and memory element described in claim 74 of the patent application, wherein the non-selective The memory device component erasing operation is performed by setting the critical electric house of the storage MOS transistor to the erase β boundary. For example, in the scope of claim 74, the erased component is wherein the erased threshold potential is from about + 4.0 V. 83. The non-volatile memory element according to claim 74, wherein detecting the non-volatile memory element detects whether a threshold voltage of the memory MOS transistor is the programming threshold potential or the erasing threshold potential . 84. The non-volatile memory component of claim 74, wherein when reading the non-volatile memory component, the potential of the second shallow diffusion well is set to be greater than the programming threshold potential but The erased threshold potential is small, and the bias potential of the bit line bias source is set to approximately +1.0V. 85. —######################################################################################################################### a deep diffusion well formed on a surface of the substrate; a second deep diffusion well of a first type of conductivity type impurity, the second deep diffusion well being formed on a surface of the substrate; - a second type of conductivity type impurity a first shallow diffusion well formed in the first deep diffusion well; a second shallow diffusion well of a second type of conductivity type impurity, the second shallow diffusion well being formed in the second deep Within the diffusion well; a charge coupled metal oxide semi-specific (M0S) transistor is connected as a capacitor - the charge coupled M〇S electric turtle on one side of the floating gate, the coupled floating single-type-type conductivity type impurity ^4The first shallow-diffusion well; and a drain of a first type of conductive impurity that diffuses into the first shallow diffusion well and is connected to the source; ^> Pressure λ II source; one storage M0S electron crystal a charge storage floating gate formed by a single-layer polymorph and connected to a program-coupled floating gate to form a floating gate; a source of a first-type conductivity type impurity a source diffusing into the second shallow diffusion well and connected to the source line bias source; and - a drain of the -type conductivity type impurity 'the pole is diffused into the second shallow diffusion well; a select gate MOS The transistor, including: - select gate, connect to - select _ control terminal; form number Α 0101 page 80 / total 丨 06 page Lu r rl .n I i C „: formation ❹ 0992007313-0 201030947 a source that diffuses into the second shallow diffusion well and is connected to the source line bias source; and a drain of the first type of conductivity type impurity, the source of which is the source of the M〇s transistor Wherein the threshold voltage of the memory MOS transistor is set to a erase critical potential to erase the non-volatile memory component, or set to a programming critical potential to program the non-volatile memory component 86. Patent application scope The non-volatile memory component of item 85 87 . 88 . The second shallow diffusion well is connected to a second well bias source. The non-carrying memory component as described in the scope of the patent application, wherein the first deep diffusion well is connected to a first: wellhead: if the application for full-time enclosure is mentioned, the second component The diffusion well is connected to a non-volatile memory element as described in claim 85, wherein the non-polar memory of the memory MOS transistor is connected to a one-line source of eccentric wear. 9〇. As claimed in claim 85, the cone-shaped element, wherein the programmed charge-coupled M0S transistor is in love (in the physical size of the memory M〇s transistor), in the capacitor of the capacitor, A large ratio of the source and the base to the floating gate is established. 91. The non-volatile memory component of claim 90, wherein the large conversion ratio is greater than 80%. The non-volatile memory device of claim 85, wherein the programming operation of the non-volatile memory device is performed by a layer between the charge storage floating gate and the drain of the memory transistor The gate oxide is used to achieve the Fowler-Nordhe im charge effect. 93. Non-volatile memory component as described in claim 89, 099103898 Form No. A0101 Page 81 / 丨06 Page 0992007313-0 201030947 94 . 95 . 96 . 97 . 99 . 99 . The programming operation for the non-volatile Z It body 7L piece is to set the potential of the first well bias source from about -7 to about one. 5 ov, set the bit line deviation source The potential is from about + 5. 〇峋 approximately v, and the threshold voltage of the MOS transistor is set to the programmed critical potential. As described in the patent specification (4), the non-volatile memory component, wherein (4) (four) boundary potential Is a non-volatile memory element as described in claim 85, wherein the erasing operation of the non-volatile memory element is performed by a layer-by-layer The gate oxide between the homozygous floating gate and the erased homozygous transistor_channel is realized by the p(10)1 over-private rm charge with the channel effect to store the critical potential of the germanium transistor. ... For example, the patent application scope is referred to in Item 3, and the burial threshold is from about +3· 〇v to about +4, 〇v. As described in claim 89. The non-volatile memory component, wherein the potential of the first well bias source is set to be from the +5. 〇v to the second well bias source*:.:·. :::* :-Vs. V:~ . JR* potential from about -7. ον to laughter - the potential of the deep well bias source is about + 5. 0V to about + 7. 0V ' and the source line bias source potential is from about -7. 0V to about - 5. 0V makes the threshold voltage of the memory MOS transistor reach the erase critical potential to complete. The non-volatile memory component of claim 85, wherein when the non-volatile memory component is read, detecting whether the threshold voltage of the memory MOS transistor is the programming threshold potential or the erasing threshold potential. The non-volatile memory element according to Item 89, wherein the potential of the first shallow diffusion well is read when the non-volatile memory impurity element is read District 099103898 Form No. A0101 No. 82 True/Bings 06 Page 0992007313-0 201030947 100 . 101 . Lu 102 · 103 . 104 . 099103898 is set to be larger than the programmed critical potential but smaller than the erase critical potential, and the bit The bias potential of the source bias source is set to approximately + uv, the source line bias source is set to the ground reference potential, and the select gate control terminal is set to the active potential to activate the select gate MOS The crystal reads the programmed state of the non-volatile memory element. An early layer polycrystalline floating gate non-volatile memory component, including a MOS capacitor and a memory MOS transistor, the size of the memory MOS transistor is allowed to use a current low voltage logic integrated circuit process and at least a process for forming a deep diffusion well of a first type of conductivity type impurity formed on the surface of the substrate; the MOS electrode or a first electrode plate connected to the gate of the storage MOS transistor The gate of the MOS transistor can float and form a floating ' ' and the physical size of the M 〇 $ capacitor is larger than that of the amp + amp of the MG capacitor. The second electrical release plate and the floating gate junction establish a large coupling ratio. Change "- such as the floating gate non-volatile memory element of the 100th 申请 of the patent application scope, wherein the Mo electrode plate is the 汲 狼 散 、 、 、 、 、 、 、 、 。 。 。 。 。 。 。 。 。 。 。 The single-layer polysilicon floating gate non-volatile memory device of claim 100, wherein the drain of the MOS transistor is connected to a one-line voltage source, and the source of the MOS transistor is connected to a source current line. The single-layer polysilicon floating gate non-volatile memory device according to the above item 1, wherein the physical size of the MOS capacitor is more than 10 times larger than the physical size of the MOS transistor, as described in claim 103. Single-layer polysilicon floating gate non-volatile memory component, wherein the physical form number A0101 % 83 1/^ 106 1 095 201030947 between the capacitor and the MOS transistor is used to provide a large coupling ratio greater than 80% 105. The single-layer polysilicon floating gate non-volatile memory element according to claim 1, wherein a large coupling ratio is applied when a voltage is applied to the second electrode plate of the MOS capacitor. A majority of the voltage can be coupled to the second electrode plate of the M〇s capacitor to be coupled to the floating gate junction. 106. Single-layer polysilicon floating gate non-volatile memory component as described in claim 1 'When a voltage is applied to the source annihilation pole of the MOS transistor, an electric field is established within the gate oxidation region of the MOS transistor to initiate edge tunneling of Fowler-Nordheim. 107. The single-layer polycrystalline floating floating non-volatile memory component according to the item iq〇, wherein when a negative 棰 is programmed, fc is applied to the second electrode plate, and a positive electrode is applied, the voltage is applied. At the extreme time, the charge at the floating gate is programmed by the nM stupid non-volatile memory element. 108. Single-layer polysilicon floating gate non-volatile memory as described in claim 1-7 Body element, wherein the negative 祯 漱 漱 : : : : : 约 约 约 约 约 约 约 到 到 到 到 到 到 到 到 到 到 到 到 到 -7 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极 正极Patent application No. i〇6 polycrystalline germanium floating gate non-volatile memory An element, wherein the positive erase voltage is applied to the second electrode plate'. The negative erase voltage is applied to the source of the MOS transistor such that the charge is injected into the floating gate junction to erase the floating gate non-volatile memory The single element polysilicon floating gate non-volatile singular element according to claim 109, wherein the positive electrode erasing voltage is from about + 6. to about + 7. 0V 'the negative electrode The erase voltage is about -5. ον. 111. The single-layer polysilicon floating gate non-volatile form number as described in claim 1 is Α0101 099103898 page 84/106 pages 201030947 112 memory device, The t-float _ turn-to-cell component is realized by injecting electrons into a floating gate. 7 Please specialize «(10) pin-shaped single crystal (4) non-volatile ° hidden body element', in which the surface Μ container is formed in the first shallow diffusion well, the storage MOS transistor is formed in the second shallow diffusion well, first, scattered Wells are formed from a second type of conductive impurity. And the second shallow expansion Fntedecfui Picpeify Of Pee 099103898 Form No. A0101 Page 85 / Total 1〇 6 f 0992007313-0